® AFE AFE1203 120 3 2Mbps, Single Pair HDSL ANALOG FRONT END FEATURES ● ● ● ● ● ● ● ● ● E1/T1 SINGLE PAIR 2B1Q OPERATION COMPLETE ANALOG INTERFACE 385mW POWER DISSIPATION PROGRAMMABLE POWER DESCRIPTION Burr-Brown’s Analog Front End greatly reduces the size and cost of a single pair HDSL (High bit rate Digital Subscriber Line) system by providing all of the active analog circuitry needed to connect an HDSL digital signal processor to an external compromise hybrid and an HDSL line transformer. The transmit and receive filter responses automatically change with clock frequency, allowing the AFE1203 to operate over a wide range of data rates. The power dissipation of the device can be reduced under digital control for operation at lower speeds. The AFE1203 will operate at bit rates from 160kbps to 2.3Mbps. It meets ETSI PSD specifications for single pair E1, as well as ETSI and ANSI PSD specifications for two pair E1 and T1. Functionally, this unit consists of a transmit and a receive section. The transmit section generates, filters, and buffers outgoing 2B1Q data. The receive section filters and digitizes the symbol data received on the telephone line. This IC operates D/A Converter 48-LEAD SSOP PACKAGE SCALEABLE DATA RATE OPERATION FROM 2.3Mbps TO 160kbps +5V ONLY (5V OR 3.3V DIGITAL) –40°C TO +85°C OPERATION on a single 5V supply. The digital circuitry in the unit can be connected to a supply from 3.3V to 5V. The chip uses only 385mW for full-speed operation. It is housed in a small 48-lead SSOP package. The receive channel is designed around a fourth-order deltasigma analog-to-digital converter. It includes a difference amplifier designed to be used with an external compromise hybrid for first-order analog echo cancellation. A programmable gain amplifier with gains 0dB to +9dB is also included. The deltasigma modulator, operating at a 24X oversampling ratio, produces a 14-bit output at symbol rates up to 1168kHz (for 2.3Mbps operation). The transmit channel consists of a digital-to-analog converter and switched-capacitor pulse forming network followed by a differential line driver. The pulse forming network receives symbol data and generates a standard 2B1Q output waveform. The differential line driver uses a composite output stage combining class B operation (for high efficiency driving large signals) with class AB operation (to minimize crossover distortion). Pulse Former Line Driver txLINEP txLINEN REFP PLLOUT PLLIN Voltage Reference Transmit Control txDAT VCM REFN txCLK rxSYNC Receive Control rxLOOP rxLINEP 2 rxGAIN Delta-Sigma Modulator 14 rxD13 - rxD0 rxLINEN rxHYBP rxHYBN Decimation Filter Patents Pending International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1998 Burr-Brown Corporation PDS-1460A Printed in U.S.A. October, 1998 SPECIFICATIONS Typical at 25°C, AVDD = +5V, DVDD = +3.3V, ftx = 1168kHz (E1 single pair rate) and Normal Power mode, unless otherwise specified. AFE1203E PARAMETER RECEIVE CHANNEL Number of Inputs Input Voltage Range Common-Mode Voltage Input Impedance Input Capacitance Input Gain Matching Resolution Programmable Gain Settling Time Gain + Offset Error Output Data Coding Data Rate Output Word Rate TRANSMIT CHANNEL Transmit Clock Rate, fTX Transmit –3dB Point Transmit Power(4) Pulse Output Common-Mode Voltage, VCM Output Resistance(5) TRANSCEIVER PERFORMANCE Uncancelled Echo(6) DIGITAL INTERFACE(5) Logic Levels VIH VIL VOH VOL POWER Analog Power Supply Voltage Digital Power Supply Voltage Power Dissipation(4, 7) Power Dissipation(7) PSRR COMMENTS MIN Differential Balanced Differential(1) 1.5V CMV Recommended All Inputs 2 Line Input vs Hybrid Input Normal Power Medium Power Low Power Normal Power, rxSYNC(3) Symbol Rate, Normal Power Symbol Rate, Medium Power Symbol Rate, Low Power 2320kbps 1168kbps 784kbps DC to 1MHz 6 5 Binary Two’s Complement 384 2320 192 1168 160 320 196 1168 196 96 80 1168 584 160 485 292 196 13 13.5 14 See Typical Performance Curves AVDD/2 1 rxGAIN = 0dB, Loopback Enabled rxGAIN = 0dB, Loopback Disabled rxGAIN = 3.25dB, Loopback Disabled rxGAIN = 6dB, Loopback Disabled rxGAIN = 9dB, Loopback Disabled |IIH| < 10µA |IIL| < 10µA IOH = –20µA IOL = 20µA MAX ±3.0 +1.5 See Typical Performance Curves 10 ±2 14 Four Gains: 0dB, 3.25dB, 6dB, and 9dB Gain, rxSYNC, or Power Mode Change(8) Tested at Each Gain Range TYP DVDD – 1 –0.3 DVDD – 0.5 TEMPERATURE RANGE Operating(5) kbps kbps kbps kHz kHz kHz kHz kHz kHz kHz dBm V Ω V V V V 3.3 5.25 385 300 240 415 55 –40 Symbol Periods %FSR(2) DVDD + 0.3 +0.8 5.25 3.15 pF % Bits dB dB dB dB dB 5 4.75 V V –67 –67 –69 –71 –73 +0.4 Specification Operating Range Specification Operating Range Normal Power Medium Power Low Power Normal Power, DVDD = 5V UNITS +85 V V V V mW mW mW mW dB °C NOTES: (1) With a balanced differential signal, the positive input is 180° out of phase with the negative input, therefore the actual voltage swing about the common mode voltage on each pin is ±1.5V to achieve a differential input range of ±3.0V or 6Vp-p. (2) FSR is Full-Scale Range. (3) The output data is available at twice the symbol rate with interpolated values. (4) With a pseudo-random equiprobable sequence of HDSL pulses; 13.5dBm applied to the transformer (27dBm output from txLINEP and txLINEN). (5) Guaranteed by design and characterization. (6) Uncancelled Echo is a measure of the total analog errors in the transmitter and receiver sections including the effect of non-linearity and noise. See the Discussion of Specifications section of this data sheet for more information. (7) Power dissipation includes only the power dissipated within the component and does not include power dissipated in the external loads. The AFE1203 is tested with a 1:2 line transformer. (8) This is the settling time required for any gain change, change of rxSYNC or any change of power mode. ® AFE1203 2 PIN DESCRIPTIONS PIN # TYPE NAME 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Ground Power Input Input Input Output Output Output Output Output Output Ground Power Output Output Output Output Output Output Output Output Input Input Input Input Input Power Input Input Input Input Ground Ground Output Output Output Power Ground Output Power Output Ground NC NC NC NC Output Input AGND AVDD txCLK txDATN txDATP rxD0 rxD1 rxD2 rxD3 rxD4 rxD5 DGND DVDD rxD6 rxD7 rxD8 rxD9 rxD10 rxD11 rxD12 rxD13 PWSEL rxSYNC rxGAIN0 rxGAIN1 rxLOOP AVDD rxHYBN rxHYBP rxLINEN rxLINEP AGND AGND REFP VCM REFN AVDD AGND txLINEN AVDD txLINEP AGND NC NC NC NC PLLOUT PLLIN DESCRIPTION Analog Ground for PLL Analog Supply (+5V) for PLL Symbol Clock XMITB Line XMIT Line ADC Output Bit-0 ADC Output Bit-1 ADC Output Bit-2 ADC Output Bit-3 ADC Output Bit-4 ADC Output Bit-5 Digital Ground Digital Supply (+3.3V to +5V) ADC Output Bit-6 ADC Output Bit-7 ADC Output Bit-8 ADC Output Bit-9 ADC Output Bit-10 ADC Output Bit-11 ADC Output Bit-12 ADC Output Bit-13 Power Control ADC Sync Signal Receive Gain Control Bit-0 Receive Gain Control Bit-1 Loopback Control Signal (loopback is enabled by positive signal) Analog Supply (+5V) Negative Input from Hybrid Network Positive Input from Hybrid Network Negative Line Input Positive Line Input Analog Ground Analog Ground Positive Reference Output, Nominally 3.5V Common-Mode Voltage (buffered), Nominally 2.5V Negative Reference Output, Nominally 1.5V Analog Supply (+5V) Analog Ground Transmit Line Output Negative Analog Supply (+5V) Transmit Line Output Positive Analog Ground Connection to Ground Recommended Connection to Ground Recommended Connection to Ground Recommended Connection to Ground Recommended PLL Filter Output PLL Filter Input The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 AFE1203 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION Analog Inputs: Current .............................................. ±100mA, Momentary ±10mA, Continuous Voltage .................................. AGND –0.3V to AVDD + 0.3V Analog Outputs Short Circuit to Ground (+25°C) ..................... Continuous AVDD to AGND ......................................................................... –0.3V to 6V DVDD to DGND ......................................................................... –0.3V to 6V PLLIN or PLLOUT to AGND ........................................ –0.3V to AVDD + 0.3V Digital Input Voltage to DGND ................................. –0.3V to DVDD + 0.3V Digital Output Voltage to DGND .............................. –0.3V to DVDD + 0.3V AGND, DGND Differential Voltage ..................................................... 0.3V Junction Temperature (TJ) ............................................................ +150°C Storage Temperature Range .......................................... –40°C to +125°C Lead Temperature (soldering, 3s) ................................................. +260°C Power Dissipation ......................................................................... 700mW Top View PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER(1) AFE1203E 48-Lead SSOP 333 TEMPERATURE RANGE –40°C to +85°C AGND 1 48 PLLIN AVDD 2 47 PLLOUT txCLK 3 46 NC txDATN 4 45 NC txDATP 5 44 NC rxD0 6 43 NC rxD1 7 42 AGND rxD2 8 41 txLINEP rxD3 9 40 AVDD rxD4 10 39 txLINEN rxD5 11 38 AGND DGND 12 37 AVDD AFE1203E NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ® AFE1203 SSOP 4 DVDD 13 36 REFN rxD6 14 35 VCM rxD7 15 34 REFP rxD8 16 33 AGND rxD9 17 32 AGND rxD10 18 31 rxLINEP rxD11 19 30 rxLINEN rxD12 20 29 rxHYBP rxD13 21 28 rxHYBN PWSEL 22 27 AVDD rxSYNC 23 26 rxLOOP rxGAIN0 24 25 rxGAIN1 TYPICAL PERFORMANCE CURVES At Output of Pulse Transformer Typical at 25°C, AVDD = +5V, and DVDD = +3.3V, unless otherwise specified. AVERAGE POWER SPECTRAL DENSITY LIMIT Power Spectral Density (dBm/Hz) –20 LOWER LIMIT T1 SPEED –80dB/decade T1 –40 E1 –60 BREAK FREQUENCY SLOPE UPPER LIMIT 196kHz 292kHz 485kHz –80dB/decade –80dB/decade –80dB/decade –118dBm/Hz –120dBm/Hz –122dBm/Hz T1, Two Pair –38dBm/Hz E1, Two Pair –40dBm/Hz E1, Single Pair (E1-SP) –42.5dBm/Hz E1 E1-SP E1-SP –80 –100 –120 –140 1k 10k 100k 1M 100M 10M Frequency (Hz) CURVE 1. Upper Bound of Power Spectral Density Measured at the Transformer Output. 0.4T 0.4T TWO PAIR T1 AND E1 LIMITS A B C D E F G H NORMALIZED LEVELS QUATENARY SYMBOLS (V) +3 +1 0.0264 0.0088 2.8248 0.9416 2.6400 0.8800 2.4552 0.8184 0.0792 0.0264 0.0264 –0.0088 –0.4224 –0.1408 –0.1320 –0.0440 0.01 1.07 1.00 0.93 0.03 –0.01 –0.16 –0.05 SINGLE PAIR E1 –1 –0.0088 –0.9416 –0.8800 –0.8184 –0.0264 0.0088 0.1408 0.0440 NORMALIZED LEVELS –3 –0.0264 –2.8248 –2.6400 –2.4552 –0.0792 0.0264 0.4224 0.1320 0.01 1.07 1.00 0.93 0.04 –0.01 –0.20 –0.05 QUATENARY SYMBOLS (V) +3 0.0250 2.6750 2.5000 2.3250 0.1000 –0.0250 –0.5000 –1.2500 +1 0.0083 0.8917 0.8333 0.7750 0.0333 –0.0083 –0.1667 –0.0417 –1 –0.0083 –0.8917 –0.8333 –0.7750 –0.0333 0.0083 0.1667 0.0417 –3 0.0250 –2.6750 –2.5000 –2.3250 –0.1000 0.0250 0.5000 0.1250 1.25T –1.2T –0.6T 14T 50T 0.5T CURVE 2. Transmitted Pulse Template and Actual Performance as Measured at the Transformer Output. INPUT IMPEDANCE vs BIT RATE Input Impedance (kΩ) 100 Two Pair T1 = 784kbps, 45kΩ Two Pair E1 = 1168kbps, 30kΩ Single Pair E1 = 2320kbps, 15kΩ 75 50 T1 E1 25 E1, Single Pair 0 200 600 1000 1400 1800 2200 2600 Bit Rate (kbps) CURVE 3. Input Impedance of rxLINE and rxHYB. ® 5 AFE1203 THEORY OF OPERATION rxLOOP INPUT rxLOOP is the loopback control signal. When enabled, the rxLINEP and rxLINEN inputs are disconnected from the AFE. The rxHYBP and rxHYBN inputs remain connected. Loopback is enabled by applying a positive signal (Logic 1) to rxLOOP. The transmit channel consists of a D/A converter and a switched-capacitor pulse forming network followed by a differential line driver. The pulse forming network receives symbol data from the DSP and generates a 2B1Q output waveform. The output meets the pulse mask and power spectral density requirements defined in European Telecommunications Standards Institute document RTR/TM-03036 for E1 mode and in sections 6.2.1 and 6.2.2.1 of Bellcore technical advisory TA-NWT-001210 for T1 mode. The differential line driver uses a composite output stage combining class B operation (for high efficiency driving large signals) with class AB operation (to minimize crossover distortion). The receive channel is designed around a fourth-order delta sigma A/D converter. It includes a difference amplifier designed to be used with an external compromise hybrid for first-order analog crosstalk reduction. A programmable gain amplifier with gains of 0dB to +9dB is also included. The delta sigma modulator operating at a 24X oversampling ratio produces 14 bits of resolution at output rates up to 584kHz. The basic functionality of the AFE1203 is illustrated in Figure 1. The receive channel operates by summing the two differential inputs, one from the line (rxLINE) and the other from the compromise hybrid (rxHYB). The connection of these two inputs so that the hybrid signal is subtracted from the line signal is described in the paragraph titled “Echo Cancellation in the AFE”. The equivalent gain for each input in the difference amp is 1. The resulting signal then passes to a programmable gain amplifier which can be set for gains of 0dB through 9dB. The ADC converts the signal to a 14-bit digital word, rxD13-rxD0. ECHO CANCELLATION IN THE AFE The rxHYB input is designed to be subtracted from the rxLINE input for first-order echo cancellation. To accomplish this, note that the rxLINE input is connected to the same polarity signal at the transformer (positive to positive and negative to negative) while the rxHYB input is connected to opposite polarity through the compromise hybrid (negative to positive and positive to negative) as shown in Figure 2. RECEIVE DATA CODING The data from the receive channel A/D converter is coded in Straight Offset Binary. ANALOG INPUT 11111111111111 Negative Full Scale 00000000000000 RECEIVE CHANNEL PROGRAMMABLE GAIN AMPLIFIER The gain of the amplifier at the input of the Receive Channel is set by two gain control pins, rxGAIN1 and rxGAIN0. The resulting gain between 0dB and +9dB is shown below. rxGAIN1 SCALEABLE TIMING The AFE1203 scales operation with the clock frequency. All internal filters, the A/D converter, the D/A converter, and the pulse former change frequency with the clock speed so that the unit can be used at different frequencies by changing the clock speed. D/A Converter txDAT OUTPUT CODE (rxD13 - rxD0) Positive Full Scale rxGAIN0 GAIN 0 0 0dB 0 1 3.25dB 1 0 6dB 1 1 9dB txLINEP Pulse Former txLINEN Differential Line Driver rxHYBP rxHYBN 14 rxD13 - rxD0 ADC rxLINEP Programmable Gain Amp FIGURE 1. Functional Block Diagram of AFE1203. ® AFE1203 6 rxLINEN Difference Amplifier 0.1µF PLLOUT REFP VCM 0.1µF 0.1µF REFN 1kΩ 47nF 200Ω 13Ω txLINEN 0.1µF Ring Neg Pos Compromise Hybrid txDATP txDATN Neg txCLK 47nF Pos 375Ω rxSYNC DSP 1:2 Transformer Tip 13Ω txLINEP PLLIN rxHYBP rxLOOP AFE1203E 100pF rxGAIN1 rxHYBN 375Ω rxGAIN0 rxD13 - rxD0 14 Input anti-alias filter fC ≅ 2MHz AGND rxLINEN 375Ω DGND 100pF AGND AGND rxLINEP AGND 375Ω AGND DVDD PLL AVDD AVDD AVDD AVDD 5V Analog 5V to 3.3V Digital 10µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF + 1 - 10µF 100µF 5Ω - 10Ω Resistor for Isolation FIGURE 2. Basic Connection Diagram. rxHYB AND rxLINE INPUT ANTI-ALIASING FILTERS The –3dB frequency of the input anti-aliasing filter for the rxLINE and rxHYB differential inputs should be approximately 2MHz for operation at 2.3Mbps. Suggested values for the filter are 375Ω for each of the two input resistors and 100pF for the capacitor. Together the two 375Ω resistors and the 100pF capacitor result in –3dB frequency of just over 2MHz. The 375Ω input resistors will result in a minimal voltage divider loss with the input impedance of the AFE1203. This circuit applies at rates of 1Mbps to 2Mbps. For slower rates, the anti-aliasing filters will give best performance with their –3dB frequency approximately equal to the bit rate. For example, a –3dB frequency of 500kHz should be used for a single pair bit rate of 500kbps. rxHYB AND rxLINE INPUT BIAS VOLTAGE The transmitter output on the txLINE pins and the rxLINE inputs are centered at midscale, 2.5V. Inside the AFE1203, the rxHYB and rxLINE signals are subtracted as described in the paragraph on echo cancellation above. This means that the rxHYB inputs need to be centered at 2.5V just as the rxLINE signal is centered at 2.5V. The external compromise hybrid must be designed so that the signal into the rxHYB inputs remains centered at 2.5V. ® 7 AFE1203 TIMING DIAGRAM Transmit Timing ttx1 ttx2 txCLK txDATP (+3 Symbol) txDATP (+1 Symbol) txDATP (–1 Symbol) txDATP (–3 Symbol) ttx1/4 ttx1/2 3ttx1/4 Receive Timing ttx1/16 min nttx1/16 rxSYNC nttx1/16 + 59ttx1/96 nttx1/16 + 11ttx1/96 rxD13 - rxD0 Data 1 Data 1a 5ns Data 2 5ns 5ns 5ns NOTES: (1) Any transmit sequence not shown will result in a zero symbol. (2) All transitions are specified relative to the rising edge of txCLK. (3) Maximum allowable error for any txDAT edge is ±ttx1/12 (±72ns for single pair E1 rate). (4) txDATN is the inverse of txDATP. (5) Both txDAT inputs are read by the AFE12 03 at 1/8, 3/8, and 5/8 of a symbol period from the rising edge of txCLK. (6) rxSYNC can shift to one of 16 discrete delay times from the rising edge of txCLK. (7) It is recommended that rxD13 - rxD0 be read on the rising edge of rxSYNC. FIGURE 3. Timing Diagram. RECEIVE TIMING The rxSYNC signal controls portions of the A/D converter’s decimation filter and the data output timing of the A/D converter. It is generated at the symbol rate by the user and must be synchronized with txCLK. The leading edge of rxSYNC can occur at the leading edge of txCLK or it can be shifted by the user in increments of 1/16 of a symbol period to one of 15 discrete delay times after the leading edge of txCLK. rate of 24X the symbol rate. The A/D converter’s decimation filter downsamples the modulator output by a factor of 12. The bandwidth of the decimation filter is equal to one-half the symbol rate. This yields two output words per symbol period. These two output words are shown as Data 1 and Data 1a in Figure 3. The specifications of the AFE1203 assume that one A/D converter output is used per symbol period and the other output is ignored. The Receive Timing diagram above suggests using the rising edge of the rxSYNC pulse to read the first data output in a symbol period. Either data output may be used. Both data outputs may be used for more flexible post-processing. RECEIVE OUTPUT DATA RATE The receive channel delta-sigma A/D converter of the AFE1203 uses a modulator which operates at an oversampling ® AFE1203 8 DISCUSSION OF SPECIFICATIONS levels, the maximum bit rate is lower and in addition, the minimum bit rate is lower. The power control pin (pin 22) has three input levels, Logic 1, Logic 0, and high impedance. In the high impedance state, up to 20µA leakage current can be tolerated out of the power control pin. The AFE1203 requires six baud periods to settle after a change in the power control pin status. UNCANCELLED ECHO The key measure of transceiver performance is uncancelled echo. This measurement is made as shown in the diagram of Figure 4. The AFE is connected to an output circuit including a typical 1:2 line transformer. The line is simulated by a 135Ω resistor. Symbol sequences are generated by the tester and applied both to the AFE and to the input of an adaptive filter. The output of the adaptive filter is subtracted from the AFE output to form the uncancelled echo signal. Once the filter taps have converged, the rms value of the uncancelled echo is calculated. Since there is no far-end signal source or additive line noise, the uncancelled echo contains only noise and linearity errors generated in the transmitter and receiver. Typical power dissipation specifications, shown in Table I, assume a 5V analog supply, a 3.3V digital supply, standard 13.5dBm delivered to the line, a pseudo random equiprobable sequence of HDSL output pulses, and a 1:2 turns ratio line transformer. The power dissipation specifications includes all power dissipated in the AFE1203—it does not include power dissipated in the external load. The external power is 16.5dBm, 13.5dBm to the line and 13.5dBm to the impedance matching resistors. The external power of 16.5dBm is 45mW. If a 5V digital supply is used rather than a 3.3V supply, the power dissipation increases by approximately 3mW. The data sheet value for uncancelled echo is the ratio of the rms uncancelled echo (referred to the receiver input through the receiver gain) to the nominal transmitted signal (13.5dBm into 135Ω, or 1.74Vrms). This echo value is measured under a variety of conditions: with loopback enabled (line input disconnected); with loopback disabled under all receiver gain ranges; and with the line shorted (S1 closed in Figure 4). POWER LEVEL PROGRAMMABLE POWER DISSIPATION The power dissipation of the AFE1203 is digitally programmable by the user to three levels: Normal, Medium, and Low. The maximum bit rate of the AFE1203 is 2.3Mbps with Normal power dissipation. At lower power dissipation MAXIMUM SPEED (Mbps) MINIMUM SPEED (kbps) txDATP PIN 22 INPUT Normal 2.320 384 385 Logic 1 Medium 1.168 192 300 Logic 0 Low 0.320 160 240 High Impedance TABLE I. Power Control Operation. 13Ω Transmit Data TYPICAL POWER DISSIPATION (mW) 1:2 5.6Ω txLINEP 13Ω 5.6Ω 135Ω S1 txLINEN 576Ω rxHYBP 1.54kΩ Adaptive Filter 100pF AFE1205 0.01µF 150Ω rxHYBN 576Ω 375Ω rxLINEP 100pF rxLINEN 375Ω Uncancelled Echo rxD13 - rxD0 FIGURE 4. Uncancelled Echo Test Diagram. ® 9 AFE1203 both a 10µF tantalum capacitor and a 0.1µF ceramic capacitor. Both capacitors should be placed between pins 1 and 2. The ceramic capacitor should be placed as close to the AFE1203 as possible. The placement of the tantalum capacitor is not as critical, but should be close. A 5Ω to 10Ω resistor should be used to connect the PLL supply (pin 2) to the analog supply. This resistor, in combination with the 10µF tantalum capacitor, form a low pass filter to keep glitches that occur on the general analog supply, AVDD, from affecting the PLL supply. The PLL ground (pin 1) should connect directly to the ground plane. The ground plane should also extend underneath PLLOUT and PLLIN (pins 47 and 48, respectively). LAYOUT The analog front end of an HDSL system has a number of conflicting requirements. It must accept and deliver digital outputs at fairly high rates of speed, phase-lock to a highspeed digital clock, and convert the line input to a highprecision (14-bit) digital output. Thus, there are really three sections of the AFE1203: the digital section, the phaselocked loop, and the analog section. A combined analog and digital ground plane is recommended. The ground plane should pass under all of the AFE1203 and its pins. The power supply for the digital section of the AFE1203 can range from 3.3V to 5V. This supply should be decoupled to ground with a ceramic 0.1µF capacitor placed as close to DGND (pin 12) and DVDD (pin 13) as possible. Ideally, both a digital power supply plane and a ground plane should run up to and underneath the digital pins of the AFE1203 (pins 3 through 26). However, DVDD may be supplied by a wide printed circuit board (PCB) trace. A ground plane underneath all digital pins is strongly recommended. The remaining portion of the AFE1203 should be considered analog. All AGND pins should be connected directly to the common ground plane and all AVDD pins should be connected to an analog 5V power plane. Both of these planes should have a low impedance path to the power supply. Ideally, all ground planes and traces and all power planes and traces should return to the power supply connector before being connected together (if necessary). Each ground and power trace pair should be routed over each other, should not overlap any portion of another pair, and the pairs should be separated by a distance of at least 0.25 inch (6mm). The Phase Locked Loop (PLL) analog supply, pin 2, must be derived from AVDD, the general analog supply. The power supply to the PLL must be in the range of 4.75V to 5.25V. The PLL section of the AFE1203 should be decoupled with ® AFE1203 10