INTEGRATED CIRCUITS DATA SHEET UMA1002 Data processor for cellular radio (DPROC2) Product specification Supersedes data of 1996 Sep 13 File under Integrated Circuits, IC17 1997 Jan 28 Philips Semiconductors Product specification Data processor for cellular radio (DPROC2) UMA1002 FEATURES • Single chip solution to all the data handling and supervisory functions • Configuration to both AMPS and TACS • Additional JTACS option • I2C-bus serial control GENERAL DESCRIPTION • All analog interface and filtering functions fully implemented on chip The UMA1002 is a low power CMOS LSI device incorporating the data transceiving, data processing, and SAT functions (including on-chip filtering) for an AMPS or TACS hand-held portable cellular radio telephone. • Error handling in hardware reduces software requirements • Robust SAT decoding and transponding circuitry In this data sheet, the UMA1002 is often referred to by the descriptive term ‘DPROC2’. • Low current consumption by on-chip power-down modes • Reduced system current consumption by new integrated power-saving features – Majority voting includes more intelligence – On-chip control filler word filter – BCH error filter – Possibility to program ESCC bits • Small physical size: SO28 or LQFP32 • External peripheral component count reduced – On-chip selectable clock divider – Integrated pull-up resistor at TXLINE • Simplified reset and abort software routines possible • The SO28 version is fully compatible with UMA1000LT and UMF1000T. QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT VDD supply voltage 2.7 3.0 5.5 IDD supply current normal operation with external clock − 1.3 1.8 mA Tamb operating ambient temperature −30 − +70 °C V ORDERING INFORMATION TYPE NUMBER PACKAGE NAME UMA1002T SO28 UMA1002H LQFP32 1997 Jan 28 DESCRIPTION VERSION plastic small outline package; 28 leads; body width 7.5 mm SOT136-1 plastic low profile quad flat package; 32 leads; body 7 × 7 × 1.4 mm SOT358-1 2 28 (27) 7 (4) MVO 10 (8) 8 (5) (3) 27 (26) COMPARATOR 1 3 ANTIALIASING FILTER DEMODD (31) DATA RECOVERY SYNCRONIZATION AND VOTING SAT RECOVERY INTERPOLATOR UMA1002 BIAS GENERATOR GATED D/A 5 (1) DOTTING DETECTOR COMPARATOR 2 ARBITRATION LOGIC SAT REGENERATION 2 (30) TXCTRL 3 18 (16) CLOCK FILTER (32) OUTPUT FILTER ST GENERATOR RACTRL 20 (19) 11 (9) 4 BUSY/VSAT SAT DETERMINATION AGND DATA RXCLK ERROR CORECTION 19 (17) SAT FILTER RXLINE Philips Semiconductors (28) INVRX RECDATA Data processor for cellular radio (DPROC2) VDDD BLOCK DIAGRAM book, full pagewidth 1997 Jan 28 VDDA MANCHESTER AND BCH ENCODING TRANSMIT BUFFER 17 (15) 15 (13) TACTRL TXCLK TXHOLD TXLINE 25 (25) 6 RESET (2) RESET, CLOCK AND POWER-DOWN GENERATOR (20) CLKSEL 12 (10) CLKIN TEST LOGIC 9 (7) 13 (11) CLKOUT I2C INTERFACE GATED D/A 22 (22) TST TSCAN 1 (29) VSSA 14 (12) VSSD INVTX MBD827 A0 Product specification Fig.1 Block diagram. JTACS 21 (21) SDA UMA1002 Pins in parenthesis apply to UMA1002H in LQFP32. (6) 23 (23) SCL 24 (24) Philips Semiconductors Product specification Data processor for cellular radio (DPROC2) UMA1002 PINNING PIN SYMBOL DESCRIPTION SO28 LQFP32 VSSA 1 29 Negative analog supply (0 V). To be connected low-ohmic to VSSD. AGND 2 30 Internally generated analog signal ground. Voltage level = 1⁄2VDDA. This pin should be connected to a blocking capacitor, no DC load allowed. DEMODD 3 31 DEMODD inputs analog data and SAT signals from the RF demodulator. This pin should normally be AC-coupled. See Chapter “AC characteristics”. DATA 4 32 Data is an analog output which provides the Manchester encoded and filtered data signal, SAT and signalling tone. This signal should normally be AC-coupled into the Audio/Data summer. See Chapter “AC characteristics”. RACTRL 5 1 Received audio control output. Open-drain output used to blank the audio path to the earpiece when a sequence of dotting followed by a synchronization word or 2 synchronization words separated by 77 bits is detected. RACTRL and TACTRL functions can be combined using one line. Output level LOW means audio muted. RESET 6 2 Master reset input resetting all internal flip-flops to the specified state. This input has no influence on analog parts, but must be controlled by an active HIGH microcontroller port. INVRX 7 4 This input inverts the sense of received data stream, which allows RF demodulators with high or low local oscillators to be used. The AMPS and TACS specifications define NRZ encoded logic 1 as a LOW-to-HIGH transition in the centre of a data bit period. The polarity of the demodulated data stream into DPROC2 depends on the receiver local oscillator. Input LOW means data normal. RXLINE 8 5 Received data signal output to the system controller. TST 9 7 Test input pin (note 1). RECDATA 10 8 Output of the recovered digital data signal (note 1). TACTRL 11 9 Transmitter audio control output. This open-drain output is used to blank the audio path and enable the data path to the modulator during data bursts on the RVC. Output level LOW means audio muted. CLKIN 12 10 1.2 MHz or 9.6 MHz external master clock input. This input signal should be accurate to 100 × 10−6 and have a worst case 60 : 40 mark-space ratio. CLKOUT 13 11 Output of 1.2 MHz clock signal (for APROC) derived from CLKIN. VSSD 14 12 Negative digital supply (0 V), internally connected to substrate. To be connected low-ohmic to VSSA. TXLINE 15 13 Open-drain bidirectional data line to the system controller (internal 100 kΩ pull-up). n.c. 16 14 Not connected. TXHOLD 17 15 This input holds off transmission of data when set to HIGH. TXCLK 18 16 Transmitted data clock input from the system controller. BUSY/VSAT 19 17 Output indicating the status of the RECC by providing output information based on a majority decision on the last 3 consecutive Busy/Idle bits (FVC = logic 0). Output level LOW means channel idle. Indicating the result of the comparison of the measured SAT and the expected SAT colour-code bits (I2C-bus register) in the voice channel mode (FVC = logic 1 and ENSM = logic 1). Output level LOW means incoming SAT not equal to expected SAT. 1997 Jan 28 4 Philips Semiconductors Product specification Data processor for cellular radio (DPROC2) UMA1002 PIN SYMBOL DESCRIPTION SO28 LQFP32 TXCTRL 20 19 Transmitter control open-drain output used to disable the transmitter during an RECC access failure. Output level LOW means RF disabled. INVTX 21 21 This input inverts the sense of transmitted data stream, which allows RF modulators with high or low local oscillators to be used. The AMPS and TACS specifications define NRZ encoded logic 1 as a LOW-to-HIGH transition in the centre of a data bit period. The polarity of the modulated data stream depends on the transmitter local oscillator. Input LOW means data inverted. TSCAN 22 22 Test switch input, only enabled if TST = logic 1, but should have a defined state. A0 23 23 Input to select the least significant bit of the I2C-bus address. SDA 24 24 Serial data input/output (I2C-bus). SCL 25 25 Serial clock input (I2C-bus). n.c. 26 18 Not connected. RXCLK 27 26 Received data clock input from the system controller. VDDD 28 27 Digital supply voltage (+3 V). VDDA − 28 Analog supply voltage (+3 V). MVO − 3 Majority voting output indicating that on FOCC the first 3 received words do not differ from each other and thus the majority decision over 5 words can already be carried out. Because of the required speed, indication is at this pin (and not via the I2C-bus) which can be monitored by the system controller. Output LOW means the receiver can be switched off. JTACS − 6 Digital input signal for JTACS, input HIGH means that data is routed from TXLINE directly without processing to gated D/A converter (if enabled by STEN bit). CLKSEL − 20 Input switch for internal divide-by-8 or divide-by-1 divider between CLKIN and CLKOUT (internal pull-down → divide-by-1 is default if not bonded out in SO28 package). Note 1. Must not be connected in existing applications. 1997 Jan 28 5 Philips Semiconductors Product specification Data processor for cellular radio (DPROC2) UMA1002 handbook, halfpage V SSA 1 28 VDDD AGND 2 27 RXCLK DEMODD 3 26 n.c. DATA 4 25 SCL RACTRL 5 24 SDA RESET 6 23 A0 INVRX 7 22 TSCAN UMA1002T RXLINE 8 21 INVTX TST 9 20 TXCTRL RECDATA 10 19 BUSY/VSAT TACTRL 11 18 TXCLK CLKIN 12 17 TXHOLD CLKOUT 13 16 n.c. V SSD 14 15 TXLINE MBD828 25 SCL 26 RXCLK 27 VDDD 28 VDDA 29 VSSA 30 AGND 32 DATA handbook, full pagewidth 31 DEMODD Fig.2 Pin configuration for SO28, SOT136-1. RACTRL 1 24 SDA RESET 2 23 A0 MVO 3 22 TSCAN INVRX 4 RXLINE 5 JTACS 6 19 TXCTRL TST 7 18 n.c. RECDATA 8 17 BUSY/VSAT 21 INVTX TXCLK 16 20 CLKSEL TXHOLD 15 n.c. 14 12 VSSD TXLINE 13 11 CLKOUT 9 TACTRL CLKIN 10 UMA1002H MBD829 Fig.3 Pin configuration for LQFP32, SOT358-1. 1997 Jan 28 6 Philips Semiconductors Product specification Data processor for cellular radio (DPROC2) UMA1002 The DPROC2 is a member of our Cellular Radio chip set, based on the I2C-bus, which meets these requirements. A cellular radio system schematic using the chip set is shown in Fig.11. FUNCTIONAL DESCRIPTION General The UMA1002 (DPROC2) is a single-chip CMOS device which handles the data and supervisory functions of an AMPS or TACS subscriber set. DPROC2 power-saving features To support current saving in the application, DPROC2 has three different modes of circuit operation implemented. They are decoded by the I2C-bus register bit FVC and by activity on the data transfer link (TXCLK and TXLINE). In power-down mode the relevant digital circuits have the clock disabled, the analog circuits have the bias currents and the switched capacitor clock switched off. These functions are: • Data reception and transmission • Control and voice channel exchanges • Error detection, correction, decoding and encoding • Supervisory Audio Tone decoding and transponding • Signalling Tone generation. • Normal mode: all circuit parts are operating (e.g. on Voice channels) In an AMPS or TACS cellular telephone system, mobile stations communicate with a base over full duplex RF channels. A call is initially set up using one out of a number of dedicated control channels. This establishes a duplex voice connection using a pair of voice channels. Any further transmission of control data occurs on these voice channels by briefly blanking the audio and simultaneously transmitting the data. The data burst is brief and barely noticeable by the user. A data rate of 10 kbits/s is used in the AMPS system and 8 kbits/s in TACS. The signalling formats for both Forward Channels (base to mobile) and Reverse Channels (mobile to base) are shown in Fig.14. • Power-down mode 1: the SAT path is in power-down (e.g. during access of the RECC) • Power-down mode 2: the SAT path and the total data transmit path are in power-down (e.g. for Idle state, DPROC2 operating only on FOCC). System power-saving features Besides the above mentioned power-down modes DPROC2 also includes features to reduce system current (e.g. switching off parts of the receiver, and put the system controller into Idle mode for longer periods of time). All these features are controlled by the I2C-bus. For further explanation of the following features refer to the Section “I2C-bus serial data link (SDA; SCL)” sub-section “I2C-bus registers”. A function known as Supervisory Audio Tone (SAT), a set of 3 audio tones (5970, 6000 and 6030 Hz), is used to indicate the presence of the mobile on the designated voice channel. This signal, which is analogous to the On-Hook signal on land lines, is sent out to the mobile by the base station on the Forward Voice Channel. The signal must be accurately recovered and transponded back to the base station to complete the ‘loop’. At the base station this signal is used to ascertain the overall quality of the communication link. MAJORITY VOTING (ONLY IN LQFP32) Majority voting includes more intelligence. This feature is enabled in FOCC with I2C-bus bit MAJ = logic 1. If 3 consecutive identical words have been received it is signalled via pin MVO. Therefore during the last 2 frame words the receiver could be switched off to save system current consumption. Another voice channel associated signal is Signalling Tone (ST). This tone (8 kHz TACS, 10 kHz AMPS) is generated by the mobile and is sent in conjunction with SAT on the Reverse Voice Channel to serve as an acknowledgement signal to a number of system orders. CONTROL FILLER WORDS FILTER System current can be further reduced by an on-chip control filler words filter in FOCC, which enables the detection of consecutive identical control filler words. If consecutive control filler words are identical (i.e. DCC, CMAC and WFOM) they will not be passed on to the microcontroller. Consequently the system controller can remain in power-saving mode. The key requirements of a hand-held portable cellular set are: • Small physical size • Minimum number of interconnections (serial bus) • Low power consumption • Low cost. 1997 Jan 28 7 Philips Semiconductors Product specification Data processor for cellular radio (DPROC2) UMA1002 PROGRAMMING OF ESCC BITS Power-up state and master reset (RESET) There is a possibility to program the expected ESCC bits, so that DPROC2 can compare expected and received SAT and signal any inconsistency to the system controller via BUSY/VSAT pin. Consequently there is no need to read the measured SAT periodically via the I2C-bus. RESET should be HIGH as soon as power supply is available. DPROC2 will not respond reliably to any inputs (including RESET) until 100 µs after the power supply has settled within the specified tolerance. The analog sections of the device will have stabilized within 5 ms. No on-chip power-on reset is provided, therefore before the device can enter normal operation RESET must be held HIGH. BCH ERROR FILTER If this feature is enabled, DPROC2 will not pass on to the microcontroller words with BCH errors. Consequently the microcontroller can remain in power-saving mode. This feature in combination with the control filler feature is defined in Table 8. RESET is an active HIGH master reset input, with a minimum active pulse width of 4 µs which may be used to reset the total logic within DPROC2 to a predefined state as illustrated in Tables 1 and 2. It is preferably only used during power-up, during normal operation it is recommended to use the fully synchronous reset signals derived from the I2C-bus bits FVC, STS and TXRST (see Table 4). To ensure correct operation TXCLK must be held HIGH during RESET operation. SELECTABLE CLOCK DIVIDER (ONLY IN LQFP32) An on-chip selectable divide-by-8 clock divider reduces external peripheral component count. Table 1 Predefined state of the digital output pins OUTPUT STATE RXLINE HIGH TXCTRL high-impedance (HIGH) TACTRL high-impedance (HIGH) RACTRL high-impedance (HIGH) BUSY/VSAT HIGH TXLINE HIGH (by 100 kΩ internal pull-up resistor) RECDATA LOW MVO HIGH SDA high-impedance (HIGH) Table 2 Predefined state of the I2C-bus registers BIT REGISTER 7 6 5 4 Status (read) LOW LOW LOW HIGH Control 1 (write) LOW LOW LOW LOW Control 2 (write) LOW LOW LOW LOW LOW 1997 Jan 28 8 3 2 1 0 LOW LOW HIGH HIGH LOW LOW LOW LOW LOW LOW LOW Philips Semiconductors Product specification Data processor for cellular radio (DPROC2) UMA1002 I2C-bus serial data link (SDA; SCL) I2C-BUS REGISTERS SDA is the bidirectional data line, SCL is the clock input from an I2C-bus master. These constitute a typical I2C link and conform to standard I2C-bus characteristics. A detailed description of the I2C-bus specification, with applications, is given in the brochure “The I2C-bus and how to use it”. This brochure may be ordered using the code 9398 393 40011. The I2C-bus register block resides internally within the I2C-bus interface block and contains various items of status and control information which are transferred to and from DPROC2 via the I2C-bus. The block is organized into three 8-bit registers: • Status register which contains read only items • Control registers 1 and 2 which contain write only items. • Data rate up to 100 kbits/s. SLAVE ADDRESS SELECT (A0) Selection of the device slave address is achieved by connecting A0 to either VSS or VDDD. The slave address is defined in accordance with the I2C-bus specifications as shown in Fig.4. handbook, halfpage 1 1 0 1 1 X (1) A0 R/W MBD831 (1) X = don’t care. Fig.4 Device slave address. Table 3 I2C-bus register map BIT REGISTER 7 6 4 3 2 1 0 Status (read) − Control 1 (write) BUFEN SERV STS TXRST ABREN FVC STEN SATEN Control 2 (write) MAJ MR1 MR0 DBCH DCFM ENSM ESCC1 ESCC0 1997 Jan 28 − 5 WSYNC BUSY 9 TXABRT TXIP MSCC1 MSCC0 Philips Semiconductors Product specification Data processor for cellular radio (DPROC2) handbook, full pagewidth S UMA1002 DPROC ADR R A STATUS P CONTROL 1 A (a) S DPROC ADR W A P (b) S DPROC ADR W A CONTROL 1 A CONTROL 2 A P MBD832 (c) (a) Read from DPROC2 status register. (b) Write to DPROC2 control register 1. (c) Write to all DPROC2 control registers. Where: S = START condition W = read/write bit (logic 0 = write) R = read/write bit (logic 1 = read) A = acknowledge bit P = STOP condition DPROC ADR = slave address of DPROC2. Fig.5 I2C-bus data format. 1997 Jan 28 10 Philips Semiconductors Product specification Data processor for cellular radio (DPROC2) Table 4 UMA1002 Description of I2C-bus register map REGISTER BITS LOGIC LEVEL DESCRIPTION Control Register 1 BUFEN SERV STS(1) 0 1.2 MHz signal not available at pin CLKOUT 1 1.2 MHz signal is available at pin CLKOUT 0 serving system data stream B selected 1 serving system data stream A selected 0 TACS selected 1 AMPS selected TXRST 1 terminates a message being transmitted on the reverse channel; monostable signal causing a reset of the message transmission circuitry and resets the I2C-bus bits TXABRT, TXIP and clears the transmit buffer ABREN 1 DPROC2 has permission to abort data transmission and disable RF on the RECC following the detection of a channel access attempt collision 0 no permission for above operations FVC(2) 0 control channel format selected 1 voice channel format selected 0 disables output of signalling tone to pin DATA 1 enables output of signalling tone to pin DATA if FVC = logic 1 0 disables output of SAT transponded signal to pin DATA 1 enables output of SAT transponded signal to pin DATA if FVC = logic 1 0 majority voting procedure on FOCC using all 5 frame words, MVO output is always HIGH 1 majority voting procedure on FOCC using the first 3 frame words, if they are all identical the MVO pin goes LOW (see Fig.6) STEN SATEN Control Register 2 MAJ MR0, MR1 see Table 5 determines set-up time of MVO signal with respect to beginning of the next dotting (see Fig.6) DBCH see Table 8 BCH error filter DCFM see Table 8 ENSM 0 enable SAT monitoring; ESCC bits are not used 1 enable SAT monitoring; ESCC bits are used for following function ESCC0, ESCC1 see Table 6 control filler message filter expected SAT colour code bits; the incoming SAT is compared to these bits, the result (expected or not expected SAT frequency) is given out by the BUSY/VSAT pin (when FVC = logic 1), which prevents periodical reading from the I2C-bus status register Status Register WSYNC 1997 Jan 28 0 DPROC2 has not acquired frame synchronization in accordance with FOCC format 1 DPROC2 has acquired frame synchronization in accordance with FOCC format 11 Philips Semiconductors Product specification Data processor for cellular radio (DPROC2) REGISTER BITS UMA1002 LOGIC LEVEL BUSY DESCRIPTION indicates the status of RECC, determined by a majority decision on the result of the last 3 consecutive Busy/Idle bits of the FOCC and is also routed to pin BUSY/VSAT 0 channel idle 1 channel busy indicates the result of the comparison of the incoming SAT and the stored SAT Colour Code bits in the Voice Channel mode and is also routed to pin BUSY/VSAT 0 incoming SAT not equal to expected SAT 1 incoming SAT equal to expected SAT TXABRT indicates that a RECC access attempt has been aborted without successful message transmission TXIP MSCC1, MSCC0 0 no access collision detected 1 transmission attempt aborted 0 no transmission on RECC or RVC in progress 1 data transmission by DPROC2 on RECC or RVC in progress see Table 7 provides information about the current measured SAT colour code Notes 1. Changing this register bit resets internally the receive and transmit logic circuitry. 2. Changing this register bit resets internally the receive logic circuitry. Table 5 Set-up time of MVO signal MR0 Table 6 MR1 Table 7 tMVO (ms) 0 0 3 0 1 6 1 0 9 1 1 12 Expected SAT colour code ESCC1 ESCC0 SAT FREQUENCY (Hz) 0 0 5970 0 1 6000 1 0 6030 1 1 no valid SAT 1997 Jan 28 Measured SAT colour code 12 MSCC1 MSCC0 SAT FREQUENCY (Hz) 0 0 5970 0 1 6000 1 0 6030 1 1 no valid SAT Philips Semiconductors Product specification Data processor for cellular radio (DPROC2) Table 8 UMA1002 Conditions for transmission of received words to system controller DBCH DCFM BCH ERROR BIT CHANGE IN CONTROL FILLER WORD DETECTED TRANSMISSION OF CONTROL FILLER WORD TO SYSTEM CONTROLLER 0 0 X X yes 0 1 0 0 no 0 1 0 1 yes 0 1 1 X yes 1 0 0 X yes 1 0 1 X no 1 1 0 0 no 1 1 0 1 yes 1 1 1 X no handbook, full pagewidth REPEAT 1 REPEAT 2 REPEAT 2 REPEAT 3 REPEAT 3 BIT WORD REPEAT 1 SYNC SYNC OF WORD A OF WORD B OF WORD A OF WORD B OF WORD A OF WORD B REPEAT 5 BIT OF WORD B SYNC MVO t MVO Fig.6 Timing of MVO output. 1997 Jan 28 13 MLC095 Philips Semiconductors Product specification Data processor for cellular radio (DPROC2) UMA1002 Digital circuit blocks SAT DETERMINATION GENERAL The SAT Determination Block indicates which, if any, of the valid SAT tones is detected from the recovered SAT. The AMPS and TACS specifications require that a determination is made at least every 250 ms. Determination involves counting the number of cycles of the regenerated SAT in this time period. This count is then compared to a set of four known counts which define the boundaries between the SAT frequencies and SAT-not-valid events. The result is then coded into the I2C status registers MSCC0 and MSCC1. The majority of the digital circuitry within the DPROC2 device is identical for both AMPS and TACS. The interconnections of the digital blocks discussed below are shown in Fig.1. DATA RECOVERY The Data Recovery Block receives wideband Manchester encoded data in sampled and sliced form from the Comparator Block, on which it performs the following functions: SAT REGENERATION • Clock recovery The SAT Regeneration Block generates a digital SAT stream for transponding back to the base station. The transponded SAT is phase-locked to the recovered SAT by means of a second digital phase-locked-loop. To minimize the total harmonic distortion of the output signal the transponded SAT is then processed by a delta modulator before being passed on to the Gated Digital-to-Analog (D/A) converter. • Manchester decoding • Data regeneration. The Clock Recovery Block extracts an 8 or 10 kHz (TACS or AMPS) phase-locked clock signal from the Manchester encoded data stream. This is implemented using a digital-phase-locked-loop (PLL) which has an adjustable ‘bandwidth’ to provide both fast acquisition and low jitter. DOTTING DETECTOR Manchester decoding is performed by exclusive ORing the recovered Manchester encoded data with the recovered clock. The Dotting Detector Block determines whether a data inversion (dotting) pattern has been received on the Forward Voice Channel. The detection of data inversion indicates that the Clock Recovery Block has acquired bit synchronization and that the narrow bandwidth mode on the clock recovery phase-locked-loop is selected. This signal is also used to indicate that a data burst is expected and activates the audio mute RACTRL, after a Word Synchronization Block has been received, for the duration of the burst. The NRZ data regeneration is performed by a digital integrate and dump circuit. This consists of an up/down counter that counts 1.2 MHz cycles during the data period. The sense of the count is determined by the result of the Manchester Decoder output. The number of counts is sampled at the end of a data period. If this number exceeds a threshold the data is latched as a logic 1 otherwise it is latched as a logic 0. SAT RECOVERY The SAT Recovery Block receives a filtered and sliced SAT signal which must be recovered before being routed to the Determination and Regeneration Blocks. The recovery is performed using a digital phase-locked loop. 1997 Jan 28 14 Philips Semiconductors Product specification Data processor for cellular radio (DPROC2) UMA1002 WORD SYNCHRONIZATION DETECTOR MAJORITY VOTING BLOCK The Word Synchronization Block performs the following functions: The Majority Voting Block performs the following functions: • Frame Synchronization • Identifying position and validity of frames in the received data stream • Reverse Control Channel status (B/I determination) • Extracting five repeats of each word from a valid frame • Valid Serving System determination. • Performing a bit-wise majority decision on the five repeats of the data word. These functions are associated solely with the Forward Control Channel and have no meaning on the Forward Voice Channel. The validity of the frames is determined by setting a counter in operation which times out and resets the circuitry after 920 or 463 bit periods from detecting valid word synchronization. The time out period selected depends on whether DPROC2 is monitoring the Forward Voice or Control Channel respectively. Information in a data stream is identified by its position with respect to a unique synchronization word. This synchronization word is an 11-bit Barker code which has a low probability of simulation in an error environment, and can be easily detected. Data received is only considered valid at times when DPROC2 has achieved frame synchronization. Up to five repeats of the message word are searched for and extracted by DPROC2. On the Forward Voice Channel the extraction of a data word for majority voting is described in the Section “Word Synchronization Detector”. In this condition the block leaves its search mode and enters its lock mode. This is indicated by bit WSYNC being set HIGH. In order to achieve this two consecutive synchronization words separated by 463 bits must be detected. Once in lock mode, the synchronization word detector is examined every 463 bits and only loses frame synchronization after 5 consecutive unsuccessful attempts at detecting the synchronization word have been made. At this point bit WSYNC is cleared and the device is returned to its search mode. DPROC2 enables two mechanisms for Majority Voting. The first is based on 5 words and is described above. The other mechanism is based on 3 consecutive identical words and thus enabling switch-off of parts of the receiver during reception of the remaining two words (see Table 5 and Fig.6). ERROR CORRECTION BLOCK The Error Correction Block performs: Information detailing the status of the Reverse Control Channel is given by the Busy/Idle bits. These occur at intervals of 11 bits within the frame, the first occurring immediately following the synchronization word. The status of the channel is determined by a majority decision on the last three consecutive Busy/Idle bits. • Extraction of a valid message from the Majority-Voted Word • Computation of the S1 and S3 syndromes • Correction of up to one error in the word • Communication of received data to the System Controller via the Received Data Serial Link. FVC: After detection of 2 consecutive sync words the circuit leaves its Search Mode and enters the Lock Mode. The data word in between is considered as valid and already stored for Majority Voting. Whenever a sync word was found the incoming data stream is examined 88 bits later for sync again. Whenever a valid sync word is detected the following data word is given to the Majority Voting block. After missing two consecutive sync words the circuit goes back to the search mode (scanning for sync every bit). If a sync word is then detected again, the following data word is immediately accepted (and not only after two correctly timed sync words). The detection process of sync words is independent of the detection of dotting. The audio mute via pin RACTRL is activated either by receiving a sync word after detection of a dotting sequence or by entering Lock Mode. 1997 Jan 28 Interpretation of parity of a received word is obtained from knowledge of the syndromes of the word. The syndromes are calculated using feedback shift registers with two characteristic polynomials: 1 + x + x6 and 1 + x + x2 + x4 + x6 Once the syndromes of a received word are known, it is possible to determine if a correctable error is present. DPROC2 only corrects up to one error although the code used has a Hamming distance of five. The occurrence of two or more errors is signalled by setting the BCH error flag, which is communicated to the System Controller via the Received Data Serial Link. 15 Philips Semiconductors Product specification Data processor for cellular radio (DPROC2) UMA1002 RECEIVED DATA SERIAL LINK Data format The Received Data Serial Link transfers data and control information from DPROC2 to the System Controller. The data is transferred on RXLINE under control of a clock signal RXCLK, generated by the System Controller. The system controller is informed of the arrival of a decoded data word in the DPROC2 output register by RXLINE being driven LOW. If the system controller chooses to ignore the received data or only partially clock the data out, the DPROC2 will reset the receive buffer for the next word after the period RWIN (see Fig.8). Each Transmit Data word consists of 5 bytes. The word format is shown in Fig.7(b). The sense and function of the fields is shown in Table 10. Link protocol Messages are normally up to 5 words in length on the Reverse Control Channel and up to 2 words in length on the Reverse Voice Channel. However, DPROC2 will transmit messages of any word length. These must be transmitted on the data stream without interruption. To avoid the need for large buffer areas, a flexible protocol is used to allow DPROC2 to control the transfer of data words. DPROC2 has an on-chip buffer which can hold one complete word of a message. While new words are being loaded into DPROC2, within the time period Buffer clear to end of TWIN, DPROC2 will maintain uninterrupted data transmission. The System Controller can abort the transmission of a message at any point activating the I2C-bus signal TXRST. This signal causes the interface to return to its power-up state and resets TXIP and TXABRT (see Table 4). On completion of these tasks TXRST will return to its inactive state. The Transmit Data Protocol is described by the timing diagram shown in Fig.8(b) and has the following parameters: Data format Each Received Data word consists of 4 bytes. The word format is shown in Fig.7(a). The sense and function of the fields is shown in Table 9. Link protocol The Received Data protocol is described by the timing diagram Fig.8(a) and has the following parameters: • Maximum receive window (RWIN) – Control Channel (TACS) = 47 ms; MAJ = 0 – Control Channel (TACS) = 30.5 ms; MAJ = 1 (in FOCC only) • Maximum transmit window (TWIN) – Control Channel (AMPS) = 37 ms; MAJ = 0 – voice channel (TACS) = 60 ms – Control Channel (AMPS) = 23.8 ms; MAJ = 1 (in FOCC only) – voice channel (AMPS) = 48 ms • Minimum clock period (tCLKmin) = 2 µs – control channel (TACS) = 29 ms • Minimum clock hold-off (tWAIT) = 2 µs. – control channel (AMPS) = 23 ms • Minimum clock period (tCLKmin) = 2 µs TRANSMIT DATA SERIAL INTERFACE • Minimum wait period (tWAIT) = 2 µs. The Transmit Data Serial Link performs reception of data from the System Controller to DPROC2 over a dedicated line TXLINE. The transfer of data is synchronous with a clock signal TXCLK, generated by the System Controller. 1997 Jan 28 Note that TXRST will clear the transmit buffer. 16 Philips Semiconductors Product specification Data processor for cellular radio (DPROC2) Table 9 UMA1002 Received data word BIT TITLE SENSE FUNCTION 31 start LOW identifies start of word 30 BCH error active HIGH indicates that an uncorrected BCH error is associated with the word 29 to 2 received data binary data received data word 1 RXLINE error active HIGH indicates that a transmission error has occurred on the microprocessor to DPROC2 serial link 0 stop HIGH identifies end of the word Table 10 Transmit data word BIT TITLE SENSE FUNCTION 39 start LOW identifies start of word 38 and 37 DCC binary data digital colour code (see Table 11) 36 to 1 transmit data binary data transmit data word 0 stop HIGH identifies end of the word MSB handbook, full pagewidth START Bit 31 LSB BCH ERROR Bit 30 RECEIVED WORD (28 bits) Bit 29 CHECK BIT (= 0) Bit 2 Bit 1 STOP Bit 0 (a) MSB START Bit 39 LSB DCC 1 Bit 38 DCC 0 Bit 37 TRANSMIT WORD (36 bits) Bit 36 STOP Bit 1 Bit 0 MBC768 (b) (a) Received data word. (b) Transmit data word. Fig.7 Data word formats. 1997 Jan 28 17 Philips Semiconductors Product specification Data processor for cellular radio (DPROC2) UMA1002 RWIN handbook, full pagewidth bit 31 bit 30 bit 29 bit 2 bit 1 bit 0 RXLINE RXCLK t WAIT t CLK (min) DPROC holds TXLINE LOW during encoder stage (a) bit 39 bit 38 bit 1 bit 0 buffer clear (2) TXLINE th buffer busy (1) t su t WAIT TXCLK TWIN MBC769 (b) (1) The buffer time depends on whether the first or subsequent words are being loaded. (2) The system controller should monitor the TXLINE during bit 0, if the status of TXLINE does not change from a HIGH-to-LOW on the rising edge of TXCLK, then a framing error has occurred. This can be caused by glitches on the clock line or if an arbitration error occurred while the DPROC2 transmit register was being loaded. The system controller should recover the situation by holding TXLINE HIGH and supplying clocks on TXCLK until TXLINE goes LOW. Then the situation should be treated as a normal channel arbitration failure as described in Section “Reverse Control Channel Access Arbitration” - “Abort procedure (see Fig.10)”. (a) DPROC2 to microcontroller link; receive data timing. (b) Microcontroller to DPROC2 link; transmit data timing. Where: th > 100 ns tsu > 500 ns. Fig.8 Data timing diagrams. 1997 Jan 28 18 Philips Semiconductors Product specification Data processor for cellular radio (DPROC2) UMA1002 BCH AND MANCHESTER ENCODING BLOCK REVERSE CONTROL CHANNEL ACCESS ARBITRATION The functions performed by this circuit block include: The AMPS and TACS specifications require a method of arbitration on the Reverse Control Channel to prevent two mobiles from transmitting on the same channel at the same time. This function is performed by DPROC2 monitoring the Busy/Idle stream sent on the Forward Control Channel. • Reception of data from the System Controller • Parity generation • Message construction • Manchester encoding. The AMPS and TACS specifications state that once the mobile has commenced transmitting on the Reverse Control Channel it must monitor the Busy/Idle stream. If this stream becomes active outside a predetermined ‘window’, measured from the start of the transmission of the message, the mobile must terminate its transmission and disable the transmitter immediately. Each 36-bit Information Word sent on the Reverse Voice and Control Channels is coded into a 48-bit code word. The code word consists of the 36-bit word followed by 12 parity bits. These parity bits are formed by clocking the information word into a 12-bit feedback shift register with characteristic polynomial: 1 + x3 + x4 + x5 + x8 + x10 + x12 In the Cellular Radio chip-set there are two levels of control of the RF transmitter; the first is absolute control by the System Controller, the second is conditional by other devices in the set. In DPROC2 the conditional control of the transmitter is performed via the output TXCTRL. This line is effectively wired ORed together, using open-drain outputs, with other devices which may wish to control the transmitter. When these devices do not wish to disable the transmitter their output is in a HIGH impedance state. The BCH Encoder Block constructs the Reverse Voice and Control Channel data streams from the information it receives from the System Controller. The streams are formed out of the four possible field types: • Dotting (data inversions) • 11-bit Synchronization Word • Digital Colour Code (see Table 11) • 48-bit code word. An exception to this procedure occurs when the Serving System instructs the mobile not to monitor the Busy/Idle bits. In this event the arbitration logic can be disabled by clearing I2C-bus register bit ABREN. The 2 bits of DCC received from the System Controller are coded into a 7-bit word as shown in Table 11. The data sense for Manchester Encoding has a NRZ logic 1 encoded as a 0-to-1 transition and a NRZ logic 0 encoded as a 1-to-0 transition. The flow of events during a Control Channel Access attempt is as follows: Initial state • Transmitter disabled • DPROC2 transmit circuitry in power-up state • TXCTRL line HIGH. Table 11 Digital colour code; 7-bit word DCC1 DCC0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1 1 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1997 Jan 28 CODED DCC 19 Philips Semiconductors Product specification Data processor for cellular radio (DPROC2) UMA1002 Access attempt procedure 1. System Controller decides to send Abort procedure (see Fig.10) message(1). 1. DPROC2 immediately disables transmitter output by driving TXCTRL LOW. 2. System Controller drives TXCTRL LOW directly. 3. System Controller switches transmitter power-on and waits for power-up for the transmitter module (RF transmitter is still disabled by TXCTRL). 2. DPROC2 sets TXABRT. 4. System Controller sets TXRST via I2C-bus to DPROC2. 4. System Controller disables transmitter via RF power amplifier. 5. System Controller sets ABREN via I2C (if required) allowing DPROC2 to control the transmitter. 5. System Controller sends TXRST to prepare DPROC2 for next transmission. 6. System Controller determines status of Reverse Control Channel by monitoring the Busy/Idle bit. If busy, waits a random time then tries again. SIGNAL TONE GENERATION (ST) 3. System Controller detects failure by monitoring TXCTRL and TXABRT. The 8 or 10 kHz (TACS or AMPS) tone generated from the Manchester Encoding Block is used as the Signalling Tone stream. 7. System Controller releases TXCTRL allowing it to be pulled HIGH enabling the transmitter output. 8. System Controller transfers the first word of the message to DPROC2 via serial link(1). 9. DPROC2 sets I2C-bus signal TXIP and starts sending message while monitoring Busy/Idle status. 10. If channel becomes busy before 56 bits and ABREN is set then perform Abort Procedure. 11. If channel remains idle after 104 bits and ABREN is set then perform Abort Procedure. 12. System controller loads the subsequent words of the message into DPROC2 when the buffer becomes clear as shown in Fig.8(b). 13. On completion of entire message DPROC2 clears TXIP and 25 ms later the System Controller disables transmitter via I2C-bus. 14. System Controller finally sends TXRST to prepare DPROC2 for next transmission. (1) At stage 1 the system controller may choose to preload DPROC2 with the first word of the message and hold it from transmission until stage 7 using the TXHOLD line. This gives a lower time overhead between detecting an IDLE channel and commencing the transmission. To use this feature TXHOLD must be driven HIGH before the last bit of data has been transferred into DPROC2. Figure 9 illustrates the DPROC2 data transmission timing. 1997 Jan 28 20 Philips Semiconductors Product specification Data processor for cellular radio (DPROC2) DPROC2 holds LOW TXLINE handbook, full pagewidth UMA1002 DPROC2 releases TXLINE DPROC holds LOW TXLINE word 1 word 2 TXLINE TXHOLD DPROC2 data dotting 30 DPROC2 releases TXLINE W.S. DCC 11 7 word 1 Parity repeat1 12 36 word 1 repeat 2 36 Parity 12 DPROC2 holds LOW TXLINE word 3 word 1 repeat 5 36 Parity 12 word 4 TXLINE continued TXHOLD continued DPROC2 data continued Parity 12 word 2 repeat 1 36 Parity word n repeat 1 36 Parity 12 word 2 repeat 2 36 Parity word n repeat 2 36 Parity word 2 Parity repeat 5 12 36 12 word 3 repeat 1 36 Parity 12 TXLINE continued TXHOLD continued DPROC2 data continued Parity 12 12 word n repeat 5 36 12 Parity 12 Fig.9 DPROC2 data transmission timing/microcontroller interface. 1997 Jan 28 21 MEA173 Philips Semiconductors Product specification Data processor for cellular radio (DPROC2) handbook, full pagewidth DPROC2 holds LOW TXLINE UMA1002 DPROC2 releases TXLINE DPROC2 holds LOW TXLINE word 1 arbitration failure Busy/Idle stream remains Idle after 104 bits word 2 I 2 C-bus send TXRST to DPROC2 DPROC2 ready for new transmisson TXLINE TXHOLD DPROC2 data dotting 30 BUSY W.S. DCC 11 7 word 1 Parity word 1 repeat 2 repeat1 12 truncated 36 104 bits has to be controlled by system controller TXCTRL I 2 C-bus TXIP TXABRT MEA172 Fig.10 DPROC data transmission timing/microcontroller interface during arbitration failure. 1997 Jan 28 22 Philips Semiconductors Product specification Data processor for cellular radio (DPROC2) UMA1002 would otherwise cause unacceptable isochronous distortion in the recovered signal. Analog circuit blocks GENERAL COMPARATORS The analog signal processing functions on DPROC2 are implemented using switched-capacitor techniques. The main filtering functions are operated at 300 kHz, and these circuits are ‘interfaced’ to the continuous time and sampled digital domains by RC active filters, passive interpolators and comparators. The Comparators form the analog-to-digital interface for the received data and SAT signals from the DEMODD pin. These comparators act as limiting amplifiers which convert the filtered sampled analog signals into 2-state sampled digital signals containing only the zero-crossing information from the analog signal. To prevent unwanted signals being processed by the digital circuitry both comparators have a hysteresis implemented The RC sections, the Anti-Alias Filter and the Clock Filter, are non-critical and are designed to tolerate process spreads. The critical filtering in the SAT Filter and the Output Filter, is performed by 300 kHz switched-capacitor circuitry. The Passive Interpolator increases the sampling rate from 300 kHz to 1.2 MHz. The sampled analog signals from the Passive Interpolator is converted to a sampled 2-state digital signal by a Comparator. The Gated D/A converter blocks and Analog Summer block together perform resynchronization and sub-sampling of the digitally generated DPROC2 output signals, and conversion to the sampled analog domain. GATED D/A CONVERTERS AND ANALOG SUMMER The Gated D/A converters and Analog Summer form the interface between the digital and analog circuitry on the transmit path of DPROC2. It is at this point that the three sampled digital signals, containing SAT, ST and encoded digital data, are combined to form a composite signal. The data streams are enabled by the I2C signals STEN, SATEN and the internal signal DATAEN respectively (DATAEN disables SAT and ST when data is being transmitted). The digital-to-analog conversion and sub-sampling operation is performed by the Gated D/A converters and Analog Summer. The typical relative signal weights applied in the summer (with respect to the data path) are shown in Table 12. These analog sections of the device are shown in Fig.1. BIAS GENERATOR The Bias Generator generates the analog ground reference voltage (AGND) used internally within the DPROC2 device. To minimize noise AGND must be externally decoupled to VSSA as shown in Fig.12. It also contains a current reference to generate all bias currents for the analog circuits. Table 12 Typical relative signal weight SIGNAL ANTI-ALIASING FILTER The Anti-Aliasing Filter is placed before the SAT filter block to prevent any unwanted signals or high-frequency noise present on the DEMODD pin being aliased into the pass-band by the sampling action of the switched-capacitor filter. To achieve this the Anti-Aliasing Filter is a time-continuous RC-active low-pass filter. ST or DATA 1.0 SAT 0.25 OUTPUT FILTER The Output Filter is a switched-capacitor filter which performs band-limiting of the DPROC2 output signals in accordance with the AMPS and TACS specifications. The required below band roll-off is achieved via external AC-coupling from the DATA pin. SAT INPUT FILTER The SAT Input Filter is a switched-capacitor filter which provides band-pass filtering of the SAT signals from the DEMODD pin to improve the SAT signal-to-noise ratio prior to recovery and transponding. CLOCK FILTER The Clock Noise Filter is a non-critical continuous time RC-active low-pass filter used to remove any switching transient residues from the output signal. It contains an output driver stage to provide a low output impedance and sufficient driving capability for the pin DATA. PASSIVE INTERPOLATOR The function of the Passive Interpolator is to increase the sampling rate at the output of the SAT filter. This reduces the coarseness of the zero-crossing information which 1997 Jan 28 RELATIVE OUTPUT LEVEL AMPS AND TACS 23 UMA1002 1.2 MHz P83CL580 PSD312L QUAD TANK VCO DATA TCXO 9.6 MHz keyboard scan bus UMA1015 Philips Semiconductors DEMOD NE606 Data processor for cellular radio (DPROC2) SECOND IF APPLICATION INFORMATION book, full pagewidth 1997 Jan 28 RSSI NE620 OR DISCRETE SOLUTION 3-wire control bus 24 1.2 MHz I2 C bus chip-on-glass LCD VCO PA BGY118A/B BGY115A/B NE5753 MOD POWER CONTROL POWER CONTROL NE5752 5V 5V DC-DC TDA7050 3V MBD830 Product specification UMA1002 Fig.11 Cellular radio system schematic for AMPS/TACS. I 2 C interface SDA RECDATA TST 10 28 SCL 24 25 19 8 9 27 10 nF demodulated data/audio RECEIVER SUBSYSTEM DEMODD 15 3 270 pF 100 kΩ 1.2 MHz OUTPUT AGND VSSA 2.2 µF 100 nF 25 INVTX INVRX n.c. CLKOUT CLKIN 1 DATA PROCESSOR UMA1002T 17 21 16 7 22 13 12 4 TXDIS 20 23 5 11 TXLINE TXCLK GENERAL PURPOSE I/O ports TXHOLD RESET AGND DATA n.c. TSCAN (+3 V) A0 VDDD (+3 V) + TX MUTE CLKIN + AUDIO PROCESSOR VOX line MBD833 Fig.12 DPROC2 baseband application circuit (SO28, SOT136-1). Product specification RX MUTE UMA1002 modulation MODOUT MICROCONTROLLER (PCB80C552) TXCTRL TACTRL RACTRL 10 nF TRANSMITTER SUBSYSTEM RXCLK 14 DATA DEMOD RXLINE 2 6 VSSD 1.2 MHz 18 BUSY/VSAT Philips Semiconductors 100 nF 10 µF Data processor for cellular radio (DPROC2) andbook, full pagewidth 1997 Jan 28 VDDD ( 3 V) I 2 C interface SDA RECDATA MVO TST 10 nF demodulated data/audio RECEIVER SUBSYSTEM 270 pF 27 8 28 24 SCL 25 17 3 5 7 26 31 13 DEMODD 100 kΩ 9.6 MHz OUTPUT AGND VSSA 2.2 µF 100 nF 26 INVTX INVRX CLKOUT CLKIN 9.6 MHz 30 15 DATA PROCESSOR UMA1002H 29 2 12 14,18 21 20 4 22 11 10 32 TXDIS 19 23 1 9 TXCLK GENERAL PURPOSE I/O ports TXHOLD RESET DATA AGND CLKSEL (+3 V) TSCAN (+3 V) A0 VDDD (+3 V) + + RX MUTE AUDIO PROCESSOR VOX Fig.13 DPROC2 baseband application circuit (LQFP32, SOT358-1). MGC630 Product specification handbook, full pagewidth n.c. UMA1002 line TXLINE TX MUTE CLKIN modulation MODOUT MICROCONTROLLER (PCB80C552) TXCTRL TACTRL RACTRL 10 nF TRANSMITTER SUBSYSTEM RXCLK 6 DATA DEMOD RXLINE JTACS VSSD 1.2 MHz 16 BUSY/VSAT Philips Semiconductors 100 nF 10 µF Data processor for cellular radio (DPROC2) 1997 Jan 28 VDDD (+3 V) VDDA (+3 V) BIT WORD REPEAT 1 SYNC SYNC OF WORD A 40 40 REPEAT 1 REPEAT 2 OF WORD B OF WORD A 40 40 REPEAT 4 OF WORD A REPEAT 5 REPEAT 4 REPEAT 5 OF WORD B OF WORD A OF WORD B Busy/Idle Bit 101 11 40 40 10 BIT SYNC (a) 40 BIT WORD REPEAT 1 SYNC SYNC OF WORD 37 11 40 BIT WORD REPEAT 2 SYNC SYNC OF WORD 37 11 BIT WORD SYNC SYNC 40 37 11 40 37 11 40 REPEAT 9 OF WORD BIT WORD REPEAT 10 BIT WORD REPEAT 11 SYNC SYNC OF WORD SYNC SYNC OF WORD (b) 30 11 7 27 BIT WORD CODED SYNC SYNC DCC 240 240 FIRST WORD REPEATED 5 TIMES SECOND WORD REPEATED 5 TIMES Philips Semiconductors 40 Data processor for cellular radio (DPROC2) 11 SIGNALLING FORMATS andbook, full pagewidth 1997 Jan 28 10 (c) 101 11 48 BIT WORD REPEAT 1 SYNC SYNC OF WORD 1 37 11 48 37 48 11 37 11 48 BIT WORD REPEAT 1 REPEAT 5 OF WORD 1 SYNC SYNC OF WORD 2 BIT BIT WORD REPEAT 2 WORD SYNC SYNC OF WORD 1 SYNC SYNC 37 11 BIT WORD SYNC SYNC 48 REPEAT 5 OF WORD 2 MBC770 (d) Product specification Fig.14 Signalling formats. UMA1002 (a) FOCC (Forward Control Channel). (b) FVC (Forward Voice Channel). (c) RECC (Reverse Control Channel). (d) RVC (Reverse Voice Channel). Philips Semiconductors Product specification Data processor for cellular radio (DPROC2) UMA1002 LIMITING VALUES In accordance with Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDD supply voltage −0.5 +6.5 V IDD supply current − 50 mA II DC input current (any input) − ±10 mA IO DC output current (any output) VI input voltages (all inputs) Ptot − ±10 mA −0.5 VDD + 0.5 V total power dissipation − 300 mW Po power dissipation per output − 10 mW Tamb operating ambient temperature −30 +70 °C Tstg storage temperature −65 +150 °C 1997 Jan 28 VDD(max) = 6 V 28 Philips Semiconductors Product specification Data processor for cellular radio (DPROC2) UMA1002 DC CHARACTERISTICS VDD = 3 V (VDDA and VDDD externally connected); Tamb = −30 to +70 °C; fCLKIN = 1.2 MHz (if CLKSEL = logic 0); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VDD supply voltage IDD operating supply current at pins VDDD and VDDA 2.7 3.0 5.5 V in FVC − 1.3 1.8 mA in FOCC − 0.4 − mA Digital inputs: INVRX, INVTX, CLKSEL, TXHOLD, TXCLK, A0, RESET, RXCLK, TST, TSCAN, CLKIN and JTACS VIL LOW level input voltage −0.3 − 0.3VDD V VIH HIGH level input voltage 0.7VDD − VDD + 0.3 V ILI LOW/HIGH level input leakage current − − 1 µA RpdCLKSEL CLKSEL internal pull-down resistance − 200 − kΩ RpdJTACS JTACS internal pull-down resistance − 200 − kΩ RpdTST TST internal pull-down resistance − 200 − kΩ pins without pull-down Digital push-pull outputs: RXLINE, BUSY/VSAT, RECDATA, MVO and CLKOUT VOL LOW level output voltage Isink = 1 mA − − 0.4 V VOH HIGH level output voltage Isource = −1 mA VDD − 0.4 − − V − − 0.4 V − − 0.4 V −0.3 − 0.3VDD V Open-drain n-channel outputs: TXCTRL, TACTRL and RACTRL VOL LOW level output voltage Isink = 2 mA Open-drain n-channel input/output: TXLINE VOL LOW level output voltage Isink = 2 mA VIL LOW level input voltage VIH HIGH level input voltage 0.7VDD − VDD + 0.3 V RpuTXLINE internal pull-up resistance − 100 − kΩ − − 100 kbits/s I2C-bus pins: SCL and SDA tdata data conversion rate Analog reference pin: AGND VAGND 1997 Jan 28 DC voltage level for VDD = 2.7 to 5.5 V − 29 0.5VDD − V Philips Semiconductors Product specification Data processor for cellular radio (DPROC2) UMA1002 AC CHARACTERISTICS VDD = 3 V (VDDA and VDDD externally connected); Tamb = −30 to +70 °C; fCLKIN = 1.2 MHz (if CLKSEL = logic 0); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Data rate of data transfer link: RXCLK, RXLINE, TXCLK, TXLINE tdata data conversion rate − − 500 kbit/s 5 − pF Clock input: CLKIN (CLKSEL = logic 0) Ci input capacitance − TCLKIN clock input period time 833.25 833.33 833.42 ns tCLKINH clock input HIGH time 40 50 60 %TCLKIN tr clock input rise time − 50 − ns tf clock input fall time − 50 − ns − 104.17 − ns Clock input: CLKIN (CLKSEL = logic 1) TCLKIN clock input period time tCLKINH clock input HIGH time 40 50 60 %TCLKIN tr clock input rise time − 5 − ns tf clock input fall time − 5 − ns − VAGND − V 1.14 1.2 1.26 V Analog output: DATA VDATA DC output voltage level Vo(p-p) output voltage level for signalling tone (peak-to-peak value) 1.9 2.0 2.1 V THD total harmonic distortion for Supervisory Audio Tone (SAT) − − 10 % RL allowed load resistance to AC ground 10 − − kΩ CL allowed load capacitance to AC ground − − 100 pF − VAGND − V 250 600 mV VDD = 3 V; note 1 VDD = 5 V; note 1 Analog input: DEMODD VDEMODD DC input voltage level 100 kΩ resistor external to AGND Vi(p-p) data input voltage level (peak-to-peak value) input via a 10 nF capacitor 200 Vi(p-p) SAT input voltage level (peak-to-peak value) 50 − − mV Zi input impedance 1 − − MΩ Note 1. Plus supply voltage variation (∆VDD), RL = 10 kΩ. 1997 Jan 28 30 Philips Semiconductors Product specification Data processor for cellular radio (DPROC2) UMA1002 PACKAGE OUTLINES SO28: plastic small outline package; 28 leads; body width 7.5 mm SOT136-1 D E A X c y HE v M A Z 15 28 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 14 e bp 0 detail X w M 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.30 0.10 2.45 2.25 0.25 0.49 0.36 0.32 0.23 18.1 17.7 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 inches 0.10 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.71 0.69 0.30 0.29 0.050 0.419 0.043 0.055 0.394 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 Z (1) θ 8o 0o Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT136-1 075E06 MS-013AE 1997 Jan 28 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-01-24 97-05-22 31 Philips Semiconductors Product specification Data processor for cellular radio (DPROC2) UMA1002 LQFP32: plastic low profile quad flat package; 32 leads; body 7 x 7 x 1.4 mm SOT358-1 c y X 24 A 17 25 16 ZE e E HE A A2 A 1 (A 3) wM θ bp Lp L pin 1 index 32 9 detail X 8 1 e ZD v M A wM bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.60 0.20 0.05 1.45 1.35 0.25 0.4 0.3 0.18 0.12 7.1 6.9 7.1 6.9 0.8 9.15 8.85 9.15 8.85 1.0 0.75 0.45 0.2 0.25 0.1 Z D (1) Z E (1) 0.9 0.5 0.9 0.5 θ o 7 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-12-19 97-08-04 SOT358 -1 1997 Jan 28 EUROPEAN PROJECTION 32 Philips Semiconductors Product specification Data processor for cellular radio (DPROC2) UMA1002 If wave soldering cannot be avoided, the following conditions must be observed: SOLDERING Introduction • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). SO Reflow soldering Wave soldering techniques can be used for all SO packages if the following conditions are observed: Reflow soldering techniques are suitable for all QFP and SO packages. • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our “Quality Reference Manual” (order code 9398 510 63011). • The longitudinal axis of the package footprint must be parallel to the solder flow. • The package footprint must incorporate solder thieves at the downstream end. METHOD (QFP AND SO) Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Wave soldering Repairing soldered joints QFP Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. 1997 Jan 28 33 Philips Semiconductors Product specification Data processor for cellular radio (DPROC2) UMA1002 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1997 Jan 28 34 Philips Semiconductors Product specification Data processor for cellular radio (DPROC2) UMA1002 NOTES 1997 Jan 28 35 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1997 SCA53 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 437027/00/04/pp36 Date of release: 1997 Jan 28 Document order number: 9397 750 01602