® AFE AFE1224 122 4 For most current data sheet and other product information, visit www.burr-brown.com 2Mbps, Single Pair ANALOG FRONT END FEATURES ● E1/T1 SINGLE PAIR 2B1Q ● SCALEABLE DATA RATE ● PROGRAMMABLE POWER DISSIPATION ● 28-LEAD SSOP ● PIN COMPATIBLE WITH AFE1124 ● COMPLETE ANALOG INTERFACE ● 64kbps TO 2320kbps OPERATION ● –40°C TO +85°C OPERATION DESCRIPTION Burr-Brown’s Analog Front End minimizes the size and cost of a single pair High bit rate Digital Subscriber Line (HDSL) system by providing all of the active analog circuitry needed to connect an HDSL digital signal processor to an external compromise hybrid and an HDSL line transformer. The transmit and receive filter responses automatically change with clock frequency, allowing the AFE1224 to operate over a wide range of data rates. The power dissipation of the device can be reduced under digital control for operation at lower speeds. The AFE1224 will operate at bit rates from 64kbps to 2.320Mbps. Functionally, this unit consists of a transmit and a receive section. The transmit section generates analog signals from 2-bit digital symbol data and filters the analog signals to create 2B1Q symbols. The on-board differential line driver provides a 13.5dBm signal to the telephone line. The receive section filters and digitizes the symbol data received on the telephone line. The AFE1224 operates on a single 5V supply. The digital circuitry in the unit can be connected to a supply from 3.3V to 5V. The chip uses only 355mW for full-speed operation. It is housed in a 28-lead SSOP package. txLINE Pulse Former txLINE Line Driver tx and rx Control Registers tx and rx Interface Lines Difference Amplifier Decimation Filter ∆Σ Modulator rxHYB rxHYB PGA rxLINE rxLINE AFE1224 Patents Pending International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1999 Burr-Brown Corporation PDS-1548A Printed in U.S.A. June, 1999 SPECIFICATIONS All specifications at 25°C, AVDD = +5V, DVDD = +3.3V, fTX = 1168kHz (E1 rate) and normal power mode, unless otherwise noted. AFE1224E PARAMETER RECEIVE CHANNEL Number of Inputs Input Voltage Range Common-Mode Voltage Input Impedance, All Inputs 78kbps 1168kbps 2320kbps Input Capacitance Input Gain Matching Resolution Programmable Gain Settling Time for Gain Change Gain + Offset Error Output Data Coding Data Rate Output Word Rate TRANSMIT CHANNEL Transmit Clock Rate, fTX Transmit –3dB Point Transmit Power(5) Pulse Output Common-Mode Voltage (VCM) Output Resistance TRANSCEIVER PERFORMANCE Uncancelled Echo(5) DIGITAL INTERFACE Logic Levels VIH VIL VOH VOL trx1 Interface POWER Analog Power Supply Voltage Digital Power Supply Voltage Power Dissipation(4, 5) Power Dissipation(4, 5) Power Supply Rejection Ratio COMMENTS MIN Differential Balanced Differential(1) 2 Line Input vs Hybrid Input 0dB, 3dB, 6dB, 9dB and 12dB Tested at Each Gain Range Normal Power Medium Power Low Power Normal Power(3) Symbol Rate, Normal Power Symbol Rate, Medium Power Symbol Rate, Low Power 2320kbps 1168kbps 784kbps DC to 1MHz V V 32 21 10 10 ±2 kΩ kΩ kΩ pF % Bits dB Symbol Periods %FSR(2) +12 6 5 Binary Two’s Complement 64 2320 64 1168 64 320 32 1168 196 96 80 1168 584 160 485 292 196 13 13.5 14 See Typical Performance Curves AVDD /2 1 –71 –71 –74 –76 –78 –80 V V V V ns 3.3 5.25 385 300 240 415 55 –40 V Ω DVDD +0.3 +0.8 5.25 3.15 kHz kHz kHz kHz kHz kHz dBm dB dB dB dB dB dB 5 4.75 kbps kbps kbps kHz –68.5 –68.5 –71 –73.5 –75.5 –77.5 +0.4 4.6 3 TEMPERATURE RANGE Operating(6) UNITS ±3.0 AVDD/2 DVDD –1 –0.3 DVDD –0.5 Specification Operating Range Specification Operating Range Normal Power Medium Power Low Power Normal Power, DVDD = 5V MAX 14 0 rxGAIN = 0dB, Loopback Enabled rxGAIN = 0dB, Loopback Disabled rxGAIN = 3dB, Loopback Disabled rxGAIN = 6dB, Loopback Disabled rxGAIN = 9dB, Loopback Disabled rxGAIN = 12dB, Loopback Disabled |IIH| < 10µA |IIL| < 10µA IOH = –20µA IOL = 20µA TYP +85 V V V V mW mW mW mW dB °C NOTES: (1) With a balanced differential signal, the positive input is 180° out-of-phase with the negative input, therefore the actual voltage swing about the commonmode voltage on each pin is ±1.5V to achieve a total input range of ±3.0V or 6Vp-p. (2) FSR is Full-Scale Range. (3) The output data is available at twice the symbol rate with interpolated values. (4) With a pseudo-random equiprobable sequence of HDSL pulses; 13.5dBm applied to the transformer (16.5dBm output from txLINE+ and txLINE–). (5) See the Discussion of Specifications section of this data sheet for more information. (6) Functionality only guaranteed over temperature range. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® AFE1224 2 PIN CONFIGURATION PIN DESCRIPTIONS Top View PIN # SSOP-28 TYPE NAME DESCRIPTION 1 — NC No Connection 2 — NC 3 Power DVDD 4 Ground DGND 5 Input txbaudCLK No Connection Digital Supply (+3.3 to +5V) Digital Ground Transmit Baud Clock NC 1 28 NC 6 Input tx48xCLK NC 2 27 AGND 7 Input Data In DVDD 3 26 txLINE+ 8 Input rxbaudCLK 9 Input rx48xCLK Receive Clock at 48x Baud Clock Output Data Out Output Data Word DGND 4 25 AVDD 10 txbaudCLK 5 24 txLINE– 11 Power DVDD 12 Ground DGND 13 Power AVDD tx48xCLK 6 Data In 7 23 AGND 22 AVDD AFE1224 rxbaudCLK 8 21 vrREF– rx48xCLK 9 20 VCM Data Out 10 19 vrREF+ Transmit Clock at 48x Baud Clock Input Data Word Receive Baud Clock Digital Supply (+3.3V to +5V) Digital Ground Analog Supply (+5V) 14 Input rxHYB– Negative Input from Hybrid Network 15 Input rxHYB+ Positive Input from Hybrid Network 16 Input rxLINE– Negative Line Input 17 Input rxLINE+ Positive Line Input 18 Ground AGND Analog Ground 19 Output vrREF+ Positive Reference Output DVDD 11 18 AGND 20 Output VCM DGND 12 17 rxLINE+ 21 Output vrREF– 22 Power AVDD AVDD 13 16 rxLINE– 23 Ground AGND rxHYB– 14 15 rxHYB+ 24 Output txLINE– 25 Power AVDD 26 Output txLINE+ 27 Ground AGND 28 — NC ABSOLUTE MAXIMUM RATINGS Common-Mode Voltage (buffered) Negative Reference Output Analog Supply (+5V) Analog Ground Negative Line Output Output Buffer Supply (+5V) Positive Line Output Output Buffer Ground No Connection ELECTROSTATIC DISCHARGE SENSITIVITY Analog Inputs: Current .............................................. ±100mA, Momentary ±10mA, Continuous Voltage .................................. AGND –0.3V to AVDD +0.3V Analog Outputs Short Circuit to Ground (+25°C) ..................... Continuous AVDD to AGND ......................................................................... –0.3V to 6V DVDD to DGND ......................................................................... –0.3V to 6V Digital Input Voltage to DGND .................................. –0.3V to DVDD +0.3V Digital Output Voltage to DGND ............................... –0.3V to DVDD +0.3V AGND, DGND, Differential Voltage .................................................... 0.3V Junction Temperature (TJ) ............................................................. +150°C Storage Temperature Range .......................................... –40°C to +125°C Lead Temperature (soldering, 3s) .................................................. +260°C Power Dissipation .......................................................................... 700mW This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER(1) AFE1224E SSOP-28 324 –40°C to +85°C AFE1224E " " " " " SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER(2) TRANSPORT MEDIA AFE1224E AFE1224E/1K Rails Tape and Reel NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “AFE1224E/1K” will get a single 1000piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book. ® 3 AFE1224 BLOCK DIAGRAM Pulse Former Filter Output Buffer txLINE– REF+ txbaudCLK tx48xCLK txLINE+ Voltage Reference Transmit Control VCM REF– Data In rxbaudCLK rx48xCLK Receive Control rxLINE+ Data Out ∆Σ Modulator rxHYB+ rxHYB– Decimation Filter ® AFE1224 rxLINE– 4 TYPICAL PERFORMANCE CURVES At Output of HDSL Pulse Transformer The curves shown below are measured at the line output of the HDSL transformer. Typical at 25°C, AVDD+ = +5V, DVDD+ = +3.3V, and fTX = 1168kHz, unless otherwise specified. AVERAGE POWER SPECTRAL DENSITY LIMIT Power Spectral Density (dBm/Hz) –20 T1 –80dB/decade T1 –40 E1 –60 E1 E1-SP E1-SP –80 –100 –120 –140 1k 10k 1M 100k 10M 100M Frequency (Hz) CURVE 1. Upper Bound of Power Spectral Density Measured at Output of HDSL Transformer. 0.4T 0.4T 1.25T –1.2T 14T 50T –0.6T 0.5T CURVE 2. Transmitted Pulse Template Measured at HDSL Transformer Output. INPUT IMPEDANCE vs BIT RATE Input Impedance (kΩ) 100 Two Pair T1 = 784kbps, 32kΩ Two Pair E1 = 1168kbps, 21kΩ Single Pair E1 = 2320kbps, 10kΩ 75 50 T1 25 E1, Single Pair E1 0 200 600 1000 1400 1800 2200 2600 Bit Rate (kbps) CURVE 3. Input Impedance of rxLINE and rxHYB. ® 5 AFE1224 THEORY OF OPERATION compromise hybrid (rxHYB). The connection of these two inputs so that the hybrid signal is subtracted from the line signal is described in the paragraph titled “Echo Cancellation in the AFE.” The equivalent gain for each input in the difference amp is one. The resulting signal then passes to a programmable gain amplifier which can be set for gains of 0dB through +12dB. Following the PGA, the ADC converts the signal to a 14-bit digital word. The AFE1224 consists of a transmit and a receive channel. It interfaces to the HDSL DSP through a six wire serial interface, three wires for the transmit channel and three wires for the receive channel. It interfaces to the HDSL telephone line transformer and external compromise hybrid through transmit and receive analog connections. The transmit channel consists of a digital-to-analog converter and a switched-capacitor pulse forming network followed by a differential line driver. The pulse forming network receives 2-bit digital symbol data and generates a filtered 2B1Q analog output waveform. The differential line driver uses a composite output stage combining class B operation (for high efficiency driving large signals) with class AB operation (to minimize crossover distortion). The receive channel is designed around a fourth-order delta sigma A/D converter. It includes a difference amplifier designed to be used with an external compromise hybrid for first order analog echo cancellation. A programmable gain amplifier with gains of 0dB to +12dB is also included. The delta-sigma modulator operating at a 24x oversampling ratio produces a 14-bit output at rates up to 584kHz (1.168Mbps). The serial interface consists of three wires for transmit and three wires for receive. The three-wire transmit interface is transmit baud rate clock, transmit 48x oversampling clock and Data Out. The three-wire receive interface is receive baud rate clock, receive 48x oversampling clock and Data In. The transmit and receive clocks are supplied to the AFE1224 from the DSP and are completely independent. DIGITAL DATA INTERFACE Data is received by the AFE1224 from the DSP on the Data In line. Data is transmitted from the AFE1224 to the DSP on the Data Out line. The paragraphs below describe the timing of these signals and data structure. Data is transmitted and received in synchronization with the 48x transmit and receive clocks (tx48xCLK and rx48xCLK). There are 48-bit times in each baud period. Data In is The receive channel operates by summing the two differential inputs, one from the line (rxLINE) and the other from the rxbaudCLK rx48xCLK Data Out HDSL DSP AFE1224 txbaudCLK tx48xCLK Data In FIGURE 1. DSP Interface. 2.5ns 2.5ns txbaudCLK from DSP A B 2.5ns tx48xCLK from DSP 2.5ns 48 Data In from DSP 1 2 3 4 15 MSB Bit 15 16 LSB Bit 0 47 48 1 MSB Bit 15 Transmit Timing Notes: (1) A baud period consists of 48 periods of the tx48xCLK. (2) The falling edge of the txbaudCLK can occur anywhere in area A. The rising edge can occur anywhere in area B. However, neither edge of the txbaudCLK can occur within 4ns (on either side) of any rising edge of tx48xCLK. (3) The AFE1224 reads Data In on the rising edge of the tx48xCLK. Data In must be stable at least 4ns before the rising edge of tx48xCLK and it must remain stable at least 4ns after the rising edge of tx48CLK. (4) Symbol data is transferred to the transmit pulse former after the LSB is read. The output analog symbol data reaches the peak of the symbol approximately 24 tx48xCLK periods later. FIGURE 2. Transmit Timing Diagram. ® AFE1224 6 received in the first 16 bits of each baud period. The remaining 32-bit periods are not used for Data In. Data Out is transmitted during the first 16 bits of the baud period. A second interpolated value is transmitted in subsequent bits of the baud period. valid on the rising edge of the tx48xCLK. The AFE1224 reads Data In on the rising edge of the tx48xCLK. The bits are defined in Table I. Data In is read by the AFE1224 during the first 16 bits periods of each baud period. Only the first 8 bits are used in the AFE1224. The second 8 bits are reserved for use in the future products. The remaining 32 bits periods of the baud period are not used for Data In. txbaudCLK: The transmit data baud rate, generated by the DSP. It is 784kHz for T1 or 1168kHz for E1. It may vary from 32kHz (64kbps) to 1168Hz (2.320Mbps). Data In Bits tx48xCLK: The transmit pulse former oversampling sampling clock, generated by the DSP. It is 48x the transmit symbol rate or 56.064MHz for 1168kHz symbol rate. This clock should run continuously. tx enable signal—This bit controls the tx Symbol definition bits. If this bit is 0, only a 0 symbol is transmitted regardless of the state of the tx Symbol definition bits. If this bit is 1, the tx Symbol definition bits determine the output symbol. Data In: This is a 16-bit output data word sent from the DSP to the AFE. The sixteen bits include tx symbol information and other control bits, as described below. The data should be clocked out of the DSP on the falling edge and should be tx Symbol Definition—These two bits determine the output 2B1Q symbol transmitted. Rx Gain Settings—These bits set the gain of the receive channel programmable gain amplifier. MSB 1 LSB 2 3 1 1 2 2 Reserved Power Control Not Used Loopback rx Gain tx Symbol tx Enable FIGURE 3. Data In Word. 2.5ns rxbaudCLK from DSP 2.5ns rx48xCLK from DSP Data Out from AFE1224 2.5ns A B 2.5ns 48 1 14 MSB Bit 15 15 16 17 23 24 LSB Bit 0 25 26 MSB Bit 15 39 40 47 48 1 MSB Bit 15 LSB Bit 0 trx1 Data 1 Interdata 8 Bits Data 1a Interdata 8 Bits Data 2 RECEIVE TIMING NOTES: (1) A baud period consists of 48 periods of the tx48xCLK. (2) The falling edge of the rxbaudCLK can occur anywhere in area A. The rising edge can occur anywhere in area B. However, neither edge of the rxbaudCLK can occur within 4ns (on either side) of any rising edge of rx48xCLK. (3) For all data bits after the MSB of Data 1, the AFE1224 transfers Data Out on the falling edge of the rx48xCLK. The time from the falling edge of rx48xCLK until Data Out is stable is tRX1. trx1 MIN MAX 3ns 4.6ns (4) The AFE1224 transfers the MSB of Data 1 on the falling edge of rxbaudCLK. If the falling edge of rxbaudCLK is synchronized with the falling edge of rx48xCLK, all of the Data Out bits will be the same width. In any case, the time from the falling edge of rxbaudCLK until the MSB of Data 1 is stable is tRX1. FIGURE 4. Receive Timing Diagram. ® 7 AFE1224 DATA OUT PER SYMBOL PERIOD Loopback Control—This bit controls the operation of loopback. When enabled (logic 1), the rxLINE+ and rxline– inputs are disconnected from the AFE. The rxHYB+ and rxHYB– inputs remain connected. When disabled, the rxLINE+ and rxLINE– inputs are connected. Power Control—These bits control the power dissipation and the maximum speed of the AFE1224. BIT DESCRIPTION BIT STATE 15 (MSB) tx Enable Signal 0 1 AFE transmits a 0 Symbol AFE transmits HDSL Symbol as defined by bits 14 and 13 14 and 13 tx Symbol Definition 00 –3 transmit symbol 01 11 10 –1 transmit symbol +1 transmit symbol +3 transmit symbol 000 001 010 011 100 101 110 111 rx gain in AFE 0dB rx gain in AFE 3dB rx gain in AFE 6dB rx gain in AFE 9dB rx gain in AFE 12dB rx gain in AFE reserved rx gain in AFE reserved rx gain in AFE reserved 12 - 10 9 rx Gain Settings Loopback Control 8 Not Used 7-6 Power Control 5-0 1 0 DATA BITS Data 1 16 Interdata Bits 8 Data 1a 16 Interdata bits 8 Total Bits/Symbol Period 48 OUTPUT STATE MSB LSB 14 2 Reserved A/D Converter Data FIGURE 5. Data Out Word. ANALOG-TO-DIGITAL CONVERTER DATA The A/D converter data from the receive channel is coded in Binary Two’s Complement. Go to loopback mode Normal Operation N/A 00 01 10 11 Spare Low speed, low power Medium Speed, power Normal Speed, power Normal Speed, power ANALOG INPUT A/D CONVERTER DATA MSB Positive Full Scale N/A TABLE I. Data Input Format. LSB 01111111111111 Mid Scale 00000000000000 Negative Full Scale 10000000000000 TABLE II. Data Output Format. rxbaudCLK: This is the receive data baud rate (symbol clock), generated by the DSP. It is 392kHz for T1 or 584kHz for E1. It can vary from 32kHz (64kbps) to 584kHz (1.168Mbps). ECHO CANCELLATION IN THE AFE The rxHYB input is subtracted from the rxLINE input for first order echo cancellation. For correct operation, be certain that the rxLINE input is connected to the same polarity signal at the transformer (+ to + and – to –) while the rxHYB input is connected to opposite polarity through the compromise hybrid (– to + and + to –). Refer to the basic connection diagram in Figure 6. rx48xCLK: This is the A/D converter over-sampling clock, generated by the DSP. It is 48x the receive symbol rate or 28.032MHz for 584kHz symbol rate. This clock should run continuously. Data Out: This is the 14-bit A/D converter output data (+ 2 spare bits) sent from the AFE to the DSP. The 14 bits from the A/D Converter will be the upper bits of the 16-bit word (bits 15-2). The spare bits (1 and 0) will be always be LOW. Eight additional bits follow which are always HIGH. The data is clocked out on the falling edge and valid at the rising edge of the rx48xCLK. The bandwidth of the A/D converter dicimation filter is equal to one-half of the symbol rate. The nominal output rate of the A/D converter is one conversion per symbol period. For more flexible post-processing, there is a second true A/D conversion available in each symbol period. In Figure 4, the first conversion is shown as Data 1 and the second conversion is shown as Data 1a. It is recommended that rxbaudCLK be used with the rx48xCLK to read Data 1 while Data 1a is ignored. However, either data output may be used and both outputs may be used for more flexible post-processing. SCALEABLE TIMING The AFE1224 scales operation with the clock frequency. All internal filters and the pulse former change frequency with the clock speed so that the unit can be used at different frequencies just by changing the clock speed. For the receive channel, the digital filtering of the deltasigma converter scales directly with the clock speed. The bandwidth of the converter’s decimation filter is always onehalf of the symbol rate. The only receive channel issue in changing baud rate is the passive single pole anti-alias filter (see the following section). For systems implementing a broad range of speeds, selectable cut-off frequencies for the passive anti-alias filter should be used. ® AFE1224 8 0.1µF REFP VCM 0.1µF 0.1µF REFN 1:2 Transformer 13Ω Tip txLINE+ 4.7nF 13Ω txLINE– Ring – Input Anti-Alias Filter fc ≅ Bit Rate 375Ω rxbaudCLK rx48xCLK 4.7nF Compromise Hybrid – + rxHYB+ AFE1224 Data Out HDSL DSP + 100pF txbaudCLK 375Ω rxHYB– tx48xCLK Data In 375Ω rxLINE– 100pF GNDA 375Ω GNDA rxLINE+ GNDA DVDD DVDD AVDD AVDD AVDD 5V Analog 5V to 3.3V Digital 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 1 - 10µF FIGURE 6. Basic Connection Diagram. For the transmit channel, the pulse shape and the power spectral density scale directly with the clock rate. The power spectral density shown in Curve 1 and the pulse template shown in Curve 2 are measured at the output of the transformer. The transformer and the RC circuit on the output provide some smoothing for the output transmission. At lower bit rates, the amount of smoothing will be less and more output filtering may be needed. filter for the rxLINE and rxHYB differential inputs should be approximately 2MHz for single pair T1 and E1 symbol rates. Suggested values for the filter are 375Ω for each of the two input resistors and 100pF for the capacitor. Together the two 375Ω resistors and the 100pF capacitor result in a 3dB frequency of just over 2MHz. The 375Ω input resistors will result in minimal voltage divider loss with the input impedance of the AFE1224. This circuit applies at rates of 1Mbps to 2Mbps. For slower rates, the anti-aliasing filters will give best performance with 3dB frequency approximately equal to the bit rate. For instance, a 3dB frequency of 320kHz may be used for a single line bit rate of 320k bits per second. rxHYB AND rxLINE INPUT ANTI-ALIASING FILTERS An external input anti-aliasing filter is needed on the hybrid and line inputs as shown in the basic connection diagram (Figure 6). The –3dB frequency of the input anti-aliasing ® 9 AFE1224 DISCUSSION OF SPECIFICATIONS The external power is 16.5dBm: 13.5dBm to the line and 13.5dBm to the impedance matching resistors. The external load power of 16.5dBm is 45mW. The typical power dissipation in the AFE1224 under various conditions is shown in Table III. UNCANCELLED ECHO A key measure of transceiver performance is uncancelled echo. Uncancelled echo is the summation of all of the errors in the transmit and receive paths of the AFE1224. It includes effects of linearity, distortion and noise. Uncancelled echo is tested in production by Burr-Brown with a circuit that is similar to the one shown in Figure 7, Uncancelled Echo Test Diagram. POWER LEVEL MAXIMUM SPEED MINIMUM SPEED TYPICAL POWER DISSIPATION Normal Medium Low 2.3Mbps 1.168Mbps 320kbps 64kbps 64kbps 64kbps 385mW 300mW 240mW TABLE III. Typical Power Dissipation. The measurement of uncancelled echo is made as follows: The AFE is connected to an output circuit including a typical 1:2 line transformer. The line is simulated by a 135Ω resistor. Symbol sequences are generated by the tester and applied both to the AFE and to the input of an adaptive filter. The output of the adaptive filter is subtracted from the AFE output to form the uncancelled echo signal. Once the filter taps have converged, the rms value of the uncancelled echo is calculated. Since there is no far-end signal source or additive line noise, the uncancelled echo contains only noise and linearity errors generated in the transmit and receive sections of the AFE1224. LAYOUT The analog front end of an HDSL system has two conflicting requirements. It must accept and deliver moderately high rate digital signals and it must generate, drive, and convert precision analog signals. To achieve optimal system performance with the AFE1224, both the digital and the analog sections must be treated carefully in board layout design. The power supply for the digital section of the AFE1224 can range from 3.3V to 5V. This supply should be decoupled to digital ground with ceramic 0.1µF capacitors placed as close to DGND and DVDD as possible. One capacitor should be placed between pins 3 and 4 and the second capacitor between pins 11 and 12. Ideally, both a digital power supply plane and a digital ground plane should run up to and underneath the digital pins of the AFE1224 (pins 5 through 10). However, DVDD may be supplied by a wide printed circuit board (PCB) trace. A digital ground plane underneath all digital pins is strongly recommended. The data sheet value for uncancelled echo is the ratio of the rms uncancelled echo (referred to the receiver input through the receiver gain) to the nominal transmitted signal (13.5dBm into 135Ω, or 1.74Vrms). This echo value is measured under a variety of conditions: with loopback enabled (line input disconnected); with loopback disabled under all receiver gain ranges; and with the line shorted (S1 closed, see Figure 7). The remaining portion of the AFE1224 should be considered analog. All AGND pins should be connected directly to a common analog ground plane and all AVDD pins should be connected to an analog 5V power plane. Both of these planes should have a low impedance path to the power supply. The analog power supply pins should be decoupled to analog ground with ceramic 0.1µF capacitors placed as close to the AFE1224 as possible. One 10µF tantalum capacitor should also be used with each AFE1224 between the analog supply and analog ground. POWER DISSIPATION The power dissipation of the AFE1224 is digitally programmable by the user to three levels: normal, medium and low. The maximum bit rate of the AFE1205 is 2.3Mbps with normal power dissipation. At lower power dissipation levels, the maximum bit rate is lower. The power dissipation listed in the Specifications Table applies under these normal operating conditions: 5V analog power supply, 3.3V digital power supply, standard 13.5dBm delivered to the line, and a pseudo-random equiprobable sequence of HDSL output pulses. The power dissipation specifications includes all power dissipated in the AFE1224, but it does not include power dissipated in the external load. Ideally, all ground planes and traces and all power planes and traces should return to the power supply connector before being connected together (if necessary). Each ground and power pair should be routed over each other, should not overlap any portion of another pair, and the pairs should be separated by a distance of at least 0.25 inch (6mm). One exception is that the digital and analog ground planes should be connected together underneath the AFE1224 by a small trace. ® AFE1224 10 13Ω Transmit Data txDATP 1:2 5.6Ω txLINEP 13Ω 5.6Ω 135Ω S1 txLINEN 576Ω rxHYBP 1.59kΩ 100pF Adaptive Filter AFE1224 0.01µF 150Ω rxHYBN 576Ω 375Ω rxLINEP 100pF 375Ω rxLINEN Uncancelled Echo rxD13 - rxD0 FIGURE 7. Uncancelled Echo Test Diagram. ® 11 AFE1224