® DAC2815 DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER (8-Bit Port Interface) FEATURES ● COMPLETE DUAL DAC — INCLUDES INTERNAL REFERENCES AND OUTPUT AMPLIFIERS ● GUARANTEED SPECIFICATIONS OVER TEMPERATURE ● GUARANTEED MONOTONIC OVER TEMPERATURE ● HIGH-SPEED 8 + 4-BIT PARALLEL INTERFACE ● LOW POWER: 300mW (150mW/DAC) ● LOW GAIN DRIFT: 5ppm/°C ● LOW NONLINEARITY: ±1/2 LSB max ● UNIPOLAR OR BIPOLAR OUTPUT ● CLEAR/RESET TO UNIPOLAR OR BIPOLAR ZERO DESCRIPTION The DAC2815 is one in a family of dual and quad 12bit digital-to-analog converters (DACs). Serial, 8-bit, 12-bit interfaces are available. The DAC2815 is complete. It contains CMOS logic, switches, a high-performance buried-zener reference, and low-noise bipolar output amplifiers. No external components are required for either unipolar 0 to 10V, 0 to –10V, or bipolar ±10V output ranges. The DAC2815 has a 2-byte (8 + 4) double-buffered interface. Data is first loaded (level transferred) into the input registers in two steps for each DAC. Then both DACs are updated simultaneously. The DAC has an asynchronous clear control for reset to unipolar or bipolar zero depending on the mode selected. This feature is useful for power-on reset or system calibration. The DAC2815 is packaged in a 28-pin plastic DIP rated for the –40°C to +85°C extended industrial temperature range. DAC2815 17 +VREF Out 10kΩ +VL 10 18 Inv In +VS 12 –VS 10V Ref 8 AGND 11 10kΩ A3 14 Inv Out DGND 28 13 VREF In 20kΩ 20 BPO A 20kΩ DAC A A1 8-Bit Port and Control In High-stability laser-trimmed thin film resistors assure high reliability and true 12-bit integral and differential linearity over the full specified temperature range. Logic 16 VOUT A 20kΩ 19 BPO B 20kΩ DAC B A2 15 VOUT B International Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1991 Burr-Brown Corporation PDS-1110B Printed in U.S.A. October, 1993 SPECIFICATIONS, Guaranteed over TA = –40°C to +85°C unless otherwise specified. ELECTRICAL Specifications as shown for VS = ±12V or ±15V, VL = +5V, and RL = 2kΩ unless otherwise noted. DAC2815AP PARAMETER CONDITIONS DIGITAL INPUTS Resolution VIH (Input High Voltage) VIL (Input Low Voltage) IIN ( Input Current) MIN 12 2 0 Unipolar Offset Error Bipolar Zero Error Gain Error Unipolar, Bipolar Power Supply Sensitivity (3) +9.980 ±5 ±0.1 ±5 ±30 ±5 ±15 +10 ±2 +10.020 ±30 +9.985 Bits V V µA µA pF ±1/2 * ±1 ±0.5 * ±10 ±0.15 * LSB LSB LSB mV mV mV % ppmFSR/V * * * ±20 * ±8 ppm/°C ppmFSR/°C ppmFSR/°C * * +10.015 ±20 40 * V ppm/°C mA mA pF mA ppm/mA ±5 * ppm/V –9.985 ±20 V ppm/°C Ω mA pF mA * * 500 ±20 –10.020 –10 * * –9.980 ±30 –10.015 0.1 * 200 ±30 3.5 7 14 * * ±7 * * 5 10 20 * * * * * * ±10 –VS + 1.4 +VS – 1.4 * * 0.1 CL = 100pF To 1/2 LSB of Full Scale To 1/2 LSB of Full Scale 2.5 3.5 10 3 Full Scale Transition CL= 100pF ® 2 V Ω mA pF mA * * µs µs V/µs MHz * 500 ±30 * * 10 10 * * * * kΩ kΩ kΩ V * * ±5 VOUT D/A GLITCH IMPULSE DAC2 815 * * * * * * * * +10/–5 +6.5/–5 ANALOG GROUND CURRENT (Code Dependent) DIGITAL CROSSTALK UNITS ±1 ±3 ±20 ±0.2 30 REFERENCE INPUT Reference Input Resistance Inverter Input Resistance BPO Input Resistance Reference Input Range DYNAMIC PERFORMANCE(5) Unipolar Mode Settling Time Bipolar Mode Settling Time Slew Rate Small-Signal Bandwidth MAX +1.5/–1 With Internal or External 10.0V Ref VS = ±11.4V to ±18V, VL = +4.5V to +5.5V TA = 25°C TA = –40°C to +85°C TYP ±1 ±1 TA = 25°C TA = –40°C to +85°C TA = +25°C TA = –40°C TO +85°C Max Load Capacitance (For Stability) Short Circuit Current Load Regulation (∆ VOUT vs ∆ ILOAD) Supply Regulation (∆ VOUT vs ∆ VS) INVERTER –10V Reference(4), Inverter Output –10V Reference Drift DC Output Impedance Output Current Max Load Capacitance (For Stability) Short Circuit Current ANALOG SIGNAL OUTPUTS Voltage Range DC Output Impedance Output Current Max Load Capacitance (For Stability) Short Circuit Current MIN 0.8 TEMPERATURE DRIFT Gain Drift Unipolar, Bipolar Unipolar Offset Drift Bipolar Zero Drift REFERENCE OUTPUT Output Voltage Reference Drift Output Current DAC2815BP MAX 5 0.8 ±1 ±10 TA = 25°C TA = –40°C to +85°C CIN (Input Capacitance) ACCURACY Integral, Relative Linearity (1) Differential Nonlinearity (2) TYP ±2 * mA 3 * nV-s 30 * nV-s SPECIFICATIONS (CONT), Guaranteed over TA = –40°C to +85°C unless otherwise specified. ELECTRICAL Specifications as shown for VS = ±12V or ±15V, VL = +5V, and RL = 2kΩ unless otherwise noted. DAC2815AP PARAMETER CONDITIONS POWER SUPPLY +VS and –VS +VL +IS –IS +IL +IL Total Power, All DACs TYP MAX MIN TYP MAX UNITS ±11.4 4.5 ±15 5 +10 –10 0.2 ±18 5.5 +13.5 –13.5 1 5 410 * * * * * * * * * * * * * * V V mA mA mA mA mW +85 +85 * * * * °C °C °C/W Digital Inputs = 0V or +VL Digital Inputs = VIL or VIH 300 TEMPERATURE RANGE Specified Operating Thermal Resistance, θJA DAC2815BP MIN –40 –40 * 75 * NOTES: (1) End point linearity. (2) Guaranteed monotonic. (3) Change in bipolar full scale output. Includes voltage output DAC, voltage reference, and reference inverter. (4) Inverter output with inverter input connected to +VREF. (5) Guaranteed but not tested. ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS +VL to AGND ................................................................................. 0V, +7V +VL to DGND ................................................................................ 0V, +7V +VS to AGND .............................................................................. 0V, +18V –VS to AGND ............................................................................... 0V,–18V AGND to DGND ................................................................................ ±0.3V Any digital input to DGND .............................................. –0.3V, +VL +0.3V Ref In to AGND .................................................................................. ±25V Ref In to DGND .................................................................................. ±25V Storage Temperature Range .......................................... –55°C to +125°C Operating Temperature Range ......................................... –40°C to +85°C Lead Temperature (soldering, 10s) ................................................ +300°C Junction Temperature .................................................................... +155°C Output Short Circuit ................................... Continuous to common or ±VS Reference Short Circuit .............................. Continuous to common or +VS Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. BurrBrown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. PACKAGE INFORMATION MODEL DAC2815AP DAC2815BP PACKAGE PACKAGE DRAWING NUMBER(1) 28-Pin Plastic DIP 28-Pin Plastic DIP 215 215 ORDERING INFORMATION NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. MODEL DAC2815AP DAC2815BP LINEARITY ERROR (LSB) ±1 ±1/2 The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 DAC2 815 PIN DESIGNATIONS PIN DESCRIPTOR FUNCTION PIN DESCRIPTOR FUNCTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D6 D7 A0 A1 CLR MODE CS –VS LE +VL AGND +VS VREF In Inv Out Data bit 6 input Data bit 7 input Address 0 input Address 1 input Asychronous input reset to zero Selection input for unipolar or bipolar reset to zero Chip select enable, DAC A and DAC B Negative analog power supply, –15V input Latch data enable, DAC A and DAC B Positive logic power supply, +5V input Analog common Positive analog power supply, +15V input ± Reference voltage input Inverter (A3) output 28 27 26 25 24 23 22 21 20 19 18 17 16 15 DGND D5 D4 D3 D2 D1 D0 WR BPO A BPO B Inv In +VREF Out VOUT A VOUT B Digital common Data bit 5 input Data bit 4 input Data bit 3 input Data bit 2 input Data bit 1 input Data bit 0 input Write input, DAC A and DAC B Bipolar offset input, DAC A Bipolar offset input, DAC B Inverter (A3) input Reference voltage, +10V output Analog output voltage, DAC A Analog output voltage, DAC B PIN CONFIGURATION TopView View Top DIP D6 1 28 DGND D7 2 27 D5 A0 3 26 D4 A1 4 25 D3 CLR 5 24 D2 MODE 6 CS 7 22 D0 –VS 8 21 WR LE 9 20 BPO A +VL 10 19 BPO B AGND 11 18 Inv In +VS 12 17 +VREF Out VREF In 13 16 VOUT A Inv Out 14 15 VOUT B DAC2815 23 D1 TYPICAL PERFORMANCE CURVES TA = +25°C, VS = ±12V or ±15V, VL = +5V unless otherwise noted. NOISE vs BANDWIDTH (Bipolar Mode) PSRR vs FREQUENCY (Bipolar Mode) 250 80 Voltage Noise (µVrms) 70 PSRR (dB) 60 50 40 VOUT = 0V 30 200 150 VOUT = +10V FFFHEX 100 20 50 VOUT = 0V 800HEX VOUT = +10V 10 0 0 1k 10k 100k 100 1M Frequency (Hz) 10k Frequency (Hz) ® DAC2 815 1k 4 100k 1M TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, VS = ±12V or ±15V, VL = +5V unless otherwise noted. +0.5 +0.01 11.6 3 11.4 2.5 +0.005 Bipolar Zero 0 0 Bipolar Offset –0.5 –0.005 –0.01 –1.0 –40 –20 0 20 40 60 11.2 2 IS 1.5 11 1 10.8 10.6 0.5 +IL (All Logic Inputs = 0V or VL) 0 10.4 –0.015 –1.5 3.5 +IL (All Logic Inputs = 2V) 80 +IL (mA) Logic Supply Gain Error 11.8 ±IS (mA) Analog Supply +1.0 POWER SUPPLY CURRENT vs TEMPERATURE +0.015 ∆ Gain Error (%) +1.5 –40 Temperature (°C) –20 0 20 40 60 80 Temperature (°C) OUTPUT VOLTAGE SWING vs RESISTOR LOAD CROSSTALK (Bipolar Mode) 25 VS = ±15V 10V REF VL = 5V 0V VOUT B 15 VOUT VOUT (Vp-p) 20 VOUT A 10 LE +5V 5 0V 0 10 100 1k Time (500ns/div) 10k NOTE: Crosstalk is dominated by digital crosstalk/ feedthrough of the LE signal. Load Resistance (Ω ) FULL-SCALE OUTPUT SWING BIPOLAR (20V Step) FULL-SCALE OUTPUT SWING UNIPOLAR (10V Step) 0V VOUT (5V/div) VOUT (5V/div) ∆ Bipolar Offset and Zero Error (mV) CHANGE OF GAIN, BIPOLAR OFFSET AND ZERO ERROR vs TEMPERATURE VOUT 0V VOUT LE +5V 0V Time (2µs/div) Time (2µs/div) ® 5 DAC2 815 TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, VS = ±12V or ±15V, VL = +5V unless otherwise noted. ∆V Around –10V (2mV/div) +10V SETTLING TIME BIPOLAR (+10V to –10V Step) VOUT +5V LE 0V –10V VOUT LE +5V 0V Time (2µs/div) SETTLING TIME UNIPOLAR (+10V to 0V STEP) SETTLING TIME UNIPOLAR (0V to +10V Step) 0V VOUT +5V LE ∆V Around +10V (1mV/div) Time (1µs/div) 0V VOUT +10V LE +5V 0V Time (1µs/div) Time (1µs/div) MAJOR CARRY GLITCH DIGITAL FEEDTHROUGH 0V VOUT (5mV/div) VOUT (20mV/div) ∆V Around –10V (1mV/div) ∆V Around +10V (2mV/div) SETTLING TIME BIPOLAR (–10V to +10V) VOUT +5V LE 0V VOUT 0V Time (1µs/div) Time (500ns/div) NOTE: Data transition 800HEX to 7FFHEX. DAC output noise due to activity on digital inputs with latch disabled. ® DAC2 815 6 TIMING CHARACTERISTICS +VL = +5V, TA = –40°C to +85°C. t1 PARAMETER MINIMUM A0-A1 10ns 10ns 30ns 10ns 0ns DATA t1—Address Valid to Write Setup Time t2—Address Valid to Write Hold Time t3—Data Setup Time t4—Data Hold Time t5—Chip Select to LE or Write Setup Time t6—Chip Select to LE or Write Hold Time t7—Write Pulse Width t8—Clear Pulse Width t2 t3 t5 CS 5V 0V t4 5V 0V t6 5V 0V t7 5V 0V LE, WR t8 0ns 5V 0V CLR 40ns 40ns NOTES: (1) All input signal rise and fall times are measured from 10% to 90% of +5V. t R = t F = 5ns. (2) Timing measurement reference level is VIH + VIL . 2 INTERFACE LOGIC TRUTH TABLE MODE CLR LE CS WR A1 A0 FUNCTION X X X X X X X X 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 X 1 X X 0 0 0 0 0 0 1 X X X 0 0 0 0 1 0 X 1 X X 0 0 1 1 X X X X X X 0 1 0 1 X X X X X X DAC A LS Input Register Loaded with D7-D0 (LSB) DAC A MS Input Register Loaded with D3-(MSB)-D0 DAC B LS Input Register Loaded with D7-D0 (LSB) DAC B MS Input Register Loaded with D3-(MSB)-D0 DAC A, DAC B Registers Updated Simultaneously from Input Registers DAC A, DAC B Registers are Transparent No Data Transfer No Data Transfer All Registers Cleared Input Registers Cleared = 000HEX, DAC Registers = 800HEX NOTE: X = Don’t care. FUNCTIONAL BLOCK DIAGRAM, DAC2815 — Dual 12-bit DAC, 8-bit Port Data In VREF In 22 27 1 2 13 20kΩ CLR 5 4-Bit Input Register WR 21 CS 8-Bit Input Register 20 BPO A Bits 8 -11 20kΩ 12-Bit Latch Register Bits 0-11 DAC A A1 16 VOUT A Bits 0 - 7 7 20kΩ LE 9 A0 3 A1 4 MODE 4-Bit Input Register Control Logic 8-Bit Input Register 19 BPO B Bits 8 -11 20kΩ 12-Bit Latch Register DAC B Bits 0-11 A2 15 VOUT B Bits 0 - 7 10kΩ 10kΩ +10V Voltage Reference 6 10 12 8 11 28 +VL +VS –VS AGND DGND A3 17 14 Inv Out 18 +VREF Out Inv In ® 7 DAC2 815 DISCUSSION OF SPECIFICATIONS DIGITAL-TO-ANALOG GLITCH Ideally, the DAC output would make a clean step change in response to an input code change. In reality, glitches occur during the transition. See Typical Performance Curves. INPUT CODES All digital inputs of the DAC2815 are TTL and 5V CMOS compatible. Input codes for the DAC2815 are either USB (Unipolar Straight Binary) or BOB (Bipolar Offset Binary) depending on the mode of operation. See Figure 3 for ±10V bipolar connection. See Figures 4 and 5 for 0 to 10V and 0 to –10V unipolar connections. DIGITAL CROSSTALK Digital crosstalk is the glitch impulse measured at the output of one DAC due to a full scale transition on the other DAC—see Typical Performance Curves. It is dominated by digital coupling. Also, the integrated area of the glitch pulse is specified in nV–s. See table of electrical specifications. UNIPOLAR AND BIPOLAR OUTPUTS FOR SELECTED INPUT DIGITAL INPUT FFFHEX 800HEX 7FFHEX 000HEX UNIPOLAR (USB) BIPOLAR (BOB) +Full scale +1/2 Full scale +1/2 Full scale – 1 LSB Zero +Full scale Zero Zero – 1 LSB –Full scale DIGITAL FEEDTHROUGH Digital feedthrough is the noise at a DAC output due to activity on the digital inputs—see Typical Performance Curves. OPERATION INTEGRAL OR RELATIVE LINEARITY This term, also known as end point linearity, describes the transfer function of analog output to digital input code. Integral linearity error is the deviation of the analog output versus code transfer function from a straight line drawn through the end points. Depending on the address selected, the 4 MSBs or the 8 LSBs are written into the appropriate input register for each DAC when the WR signal is brought low. This data is latched in the input register when the WR goes high. Data are then transferred from the input registers to the DAC latch registers by bring LE low. The data are latched in the DAC latch registers when LE goes high. Both DACs are updated simultaneously. When CLR is brought low, the input registers are cleared to 000HEX (–10V), while the DAC registers = 800HEX. If LE is brought low, the DACs are updated with 000HEX resulting in –10V (bipolar) or 0V (unipolar) on the output. DIFFERENTIAL NONLINEARITY Differential nonlinearity is the deviation from an ideal 1 LSB change in the output voltage when the input code changes by 1 LSB. A differential nonlinearity specification of ±1 LSB maximum guarantees monotonicity. CIRCUIT DESCRIPTION Each of the two DACs in the DAC2815 consists of a CMOS logic section, a CMOS DAC cell, and an output amplifier. One buried-zener +10.0V reference and a reference inverter (for a –10.0V reference) are shared by both DACs. UNIPOLAR OFFSET ERROR The output voltage for code 000HEX when the DAC is in the unipolar mode of operation. BIPOLAR ZERO ERROR The output voltage for code 800HEX when the DAC is in the bipolar mode of operation. Figure 1 is a simplified circuit for a DAC cell. An R, 2R ladder network is driven by a voltage reference at VREF. Current from the ladder is switched either to IOUT or AGND by 12 single-pole double-throw CMOS switches. This maintains constant current in each leg of the ladder regardless of GAIN ERROR The deviation of the output voltage span (VMAX – VMIN) from the ideal span of 10V – 1 LSB (unipolar mode) or 20V – 1 LSB (bipolar mode). The gain error is specified with and without the internal +10V reference error included. R R R VREF 2R 2R 2R 2R 2R R R FB IOUT OUTPUT SETTLING TIME The time required for the output voltage to settle within a percentage-of-full-scale error band for a full scale transition. Settling to ±0.012% (1/2 LSB) is specified for the DAC2815. D11 (MSB) D10 D9 D0 (LSB) AGND FIGURE 1. Simplified Circuit Diagram of DAC Cell. ® DAC2 815 8 DAC2815 DAC2815 DAC A DAC A VOUT A VOUT A DAC B DAC B VOUT B VOUT B AGND AGND R GND R GND NOTE: Ideally RGND = 0Ω FIGURE 2. Recommended Ground Connections for Multiple DAC packages. OUTPUT RANGE CONNECTIONS digital input code. This makes the resistance at VREF constant (it can be driven by either a voltage or current reference). The reference can be either positive or negative polarity with a range of up to ±10V. ±10V Output Range For a ±10V bipolar outputs connect the DAC2815 as shown in Figure 3. Connect the MODE to logic high (+5V) for reset to bipolar zero. With MODE connected low (GND) reset will be to –Full-Scale. CMOS switches included in series with the ladder terminating resistor and the feedback resistor, RFB, compensate for the temperature drift of the ladder switch ON resistance. 0 To +10V Output Range The output op amps are connected as transimpedance amplifiers to convert the DAC-cell output current into an output voltage. They have been specially designed and compensated for precision and fast settling in this application. For 0 to +10V unipolar outputs connect the DAC2815 as shown in Figure 4. Connect the MODE to logic low (GND) for reset to unipolar zero. 0 To –10V Output Range For 0 to –10V unipolar outputs connect the DAC2815 as shown in Figure 5. Connect the MODE to logic low (GND) for reset to unipolar zero. POWER SUPPLY CONNECTIONS The DAC2815 is specified for operation with power supplies of VL = +5V and VS = either ±12V or ±15V. Even with the VS supplies at ±11.4V the DACs can swing a full ±10V. Power supply decoupling capacitors (1µF tantalum) should be located close to the DAC power supply connections. CONNECTION TO DIGITAL BUS DAC2815s can easily be connected to a µprocessor bus. Decode your address lines to derive the control signals shown in Figure 6. Only one LATCH signal is required for a system where all DAC2815s are updated simultaneously. If you want to update DAC2815s independently, use separate LATCH signals. The LATCH and WRITE signals can be brought low simultaneously to update the DAC registers with the same processor instruction that writes the final 8-bit data word the DAC input registers. Separate digital and analog ground pins are provided to permit separate current returns. They should be connected together at one point. Proper layout of the two current returns will prevent digital logic switching currents from degrading the analog output signal. The analog ground current is code dependent so the impedance to the system reference ground must be kept to a minimum. Connect DACs as shown in Figure 2 or use a ground plane to keep ground impedance less than 0.1Ω for less than 0.1LSB error. –10V REFERENCE An internal inverting amplifier (Gain = –1.0V/V) is provided to invert the +10V reference. Connect +VREF Out to Inv In for a –10V reference at Inv Out. ® 9 DAC2 815 +5V 10 DAC2815 17 + 1µF 10kΩ 12 +15V 1µF 10V Ref + 10kΩ A3 14 8 –15V 1µF 18 + 13 20kΩ 20 20kΩ DAC A A1 8-Bit Port and Control In 20kΩ 16 VOUT A 19 20kΩ DAC B A2 MODE 6 28 VOUT B 11 DGND +5V 15 AGND FIGURE 3. Analog Connections for ±10V DAC Output. +5V 10 DAC2815 17 + 1µF 10kΩ 12 +15V 1µF + 10V Ref 10kΩ A3 14 8 –15V 1µF 18 + 13 20kΩ 20 20kΩ DAC A A1 8-Bit Port and Control In 20kΩ 16 VOUT A 19 20kΩ DAC B A2 MODE 6 28 11 DGND FIGURE 4. Analog Connections for 0 to +10V DAC Output. ® DAC2 815 10 AGND 15 VOUT B DAC2815 10 +5V + 1µF 10V Ref 12 +15V 1µF 17 + 8 –15V 13 1µF 20kΩ + 20 20kΩ DAC A A1 8-Bit Port and Control In 20kΩ 16 VOUT A 19 20kΩ DAC B A2 MODE 6 28 15 VOUT B 11 DGND AGND FIGURE 5. Analog Connections for 0 to –10V DAC Output. Data WRITE 1 LATCH A0 A1 1-2, 22-27 21 9 3 4 1-2, 22-27 WRITE 2 21 9 3 4 DAC2815 Data In CS 7 WR LE A0 A1 DAC2815 Data In CS 7 WR LE A0 A1 FIGURE 6. Logic Connection for Multiple DAC2815 Packages. ® 11 DAC2 815