® DAC2813 DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER (12-bit port interface) FEATURES ● INTEGRAL LINEARITY ERROR: ±1/2LSB max ● ±12V to ±15V SUPPLIES ● 28-PIN PLASTIC DIP PACKAGE ● COMPLETE WITH REFERENCE AND OUTPUT AMPLIFIERS ● 12-BIT PORT INTERFACE ● ANALOG OUTPUT RANGE: ±10V ● MONOTONICITY GUARANTEED OVER TEMPERATURE DESCRIPTION DAC2813 is a complete dual 12-bit digital-to-analog converter with bus interface logic. Each package includes a precision +10V voltage reference, doublebuffered bus interface including a RESET function and 12-bit D/A converters with voltage-output operational amplifiers. The double-buffered interface consists of a 12-bit input latch and a D/A latch for each D/A converter. A RESET control allows the D/A outputs to be asynchronously reset to bipolar zero, a feature useful for power-up reset, system initialization and recalibration. DAC2813 output range resistors are internally connected for 20V full scale range. A 0 to 10V range can be connected using the bipolar offset resistor. Gain and bipolar offset of each D/A are adjustable with external trim potentiometers. DAC2813 is available in one performance grade with a integral linearity error of 1/2LSB and 12-bit monotonicity guaranteed over temperature. It is packaged in 28-pin 0.6in. wide plastic DIP package and specified over –40oC to +85oC. 10V Reference VREF OUT VREF IN 1 DAC2813 BPO 1 D/A 1 VOUT 1 DB0 LSB 12 12-bit Latches VREF IN 2 BPO 2 DB11 MSB D/A 2 VOUT 2 International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1992 Burr-Brown Corporation PDS-1147C Printed in U.S.A. October, 1993 SPECIFICATIONS ELECTRICAL At TA = +25oC, +VCC = +12V or +15V, –VCC = –12V or –15V, unless otherwise noted. PARAMETER CONDITIONS MIN DAC2813AP TYP MAX UNITS +5.5(3) +0.8 V V ±20 ±20 µA µA ±1/4 ±1/2 ±0.05 ±0.05 ±1/2 ±1 ±0.2 ±0.2 LSB LSB % %FSR(4) ±5 ±1 ±20 ±10 ppmFSR/%+VCC ppmFSR/%–VCC ±5 ±5 ±1/2 Guaranteed ±30 ±15 ±3/4 ppm/°C ppmFSR/°C LSB 4.5 2 10 0.1 6 µs µs V/µs LSB ±10 V mA Ω +10.05 V 0.2 ±5 Indefinite ±25 mA Ω ppm/°C +15 –15 +16.5 –16.5 V V 24 12 540 30 14 660 mA mA mW –3 +3 V –40 –60 +85 +100 °C °C °C/W INPUTS DIGITAL INPUTS Input Code (1) Logic Levels (2) VIH VIL Logic Input Currents DB0-DB11, WR, LDAC, RESET,ENX IIH IIL Over Temperature Range Bipolar Offset Binary +2 0 VI = +2.7V VI = +0.4V TRANSFER CHARACTERISTICS ACCURACY Linearity Error Differential Linearity Error Gain Error (5,6) Bipolar Zero Error (5,7) Power Supply Sensitivity Of Full Scale +VCC –VCC DRIFT Over Specification Temperature Range Gain Bipolar Zero Drift Linearity Error over Temperature Monotonicity DYNAMIC CHARACTERISTICS SETTLING TIME (8) Full Scale Range Change 1LSB Output Step (9) At Major Carry Slew Rate Crosstalk (10) OUTPUT Output Voltage Range Output Current Output Impedance Short Circuit to ACOM Duration To within ±0.012%FSR of Final Value 5kΩ || 500pF Load 20V Range 5kΩ Loads ±VCC ≥ ±11.4V ±5 0.2 Indefinite REFERENCE VOLTAGE Voltage Source Current Available for External Loads Impedance Temperature Coefficient Short Circuit to Common Duration POWER SUPPLY REQUIREMENTS Voltage:+VCC –VCC Current: +9.95 +10.00 2 +11.4 –11.4 No Load ±VCC = ±15V +VCC –VCC Power Dissipation Potential at DCOM with Respect to ACOM (11) TEMPERATURE RANGES Specification Storage Thermal Resistance, θJA,Plastic DIP 30 NOTES: (1) For Two’s Complement Input Coding invert the MSB with an external logic inverter. (2) Digital inputs are TTL and +5V CMOS compatible over the specification temperature range. (3) Open DATA input lines will be pulled above +5.5V. See discussion under LOGIC INPUT COMPATIBILITY section. (4) FSR means Full Scale Range. For example, for ±10V output, FSR = 20V. (5) Adjustable to zero with external trim potentiometer. (6) Specified with 500Ω connected between VREF OUT and VREF IN. (7) Error at input code 800HEX. DAC2813 specified with 100Ω connected betweenVREF OUT and VREF IN; and with 500Ω connected between VREF OUT and BPO. (8) Maximum represents the 3σ limit. Not 100% tested for this parameter. (9) For the worst-case code change: 7FF HEX to 800 HEX and 800 HEX to 7FF HEX. (10) Crosstalk is defined as the change in any output as a result of any other output being driven from –10V to +10V at rated output current. (11) The maximum voltage at which ACOM and DCOM may be separated without affecting accuracy specifications. ® DAC2813 2 ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC DISCHARGE SENSITIVITY +VCC to ACOM ............................................................................ 0 to +18V –VCC to ACOM ............................................................................ 0 to –18V +VCC to –VCC ............................................................................... 0 to +36V ACOM to DCOM .................................................................................. ±4V Digital Inputs to DCOM ........................................................... –1V to +VCC External Voltage applied to BPO Resistor ......................................... ±18V VREF OUT .............................................................. Indefinite short to ACOM VOUT ............................................................................ Momentary to ±18V Lead Temperature, soldering 10s .................................................. +300oC Max Junction Temperature .............................................................. 165oC Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr-Brown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. PACKAGE/ORDERING INFORMATION NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. PACKAGE PACKAGE DRAWING NUMBER(1) TEMPERATURE RANGE 28-Pin DBL Wide DIP 215 –40°C to +85°C PRODUCT DAC2813AP NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. BLOCK DIAGRAM MSB DB11 1 WR 14 EN1 16 LDAC 17 LSB DB0 2 3 4 5 6 7 8 9 10 11 12 12 24.9kΩ 12-Bit Input Latch 24 BPO 1 28 VOUT 1 26 VREF IN 1 23 BPO 2 27 VOUT 2 25 VREF IN 2 25kΩ 12-Bit D/A Latch 0–800µA RESET 13 12-Bit D/A Converter 49.5kΩ 12 24.9kΩ EN2 12-Bit Input Latch 15 25kΩ 12-Bit D/A Latch 0–800µA 12-Bit D/A Converter 49.5kΩ +10V Reference 21 22 VREF OUT ACOM 18 19 20 DCOM –VCC +VCC NOTE: RESET does not reset input latches. ® 3 DAC2813 TIMING DIAGRAMS WRITE CYCLE #2 WRITE CYCLE #1 (Load second rank from first rank: ENX = 1) (Load first rank from Data Bus: LDAC = 1) > 50ns > 50ns LDAC ENX > 50ns > 50ns WR DB11–DB0 tSETTLING > 5ns WR ±1/2LSB V OUT > 50ns TRUTH TABLE RESET COMMAND (Bipolar Mode) WR EN1 EN2 X X X X 0 1 X 0 0 0 X 1 1 0 1 X 1 0 1 1 X 1 1 1 0 1 1 1 1 1 0 0 0 0 1 ENX, LDAC, WR = Don’t Care LDAC RESET OPERATION Reset both D/A Latches. Does not reset input latches. No Operation No Operation Load Data into First Rank for D/A 2 Load Data into First Rank for D/A 1 Load Second Rank from First Rank, both D/As All Latches Transparent Reset +10V VOUT > 50ns tSETTLING 0V ±1/2LSB “X” = Don’t Care –10V PIN DESCRIPTIONS PIN NAME FUNCTION 1 2 3 4 5 6 7 8 9 10 11 12 13 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RESET 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 WR EN2 EN1 LDAC DCOM –VCC +VCC VREF OUT ACOM BPO2 BPO1 VREF IN 2 VREF IN 1 VOUT 2 VOUT 1 DATA, MSB, positive true. DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA, LSB. Resets output of all D/As to bipolar-zero. The D/A remains in this state until overwritten an LDAC-WR command. RESET does not reset the input latch. After power–up and reset, input latches will be in an indeterminant state. Write strobe. Must be low for data transfer to any latch (except RESET). Enable for 12-bit input data latch of D/A 2. NOTE: This logic path is slower than the WR\ path. Enable for 12-bit input data latch of D/A 1. NOTE: This logic path is slower than the WR\ path. Load DAC enable. Must be low with WR for data transfer to the D/A latch and simultaneous update of both D/A converters. Digital common, logic currents return. Analog supply input, nominally –12V or –15V referred to ACOM. Analog supply input, nominally +12V or +15V referred to ACOM. +10V reference output. Analog common, +VCC, –VCC supply return. Bipolar offset. Connect to pin 21 (VREF OUT) through a 100Ω resistor or through a 200 potentiometer for Bipolar Offset Adjust for D/A 2. Bipolar offset. Connect to pin 21 (VREF OUT) through a 100Ω resistor or through a 200 potentiometer for Bipolar Offset Adjust or D/A 1. Connect to VREF OUT through 500Ω fixed resistor or through a 1kΩ gain adjustment potentiometer for D/A 2. Connect to VREF OUT through 500Ω fixed resistor or through a 1kΩ gain adjustment potentiometer for D/A 1. D/A 2 analog output. D/A 1 analog output. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® DAC2813 4 TYPICAL PERFORMANCE CURVES POWER SUPPLY REJECTION vs POWER SUPPLY RIPPLE FREQUENCY DIGITAL INPUT CURRENTvs INPUT VOLTAGE 1k 12.0 9.6 +VCC 100 7.2 Input Current (µA) 10 –VCC WR 4.8 ENX 2.4 RESET, LDAC 0 –2.4 DB0-DB11 –4.8 1 –7.2 –9.6 –12.0 0.1 10 100 1k 10k 100k 1M –2 0 2 CHANGE OF GAIN AND OFFSET ERROR vs TEMPERATURE 0.8 0 Unipolar Offset Gain Error –0.5 –0.4 –1 Linearity Error (LSB) ∆ Gain Error (%) 0.4 0 0 –0.8 –20 20 60 Temperature (°C) 100 –0.5 000 140 400 800 C00 FFF Input Code (Hexidecimal) ± FULL SCALE OUTPUT SWING MAJOR CARRY GLITCH 15 250 VOUT 10 200 150 WR +5 0 0 100 VOUT (mV) 5 WR (V) VOUT (V) 8 0.5 ∆ Bipolar/Unipolar Offset (%) (For 10V FSR; Double for 20V FSR) Bipolar Offset –60 6 INTEGRAL LINEARITY ERROR 1 0.5 4 Input Voltage (V) Frequency (Hz) –5 50 0 Data = 7FFH Data = 800H WR (V) [Change in FSR]/[Change in Supply Voltage] (ppm of FSR/ %) At TA = +25°C, VCC = ±15V, unless otherwise noted. Data = 7FFH +10 0 –10 –15 0 5 10 15 Time (µs) 20 25 –2 0 2 4 6 8 10 12 14 Time (µs) ® 5 DAC2813 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VCC = ±15V, unless otherwise noted. SETTLING TIME, +10V TO –10V VOUT 20 SETTLING TIME, –10V TO +10V 20 1LSB = 4.88mV 1LSB = 4.88mV VOUT 0 WR –10 +5 0 –20 –2 0 2 4 6 8 10 0 VOUT –10 WR –20 –40 12 +5 0 VOUT –2 0 2 Time (µs) 4 6 8 10 12 14 Time (µs) DISCUSSION OF SPECIFICATIONS LINEARITY ERROR SETTLING TIME Linearity error is defined as the deviation of the analog output from a straight line drawn between the end points (digital inputs all “1s” and all “0s”). DAC2813 linearity error is ±1/2LSB max at +25oC. Settling Time is the total time (including slew time) for the output to settle to within an error band around its final value after a change in input. Settling times are specified to ±0.01% of Full Scale Range (FSR) for two conditions: one for a FSR output change of 20V (25kΩ feedback) and one for a 1LSB change. The 1LSB change is measured at the Major Carry (7FFHEX to 800HEX, and 800HEX to 7FFHEX), the input code transition at which worst-case settling time occurs. DIFFERENTIAL LINEARITY ERROR Differential Linearity Error (DLE) is the deviation from a 1LSB output change from one adjacent state to the next. A DLE specification of 1/2LSB means that the output step size can range from 1/2LSB to 3/2LSB when the digital input code changes from one code word to the adjacent code word If the DLE is more positive than –1LSB, the D/A is said to be monotonic. OPERATION INTERFACE LOGIC The bus interface logic of the DAC2813 consists of two independently addressable latches in two ranks for each D/A converter. The first rank consists of one 12-bit input latch which can be loaded directly from a 12- or 16-bit microprocessor/microcontroller bus. The input latch holds data temporarily before it is loaded into the second latch, the D/A latch. This double buffered organization permits simultaneous update of all D/As. MONOTONICITY A D/A converter is monotonic if the output either increases or remains the same for increasing digital input values. DAC2813 is monotonic over their specification temperature range –40oC to +85oC. DRIFT Gain Drift is a measure of the change in the Full Scale Range (FSR) output over the specification temperature range. Gain Drift is expressed in parts per million per degree Celsius (ppm/oC). All latches are level-triggered. Data present when the control signals are logic “0” will enter the latch. When the control signals return to logic “1”, the data is latched. CAUTION: DAC2813 was designed to use WR as the fast strobe. WR/ has a much faster logic path than ENX (or LDAC). Therefore, if one permanently wires WR to DCOM and uses only ENX to strobe data into the latches, the DATA Bipolar Zero Drift is measured with a data input of 800HEX. The D/A is configured for bipolar output. Bipolar Zero Drift is expressed in parts per million of Full Scale Range per degree Celsius (ppm of FSR/oC). ® DAC2813 6 WR (V) VOUT ∆ Around +10V (mV) 10 WR (V) VOUT ∆ Around –10V (mV) 10 HOLD time will be long, approximately 20ns to 30ns and this time will vary considerably in this range from unit to unit. DATA HOLD time using WR is 5ns max. DAC2813 can be used with two’s complement coding if a logic inverter is used ahead of the MSB input (DB11). DAC2813 can be connected for 0 to +10V unipolar operation by using the BPO resistors, plus a 100Ω series resistor, in parallel with the internal feedback resistor. In this case, an input code of 000HEX gives zero volt output, an input of FFFHEX gives an output 1LSB below positive full scale. RESET FUNCTION The Reset function resets only the D/A latch. Therefore, after a RESET, good data must be written to all the input latches before an LDAC – WR command is issued. Otherwise, old data or unknown data is present in the input latches and will be transferred to the D/A latch producing an analog output value that may be unwanted. INTERNAL/EXTERNAL REFERENCE USE DAC2813 contains a +10V ±50mV voltage reference, VREF . VREF OUT is available to drive external loads sourcing up OUT to 2mA. The load current should be constant, otherwise the gain (and bipolar offset, if connected) of the D/A converters will vary. LOGIC INPUT COMPATIBILITY DAC2813 digital inputs are TTL compatible (1.4V switching level) over the operating range of +VCC. Each input has low leakage and high input impedance. Thus the inputs are suitable for being driven by any type of 5V logic. An equivalent circuit of a digital input is shown in Figure 1. For DAC2813 VREF OUT must be connected to VREF IN 1 and VREF IN 2 through gain adjust resistors with a nominal value of 500Ω. Trim potentiometers with a nominal value of 1000Ω can be used to provide adjustment to zero gain error. Open DATA input lines will float to 7V or more. Although this will not harm the DAC2813, current spikes will occur in the input lines when a logic 0 is asserted and, in addition, the speed of the interface will be slower. A digital output driving a DATA input line of the DAC2813 must not drive, or let the DATA input float, above +5.5V. Unused DATA inputs should be connected to DCOM. It is possible to use references other than +10V. The recommended range of reference voltage is from +8V to +11V, which allows both 8.192V and 10.24V ranges to be used. However, DAC2813 is optimized for fixed-reference applications. If the reference voltage is expected to time-vary over a wide range, a CMOS multiplying D/A is a better choice. Unused CONTROL inputs should be connected to a voltage greater than +2V but not greater than +5.5V. If this voltage is not available, the control inputs can be connected to +VCC through a 100kΩ resistor to limit the input current. Range of Gain Adjust ≈ ±1% + Full Scale Digital Input Analog Output 1LSB R 6.8V 10 to 20pF II DCOM DIGITAL INPUT Data, LDAC, WR, RESET ENX All Bits Logic 0 Range of Offset Adjust Offset Adj. Translates the Line ≈ ±0.4% DAC2813 RΩ 500 330 Full Scale Range Bipolar Offset Gain Adjust Rotates the Line All Bits Logic 1 MSB on All Others Off – Full Scale Digital Input FIGURE 2. Relationship of Offset and Gain Adjustments for a Bipolar D/A Converter. FIGURE 1. Equivalent Digital Input Circuit. ANALOG OUTPUT INPUT CODING DAC2813 accepts positive-true binary input codes. Input coding for bipolar analog outputs is Bipolar Offset Binary (BOB), where an input code of 000HEX gives a minus fullscale output, an input of FFFHEX gives an output 1LSB below positive full scale, and zero occurs for an input code of 800HEX. DIGITAL INPUT FFFHEX 800HEX 7FFHEX 000HEX 1LSB UNIPOLAR 0 TO +10V BIPOLAR ±10V +9.9976V +5.0000V +4.9976V 0.0000V 2.44mV +9.9951V 0.0000V –0.0049V –10.0000V 4.88mV TABLE III. Analog Output Calibration Values. ® 7 DAC2813 GAIN AND OFFSET ADJUSTMENTS Figure 2 illustrates the relationship of offset and gain adjustments to a bipolar connected D/A converter. Offset should be adjusted first to avoid interaction of adjustments. (ACOM) be connected directly to a ground plane under the package. If a ground place is not used, connect the ACOM and DCOM pins together close to the package. Since the reference point for VOUT and VREF OUT is the ACOM pin, it is also important to connect the load directly to the ACOM pin. The change in current in the ACOM pin due to an input date word change from 000HEX to FFFHEX is only 1mA for each D/A converter. Offset Adjustment For bipolar analog output operation, apply digital input code 000HEX to produce the maximum negative output and adjust the offset potentiometer for –10.000V. See Table III for calibration values and codes. OUTPUT VOLTAGE SWING AND RANGE CONNECTIONS DAC2813 output amplifiers provide a ±10V output swing while operating on supplies as low as ±12V ±5%. Gain Adjustment For either unipolar or bipolar operation, apply digital input code FFFHEX gives the maximum positive voltage output. Adjust the gain potentiometer for this positive full scale voltage. See Table III for calibration values. DAC2813 is internally connected to provide ±10V output when the bipolar offset pins BPO1 and/or BPO2 are connected, through 100Ω resistors, to VREF OUT. For a unipolar 0 to +10V output, the BPO resisitor, in series with a 100Ω external resistor, may be paralleled with the internal feedback resistor to provide the correct scaling. The internal feedback resistors (25kΩ) and the bipolar offset resistor (24.9kΩ) are trimmed to an absolute tolerance of ±2%. INSTALLATION POWER SUPPLY CONNECTIONS Power supply decoupling capacitors should be added as shown in Figure 4. Best settling time performance occurs using a 1 to 10µF tantalum capacitor at –VCC. Applications with less critical settling time may be able to use 0.01µF at –VCC as well as at +VCC. The capacitors should be located close to the package. 12- AND 16-BIT BUS INTERFACES DAC2813 data is latched into the input latches of each D/A by asserting low each ENx individually and transferring the data from the bus to each input latch by asserting WR low. All D/A outputs in each package are then updated simultaneously by asserting LDAC and WR low. Be sure and read the CAUTION statement in the LOGIC INPUT COMPATIBILITY section. DAC2813 features separate digital and analog power supply returns to permit optimum connections for low noise and high speed performance. It is recommended that both DIGITAL COMMON (DCOM) and ANALOG COMMON DAC2813 DAC2813 1 DB11 VOUT 1 28 2 DB10 VOUT 2 27 3 DB9 VREF IN 1 26 4 DB8 VREF IN 2 25 5 DB7 BPO 1 24 6 DB6 BPO 2 23 7 DB5 ACOM 22 8 DB4 VREF OUT 21 DB3 +V CC 20 –V CC 19 9 10 DB2 11 DB1 DCOM 18 12 DB0 LDAC 17 13 RESET EN1 16 14 WR EN2 15 Gain 1 1kΩ Gain 2 1kΩ 200Ω VOUT 2 VOUT 1 200Ω + 0.01µF + 0.01µF (1) 1 DB11 VOUT 1 28 2 DB10 VOUT 2 27 3 DB9 VREF IN 1 26 4 DB8 VREF IN 2 25 5 DB7 BPO 1 24 6 DB6 BPO 2 23 7 DB5 ACOM 22 8 DB4 VREF OUT 21 +VS 9 DB3 +V CC 20 –VS 10 (1) 10µF tantalum for optimum settling performance. BIPOLAR ±10V DB2 Gain 1 1kΩ Gain 2 1kΩ VOUT 2 VOUT 1 100Ω 100Ω + 0.01µF –V CC 19 11 DB1 DCOM 18 12 DB0 LDAC 17 13 RESET EN1 16 14 WR EN2 15 + 0.01µF (1) +VS –VS (1) 10µF tantalum for optimum settling performance. UNIPOLAR 0 to +10V FIGURE 3. DAC2813 Power Supply, Output Range, Gain and Offset Adjust Connections. Unipolar output connected DAC2813s have Gain Adjust only. ® DAC2813 8 1kΩ pot or 500Ω fixed 1kΩ pot or 500Ω fixed 26 21 24.9kΩ 24 26 VREF OUT VREF OUT 21 24.9kΩ BPO1 25kΩ 24 VOUT1 100Ω BPO1 25kΩ 200Ω pot or 100Ω fixed 28 I DAC1 VREF IN1 VREF IN1 ±10V 28 I DAC1 VOUT1 0 to +10V 1kΩ pot or 500Ω fixed 1kΩ pot or 500Ω fixed 25 24.9kΩ 23 VREF IN2 25 25kΩ 23 22 VOUT2 100Ω BPO2 25kΩ 200Ω pot or 100Ω fixed 27 I DAC2 24.9kΩ BPO2 VREF IN2 ±10V 27 I DAC2 ACOM 22 VOUT2 0 to +10V ACOM 0 to +10V Range ±10V Range FIGURE 4. DAC2813 Output Amplifier Range Connnections. ® 9 DAC2813