® DAC667 DAC 667 Microprocessor-Compatible 12-BIT DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION ● ±3/4LSB MAX NONLINEARITY OVER TEMPERATURE The DAC667 is a complete monolithic integrated circuit microprocessor-compatible 12-bit digital-to-analog converter. It includes a precision voltage reference, microcomputer interface logic, double-buffered latch, and a 12-bit D/A converter with a voltage output amplifier. Fast current switches and a laser-trimmed thin-film resistor network provide a highly accurate and fast D/A converter. ● MONOTONICITY GUARANTEED OVER TEMPERATURE ● MICROCOMPUTER INTERFACE: Double-Buffered Latch ● VOLTAGE OUTPUT: ±10V, ±5V, +10V With ±12V to ±15V Supplies ● LOW POWER DISSIPATION: 345mW typ A double-buffered latch facilitates microcomputer interfacing to 4-, 8-, 12-, or 16-bit data buses. The input buffer latch holds the 12-bit data until it is transferred to an internal 12-bit D/A converter latch, giving precise timing control over an analog output change. ● PIN COMPATIBLE WITH AD667 The DAC667 is specified to ±1/2LSB maximum linearity error at +25°C. The DAC667 is guaranteed monotonic over the specification temperature range. The DAC667 is available in 28-pin, 0.6" wide plastic DIP package. +VCC Power Gnd –VEE 8 16 10 Ref Out 6 Ref In 7 12-Bit D/A Converter A3 12 12-Bit Parallel Latch A0 15 A1 14 Reference 19.95k Ω 1 20V Span 2 10V Span 3 Summing Junction 9 VOUT 5 AGND 4 Bipolar Offset 5kΩ 5kΩ 9.95kΩ A2 13 CS 11 4 Bits 28 27 DB11 • MSB 4 Bits 26 • • 25 • • 24 • • 23 • • 4 Bits 22 • • 21 • • 20 • • 19 • • • 18 17 • DB0 LSB International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1990 Burr-Brown Corporation PDS-1091C 1 DAC667 Printed in U.S.A. March, 1998 SPECIFICATIONS At TA = +25°C, ±12V. ±15V power supplies, unless otherwise noted. DAC667JP PARAMETER MIN DIGITAL INPUTS Resolution Logic Levels (TTL Compatible, TMIN to TMAX)(1) VIH (Logic 1) VIL (Logic 0) IIH (VIH = 5.5V) IIL (VIL = 0.8V) TYP +2 0 3 1 ACCURACY Linearity Error at +25°C TA = TMIN to TMAX Differential Linearity Error at +25°C TA = TMIN to TMAX Gain Error(2) Unipolar Offset Error(2) Bipolar Zero(2) ±1/4 ±1/2 ±1/2 Monotonicity Guaranteed ±0.1 ±1 ±0.05 DRIFT Differential Linearity Gain (Full Scale), TA = +25°C to TMIN or TMAX Unipolar Offset, TA = +25°C to TMIN or TMAX Bipolar Zero, TA = +25°C to TMIN or TMAX ±2 ±5 ±1 ±5 CONVERSION SPEED Settling Time to ±0.01% of FSR for FSR Change (2kΩ || 500pF Load, CF = 0) With 10kΩ Feedback With 5kΩ Feedback For LSB Change Slew Rate 3 2 2 MAX UNITS 12 Bits +5.5 +0.8 10 5 V V µA µA ±1/2 ±3/4 ±3/4 LSB LSB LSB LSB % of FSR(3) LSB % of FSR ±0.2 ±2 ±0.1 ±30 ±3 ±10 4 3 8 ANALOG OUTPUT Ranges(4) Output Current Output Impedance (DC) Short Circuit Current ±5 REFERENCE OUTPUT External Current 9.9 0.1 ±2.5, ±5, ±10, +5, +10 0.05 40 POWER SUPPLY SENSITIVITY VCC = +11.4 to +16.5VDC VEE = –11.4 to –16.5VDC POWER SUPPLY REQUIREMENTS Rated Voltages Range(4) Supply Current +11.4 to +16.5VDC –11.4 to –16.5VDC ±11.4 0 –40 –65 of of of of FSR/°C FSR/°C FSR/°C FSR/°C µs µs µs V/µs V mA Ω mA 10 1 10.1 V mA 5 5 10 10 ppm of FS/% ppm of FS/% ±16.5 V V 17 12 mA mA +70 +85 +125 °C °C °C ±12, ±15 14 9 TEMPERATURE RANGE Specification Operating Storage ppm ppm ppm ppm The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® DAC667 2 ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS VCC to Power Ground .............................................................. 0V to +18V VEE to Power Ground .............................................................. 0V to –18V Digital Inputs (Pins 11–15, 17–28) to Power Ground ............. –1V to +7V Ref In to Reference Ground .............................................................. ±12V Bipolar Offset to Reference Ground ................................................. ±12V 10V Span Resistor to Reference Ground ......................................... ±12V 20V Span Resistor to Reference Ground ......................................... ±24V Ref Out, VOUT (Pins 6, 9) .................... Indefinite Short to Power Ground, Momentary Short To VCC Power Dissipation ........................................................................ 1000mW This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE TEMPERATURE RANGE LINEARITY ERROR max at 25°C GAIN TC, max (ppm/°C) PACKAGE DRAWING NUMBER(1) DAC667JP 28-Pin Plastic DIP 0°C to +70°C ±1/2LSB ±30 215 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. TIMING SPECIFICATIONS SYMBOL PARAMETER MIN TYP tDC tAC tCP tDH tSETT Data Valid to End of CS Address Valid to End of CS CS Pulse Width Data Hold Time Output Voltage Settling Time 50 100 100 0 – – – – – 2 MAX UNITS – – – – 4 ns ns ns ns µs All models, TA = +25°C, VCC = +12V or +15V, VEE = –12V or –15V. TIMING DIAGRAMS Write Cycle #1 Load first rank from Data Bus; A3 = 1. Write Cycle #2 Load second rank from first rank; A2, A1, A0 = 1. t tAC tAC A3 A2–A0 tCP tDC CS DB11–DB0 tSETT tCP tDH Output CS ±1/2LSB ® 3 DAC667 DISCUSSION OF SPECIFICATIONS INTERFACE LOGIC The bus interface logic of the DAC667 consists of four independently addressable latches in two ranks. The first rank consists of three four-bit input latches which can be loaded directly from a 4-, 8-, 12- or 16-bit microprocessor/ microcontroller bus. These latches hold data temporarily while a complete 12-bit word is assembled before loading it into the second rank of latches. This double buffered organization prevents the generation of spurious analog output values while the complete word is being assembled. All latches are level-triggered. Data present when the control signals are logic 0 will enter the latch. When the control signals return to logic 1, the data is latched. A truth table for the control signals is presented in Table I. LINEARITY ERROR Linearity error is defined as the deviation of the analog output from a straight line drawn between the end points (digital inputs all ones and all zeros). DAC667 linearity error is specified at ±1/4LSB max at ±1/2LSB max for J grade. DIFFERENTIAL LINEARITY ERROR Differential linearity error (DLE) is the deviation from a 1LSB output change from one adjacent state to the next. A DLE specification of 1/2LSB means that the output step size can range from 1/2LSB to 3/2LSB when the digital input code changes from one code word to the adjacent code word. If the DLE is more positive than –1LSB, the D/A is said to be monotonic. MONOTONICITY A D/A converter is monotonic if the output either increases or remains the same for increasing digital input values. The DAC667 is monotonic over the specification temperature range. CS A3 A2 A1 A0 OPERATION 1 X 0 0 0 0 0 X 1 1 1 1 0 0 X 1 1 1 0 1 0 X 1 1 0 1 1 0 X 1 0 1 1 1 0 No Operation No Operation Enable Four LSBs of First Rank Enable Four Middle Bits of First Rank Enable Four MSBs of First Rank Loads Second Rank from First Rank All Latches Transparent X = Don’t care. TABLE I. DAC667 Truth Table. DRIFT Gain drift is a measure of the change in the full scale range (FSR) output over the specification temperature range. Gain drift is expressed in parts per million per degree Celsius (ppm/°C). Unipolar offset drift is measured with a data input of 000HEX. The D/A is configured for unipolar output. Unipolar offset drift is expressed in parts per million of full scale range per degree Celsius (ppm of FSR/°C). It is permissible to enable more than one of the latches simultaneously. If a first rank latch is enabled coincident with the second rank latch, the data will reach the second rank correctly if the timing specifications on page 2 are met. LOGIC INPUT COMPATIBILITY The DAC667 digital inputs are TTL compatible (1.4V switching level) with a low leakage, high input impedance. Thus the inputs are suitable for being driven by any type of 5V logic. An equivalent circuit of a digital input is shown in Figure 1. Bipolar zero drift is measured with a data input of 800HEX. The D/A is configured for bipolar output. Bipolar zero drift is expressed in parts per million of full scale range per degree Celsius (ppm of FSR/°C). 1kΩ SETTLING TIME Digital Input Settling time is the total time (including slew time) for the output to settle to within an error band around its final value after a change in input. Three settling times are specified to ±0.01% of full scale range (FSR): two for FSR output changes of 20V (10kΩ feedback) and 10V (5kΩ feedback), and one for a 1LSB change. The 1LSB change is measured at the major carry (7FFHEX to 800HEX, and 800HEX to 7FFHEX), the input transition at which worst-case settling time occurs. 6.8V II DCOM FIGURE 1. Equivalent Digital Input Circuit. DAC667 data inputs will float to logic 1 and control inputs will float to logic 0 if left open. It is recommended that any unused inputs be connected to power common to improve noise immunity. OPERATION INPUT CODING The DAC667 accepts positive-true binary input codes. DAC667 is a monolithic integrated-circuit 12-bit D/A converter. It is complete with 12-bit D/A switches and ladder network, voltage reference, output amplifier and microprocessor bus interface as shown in the front-page diagram. Input coding for unipolar analog output is straight binary (USB), where all zeros (000HEX) on the data inputs gives a ® DAC667 5pF 4 zero analog output and all ones (FFFHEX) gives an analog output 1LSB below full scale. Input coding for bipolar analog outputs is bipolar offset binary (BOB), where an input code of 000HEX gives a minus full-scale output, an input of FFFHEX gives an output 1LSB below positive full scale, and zero occurs for an input code of 800HEX. Range of Gain Adj. ≈ ±1% + Full Scale 1LSB Analog Output All Bits Logic 0 The DAC667 can be used with two’s complement coding if a logic inverter is used ahead of the MSB input (DB11). INTERNAL/EXTERNAL REFERENCE USE DAC667 contains a +10V reference which is trimmed to typically ±0.2% and tested and guaranteed to ±1%. VREF OUT must be connected to VREF IN through a gain adjust resistor with a nominal value of 50Ω. A trim potentiometer with a nominal value of 100Ω can be used to provide adjustment to zero gain error. If an external 10.000V reference is used, it may be necessary to increase the trim range slightly. Full Scale Range Gain Adjust Rotates the Line Bipolar Offset MSB on All Others Off Range of Offset Adjust Offset Adj. Translates the Line ≈ ±0.4% All Bits Logic 1 – Full Scale Digital Input FIGURE 3. Relationship of Offset and Gain Adjustments for a Bipolar D/A Converter. The reference output may be used to drive external loads, sourcing up to 5mA. The load current should be constant, otherwise the gain (and bipolar offset, if connected) of the converter will vary. Offset Adjustment For unipolar (USB) operation, apply the digital input code that should produce zero voltage output and adjust the offset potentiometer for zero output. For bipolar (BOB, BTC) operation, apply the digital input code that produces the maximum negative output voltage and adjust the offset potentiometer for minus full scale voltage. See Table II for calibration values and codes. It is possible to use references other than +10V. The recommended range of reference voltage is from +8V to +11V, which allows both 8.192V and 10.24V ranges to be used. The DAC667 is optimized for fixed-reference applications. If the reference voltage is expected to vary over a wide range, a CMOS multiplying D/A is a better choice. GAIN AND OFFSET ADJUSTMENTS Figures 2 and 3 illustrate the relationship of offset and gain adjustments to a unipolar- and a bipolar-connected DAC667. Offset should be adjusted first to avoid interaction of adjustments. ANALOG OUTPUT DIGITAL INPUT 0 to +5V 0 to +10V ±2.5V ±5V ±10V FFFHEX 800HEX 7FFHEX 000HEX 1LSB +4.9987V +2.5000V +2.4987V 0.0000V 1.22mV +9.9976V +5.0000V +4.9976V 0.0000V 2.44mV +2.4987V 0.0000V –0.0013V –2.5000V 1.22mV +4.9976V 0.0000V –0.0024V –5.0000V 2.44mV +9.9951V 0.0000V –0.0049V –10.0000V 4.88mV TABLE II. Calibration Values. Range of Gain Adj. ≈ ±1% + Full Scale Gain Adjustment For either unipolar or bipolar operation, apply the digital input that gives the maximum positive voltage output. Adjust the gain potentiometer for this positive full scale voltage. See Table II for calibration values. Full Scale Range Analog Output 1LSB Range of Offset Adj. ≈ ±0.4% Gain Adjust Rotates the Line All Bits Logic 0 SETTLING TIME PERFORMANCE All Bits Logic 1 The switches, reference and output amplifier of the DAC667 are designed for optimum settling time performance (Figure 4). Figure 4a shows the full scale range step response, VOUT –10V to +10V to –10V, for data input 000HEX to FFFHEX to 000HEX. Figure 4b shows the settling time response at plus full scale (+10V) for an output transition from –10V to +10V. Figure 4c shows the settling time response at minus Digital Input Offset Adjust Translates the Line FIGURE 2. Relationship of Offset and Gain Adjustments for a Unipolar D/A Converter. ® 5 DAC667 high speed performance. It is recommended that both power ground (pin 16) and analog ground (AGND, pin 5) be connected directly to a ground plane under the package. If a ground plane is not used, connect the AGND and power ground pins together close to the package. Since the reference point for VOUT and VREF OUT is the AGND pin, it is also important to connect the load directly to the AGND pin. full scale (–10V) for an output transition from +10V to –10V. Figure 4d shows the major carry glitch response for input code transitions 7FFHEX to 800HEX and for 800HEX to 7FFHEX. Unlike the Analog Devices AD667, the Burr-Brown DAC667 does not require an external capacitor (Cf = 20pF) across RSPAN to eliminate overshoot. Using the 20pF with the BurrBrown DAC667 increases the settling time about one microsecond. The DAC667 settling time is specified at 7µs maximum. The AD667 is specified at 4µs maximum. The change in current in the AGND pin due to an input data word change from 000HEX to FFFHEX is only 1mA. OUTPUT VOLTAGE SWING AND RANGE CONNECTIONS The DAC667 output amplifier can provide ±10V output swing while operating on ±11.4V supplies. The Analog Devices AD667 requires a minimum of ±12.5V to achieve an output swing of ±10V. INSTALLATION POWER SUPPLY CONNECTIONS Note that the metal lid of the ceramic-packaged DAC667 is connected to –VEE. Take care to avoid accidental short circuits in tightly spaced installations. Internal scaling resistors provided in the DAC667 may be connected to produce bipolar output voltage ranges of ±10V, ±5V or ±2.5V or unipolar output voltage ranges of 0 to +5V or 0 to +10V. Refer to Figures 6, 7 and 8. Connections for various output ranges are shown in Table III. Power supply decoupling capacitors should be added as shown in Figure 5. Best settling performance occurs using a 1µF to 10µF tantalum capacitor at –VEE. Applications with less critical settling time may be able to use 0.01µF at –VEE as well as at +VCC. The capacitors should be located close to the DAC667 package. The internal feedback resistors (5kΩ) and the bipolar offset resistor (9.95kΩ) are trimmed to an absolute tolerance of about ±10%. DAC667 features separate digital and analog power supply returns to permit optimum connections for low noise and (b) PLUS FULL SCALE SETTLING, –10V TO +10V (a) ± FULL SCALE OUTPUT SWING 20 Cf = 0 Cf = 0 15 0 –5 VOUT 4 CS –10 –15 2 Data = 000 HEX Data = FFFHEX Data = 000HEX CS (V) 0 VOUT 5 1LSB/Division 5 CS (V) V OUT (V) 10 0 –20 2µs/Division 1µs/Division (c) MINUS FULL SCALE SETTLING, +10V TO –10V (d) MAJOR CARRY GLITCH 250 2 200 150 100 VOUT (mV) VOUT 1LSB/Division 0 50 0 Data = 7FFH Data = 800H VOUT WR (V) CS CS (V) 4 Data = 7FFH +10 0 Cf = 0 2µs/Division 1µs/Division FIGURE 4. Settling Time Performance, ZLOAD = 2kΩ || 500pF. ® DAC667 6 1 20V Span DB11 28 2 10V Span DB10 27 MSB +VCC 100kΩ 1 20V Span DB11 28 2 10V Span DB10 27 3 Sum Jct. DB9 26 4 Bipolar Off. DB8 25 5 AGND DB7 24 6 V REF OUT DB6 23 7 V REF IN DB5 22 8 +VCC DB4 21 MSB 50kΩ (2) 3 100Ω 100Ω VOUT +VCC 0.01µF –VCC (3) Sum Jct. DB9 26 4 Bipolar Off. DB8 25 5 AGND DB7 24 6 V REF OUT DB6 23 7 V REF IN DB5 22 8 +VCC DB4 21 9 V OUT DB3 20 10 –VEE DB2 19 11 CS DB1 18 100Ω –VCC 100Ω VOUT +VCC 0.01µF –VCC (3) 0.01µF (1) 9 V OUT DB3 20 10 –VEE DB2 19 11 CS DB1 18 12 A3 DB0 17 NOTES: (1) 10µF tantalum for optimum settling performance. (2) Unipolar offset adjust is not necessary in most applications. (3) For the ceramic package, the lid is connected to –V CC . 0.01µF (1) 12 A3 DB0 17 13 A2 Pwr Gnd 16 13 A2 Pwr Gnd 16 14 A1 A0 15 14 A1 A0 15 LSB Bipolar LSB Unipolar FIGURE 5. Power Supply, Gain and Offset Connections. 4 Summing Junction 9.95kΩ Bipolar Offset VREF OUT 6 10V Span 3 Bipolar Offset 100Ω 2 5kΩ 5kΩ 1 4 20V Span 20V Span 9 I DAC 1 VOUT 5kΩ 10V Span 5kΩ Summing Junction 9.95kΩ 5 Decrease V OUT 2 AGND 3 FIGURE 6. Output Amplifier Voltage Range Scaling Circuit. VOUT Bipolar Offset +VCC 100kΩ 10V Span 9.95kΩ 2 5kΩ 100Ω –V EE FIGURE 8. ±5V Bipolar Voltage Output. Increase V OUT Summing Junction MICROCOMPUTER BUS INTERFACING 3 VOUT I DAC ±5V 5 50kΩ 1 5kΩ 9 AGND 4 20V Span I DAC 9 8-BIT BUS INTERFACE The DAC667 interfaces easily to 8-bit microprocessor systems of all types. The control logic makes possible the use of right- or left-justified data formats. Data formats for 8-bit buses are illustrated in Figure 9. 0 to +10V AGND 5 FIGURE 7. 0 to +10V Unipolar Voltage Output. ® 7 DAC667 OUTPUT RANGE DIGITAL INPUT CODES CONNECT PIN 9 TO CONNECT PIN 1 TO CONNECT PIN 2 TO ±10V ±5V ±2.5V 0 to +10V 0 to +5V Offset Binary Offset Binary Offset Binary Straight Binary Straight Binary 1 1 and 2 2 1 and 2 2 9 2 and 9 3 2 and 9 3 NC 1 and 9 9 1 and 9 9 CONNECT PIN 4 TO 6 (Through 50Ω fixed or 100Ω trim resistor.) 6 (Through 50Ω fixed or 100Ω trim resistor.) 6 (Through 50Ω fixed or 100Ω trim resistor.) 5 (Or optional trim. See Figure 7.) 5 (Or optional trim. See Figure 7.) TABLE III. Output Voltage Range Connections. DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB1 DB0 X X X X DB11 DB10 DB9 DB8 DB3 DB1 DB0 DB2 D7 D6 D5 D4 D3 D2 D1 D0 (a) Left-Justified X X X X DB7 DB6 DB5 DB4 DB2 DB11 (MSB) DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DAC667 DB1 DB0 (LSB) WR (b) Right-Justified A15 Address Decoder CS A2 A1 FIGURE 9. 12-Bit Data Formats for 8-Bit Systems. A0 Whenever a 12-bit D/A is loaded from an 8-bit bus, two bytes are required. If the software program considers the data to be a 12-bit binary fraction (between 0 and 4095/ 4096), the data is left-justified, with the eight most significant bits in one byte and the remaining bits in the upper half of another byte. Right-justified data calls for the eight least significant bits to occupy one byte, with the four most significant bits residing in the lower half of another byte, simplifying integer arithmetic. Figure 10 shows an addressing scheme for use with a DAC667 set up for left-justified data in an 8-bit system. The base address is decoded from the high-order address bits and the resultant active-low signal is applied to CS. The two LSBs of the address bus are connected as shown to the DAC667 address inputs. The latches now reside in two consecutive locations, with location X01 loading the four LSBs and location X10 loading the eight MSBs and updating the output. FIGURE 10. Left-Justified 8-Bit Bus Interface. Right-justified data can also be accommodated as shown in Figure 11. The DAC667 still occupies two adjacent locations in the processor’s memory map. Location X01 loads the eight LSBs and location X10 loads the four MSBs and updates the output. 12- AND 16-BIT BUS INTERFACES For operation with 12- and 16-bit buses, all four address lines (A0 through A3) are connected to logic 0, and the latch is enabled by CS asserted low. The DAC667 thus occupies a single memory location. This configuration uses the first and second rank registers simultaneously. The CS input can be driven from an activelow decoded address. It should be noted that any data bus activity during the period when CS is low will cause activity at the DAC667 output. If data is not guaranteed stable during this period, the second rank register can be used to provide double buffering. See Figure 12. ® DAC667 A0 A1 A2 A3 8 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 WR A15 DB11 (MSB) DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DAC667 DB1 DB0 (LSB) Address Decoder DB11 (MSB) DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DAC667 DB1 DB0 (LSB) D7 D6 D5 D4 D3 D2 D1 D0 WR A15 CS A0 Address Decoder CS A2 A0 A1 A2 A3 A1 A0 FIGURE 12. Connections for 12- and 16-Bit Bus Interface. A0 A1 A2 A3 FIGURE 11. Right-Justified 8-Bit Bus Interface. ® 9 DAC667