DAC813 ® DAC 813 DAC 813 Microprocessor-Compatible 12-BIT DIGITAL-TO-ANALOG CONVERTER FEATURES converter with voltage output operational amplifier. Fast current switches and laser-trimmed thin-film resistors provide a highly accurate, fast D/A converter. ● ±1/2LSB NONLINEARITY OVER TEMPERATURE ● GUARANTEED MONOTONIC OVER TEMPERATURE Digital interfacing is facilitated by a double buffered latch. The input latch consists of one 8-bit byte and one 4-bit nibble to allow interfacing to 8-bit (right justified format) or 16-bit data buses. Input gating logic is designed so that the last nibble or byte to be loaded can be loaded simultaneously with the transfer of data to the D/A latch saving computer instructions. ● LOW POWER: 270mW typ ● DIGITAL INTERFACE DOUBLE BUFFERED: 12 AND 8 + 4 BITS ● SPECIFIED AT ±12V AND ±15V POWER SUPPLIES ● RESET FUNCTION TO BIPOLAR ZERO ● 0.3" WIDE DIP AND SO PACKAGES A reset control allows the DAC813 D/A latch to asynchronously reset the D/A output to bipolar zero, a feature useful for power-up reset, recalibration, or for system re-initialization upon system failure. DESCRIPTION The DAC813 is specified to ±1/2LSB maximum linearity error (J, A grades) and ±1/4LSB (K grade). It is packaged in 28-pin 0.3" wide plastic DIP and 28-lead plastic SOIC The DAC813 is a complete monolithic 12-bit digitalto-analog converter with a flexible digital interface. It includes a precision +10V reference, interface control logic, double-buffered latch and a 12-bit D/A Reset 4 MSBs 8 LSBs Input Latch Input Latch 4 8 BPO 24.9kΩ 20V Span 25kΩ D/A Latch 20V Span 12 10V Reference 49.5kΩ VREF OUT 12-Bit D/A Converter 25kΩ VOUT VREF IN International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1990 Burr-Brown Corporation PDS-1077G 1 DAC813 Printed in U.S.A. March, 1998 SPECIFICATIONS At TA = +25°C, ±VCC = ±12V or ±15V and load on VOUT = 5kΩ || 500pF to common, unless otherwise noted. DAC813JP, JU, AU PARAMETER CONDITIONS DIGITAL INPUTS Resolution Codes(1) Digital Inputs Over Temperature Range(2) VIH(3) VIL DATA Bits, WR, Reset, LDAC, LMSB, LLSB IIH IIL ACCURACY Linearity Error Differential Linearity Error Gain Error(4) Unipolar Offset Error(5) Bipolar Zero Error(6) Monotonicity Power Supply Sensitivity: +VCC –VCC DRIFT Gain Unipolar Offset Bipolar Zero Linearity Error Over Temperature Range Monotonicity Over Temperature Range SETTLING TIME(8) (To Within ±0.01% of FSR of Final Value; 5kΩ || 500pF load) For Full Scale Range Change MIN TEMPERATURE RANGE Specification: J, K A Operating: J, K A Storage: J, K A MIN TYP MAX UNITS ✻ Bits ✻ ✻ ✻ ✻ VDC VDC µA µA ±1/8 ±1/4 ✻ ✻ ✻ ✻ ✻ ✻ ±1/4 ±1/2 ✻ ✻ ✻ LSB LSB % % of FSR(7) % of FSR ✻ ✻ ppm of FSR/% ppm of FSR/% 12 +2 0 ✻ +5.5 +0.8 ±10 ±10 VIN = +2.7V VIN = +0.4V ✻ ✻ ±1/4 ±1/2 ±0.05 ±0.01 ±0.02 Guaranteed 5 1 ±1/2 ±3/4 ±0.2 ±0.02 ±0.2 ±5 ±1 ±3 ±1/2 Guaranteed ±30 ±3 ±10 ±3/4 ✻ ✻ ✻ ±1/4 ✻ ±15 ±3 ±5 ±1/2 ppm/°C ppm of FSR/°C ppm of FSR/°C LSB 20V Range 10V Range 4.5 3.3 2 10 6 5 ✻ ✻ ✻ ✻ ✻ ✻ µs µs µs V/µs ±VCC > ±11.4V ±VCC > ±11.4V 0 to +10 ±5, ±10 20V Range Over Specification Temperature Range ±5 10 10 ✻ ✻ V V mA Ω ✻ At DC REFERENCE VOLTAGE Voltage Source Current Available for External Loads Impedance Temperature Coefficient Short Circuit to Common Duration POWER SUPPLY REQUIREMENTS Voltage: +VCC –VCC Current: +VCC + VL –VCC Potential at DCOM with Respect to ACOM(10) Power Dissipation MAX USB, BOB For 1LSB Change at Major Carry(9) Slew Rate ANALOG OUTPUT Voltage Range: Unipolar Bipolar Output Current Output Impedance Short Circuit to Common Duration TYP DAC813KP, KU ✻ ✻ 0.2 Indefinite +9.95 5 +11.4 –11.4 No Load No Load +10 +10.05 2 ±5 Indefinite ±25 +15 –15 13 –5 –3 270 0 –40 –40 –55 –60 –65 +16.5 –16.5 15 –7 +3 330 +70 +85 +85 +125 +100 +150 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ V mA Ω ppm/°C ✻ ✻ ✻ ✻ ✻ ✻ VDC VDC mA mA V mW ✻ ✻ ✻ ✻ ✻ ✻ °C °C °C °C °C °C ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ Same as specification for DAC813AU, JP, JU. NOTES: (1) USB = Unipolar Straight Binary; BOB = Bipolar Offset Binary. (2) TTL and 5V CMOS compatible. (3) Open DATA input lines will be pulled above +5.5V. See discussion under LOGIC INPUT COMPATIBILITY in the OPERATION section. (4) Specified with 500Ω Pin 6 to 7. Adjustable to zero with external trim potentiometer. (5) Error at input code 000HEX for unipolar mode, FSR = 10V. (6) Error at input code 800HEX for bipolar range. Specified with 100Ω Pin 6 to 4 and with 500Ω pin 6 to 7. See page 9 for zero adjustment procedure. (7) FSR means Full Scale Range and is 20V for the ±10V range. (8) Maximum represents the 3σ limit. Not 100% tested for this parameter. (9) At the major carry, 7FFHEX to 800HEX and 800HEX to 7FFHEX. (10) The maximum voltage at which ACOM and DCOM may be separated without affecting accuracy specifications. ® DAC813 2 ABSOLUTE MAXIMUM RATINGS(1) PIN DESCRIPTIONS PIN 1 2, 3 4 NAME DESCRIPTION +VL Positive supply pin for logic circuits. Connect to +VCC. 20V Range Connect Pin 2 or Pin 3 to Pin 9 (VOUT) for a 20V FSR. Connect both to Pin 9 for a 10V FSR. BPO Bipolar offset. Connect to Pin 6 (VREF OUT) through 100Ω resistor or 200Ω potentiometer for bipolar operation. 5 ACOM Analog common, ±VCC supply return. 6 VREF OUT +10V reference output referred to ACOM. 7 VREF IN Connected to VREF OUT through a 1kΩ gain adjustment potentiometer or a 500Ω resistor. 8 +VCC Analog supply input, nominally +12V to +15V referred to ACOM. +VCC to ACOM .......................................................................... 0 to +18V –VCC to ACOM .......................................................................... 0 to –18V +VCC to –VCC ............................................................................ 0 to +36V DCOM with respect to ACOM ............................................................. ±4V Digital Inputs (Pins 11–15, 17–28) to DCOM .................... –0.5V to +VCC External Voltage Applied to BPO Span Resistor .............................. ±VCC VREF OUT ........................................................... Indefinite Short to ACOM VOUT ................................................................. Indefinite Short to ACOM Power Dissipation .......................................................................... 750mW Lead Temperature (soldering, 10s) ............................................... +300°C Max Junction Temperature ............................................................ +165°C Thermal Resistance, θJ-A:Plastic DIP and SOIC ........................ 130°C/W Ceramic DIP ......................................... 85°C/W NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. 9 VOUT D/A converter voltage output. 10 –VCC Analog supply input, nominally –12V or –15V referred to ACOM. 11 WR Master enable for LDAC, LLSB, and LMSB. Must be low for data transfer to any latch. 12 LDAC Load DAC. Must be low with WR for data transfer to the D/A latch and simultaneous update of the D/A converter. 13 Reset When low, resets the D/A latch such that a Bipolar Zero output is produced. This control overrides all other data input operations. 14 LMSB Enable for 4-bit input latch of D8-D11 data inputs. NOTE: This logic path is slower than the WR path. 15 LLSB Enable for 8-bit input latch of D0-D7 data inputs. NOTE: This logic path is slower than the WR path. 16 DCOM Digital common. 17 D0 Data Bit 1, LSB. 18 D1 Data Bit 2. 19 D2 Data Bit 3. 20 D3 Data Bit 4. 21 D4 Data Bit 5. 22 D5 Data Bit 6. 23 D6 Data Bit 7. 24 D7 Data Bit 8. 25 D8 Data Bit 9. 26 D9 Data Bit 10. 27 28 D10 D11 Data Bit 11. Data Bit 12, MSB, positive true. ELECTROSTATIC DISCHARGE SENSITIVITY Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. BurrBrown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER(1) DAC813JP DAC813JU DAC813KP DAC813KU DAC813AU 28-Pin Plastic DIP 28-Lead Plastic SOIC 28-Pin Plastic DIP 28-Lead Plastic SOIC 28-Lead Plastic SOIC 246 217 246 217 217 TEMPERATURE RANGE LINEARITY ERROR, MAX AT +25°C (LSB) GAIN DRIFT (ppm/°C) 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C –40°C to +85°C ±1/2 ±1/2 ±1/4 ±1/4 ±1/2 ±30 ±30 ±15 ±15 ±30 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 DAC813 MINIMUM TIMING DIAGRAMS WRITE CYCLE #1 (Load first rank from Data Bus: LDAC = 1) > 50ns LLSB, LMSB > 50ns DB11–DB0 >5ns WR > 50ns WRITE CYCLE #2 (Load second rank from first rank: LLSB, LMSB = 1) > 50ns LDAC > 50ns WR tSETTLING ±1/2LSB RESET COMMAND (Bipolar Mode) LLSB, LMSB, LDAC, WR = Don’t Care Reset +10V > 50ns VOUT tSETTLING 0V ±1/2LSB –10V ® DAC813 4 TYPICAL PERFORMANCE CURVES POWER SUPPLY REJECTION vs POWER SUPPLY RIPPLE FREQUENCY DIGITAL INPUT CURRENT vs INPUT VOLTAGE 1k 4 LLSB, WR +VCC 100 2 Input Current (µA) 10 –VCC 1 LMSB, LDAC 0.1 10 100 1k 10k 100k 0 Reset –2 Data –4 1M –2 0 2 Frequency (Hz) CHANGE OF GAIN AND OFFSET ERROR vs TEMPERATURE 0.8 0 Unipolar Offset Gain Error –0.5 –0.4 –1 Linearity Error (LSB) ∆ Gain Error (%) 0.4 0 0 –0.8 –20 20 60 Temperature (°C) 100 –0.5 000 140 400 800 C00 FFF Input Code (Hexidecimal) MAJOR CARRY GLITCH ± FULL SCALE OUTPUT SWING 15 250 200 VOUT 10 150 WR +5 0 0 100 VOUT (mV) 5 WR (V) VOUT (V) 8 0.5 ∆ Bipolar/Unipolar Offset (%) (For 10V FSR; Double for 20V FSR) Bipolar Offset –60 6 INTEGRAL LINEARITY ERROR 1 0.5 4 Input Voltage (V) –5 50 0 Data = 7FFH Data = 800H WR (V) [Change in FSR]/[Change in Supply Voltage] (ppm of FSR/ %) At TA = +25°C, VCC = ±15V, unless otherwise noted. Data = 7FFH +10 0 –10 –15 0 5 10 15 20 25 –2 Time (µs) 0 2 4 6 8 10 12 14 Time (µs) ® 5 DAC813 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VCC = ±15V, unless otherwise noted. SETTLING TIME, +10V TO –10V SETTLING TIME, –10V TO +10V 20 VOUT 20 1LSB = 4.88mV 1LSB = 4.88mV 0 WR –10 +5 0 –20 –2 0 2 4 6 8 10 0 VOUT –10 WR –20 –40 12 –2 0 2 6 8 10 12 14 MONOTONICITY A D/A converter is monotonic if the output either increases or remains the same for increasing digital inputs. All grades of DAC813 are monotonic over their specification temperature range. INPUT CODES The DAC813 accepts positive-true binary input codes. DAC813 may be connected by the user for any one of the following codes: USB (Unipolar Straight Binary), BOB (Bipolar Offset Binary) or, using an external inverter on the MSB line, BTC (Binary Two’s Complement). See Table I. DRIFT Gain Drift is a measure of the change in the Full Scale Range (FSR) output over the specification temperature range. Gain Drift is expressed in parts per million per degree Celsius (ppm/°C). ANALOG OUTPUT FFFHEX 800HEX 7FFHEX 000HEX 4 Time (µs) DISCUSSION OF SPECIFICATIONS MSB to LSB 0 VOUT Time (µs) DIGITAL INPUT +5 WR (V) ∆ Around +10V (mV) 10 WR (V) ∆ Around –10V (mV) 10 USB Unipolar Straight Binary BOB Bipolar Offset Binary BTC* Binary Two’s Complement + Full Scale + 1/2 Full Scale + 1/2 Full Scale – 1LSB Zero + Full Scale Zero Zero – 1LSB – Full Scale Zero – 1LSB – Full Scale + Full Scale Zero Unipolar Offset Drift is measured with a data input of 000HEX. The D/A is configured for unipolar output. Unipolar Offset Drift is expressed in parts per million of Full Scale Range per degree Celsius (ppm of FSR/°C). Bipolar Zero Drift is measured with a data input of 800HEX. The D/A is configured for bipolar output. Bipolar Zero Drift is expressed in parts per million of Full Scale Range per degree Celsius (ppm of FSR/°C). * Invert MSB of BOB code with external inverter to obtain BTC code. TABLE I. Digital Input Codes. SETTLING TIME LINEARITY ERROR Linearity error as used in D/A converter specifications by Burr-Brown is the deviation of the analog output from a straight line drawn between the end points (inputs all “1s” and all “0s”). The DAC813 linearity error is specified at ±1/4LSB (max) at +25°C K grades, and ±1/2LSB (max) for J grades. Settling Time is the total time (including slew time) for the output to settle within an error band around its final value after a change in input. Three settling times are specified to ±0.012% of Full Scale Range (FSR): two for maximum full scale range changes of 20V and 10V, and one for a 1LSB change. The 1LSB change is measured at the major carry (7FFHEX to 800HEX and 800HEX to 7FFHEX), the input transition at which worst-case settling time occurs. DIFFERENTIAL LINEARITY ERROR REFERENCE SUPPLY Differential linearity error (DLE) is the deviation from a 1LSB output change from one adjacent state to the next. A DLE specification of 1/2LSB means that the output step size can range from 1/2LSB to 3/2LSB when the input changes from one state to the next. Monotonicity requires that DLE be less than 1LSB over the temperature range of interest. DAC813 contains an on-chip +10V reference. This voltage (pin 6) has a tolerance of ±50mV. VREF OUT must be connected to VREF IN through a gain adjust resistor with a nominal value of 500Ω. The connection can be made through an optional 1kΩ trim resistor to provide adjustment to zero ® DAC813 6 gain error. The reference output may be used to drive external loads, sourcing at least 5mA. This current should be constant, otherwise the gain of the converter will vary. WR POWER SUPPLY SENSITIVITY Power supply sensitivity is a measure of the effect of a power supply change on the D/A converter output. It is defined as a ppm of FSR output change per percent of change in either +VCC or –VCC about the nominal voltages expressed in ppm of FSR/%. The first performance curve on page 5 shows typical power supply rejection versus power supply ripple frequency. WR 11 LMSB 14 26 25 24 23 OPERATION No operation D/A latch set to 800HEX Enables 4 MSBs input latch Enables 8 LSBs input latch Loads D/A latch from input latches Makes all latches transparent The DAC813 digital inputs are TTL, 5V CMOS compatible over the operating range of +VCC. The input switching threshold remains at the TTL threshold over the supply range. An equivalent circuit of a digital input is shown in Figure 2. The logic input current over temperature is low enough to permit driving the DAC813 directly from the outputs of 5V CMOS devices. All latches are level-triggered. Data present when the control signals are logic “0” will enter the latch. When any one of the control signals returns to logic “1”, the data is latched. A truth table for the control signals is presented in Table II. 27 1 0 1 1 1 1 LOGIC INPUT COMPATIBILITY Input latches hold data temporarily while a complete 12-bit word is assembled before loading into the D/A latch. This double-buffered organization prevents the generation of spurious analog output values. Each latch is independently addressable. 28 X X 1 1 0 0 CAUTION: DAC813 was designed to use WR as the fast strobe. WR has a much faster logic path than ENX (or LDAC). Therefore, if one permanently wires WR to DCOM and uses only ENX to strobe data into the latches, the DATA HOLD time will be long, approximately 15ns to 30ns, and this time will vary considerably in this range from unit to unit. DATA HOLD time using WR is 5ns max. INTERFACE LOGIC D7 X X 0 1 1 0 TABLE II. DAC813 Interface Logic Truth Table. DAC813 is a complete single IC chip 12-bit D/A converter. The chip contains a 12-bit D/A converter, voltage reference, output amplifier, and microcomputer-compatible input logic as shown in Figure 1. D8 X X 1 0 1 0 “X” = Don’t Care OPERATION MSB D11 LLSB LMSB LDAC RESET 1 X 0 0 0 0 Open DATA input lines will float to 7V or more. Although this will not harm the DAC813, current spikes will occur in the input lines when a logic 0 is asserted and, in addition, 22 21 20 19 18 LSB D0 VL(1) DCOM 17 1 16 24.9kΩ 4-Bit Latch 4 BPO 2 20V Range 3 20V Range 9 VOUT 25kΩ LLSB 15 LDAC 12 Reset 13 8-Bit Latch 25kΩ 12-Bit D/A Latch 0–800µA 12-Bit D/A Converter 49.5kΩ +10V Reference NOTE: (1) VL must be connected to +VCC. 7 6 5 8 10 VREF IN VREF OUT ACOM +VCC –VCC FIGURE 1. DAC813 Block Diagram. ® 7 DAC813 1kΩ* Digital Input BTC) configurations, apply the digital input code that should produce the maximum negative output voltage and adjust the offset potentiometer for minus full scale voltage. Example: If the full scale range is connected for 20V, the maximum negative output voltage is –10V. See Table III for corresponding codes. See page 5 for II 6.8V 5pF II DCOM * R = 500Ω for LLSB. GAIN ADJUSTMENT For either unipolar or bipolar configurations, apply the digital input that should give the maximum positive voltage output. Adjust the gain potentiometer for this positive full scale voltage. See Table III for positive full scale voltages. FIGURE 2. Equivalent Input Circuit for Digital Inputs. the speed of the interface will be slower. A digital output driving a DATA input line of the DAC813 must not drive, or let the DATA input float, above +5.5V. Unused DATA inputs should be connected to DCOM. DIGITAL INPUT RESET FUNCTION When asserted low (<0.8V), RESET (Pin 13) forces the D/A latch to 800HEX regardless of any other input logic condition. If the analog output is connected for bipolar operation (either ±10V or ±5V), the output will be reset to Bipolar Zero (0V). If the analog output is connected for unipolar operation (0 to +10V), the output will be reset to half-scale (+5V). MSB to LSB 0 to +10V ±5V ±10V FFFHEX 800HEX 7FFHEX 000HEX 1LSB +9.9976V +5.0000V +4.9976V 0.0000V 2.44mV +4.9976V 0.0000V –0.0024V –5.0000V 2.44mV +9.9951V 0.0000V –0.0049V –10.0000V 4.88mV TABLE III. Digital Input/Analog Output. INSTALLATION If RESET is not used, it should be connected to a voltage greater than +2V but not greater than +5.5V. If this voltage is not available Reset can be connected to +VCC through a 100kΩ to 1MΩ resistor to limit the input current. POWER SUPPLY CONNECTIONS Note that the lid of the ceramic packaged DAC813 is connected to –VCC. Take care to avoid accidental short circuits in tightly spaced installations. GAIN AND OFFSET ADJUSTMENTS Figures 3 and 4 illustrate the relationship of offset and gain adjustments to unipolar and bipolar D/A converter output. Power supply decoupling capacitors should be added as shown in Figure 5. Optimum settling performance occurs using a 1 to 10µF tantalum capacitor at –VCC and at least a 0.01µF ceramic capacitor at +VCC. Applications with less critical settling time may be able to use 0.01µF at –VCC as well. The 0.01µF capacitors should be located close to the DAC813. Pin 1 supplies internal logic and must be connected to +VCC. OFFSET ADJUSTMENT For unipolar (USB) configurations, apply the digital input code that should produce zero voltage output and adjust the offset potentiometer for zero output. For bipolar (BOB, Range of Gain Adjust ≈ ±1% + Full Scale ANALOG OUTPUT Range of Gain Adjust ≈ ±1% + Full Scale 1LSB Full Scale Range Range of Offset Adj. ≈ ±0.4% Gain Adjust Rotates the Line All Bits Logic 0 Analog Output Analog Output 1LSB All Bits Logic 1 Range of Offset Adjust Offset Adj. Translates the Line ≈ ±0.4% Digital Input Offset Adjust Translates the Line FIGURE 3. Relationship of Offset and Gain Adjustments for a Unipolar D/A Converter. Full Scale Range Bipolar Offset Gain Adjust Rotates the Line MSB on All Others Off All Bits Logic 1 – Full Scale Digital Input FIGURE 4. Relationship of Offset and Gain Adjustments for a Bipolar D/A Converter. ® DAC813 All Bits Logic 0 8 200Ω 1kΩ VOUT +VCC 0.01µF –VCC (3) 1 VL D11 28 2 20V Range D10 27 +VCC 3 20V Range 26 10k Ω to 100kΩ D9 4 BPO D8 25 5 ACOM D7 24 6 V REF OUT D6 23 7 V REF IN D5 22 8 +VCC D4 21 9 V OUT D3 20 10 (2) 1kΩ VOUT +VCC 19 0.01µF –VCC VL D11 28 2 20V Range D10 27 3 20V Range D9 26 4 BPO D8 25 5 ACOM D7 24 6 V REF OUT D6 23 7 V REF IN D5 22 8 +VCC D4 21 9 V OUT D3 20 10 –VCC D2 19 3MΩ 0.01µF –VCC 1 (3) –VCC D2 11 WR D1 18 11 WR D1 18 12 LDAC D0 17 12 LDAC D0 17 13 Reset DCOM 16 13 Reset DCOM 16 14 LMSB LLSB 15 14 LMSB LLSB 15 + + 0.01µF (1) (1) 10µF tantalum for optimum settling performance. (2) Unipolar offset is not necessary in most applications and can lead to noise pickup. (3) Note that for the ceramic package the lid is connected to –VCC . 0.01µF (1) BIPOLAR UNIPOLAR FIGURE 5. Power Supply, Gain, and Offset Connections. APPLICATIONS DAC813 features separate digital and analog power supply returns to permit optimum connections for low noise and high speed performance. It is recommended that both Analog Common (ACOM, Pin 5) and Digital Common (DCOM, Pin 16) be connected directly to a ground plane under the package. If a ground plane is not used, connect the ACOM and DCOM pins together close to the package. Since the reference point for VOUT and VREF OUT is the ACOM pin, it is also important to connect the load directly to the ACOM pin. Refer to Figure 5. The change in current in the Analog Common pin (ACOM, Pin 5) due to an input data word change from 000HEX to FFFHEX is only 800µA. MICROCOMPUTER BUS INTERFACING The DAC813 interface logic allows easy interface to microcomputer bus structures. The control signal is derived from external device select logic and the I/O Write or Memory Write (depending upon the system design) signals from the microcomputer. The latch enable lines LMSB, LLSB, and LDAC determine which of the latches are selected. It is permissible to enable two or more latches simultaneously, as shown in some of the following examples. The double-buffered latch permits data to be loaded into the input latches of several DAC813s and later strobed into the D/A latch of all D/As, simultaneously updating all analog outputs. All the interface schemes shown below use a base address decoder. If blocks of memory are used, the base address decoder can be simplified or eliminated altogether. OUTPUT RANGE CONNECTIONS Internal scaling resistors provided in the DAC813 may be connected to produce bipolar output voltage ranges of ±10V and ±5V or unipolar output voltage range of 0 to +10V. Refer to Figure 6. The internal feedback resistors (25kΩ) and the bipolar offset resistor (24.9kΩ) are trimmed to an absolute tolerance of less than ±2%. Therefore, one can change the range by adding a series resistor in various feedback circuit configurations. For example, a 600Ω resistor in series with the 20V range terminal can be used to obtain a 20.48V (±10.24V) range (5mV LSB). A 7.98kΩ resistor in series with the 10V range connection (20V ranges in parallel) gives a 16.384V (±8.192V) bipolar range (4mV LSB). Gain drift will be affected by the mismatch of the temperature coefficient of the external resistor with the internal D/A resistors. 8-BIT INTERFACE The control logic of DAC813 permits interfacing to rightjustified data formats, illustrated in Figure 7. When a 12-bit D/A converter is loaded from an 8-bit bus, two bytes of data are required. Figure 8 illustrates an addressing scheme for right-justified data. The base address is decoded from the high-order address bits. A0 and A1 address the appropriate latches. Note that adjacent addresses are used. X10HEX loads the 8 LSBs and X01HEX loads the 4 MSBs and simultaneously transfers input latch data to the D/A latch. Addresses X00HEX and X11HEX are not used. ® 9 DAC813 INTERFACING MULTIPLE DAC813s IN 8-BIT SYSTEMS Many applications, such as automatic test systems, require that the outputs of several D/A converters be updated simultaneously. The interface shown in Figure 9 uses a 74LSB138 decoder to decode a set of eight adjacent addresses to load the input latches of four DAC813s. The example uses a right-justified data format. A ninth address using A3 causes all DAC813s to be updated simultaneously. If a certain DAC813 is always loaded last (for instance, D/A #4), A3 is not needed, saving 8 address 24.9kΩ spaces for other uses. Incorporate A3 into the base address decoder, remove the inverter, connect the common LDAC line to LLSB of D/A #4, and connect D1 of the 74LS138 to +5V. 12- AND 16-BIT MICROCOMPUTER INTERFACE For this application the input latch enable lines, LMSB and LLSB, are tied low, causing the latches to be transparent. The D/A latch, and therefore DAC813, is selected by the address decoder and strobed by WR. Be sure and read the CAUTION statement in the LOGIC INPUT COMPATIBILITY section. NC X 4 BPO 20V 25kΩ 3 X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Right-Justified 25kΩ 2 X FIGURE 7. 12-Bit Data Format for 8-Bit Systems. 0 TO +10V RANGE 20V 17 D0 25 D8 18 D1 26 D9 19 D2 27 D10 20 D3 28 D11 DB4 21 D4 DB5 22 D5 DB6 23 D6 DB7 24 D7 11 WR 12 LDAC 14 LMSB 15 LLSB 13 Reset DB0 9 I DAC VOUT 0 to +10V DB1 6 ACOM DB2 VREF OUT 24.9kΩ BPO 25kΩ 2 20V 25kΩ 3 NC DB3 200Ω pot or 100Ω fixed Microcomputer 4 ±10V RANGE 20V 9 I DAC 5 6 VOUT WR ±10V A15 ACOM A2 VREF OUT Base Address Decoder A1 24.9kΩ 4 BPO 25kΩ 2 20V 25kΩ 3 9 I DAC 5 A0 200Ω pot or 100Ω fixed Reset Circuitry ±5V RANGE FIGURE 8. Right-Justified Data Bus Interface. 20V VOUT ±5V ACOM FIGURE 6. Output Amplifier Voltage Range Scaling Circuit. ® DAC813 DAC813 5 10 WR A15 WR Base Address Decoder A4 LDAC DAC813 (1) LLSB CS LMSB A3 WR 15 LDAC DAC813 (2) LLSB 14 LMSB Microcomputer 74LS138 4 5 6 G2A G2B G1 Y0 Y1 Y2 Y3 13 12 Y4 11 3 A2 2 A1 1 A0 A3 Y5 10 C B Y6 A Y7 ADDRESS BUS A2 A1 A0 9 7 WR LDAC DAC813 (4) LLSB LMSB OPERATION 0 0 0 0 Load 8 LSB – D/A #1 0 0 0 1 Load 4 MSB – D/A #1 0 0 1 0 Load 8 LSB – D/A #2 0 0 1 1 Load 4 MSB – D/A #2 0 1 0 0 Load 8 LSB – D/A #3 0 1 0 1 Load 4 MSB – D/A #3 0 1 1 0 Load 8 LSB – D/A #4 0 1 1 1 Load 4 MSB – D/A #4 1 X X X Load D/A Latch—All D/A FIGURE 9. Interfacing Multiple DAC813s to an 8-Bit Bus. ® 11 DAC813