900 MHz ISM Band Analog RF Front End ADF9010 840 MHz to 960 MHz ISM bands Rx baseband analog low-pass filtering and PGA Integrated RF Tx upconverter Integrated integer-N PLL and VCO Integrated Tx PA preamplifier Differential fully balanced architectures 3.3 V supply Low power mode: <1 mA power-down current Programmable Rx LPF cutoff 330 kHz, 880 kHz, 1.76 MHz, and bypass Rx PGA gain settings: 3 dB to 24 dB in 3 dB steps Low noise BiCMOS technology 48-lead, 7 mm × 7 mm LFCSP APPLICATIONS FUNCTIONAL BLOCK DIAGRAM RXVDD VP AVDD CE DVDD VCM ADF9010 RxBBIP RxBBIN Rx INIP RxININ RxCM VCM DC OFFSET CORRECTION OVF RxBBQP RxINQP RxINQN 24-BIT INPUT SHIFT REGISTER DC OFFSET CORRECTION PLL MUXOUT RSET CP CHARGE PUMP R COUNTER PHASE FREQUENCY DETECTOR B COUNTER VTUNE 900 MHz RFID readers Unlicensed band 900 MHz applications REF IN N COUNTER N = BP + A PRESCALER P/P + 1 A COUNTER LOOUTP CEXT1 CEXT2 CEXT3 CEXT4 CT ÷4 LOOUTN RxBBQN SCLK SDATA SLE QUADRATURE PHASE SPLITTER TxBBIP TxBBIN TxOUTP TxOUTN TxBBQP TxBBQN DGND AGND 07373-001 FEATURES Figure 1. GENERAL DESCRIPTION The ADF9010 is a fully integrated RF Tx modulator and Rx analog baseband front end that operates in the frequency range from 840 MHz to 960 MHz. The receive path consists of a fully differential I/Q baseband PGA, low-pass filter, and general signal conditioning before connecting to an Rx ADC for baseband conversion. The Rx LPF gain ranges from 3 dB to 24 dB, programmable in 3 dB steps. The Rx LPF features four programmable modes with cutoff frequencies of 330 kHz, 880 kHz, and 1.76 MHz, or the filter can be bypassed if necessary. The transmit path consists of a fully integrated differential Tx direct I/Q upconverter with a high linearity PA driver amplifier. It converts a baseband I/Q signal to an RF carrier-based signal between 840 MHz and 960 MHz. The highly linear transmit signal path ensures low output distortion. Complete local oscillator (LO) signal generation is integrated on chip, including the integer-N synthesizer and VCO, which generate the required I and Q signals for transmit I/Q upconversion. The LO signal is also available at the output to drive an external RF demodulator. Control of all the on-chip registers is via a simple 3-wire serial interface. The device operates with a power supply ranging from 3.15 V to 3.45 V and can be powered down when not in use. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. ADF9010 TABLE OF CONTENTS Features .............................................................................................. 1 R Counter .................................................................................... 12 Applications ....................................................................................... 1 A and B Counters ....................................................................... 12 Functional Block Diagram .............................................................. 1 Tx Section .................................................................................... 14 General Description ......................................................................... 1 Interfacing ................................................................................... 14 Revision History ............................................................................... 2 Latch Structure ........................................................................... 15 Specifications..................................................................................... 3 Control Latch .............................................................................. 21 Transmit Characteristics.............................................................. 3 Tx Latch ....................................................................................... 21 Receive Baseband Characteristics .............................................. 4 Rx Calibration Latch .................................................................. 21 Integer-N PLL and VCO Characteristics .................................. 5 LO Latch ...................................................................................... 22 Write Timing Characteristics...................................................... 6 Rx Latch ....................................................................................... 22 Absolute Maximum Ratings............................................................ 7 Initialization ................................................................................ 22 Transistor Count ........................................................................... 7 Interfacing ................................................................................... 22 ESD Caution .................................................................................. 7 Applications Information .............................................................. 23 Pin Configuration and Function Descriptions ............................. 8 Demodulator Connection ......................................................... 23 Typical Performance Characteristics ........................................... 10 LO and Tx Output Matching .................................................... 24 Circuit Description ......................................................................... 12 PCB Design Guidelines ............................................................. 24 Rx Section .................................................................................... 12 Outline Dimensions ....................................................................... 25 LO Section ................................................................................... 12 Ordering Guide .......................................................................... 25 REVISION HISTORY 8/08—Revision 0: Initial Version Rev. 0 | Page 2 of 28 ADF9010 SPECIFICATIONS TRANSMIT CHARACTERISTICS AVDD = DVDD = 3.3 V ± 5%, AGND = DGND = GND = 0 V, TA = 25°C, dBm refers to 50 Ω, 1.4 V p-p differential sine waves in quadrature on a 500 mV dc bias, baseband frequency = 1 MHz, unless otherwise noted. Table 1. Parameter TRANSMIT MODULATOR CHARACTERISTICS Operating Frequency Range Min B Version 1 Typ 840 Output Power Output P1 dB Carrier Feedthrough Sideband Suppression Output IP3 Noise Floor TRANSMIT BASEBAND CHARACTERISTICS Input Impedance of Each Pin Input Capacitance of Each Pin Input Signal Level Common-Mode Output Level Tx Baseband 3 dB Bandwidth POWER SUPPLIES Voltage Supply IDD Digital IDD Rx Baseband Tx Modulator LO Synthesizer and VCO Total IDD Power-Down Rx VDD AVDD DVDD LOGIC INPUTS (SERIAL INTERFACE) Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINH/IINL Input Capacitance, CIN LOGIC OUTPUTS (MUXOUT) Output High Voltage, VOH Output Low Voltage, VOL 1 Max Unit Test Conditions/Comments 960 MHz Range over which uncompensated sideband suppression < −30 dBc VIQ = 1.4 V p-p differential 3 10 −40 −46 24 dBm dBm dBm dBc dBm −158 dBm/Hz 4 3 1.4 0.6 20 kΩ typ pF V p-p V MHz 3.15 5 70 140 140 360 1 1 POUT = −4 dBm per tone, 10 MHz and 12 MHz baseband input frequencies used. Single-ended frequencies up to 2 MHz At 10 MHz Measured differentially at I or Q 3.45 V 6 80 410 mA mA mA mA mA 1 20 20 mA μA μA V V μA pF 1.8 V logic compatible 0.4 ±1 5 0.4 V V IOL = 500 μA IOH = 500 μA 1.4 DVDD − 0.4 Operating temperature range for the B version is −40°C to +85°C. Rev. 0 | Page 3 of 28 Maximum gain settings Full power, baseband inputs biased at 0.5 V + 5 dBm LO power setting selected ADF9010 RECEIVE BASEBAND CHARACTERISTICS AVDD = DVDD = 3.3 V ± 5%, AGND = DGND = GND = 0 V, TA = 25°C, dBm refers to 50 Ω, 1.4 V p-p differential sine waves in quadrature on a 500 mV dc bias, baseband frequency = 1 MHz, unless otherwise noted. Table 2. Parameter RECEIVE BASEBAND PGA Highest Voltage Gain Lowest Voltage Gain Gain Control Range Gain Control Step Noise Spectral Density (Referred to Input) RECEIVE BASEBAND FILTERS 3 dB Cutoff Frequency (Mode 0) Gain Flatness Differential Group Delay Min B Version 1 Typ Max 24 3 18 3 3.5 320 0.5 500 150 Attenuation Template @ 330 kHz Offset @ 500 kHz Offset @ 1 MHz Offset 3 dB Cutoff Frequency (Mode 1) Gain Flatness Differential Group Delay −3 −8 −28 880 0.5 500 150 Attenuation Template @ 880 kHz Offset @ 2 MHz Offset @ 4 MHz Offset 3 dB Cutoff Frequency (Mode 2) Gain Flatness Differential Group Delay −3 −17 −38 1.76 0.5 500 150 Attenuation Template @ 1.76 MHz Offset @ 4 MHz Offset @ 8 MHz Offset @ 16 MHz Offset 3 dB Cutoff Frequency (Mode 3) Gain Flatness Differential Group Delay @ 2 MHz Offset @ 4 MHz Offset Input Impedance of Each Pin @ 24 dB gain @ 3 dB gain Input Capacitance of Each Pin Input Signal Level Common-Mode Output Level Maximum Residual DC 1 −3 −18 −38 −60 4 0.5 500 −0.5 −2 250 4 3 2 1.65 150 Operating temperature range for the B version is −40°C to +85°C. Rev. 0 | Page 4 of 28 Unit Test Conditions/Comments dB dB dB dB nV/√Hz Programmable using 3-bit interface kHz dB μs μs dB dB dB kHz dB μs μs dB dB dB MHz dB μs μs dB dB dB dB MHz dB μs dB dB Ω kΩ pF V p-p V mV At maximum PGA gain After filter calibration Typical from dc to 90 kHz DC to 360 kHz 170 kHz to 310 kHz After filter calibration After filter calibration DC to 90 kHz DC to 360 kHz 170 kHz to 310 kHz After filter calibration After filter calibration DC to 90 kHz DC to 360 kHz 170 kHz to 310 kHz After filter calibration After filter calibration DC to 90 kHz DC to 360 kHz At 10 MHz Measured differentially at I or Q On Rx baseband outputs Baseband gain 0 dB − 27 dB ADF9010 INTEGER-N PLL AND VCO CHARACTERISTICS Table 3. Parameter VCOOPERATING FREQUENCY LO OUTPUT CHARACTERISTICS VCO Control Voltage Sensitivity Min 3360 Harmonic Content (Second) Harmonic Content (Third) Frequency Pushing (Open Loop) Frequency Pulling (Open Loop) Lock Time Output Power Output Power Variation NOISE CHARACTERISTICS VCO Phase Noise Performance 2 @ 100 kHz Offset @ 1 MHz Offset @ 10 MHz Offset In-Band Phase Noise 3, 4 Normalized In-Band Phase Noise Floor3, 4 Spurious Frequencies at Output Channel Spacing PHASE DETECTOR Phase Detector Frequency 5 Maximum Allowable Prescaler Output Frequency 6 CHARGE PUMP ICP Sink/Source High Value Low Value RSET Range ICP Three-State Leakage Current Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature PLL REFERENCE Reference Clock Frequency Reference Clock Sensitivity Reference Input Capacitance REFIN Input Current B Version 1 Typ Max 3840 Unit MHz 8 MHz/V −27 −14 1.2 10 1000 −4 to +5 dBc dBc MHz/V Hz μs dBm ±3 dB Test Conditions/Comments Measured at LO output (900 MHz) 3.6 GHz VCO frequency (taking into account divide by 4) Into 2.00 VSWR load. 10 kHz loop bandwidth LO outputs combined in a 1:1 transformer; programmable in 3 dB steps Measured at LO output (900 MHz) −120 −141 −154 −96 −220 −70 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc 8 325 @ 1 kHz offset from carrier 900 MHz offset, 1 MHz PFD frequency, 250 kHz channel spacing; loop bandwidth = 7.5 kHz MHz MHz With RSET = 4.7 kΩ 5 0.625 2.7 10 0.2 2 1.5 2 10 0.7 104 PLL VDD 5 ±100 1 mA mA kΩ nA % % % 1.25 V ≤ VCP ≤ 2.5 V 1.25 V ≤ VCP ≤ 2.5 V VCP = 2.0 V MHz V p-p pF μA Operating temperature range for the B version is −40°C to +85°C. The noise of the VCO is measured in open-loop conditions. The phase noise is measured with the EVAL-ADF9010EBZ1 evaluation board and the Agilent E5052A spectrum analyzer. The spectrum analyzer provides the REFIN for the synthesizer; offset frequency = 1 kHz. 4 fREFIN = 10 MHz; fPFD = 1000 kHz; N = 3600; loop BW = 25 kHz. 5 Guaranteed by design. Sample tested to ensure compliance. 6 This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that is less than this value. 2 3 Rev. 0 | Page 5 of 28 ADF9010 WRITE TIMING CHARACTERISTICS AVDD = DVDD = 3.3 V ± 5%; AGND = DGND = GND = 0 V; TA = 25°C, guaranteed by design, but not production tested. Table 4. Limit at tMIN to tMAX (B Version) 10 10 25 25 10 20 Unit ns min ns min ns min ns min ns min ns min t3 SCLCK SDATA t1 DB23 (MSB) Test Conditions/Comments SDATA to SCLK setup time SDATA to SCLK hold time SCLK high duration SCLK low duration SCLK to SLE setup time SLE pulse width t4 t2 DB22 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t6 SLE t5 SLE 07373-002 Parameter t1 t2 t3 t4 t5 t6 Figure 2. Write Timing Diagram Rev. 0 | Page 6 of 28 ADF9010 ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise noted. Table 5. Parameter DVDD, RxVDD , AVDD to GND1 RxVDD, AVDD to DVDD VP to GND1 Digital I/O Voltage to GND1 Analog I/O Voltage to GND1 Charge Pump Voltage to GND1 REFIN, LOEXTP, LOEXTN to GND1 LOEXTP to LOEXTN Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature LCSP θJA Thermal Impedance Reflow Soldering Peak Temperature Time at Peak Temperature 1 Rating −0.3 V to +3.9 V −0.3 V to +0.3 V −0.3 V to +5.5 V −0.3 V to VDD + 0.3 V −0.3 V to AVDD + 0.3 V −0.3 V to VP to GND1 −0.3 V to VDD + 0.3 V ±320 mV −40°C to +85°C −65°C to +150°C 150°C 26°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high-performance RF integrated circuit with an ESD rating of <0.5 kV and is ESD sensitive. Proper precautions should be taken for handling and assembly. TRANSISTOR COUNT The ADF9010 transistor count is 40,454 (CMOS) and 994 (bipolar). ESD CAUTION 260°C/W 40 sec GND = AGND = DGND = 0 V. Rev. 0 | Page 7 of 28 ADF9010 48 47 46 45 44 43 42 41 40 39 38 37 RxINQN RxINQP RxV DD NC AGND OVF MUXOUT SLE SDATA SCLK CE DVDD PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RxINIP 1 RxININ 2 3 4 5 6 7 8 9 10 11 12 ADF9010 TOP VIEW (Not to Scale) 36 35 34 33 RxBBIN RxBBIP RxBBQP RxBBQN 32 31 30 29 28 27 26 25 CEXT3 CEXT4 RSET AVDD TxBBIN TxBBIP TxBBQP TxBBQN NC = NO CONNECT 07373-004 CT CEXT 1 CEXT 2 AVDD VTUNE AGND LOEXT P LOEXTN AVDD TXOUTP TXOUTN AGND 13 14 15 16 17 18 19 20 21 22 23 24 RxV DD LOOUTN LOOUTP AGND DGND REFIN DVDD VP CP AGND PIN 1 INDICATOR Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1, 2 3, 46 Mnemonic RxINIP, RxININ RxVDD 4, 5 LOOUTN, LOOUTP 6, 12, 18, 24, 44 7 8 AGND DGND REFIN 9, 37 DVDD 10 VP 11 CP 13 CT 14 CEXT1 15 CEXT2 16, 21, 29 AVDD Description Input/Complementary In-Phase Input to the Receive Filter Stage. Receiver Filter Power Supply. This voltage ranges from 3.15 V to 3.45 V. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. RxVDD must be the same value as AVDD and DVDD. Buffered Local Oscillator Output. These outputs are used to provide the LO for the external RF demodulator. These require an RF choke to AVDD and a dc bypass capacitor before connection to a demodulator. Analog Ground. This is the ground return path of analog circuitry. Digital Ground. PLL Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of 100 kΩ (see Figure 13). This input can be driven from a TTL or CMOS crystal oscillator, or it should be ac-coupled. Digital Power Supply. This voltage ranges from 3.15 V to 3.45 V. Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD. This pin supplies the voltage to the charge pump. If the internal VCO is used, it should equal AVDD and DVDD. If an external VCO is used, the voltage can be AVDD < VP < 5.5 V. Charge Pump Output. When enabled, this pin provides ±ICP to the external loop filter, which in turn drives the external VCO. A capacitor connected to this pin is used to roll off noise from the VCO. It should be decoupled to AGND with a value of 10 nF. The output voltage on this part is proportional to temperature. At ambient temperature, the voltage is 2.0 V. A capacitor connected to this pin is used to roll off noise from the VCO. It should be decoupled to AGND with a value of 10 nF. A capacitor connected to this pin is used to roll off noise from the VCO. It should be decoupled to AGND with a value of 10 nF. Analog Power Supply. This voltage ranges from 3.15 V to 3.45 V. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD. Rev. 0 | Page 8 of 28 ADF9010 Pin No. 17 Mnemonic VTUNE 19, 20 LOEXTP, LOEXTN 22, 23 TxOUTP, TxOUTN 25, 26 27, 28 30 TxBBQN, TxBBQP TxBBIP, TxBBIN RSET Description Control Input to the VCO. This input determines the VCO frequency and is derived from filtering the CP output. Single-Ended External VCO Input of 50 Ω. This is used if the ADF9010 utilizes an optional external VCO. These pins are internally dc-biased and must be ac-coupled. AC-couple LOEXTN to ground with 100 pF and ac-couple the VCO signal with 100 pF through LOEXTP. Buffered Tx Output. These pins contain the Tx output signal, which can be combined in a balun for best results. Baseband Quadrature Phase Input/Complementary Input to the Transmit Modulator. Baseband In-Phase Input/Complementary to the Transmit Modulator. Connecting a resistor between this pin and AGND sets the maximum charge pump output current. The nominal voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is ICPMAX = 25.5/RSET 31 CEXT4 32 CEXT3 33, 34 RxBBQN, RxBBQP 35, 36 RxBBIP, RxBBIN 38 CE 39 SCLK 40 SDATA 41 SLE 42 MUXOUT 43 OVF 45 47, 48 NC RxINQP, RxINQN where: RSET is 5.1 kΩ. ICPMAX is 5 mA. A capacitor connected to this pin is used to roll off noise from the VCO. It should be decoupled to AGND with a value of 10 nF. A capacitor connected to this pin is used to roll off noise from the VCO. It should be decoupled to AGND with a value of 10 nF. Output/Complementary Filtered Quadrature Signals from the Receive Filter Stage. The filtered output is passed to the baseband MxFE chip. Output/Complementary Filtered In-Phase from the Receive Filter Stage. The filtered output is passed to the baseband MxFE chip. Chip Enable. A Logic 0 on this pin powers down the device. A Logic 1 on this pin enables the device depending on the status of the power-down bits. Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the SCLK rising edge. This is a high impedance CMOS input. Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This is a high impedance CMOS input. Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into one of the four latches; the latch uses the control bits. This multiplexer output allows either the PLL lock detect, the scaled VCO frequency, or the scaled PLL reference frequency to be accessed externally. A rising edge on this pin drops the gain of the Rx path by 6 dB. This is used to rapidly drop the gain if the ADC detects an overload. No Connect. Input/Complementary Quadrature Input to the Receive Filter Stage. Rev. 0 | Page 9 of 28 ADF9010 TYPICAL PERFORMANCE CHARACTERISTICS 28 –40 26 25 OIP3 (dBm) –80 –100 24 23 22 21 –120 20 –140 10k 10M 100k 1M FREQUENCY (Hz) 100M Figure 4. LO Phase Noise (900 MHz, Including Open-Loop VCO Noise) LO FREQUENCY (MHz) Figure 7. Output IP3 (dBm) vs. LO Frequency (Hz), with Supply and Temperature Variations; Two-Tone Test (10 MHz and 12 MHz Baseband Input Frequencies) 0 9 –10 SIDEBAND SUPRESSION (dBc) 7 6 2 1 +25°C 3.15V SBS +25°C 3.3V SBS +25°C 3.45V SBS –40°C 3.15V SBS –40°C 3.3V SBS –40°C 3.45V SBS +85°C 3.15V SBS +85°C 3.3V SBS +85°C 3.45V SBS –20 –30 –40 –50 –60 –70 07373-108 3 –40°C 3.15V P OUT –40°C 3.3V P OUT –40°C 3.45V P OUT +25°C 3.15V POUT +25°C 3.3V POUT +25°C 3.45V POUT +85°C 3.15V POUT +85°C 3.3V POUT +85°C 3.45V POUT 07373-105 Tx OUTPUT POWER (dBm) 8 4 +85°C 3.15V OIP3 +85°C 3.3V OIP3 +85°C 3.45V OIP3 18 840 850 860 870 880 890 900 910 920 930 940 950 960 10 5 +25°C 3.15V OIP3 +25°C 3.3V OIP3 +25°C 3.45V OIP3 19 07373-013 –160 1k –40°C 3.15V OIP3 –40°C 3.3V OIP3 –40°C 3.45V OIP3 07373-107 –60 PHASE NOISE (dBc/Hz) 27 900MHz LO 10MHz REF IN 1MHz PFD INTEGRATED PHASE ERROR: 0.75 rms –80 840 850 860 870 880 890 900 910 920 930 940 950 960 0 840 850 860 870 880 890 900 910 920 930 940 950 960 LO FREQUENCY (MHz) LO FREQUENCY (MHz) Figure 5. Single Sideband Tx Power Output (dBm) vs. LO frequency (Hz) with Supply and Temperature Variations; Outputs Combined in 50:100 Balun Figure 8. Unwanted Sideband Suppression (dBc) vs. LO Frequency (Hz) with Supply and Temperature Variations 20 20 10 15 0 –10 POWER (dBc) –20 5 –40°C 3.15V P OUT –40°C 3.3V P OUT –40°C 3.45V P OUT +25°C 3.15V POUT +25°C 3.3V POUT +25°C 3.45V POUT +85°C 3.15V POUT +85°C 3.3V POUT +85°C 3.45V POUT IDEAL –5 –10 –15 –10 –5 0 5 10 15 –30 –40 –50 –60 –70 25°C 3.3V POUT (dBm) 25°C 3.3V SBS (dBc) 25°C 3.3V LOFT (dBc) 25°C 3.3V HD2 (dBm) 25°C 3.3V HD3 (dBm) –80 –90 –100 0.2 20 1.0 1.4 1.8 2.2 2.6 3.0 3.4 DIFFERENTIAL INPUT VOLTAGE (V) PIN (dBm) Figure 6. Power Output vs. Baseband Input Power with Supply and Temperature Variations 0.6 07373-109 0 07373-106 POUT (dBm) 10 Figure 9. Second- and Third-Order Distortion, Sideband Suppression (dBc), Carrier Feedthrough (dBm) and SBS POUT vs. Baseband Differential Input Level; LO Frequency = 900 MHz Rev. 0 | Page 10 of 28 ADF9010 9 20 8 0 –20 POWER (dB) 6 5 4 3 –40°C 3.15V P OUT –40°C 3.3V P OUT –40°C 3.45V P OUT 1 0 1 +25°C 3.15V POUT +25°C 3.3V POUT +25°C 3.45V POUT 10 INPUT FREQUENCY (MHz) +85°C 3.15V P OUT +85°C 3.3V POUT +85°C 3.45V P OUT 100 –40 Fc 330KHz Fc 1MHz Fc 2MHz BYPASS –60 –80 –100 10k Figure 10. Single Sideband Power vs. Baseband Input Frequency, with Supply and Temperature Variations; Maximum Gain Setting Selected; LO Frequency = 900 MHz Rev. 0 | Page 11 of 28 100k 1M FREQUENCY (Hz) 10M Figure 11. Rx Filter Performance, Power vs. Input Frequency 07373-111 2 07373-110 Tx OUTPUT POWER (dBm) 7 ADF9010 CIRCUIT DESCRIPTION R COUNTER Rx SECTION The 14-bit R counter allows the input clock frequency to be divided down to produce the input clock to the phase frequency detector (PFD). Division ratios from 1 to 8191 are allowed. OVF RxBBIP RxININ RxBBIN A AND B COUNTERS 07373-005 RxINIP DC OFFSET CORRECTION Figure 12. Rx Filter The Rx section of the ADF9010 features programmable baseband low-pass filters. These are used to amplify the desired Rx signal from the demodulator while removing the unwanted portion to ensure no antialiasing occurs in the Rx ADC. These filters have a programmable gain stage, allowing gain to be selected from 3 dB to 24 dB in steps of 3 dB. The bandwidth of these filters is also programmable, allowing 3 dB cutoff frequencies of 330 kHz, 880 kHz, and 1.76 MHz, along with a bypass mode. The filters utilize a fourth-order Bessel transfer function (see the Specifications section for more information). If desired, the filter stage can be bypassed. Additionally, a rising edge on the OVF pin reduces the gain of the Rx amplifiers by 6 dB. This is to correct a potential overflow of the input to the ADC. The A and B CMOS counters combine with the dual modulus prescaler to allow a wide range of division ratios in the PLL feedback counter. The counters are specified to work when the prescaler output is 300 MHz or less. Pulse Swallow Function The A and B counters, in conjunction with the dual-modulus prescaler (see Figure 14), make it possible to generate large divider ratios. The equation for N is as follows: N = BP + A where: N is the overall divider ratio of the signal from the external RF input. P is the preset modulus of the dual-modulus prescaler. B is the preset divide ratio of the binary 13-bit counter (3 to 8191). A is the preset divide ratio of the binary 5-bit swallow counter (0 to 31). N = BP + A 13-BIT B COUNTER Updating the Rx calibration latch with the calibration bit enabled calibrates the filter to remove any dc offset. The 3 dB cutoff frequency (fC) of the filters is calibrated also. FROM RF INPUT STAGE LO SECTION PRESCALER P/P + 1 MODULUS CONTROL LOAD LOAD 6-BIT A COUNTER LO Reference Input Section The LO input stage is shown in Figure 13. SW1 and SW2 are normally closed switches; SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down. POWER-DOWN CONTROL NC 100kΩ SW2 TO R COUNTER BUFFER SW1 SW3 NO Figure 13. Reference Input Stage 07373-006 REFIN NC TO PFD N DIVIDER 07373-007 PGA SETTING Figure 14. A and B Counters Prescaler (P/P + 1) The dual-modulus prescaler (P/P + 1), along with the A and B counters, enables the large division ratio, N, to be realized (N = BP + A). The dual-modulus prescaler, operating at CML levels, takes the clock from the RF input stage and divides it down to a manageable frequency for the A and B CMOS counters. The prescaler is programmable. The prescaler can be set in software to 8/9, 16/17, or 32/33. For the ADF9010, however, the 16/17 and 32/33 settings should be used. It is based on a synchronous 4/5 core. A minimum divide ratio is possible for fully contiguous output frequencies. This minimum is determined by P, the prescaler value, and is given by (P2 − P). Rev. 0 | Page 12 of 28 ADF9010 DVDD PFD and Charge Pump The phase frequency detector (PFD) takes inputs from the R counter and N counter (N = BP + A) and produces an output proportional to the phase and frequency difference between them (see Figure 15). VP D1 Q1 DIGITAL LOCK DETECT R COUNTER OUTPUT MUX MUXOUT CONTROL N COUNTER OUTPUT SDOUT UP U1 R DIVIDER 07373-114 HI CHARGE PUMP ANALOG LOCK DETECT DGND Figure 16. MUXOUT Circuit CLR1 Voltage-Controlled Oscillator (VCO) CLR2 HI D2 Q2 The VCO core in the ADF9010 uses 16 overlapping bands, as shown in Figure 17, to allow a wide frequency range to be covered with a low VCO sensitivity (KV) and to result in good phase noise and spurious performance. The VCO operates at 4× the LO frequency, providing an output range of 840 MHz to 960 MHz. CP U3 DOWN The correct band is chosen automatically by the band select logic at power-up or whenever the LO latch is updated. During band select, which takes five PFD cycles, the VCO VTUNE is disconnected from the output of the loop filter and connected to an internal reference voltage. U2 N DIVIDER CPGND R DIVIDER 3.5 CP OUTPUT 3.0 07373-008 N DIVIDER 2.5 VTUNE (V) Figure 15. PFD Simplified Schematic and Timing (In Lock) MUXOUT The output multiplexer on the ADF9010 allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M3, M2, and M1 in the control latch. The full truth table is shown in Figure 22. Figure 16 shows the MUXOUT section in block diagram form. 2. 1.5 1.0 SERIES 1 0.5 0 750 Lock Detect MUXOUT can be programmed for two types of lock detect: digital and analog. Digital lock detect is active high. If the LDP in the R counter latch is set to 0, digital lock detect is set high when the phase error on three consecutive phase detector cycles is less than 15 ns. With the LDP set to 1, five consecutive cycles of less than 15 ns phase error are required to set the lock detect. It stays set high until a phase error of greater than 25 ns is detected on any subsequent PD cycle. The N-channel open-drain analog lock detect should be operated with an external pull-up resistor of 10 kΩ nominal. When a lock has been detected, this output is high with narrow low-going pulses. 07373-020 DELAY 800 850 900 FREQUENCY (Hz) 950 1000 Figure 17. VCO Bands The R counter output is used as the clock for the band select logic and should not exceed 1 MHz. A programmable divider is provided at the R counter input to allow division by 1, 2, 4, or 8 and is controlled by Bit BSC1 and Bit BSC2 in the Tx latch. Where the required PFD frequency exceeds 1 MHz, the divide ratio should be set to allow enough time to select the correct band. After the band is selected, normal PLL action resumes. The nominal value of KV is 32 MHz/V or 8 MHz/V, taking into account the divide by 4. The output from the VCO is divided by 4 for the LO inputs to the mixers, and for the LO output drive to the demodulator. Rev. 0 | Page 13 of 28 ADF9010 LO Output Mixers The LOOUTP and LOOUTN pins are connected to the collectors of an NPN differential pair driven by buffered outputs from the VCO, as shown in Figure 18. To allow optimal power dissipation vs. the output power requirements, the tail current of the differential pair is programmable via Bit TP1 and Bit TP2 in the control latch. The four current levels that can be set are: 6 mA, 8.5 mA, 11.5 mA, and 17.5 mA. These levels give output power levels of −4 dBm, −1 dBm, +2 dBm, and +5 dBm, respectively, if both outputs are combined in a 1 + 1:1 transformer or a 180° microstrip coupler. The ADF9010 has two double-balanced mixers, one for the in-phase channel (I channel) and one for the quadrature channel (Q channel). Both mixers are based on the Gilbert cell design of four cross-connected transistors. If the outputs are used individually, the optimum output stage consists of a shunt inductor to VDD. Another feature of the ADF9010 is that the supply current to the RF output stage is shut down until the part achieves lock as measured by the digital lock detect circuitry. This is enabled by the mute Tx until lock detect (F4) bit in the control latch. LOOUTP The TxOUTP and TxOUTN pins of the ADF9010 are connected to the collectors of four NPN differential pairs driven by the baseband signals, as shown in Figure 20. To allow the user optimal power dissipation vs. the output power requirements, the tail current of the differential pair is programmable via Bit TP1 and Bit TP2 in the control latch. Two levels can be set; these levels give output power levels of −3 dBm and, +3 dBm, respectively, using a 50 Ω resistor to VDD and ac coupling into a 50 Ω load. Alternatively, both outputs can be combined in a 1 + 1:1 transformer or a 180° microstrip coupler. This buffer can be powered off if desired. Another feature of the ADF9010 is that the supply current to the Tx output stage is shut down until the part achieves lock as measured by the digital lock detect circuitry. This is enabled by the mute LO until lock detect bit (F5) in the control latch. BUFFER/ DIVIDE BY 4 TxOUTP TxOUTN Figure 18. LO Output Section LOIP LOIN LOQP LOQN IP Tx SECTION IN ÷4 LOOUTP LOOUTN TXBBIN TxOUTN QUAD PHASE SPLITTER INT/ EXT LOEXT P LOEXT N TxBBQP TxBBQN 07373-011 TxOUTP QN Figure 20. Tx Section VCO TXBBIP QP 07373-012 07373-010 VCO LOOUTN Tx Output Figure 19. Tx Section Tx Baseband Inputs Differential in-phase (I) and quadrature baseband (Q) inputs are high impedance inputs that must be dc-biased to approximately 500 mV dc and e driven from a low impedance source. Nominal characterized ac signal swing is 700 mV p-p on each pin. This results in a differential drive of 1.4 V p-p with a 500 mV dc bias. INTERFACING Input Shift Register The digital section of the ADF9010 includes a 24-bit input shift register. Data is clocked into the 24-bit shift register on each rising edge of SCLK. The data is clocked in MSB first. Data is transferred from the shift register to one of four latches on the rising edge of SLE. The destination latch is determined by the state of the two control bits (C2, C1) in the shift register. These are the two LSBs, DB1 and DB0, as shown in Figure 21. The truth table for Bit C3, Bit C2, and Bit C1 is shown in Table 7. It displays a summary of how the latches are programmed. Note that some bits are used for factory testing and should not be programmed by the user. Table 7. Truth Table C3 X 0 1 X X Rev. 0 | Page 14 of 28 Control Bits C2 C1 0 0 0 1 0 1 1 1 0 1 Data Latch Control latch Tx latch Rx calibration LO latch Rx filter ADF9010 LATCH STRUCTURE Figure 21 shows the three on-chip latches for the ADF9010. The two LSBs determine which latch is programmed. MUTE MUTE Tx LO UNTIL UNTIL LD LD DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 RES PD4 PD3 PD2 PD1 TP2 TP1 CPI3 CPI2 CPI1 P2 P1 F4 F5 F3 COUNTER RESET LO OUTPUT POWER PD POLARITY CHARGE PUMP CURRENT CP THREESTATE Tx OUTPUT POWER PD Tx PD VCO PD PLL PD Rx RESERVED CONTROL LATCH MUXOUT CONTROL BITS RESERVED DB8 DB7 DB6 DB5 DB4 DB3 DB2 F2 M3 M2 M1 F1 RES RES DB1 DB0 C2 (0) C1 (0) Tx LATCH Tx MOD LO PHASE SELECT LO PHASE SELECT BAND SELECT CLOCK DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 P2 P3 P1 T3 T2 T1 BSC2 BSC1 CONTROL BITS 13-BIT REFERENCE COUNTER R13 R12 R11 R10 R9 R8 R7 DB8 DB7 DB6 DB5 DB4 DB3 R6 R5 R4 R3 R2 R1 DB2 DB1 DB0 C3 (0) C2 (0) C1 (1) Tx MOD LO PHASE SELECT LO PHASE SELECT BAND SELECT CLOCK Rx FILTER CAL Rx CALIBRATION HIGH-PASS FILTER BOOST TIMEOUT COUNTER Rx CALIBRATION DIVIDER CONTROL BITS DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 RC1 HP6 HP5 HP4 HP3 HP2 HP1 C3 (1) C2 (0) C1 (1) P3 P2 P1 T3 T2 T1 BSC2 BSC1 R13 RC6 RC5 RC4 RC3 RC2 DB2 DB1 DB0 N DIV MUX PRESCALER CP GAIN LO LATCH 13-BIT B COUNTER DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 P2 P1 G1 M1 B13 B12 B11 B10 B9 B8 B7 B6 CONTROL BITS 5-BIT A COUNTER B5 B4 B3 DB8 DB7 DB6 DB5 DB4 DB3 DB2 B2 B1 A5 A4 A3 A2 A1 DB1 DB0 C2 (1) C2 (0) TEST MODES DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 T16 T15 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 Figure 21. Latch Summary Rev. 0 | Page 15 of 28 T2 Rx FILTER BANDWIDTH Rx FILTER GAIN STEPS DB8 DB7 DB6 DB5 DB4 DB3 DB2 T1 HP BW2 BW1 G3 G2 G1 CONTROL BITS DB1 DB0 C2 (1) C1 (1) 07373-014 HPF BOOST Rx LATCH MUTE MUTE LO Tx UNTIL UNTIL LD LD DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 PD4 PD3 PD2 PD1 TP2 TP1 CPI3 CPI2 CPI1 P2 P1 F5 F4 F3 MUXOUT DB8 DB7 DB6 DB5 DB4 DB3 DB2 F2 M3 M2 M1 F1 RES RES F1 0 1 POWER DOWN Rx DISABLED ENABLED PD3 0 1 CONTROL BITS DB1 COUNTER OPERATION NORMAL COUNTERS HELD IN RESET M3 0 0 M2 0 0 M1 0 1 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 1 0 1 OUTPUT THREE-STATE OUTPUT DIGITAL LOCK DETECT (ACTIVE HIGH) N DIVIDER OUTPUT DVDD R DIVIDER OUTPUT N-CHANNEL OPEN-DRAIN LOCK DETECT SERIAL DATA OUTPUT DGND POWER DOWN PLL DISABLED ENABLED PD2 0 1 F2 0 1 POWER DOWN VCO DISABLED ENABLED PD1 0 1 POWER DOWN Tx DISABLED ENABLED F3 0 1 TP2 0 0 1 1 TP1 0 1 0 1 Tx OUTPUT POWER FULLY ON –6dB –6dB MUTE F4 0 1 ICP (mA) CPI3 0 0 0 0 1 1 1 1 CPI2 0 0 1 1 0 0 1 1 CPI1 0 1 0 1 0 1 0 1 2.7kΩ 1.25 2.50 3.75 5.00 6.25 7.50 8.75 10.0 4.7kΩ 0.63 1.25 1.87 2.50 3.13 3.75 4.38 5.00 10kΩ 0.31 0.63 0.94 1.25 1.56 1.87 2.19 2.50 PHASE DETECTOR POLARITY NEGATIVE POSITIVE CHARGE PUMP OUTPUT NORMAL THREE-STATE MUTE Tx UNTIL LOCK DETECT DISABLED ENABLED MUTE LO UNTIL LOCK DETECT DISABLED ENABLED F5 0 1 P2 P1 LO OUTPUT POWER (COMBINED) 0 0 1 1 0 1 0 1 –4 dBm –1 dBm +2 dBm +5 dBm Figure 22. Control Latch Rev. 0 | Page 16 of 28 DB0 C2 (0) C1 (0) THESE BITS ARE RESERVED AND SHOULD BE SET TO 0, 1 THIS BIT IS RESERVED FOR FACTORY TESTING AND SHOULD BE SET TO 0 PD4 0 1 RESERVED 07373-015 RES COUNTER RESET LO OUTPUT POWER PD POLARITY CHARGE PUMP CURRENT CP THREESTATE Tx OUTPUT POWER PD Tx PD VCO PD PLL PD Rx RESERVED ADF9010 ADF9010 Tx MOD LO PHASE SELECT LO PHASE SELECT BAND SELECT CLOCK DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 P2 P3 P1 T3 T2 T1 BSC2 BSC1 CONTROL BITS 13-BIT REFERENCE COUNTER R13 R12 R11 R10 R9 R8 DB8 DB7 DB6 DB5 DB4 DB3 R6 R5 R4 R3 R2 R1 R7 DB2 DB1 DB0 C3 (0) C2 (0) C1 (1) X = DON’T CARE BSC2 0 0 1 1 BSC1 0 1 0 1 R13 0 0 0 R12 0 0 0 R11 0 0 0 .......... .......... .......... .......... R3 0 0 0 R2 0 1 1 R1 1 0 1 DIVIDE RATIO 1 2 3 0 . 0 . 0 . .......... .......... 1 . 0 . 0 . 4 . . . 1 1 . . 1 1 . . 1 1 .......... .......... .......... .......... . . 1 1 . . 0 0 . . 0 1 . . 8188 1 1 1 .......... 1 1 0 8189 8190 1 1 1 .......... 1 1 1 8191 BAND SELECT CLOCK DIVIDER NOT ALLOWED NOT ALLOWED NOT ALLOWED 8 THESE BITS ARE RESERVED AND SHOULD BE SET TO 1,1 P3 0 0 0 0 1 1 1 1 P2 0 0 1 1 0 0 1 1 P1 0 1 0 1 0 1 0 1 T2 0 0 1 1 X T1 0 1 0 1 X OUTPUT NORMAL QUADRATURE I TO BOTH Q TO BOTH EXTERNAL LO, QUADRATURE ALL OFF OUTPUT I OUT Q OUT IB OUT QB OUT EXTERNAL I EXTERNAL Q EXTERNAL I TO PLL, OUT OFF ALL OFF 07373-016 T3 0 0 0 0 1 Figure 23. Tx Latch Rev. 0 | Page 17 of 28 BAND SELECT CLOCK Tx MOD LO PHASE SELECT LO PHASE SELECT Rx FILTER CAL ADF9010 HIGH-PASS FILTER BOOST TIMEOUT COUNTER Rx CALIBRATION DIVIDER CONTROL BITS DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 RC1 HP6 HP5 HP4 HP3 HP2 HP1 C3 (1) C2 (0) C1 (1) P3 P2 P1 T3 T2 T1 BSC2 BSC1 R13 RC6 RC5 RC4 RC3 RC2 DB2 DB1 DB0 X = DON’T CARE BSC2 0 0 1 1 BSC1 0 1 0 1 F5 Rx FILTER fC CALIBRATION 0 1 DISABLED ENABLED BAND SELECT CLOCK DIVIDER NOT ALLOWED NOT ALLOWED NOT ALLOWED 8 HP6 .......... HP2 HP1 TIMEOUT COUNTER CYCLES 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... 0 0 1 1 . . . 0 0 1 1 0 1 0 1 . . . 0 1 0 1 0 1 2 3 . . . 60 61 62 63 THESE BITS ARE RESERVED AND SHOULD BE SET TO 1,1 P2 0 0 1 1 X T2 0 0 1 T1 0 1 0 OUTPUT NORMALQUADRATURE I TO BOTH Q TO BOTH 0 1 1 X 1 X EXTERNAL LO, QUADRATURE ALL OFF P1 0 1 0 1 X OUTPUT I OUT Q OUT IB OUT QB OUT ALL OFF CAL COUNTER DIVIDE RATIO RC6 .......... RC2 RC1 0 0 0 0 .......... .......... .......... .......... 0 0 1 1 0 1 0 1 0 1 2 3 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... . . . 0 0 1 1 . . . 0 1 0 1 . . . 60 61 62 63 Figure 24. Rx Calibration Latch Rev. 0 | Page 18 of 28 07373-017 P3 0 0 0 0 1 T3 0 0 0 PRESCALER N DIV MUX CP GAIN ADF9010 13-BIT B COUNTER DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 P2 P1 G1 M1 B13 B12 B11 B10 B9 B8 B7 B6 CONTROL BITS 5-BIT A COUNTER B5 B4 B3 DB8 DB7 DB6 DB5 DB4 DB3 DB2 B2 B1 A5 A4 A3 A2 A1 DB1 DB0 C2 (1) C2 (0) X = DON’T CARE A5 N DIV MUX OPERATION 0 1 VCO FEEDBACK TO N DIVIDER. MUX FEEDBACK TO N DIVIDER. .......... .......... 0 0 0 .......... .......... .......... 0 1 1 1 0 1 1 2 3 . . . 1 .......... .......... .......... .......... . . . 0 . . . 0 . . . 28 1 .......... 0 1 29 1 .......... 1 0 30 1 .......... 1 1 31 B12 B11 B3 B2 B1 B COUNTER DIVIDE RATIO 0 0 .......... 0 0 0 NOT ALLOWED 0 0 0 0 0 0 0 0 0 .......... .......... .......... 0 0 0 0 1 1 1 0 1 NOT ALLOWED NOT ALLOWED 3 . . . 1 1 1 1 . . . 1 1 1 1 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... . . . 1 1 1 1 . . . 0 0 1 1 . . . 0 1 0 1 . . . 8188 8189 8190 8191 OPERATION USE THE PROGRAMMED CHARGE PUMP CURRENT SETTING FROM CONTROL REGISTER 1 USE THE MAXIMUM CHARGE PUMP CURRENT SETTING A COUNTER DIVIDE RATIO 0 B12 0 A1 0 0 0 0 CP GAIN A2 P2 P1 PRESCALER VALUE 0 0 1 1 0 1 0 1 8/9 16/17 32/33 32/33 07373-018 N = BP + A, P IS THE PRESCALER VALUE SET IN THE FUNCTION LATCH. B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTINUOUSLY ADJACENT VALUES OF (N × F REF) AT THE OUTPUT, NMIN IS (P2 – P). Figure 25. LO Latch Rev. 0 | Page 19 of 28 HPF BOOST ADF9010 TEST MODES T16 T15 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 DB7 DB6 DB5 DB4 DB3 DB2 T1 HP BW2 BW1 G3 G2 G1 C2 (1) C1 (1) G1 0 1 0 1 0 1 0 1 FILTER GAIN 3dB 6dB 9dB 12dB 15dB 18dB 21dB 24dB THESE BITS ARE USED FOR FACTORY TESTING AND SHOULD NOT BE PROGRAMMED BY THE USER. THEY SHOULD BE SET TO 0. Rev. 0 | Page 20 of 28 G2 0 0 1 1 0 0 1 1 DB1 DB0 HPF BOOST DISABLED ENABLED BW2 0 0 1 1 Figure 26. Rx Latch CONTROL BITS DB8 G3 0 0 0 0 1 1 1 1 HP 0 1 Rx FILTER GAIN STEPS BW1 0 1 0 1 Rx FILTER BANDWIDTH LOW 1MHz 2MHz BYPASSED 07373-019 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 Rx FILTER BANDWIDTH ADF9010 CONTROL LATCH Tx LATCH With (C2, C1) = (0, 0), the control latch is programmed. Figure 22 shows the input data format for programming the control latch. With (C3, C2, C1) = (0, 0, 1), the Tx latch is programmed. Figure 23 shows the input data format for programming the Tx latch. Power-Down LO Phase Select Programming a 1 to PD4, PD3, PD2, PD1 powers down the circuitry for the Rx filters, PLL, VCO, and Tx sections, respectively. Programming a 0 enables normal operation for each section. Bit P3, Bit P2, and Bit P1 set the phase of the LO output to the demodulator. This enables the user to select the phase delay of the Rx LO signal to the demodulator in 90° steps. See the truth table in Figure 23. The Rx LO output can be disabled if desired. Tx Output Power Tx Modulation LO Phase Select Bit TP1 and Bit TP2 set the output power level of the VCO. See the truth table in Figure 22. Bit T3, Bit T2, and Bit T1 set the input modulation of the VCO. Normal quadrature to each mixer can be replaced by choosing one LO phase to both mixers if desired. The normal (I) or quadrature (Q) phase can be chosen. See the truth table in Figure 23. Charge Pump Current Bit CPI3, Bit CPI2, and Bit CPI1 determine Current Setting 2. See the truth table in Figure 22. LO Output Power Bit P1 and Bit P2 set the output power level of the LO. See the truth table in Figure 22. Mute LO Until Lock Detect R13 to R1 set the counter divide ratio. The divide range is 1 (00 … 001) to 8191 (111 … 111). Rx CALIBRATION LATCH Mute Tx Until Lock Detect With (C3, C2, C1) = (1, 0, 1), the Rx calibration latch is programmed. Figure 24 shows the input data format for programming the Rx calibration latch. Bit F4 is the mute Tx until lock detect bit. This function, when enabled, ensures that the Tx outputs are not switched on until the PLL is locked. LO Phase Select Charge Pump Three-State Bit F3 puts the charge pump into three-state mode when programmed to a 1. It should be set to 0 for normal operation. Phase Detector Polarity Bit F2 sets the phase detector polarity. The positive setting enabled by programming a 1 is used when using the on-chip VCO with a passive loop filter or with an active noninverting filter. It can also be set to 0. This is required if an active inverting loop filter is used. The on-chip multiplexer is controlled by M3, M2, and M1. See the truth table in Figure 22. Counter Reset Bit F1 is the counter reset bit for the PLL of the ADF9010. When this bit is set to 1, the R, A, and B counters are held in reset. For normal operation, this bit should be 0. Reserved Bits DB3 and DB2 are spare bits that are reserved. They should be programmed to 0 and 1, respectively. Bits BSC2 and Bit BSC1 set a divider for the band select logic clock input. The recommended setting is 1, 1, which programs a value of 8 to the divider. No other setting is allowed. Reference Counter Bit F5 is the mute until lock detect bit. This function, when enabled, ensures that the LO outputs are not switched on until the PLL is locked. MUXOUT Control Band Select Clock Bit P3, Bit P2, and Bit P1 set the phase of the LO output to the demodulator. This enables the user to select the phase delay of the Rx LO signal to the demodulator in 90° steps. See the truth table in Figure 24. The Rx LO output can be disabled if desired. Tx Modulation LO Phase Select Bit T3, Bit T2, and Bit T1 set the input modulation of the VCO. Normal quadrature to each mixer can be replaced by choosing one LO phase to both mixers if desired. The normal (I) or quadrature (Q) phase can be chosen. See the truth table in Figure 24. Band Select Clock Bit BSC2 and Bit BSC1 set a divider for the band select logic clock input. The recommended setting is 1, 1, which programs a value of 8 to the divider. No other setting is allowed. Rx Filter Calibration Setting Bit R13 high performs a calibration of the Rx filters’ cutoff frequency, fC. Setting this bit to 0 ensures the filter cutoff frequency calibration sequence is not initiated if this latch is programmed. Rev. 0 | Page 21 of 28 ADF9010 Rx Calibration Divider A Counter Latch Bit RC6 to Bit RC1 program a 6-bit divider, which outputs a divided REFIN signal to assist calibration of the cutoff frequency, fC, of the Rx filters. The calibration circuit uses this divideddown PLL reference frequency to ensure an accurate cutoff frequency in the Rx filter. The divider value should be chosen to ensure that the frequency of the divided down signal is exactly 2 MHz, that is, if a 32 MHz crystal is used as the PLL REFIN frequency, then a value of 16 should be programmed to the counter to ensure accurate calibration. Bit A5 to Bit A1 program the 5-bit A counter. The divide range is 0 (00000) to 31 (11111). High-Pass Filter Boost Timeout Counter In most applications of the ADF9010, a high-pass filter is placed between the demodulator outputs and the ADF9010 Rx inputs. The capacitors used in these filters may require a long charge up time, and to address this, a filter boost function exists that charges up the capacitor to ~1.6 V. The duration for this boost is set by the product of the period of the Rx calibration signal, (REFIN divided by the Rx calibration divider) and the 6-bit value programmed to these registers. This value can be as large as 63. Programming a value of 000000 leads to the calibration time being manually set by the HPF boost in the Rx latch. It becomes necessary in such cases to program this bit to 0 for normal Rx operation. LO LATCH Rx LATCH Program the Rx latch with (C2, C1) = (1, 1). Figure 26 shows the input data format for programming the LO latch. High-Pass Filter Boost This function is enabled by setting the HP bit to 1. A 0 disables this function. This is used to reduce settling time on the highpass filter from the Rx demodulator. This is usually used in conjunction with the high-pass filter boost counter (See the Rx Calibration Latch section). Rx Filter Bandwidth The Rx filter bandwidth is programmable and is controlled by Bit BW2 and Bit BW1. See the truth table in Figure 26. Rx Filter Gain Steps Bit G3 to Bit G1 set the gain of the Rx filters. The gain can vary from 3 dB to 24 dB in 3 dB steps. See the truth table in Figure 26. INITIALIZATION The correct initialization sequence for the ADF9010 is as follows: 1. Program the LO latch with (C2, C1) = (1, 0). Figure 25 shows the input data format for programming the LO latch. 2. Prescaler Bit P2 and Bit P1 in the LO latch set the prescaler values. 3. CP Gain Power-down all blocks: Tx, Rx, PLL, and VCO. Set the Tx output power off control latch to (1, 1). Set the LO phase select off (P1, P2, P3) in Tx latch to (1, 1, 1). Program the R1 latch with the desired R counter and Tx values. Program R5 with Rx calibration data for frequency calibration and high-pass filter boost. Program R0 to power up all LO and Tx/Rx blocks. Program R2 to encode correct LO frequency. Program R3 to power up Rx filter. Setting G1 to 0 chooses the programmed charge pump current setting from the control latch. Setting this bit to 1 chooses the maximum possible setting. 4. 5. 6. N Div Mux INTERFACING Setting M1 to 0 feeds the VCO signals back to the N divider. Setting this bit to 1 allows the mux signal to be fed back instead. The ADF9010 has a simple SPI®-compatible interface for writing to the device. SCLK, SDATA, and SLE control the data transfer. See Figure 2 for the timing diagram. The maximum allowable serial clock rate is 20 MHz. This means that the maximum update rate possible for the device is 833 kHz or one update every 1.2 μs. This is certainly more than adequate for systems that have typical lock times in hundreds of microseconds. B Counter Latch Bit B13 to Bit B1 program the B counter. The divide range is 3 (00 … 0011) to 8191 (11 … 111). Rev. 0 | Page 22 of 28 ADF9010 APPLICATIONS INFORMATION RXVDD VP AVDD CE DVDD VCM ADF9010 MxFE RxBBIP RxINIP RxININ SHA RxBBIN VCM DC OFFSET CORRECTION ADC OVF AGC RxBBQP Rx INQP RxINQN 24-BIT INPUT SHIFT REGISTER ANTENNA SWITCH MODULE DC OFFSET CORRECTION MUXOUT RSET CP SHA RxBBQN SCLK SDATA SLE Tx BASEBAND PLL CHARGE PUMP PHASE FREQUENCY DETECTOR REF IN R COUNTER B COUNTER N COUNTER N = BP + A VTUNE PRESCALER P/P + 1 A COUNTER DIGITAL CONTROL CEXT1 Rx BASEBAND CEXT2 CEXT3 CEXT4 CT BALUN LOOUTP CLK DATA LE EN TxBBIP LOOUTN PA MODULE 24-BIT INPUT SHIFT REGISTER DAC TxBBIN TxOUTP AUX DAC BALUN TxBBQP TxOUTN AUX DAC AUX DAC DAC TxBBQN AGND 07373-003 DGND Figure 27. Applications Diagram On the transmit side, the MxFE generates quadrature analog baseband signals, which are upconverted to RF using the integrated PLL and VCO. The modulated RF signals are combined using a balun and gained up to 30 dBm by a power amplifier. shunt capacitors and series inductors. Due to the large selfblocker, a 100 nF capacitor removes the dc generated by the self-blocker inherent to RFID systems. This system is used on the EVAL-ADF9010EBZ1 evaluation board. IHI DEMOD 100nF 0Ω 1.2nF RxINIP ADF9010 47pF ADL5382 DEMODULATOR CONNECTION ILO 0Ω 100nF Figure 28. ADL5382 to ADF9010 Rx Interface To receive the back-scattered signals from an RFID tag, the ADF9010 needs to be used with a high dynamic range demodulator, such as the ADL5382 that is suitable for RFID applications. Some extra filtration is provided by the optional Rev. 0 | Page 23 of 28 RxININ 07373-021 The diagram in Figure 27 shows the ADF9010 in an RFID application. The demodulator is driven by the LOOUTx pins of the ADF9010. This demodulator produces quadrature baseband signals that are gained up in the ADF9010 Rx filters. These filtered analog baseband signals are then digitized by the ADC on a mixed signal front-end (MxFE) part. The digital signals are then processed by DSP. ADF9010 LO AND Tx OUTPUT MATCHING The LO and Tx output stages are each connected to the collectors of an NPN differential pair driven by buffered outputs from the VCO or mixer outputs, respectively. The recommended matching for each of these circuits consists of a 7.5 nH shunt inductor to VDD, a 100 pF series capacitor, and in the case of the Tx output a 50:100 balun to combine the Tx outputs. The Anaren BD0810J50100A00 is ideally suited to this task. PCB DESIGN GUIDELINES The lands on the chip scale package (CP-48-1) are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land should be centered on the pad. This ensures that the solder joint size is maximized. The bottom of the chip scale package has a central thermal pad. The thermal pad on the printed circuit board should be at least as large as this exposed pad. On the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. This ensures that shorting is avoided. Thermal vias can be used on the printed circuit board thermal pad to improve thermal performance of the package. If vias are used, they should be incorporated in the thermal pad at a 1.2 mm pitch grid. The via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 oz. copper to plug the via. The user should connect the printed circuit board thermal pad to AGND. Rev. 0 | Page 24 of 28 ADF9010 OUTLINE DIMENSIONS 7.00 BSC SQ 0.60 MAX 37 36 PIN 1 INDICATOR 0.50 BSC 1 5.25 5.10 SQ 4.95 (BOTTOM VIEW) 25 24 13 12 0.25 MIN 5.50 REF 0.80 MAX 0.65 TYP SEATING PLANE PIN 1 INDICATOR EXPOSED PAD 6.75 BSC SQ 0.50 0.40 0.30 12° MAX 48 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 080108-A TOP VIEW 1.00 0.85 0.80 0.30 0.23 0.18 0.60 MAX Figure 29. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm × 7 mm Body, Very Thin Quad (CP-48-1) Dimensions shown in millimeters ORDERING GUIDE Model ADF9010BCPZ 1 ADF9010BCPZ-RL1 ADF9010BCPZ-RL71 EVAL-ADF9010EBZ1 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) Evaluation Board Z = RoHS Compliant Part. Rev. 0 | Page 25 of 28 Package Option CP-48-1 CP-48-1 CP-48-1 ADF9010 NOTES Rev. 0 | Page 26 of 28 ADF9010 NOTES Rev. 0 | Page 27 of 28 ADF9010 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07373-0-8/08(0) Rev. 0 | Page 28 of 28