® DAC725 Dual 16-Bit DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION ● COMPLETE DUAL VOUT DAC ● DOUBLE-BUFFERED INPUT REGISTER The DAC725 is a dual 16-bit DAC, complete with internal reference and output op amps. The DAC725 is designed to interface to an 8-bit microprocessor bus, but can also be interfaced to wider buses. The hybrid construction minimizes the digital feedthrough typically associated with products that combine the digital bus interface circuitry with high-accuracy analog circuitry. ● HIGH-SPEED DATA INPUT: Serial or Parallel ● HIGH ACCURACY: ±0.003% Linearity Error ● 14-BIT MONOTONICITY OVER TEMPERATURE ● PLASTIC PACKAGE ● CLEAR INPUT TO SET ZERO OUTPUT High Byte Low Byte The 16-bit data word is loaded into either of the DACs in two 8-bit bytes per 16-bit word. The versatility of the control lines allows the data word to be directed to either DAC, in any order. The voltage-out DACs are dedicated to a bipolar output voltage of ±10V. The output is immediately set to 0V when the Clear command is given. This feature, combined with the bus interfacing and complete DAC circuitry, makes the DAC725 ideal for automatic test equipment, power control, servo systems, and robotics applications. 8 D/A Latch 16 8 16Bit D/A (A) CS (A) 8-Bit Data Bus CS (B) Low Byte A0 A1 A2 Control Logic CLR High Byte WR (A) 8 D/A Latch 16 8 WR (B) 16Bit D/A (B) International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1987 Burr-Brown Corporation PDS-757D Printed in U.S.A. August, 1993 SPECIFICATIONS ELECTRICAL At TA = +25°C, VCC = ±15V, and after a 10-minute warm-up unless otherwise noted. DAC725JP PARAMETER MIN DAC725KP TYP MAX MIN TYP MAX UNITS * Bits * * * * V V µA µA ±0.0015 0.003 ±0.003 * * ±0.003 ±0.006 ±0.006 ±0.15 * * * * * % of FSR(2) % of FSR % of FSR % % of FSR Bits % of FSR/%VCC % of FSR/%VDD * * ±0.003 ±25 ±12 ±0.006 ±0.006 ppm/°C ppm of FSR/°C % of FSR % of FSR * * * 8 4 µs µs V/µs INPUT DIGITAL INPUT Resolution Bipolar Input Code Logic Levels(1): VIH VIL IIH (VI = +2.7V) IIL (VI = +0.4V) 16 Binary Twos Complement +2 –1 * +5.5 +0.8 1 1 * * TRANSFER CHARACTERISTICS ACCURACY Linearity Error Differential Linearity Error(3) At Bipolar Zero: KP(3, 4) Gain Error(5) Bipolar Zero Error(5) Montonicity Over Specified Temp. Range Power Supply Sensitivity: +VCC, –VCC VDD ±0.003 ±0.0045 ±0.006 ±0.012 ±0.07 ±0.05 ±0.2 ±0.1 ±0.0015 ±0.0001 ±0.006 ±0.001 13 DRIFT (Over Specified Temperature Range) Gain Drift Bipolar Zero Drift Differential Linearity Over Temperature(3) Linearity Error Over Temperature(3) 14 ±10 ±5 ±0.0045 SETTLING TIME (to ±0.003% of FSR)(6) 20V Step (2kΩ load) 1LSB Step at Worst-Case Code(7) Slew Rate ±0.012 ±0.012 4 2.5 10 OUTPUT Output Voltage Range(8) Output Current Output Impedance Short Circuit to Common Duration ±10 ±5 * * 0.15 Indefinite V mA Ω * * POWER SUPPLY REQUIREMENTS Voltage: +VCC –VCC VDD Current (No load, ±15V supplies): +VCC –VCC VDD Power Dissipation (±15V supplies) +11.4 –11.4 +4.5 +15 –15 +5 +29 –35 +6 920 +16.5 –16.5 +5.5 +35 –40 +10 1175 * * * +70 +150 * * * * * * * * * * * * * * * * V V V mA mA mA mW * * °C °C TEMPERATURE RANGE Specification Storage 0 –60 *Specification same as model to the left. NOTES: (1) Digital inputs are TTL, LSTTL, 54/74HC and 54/74HTC compatible over the specification temperature range. (2) FSR means Full-Scale Range. For example, for ±10V output, FSR = 20V. (3) ±0.0015% of FSR is equal to 1LSB in 16-bit resolution. ±0.003% of FSR is equal to 1LSB in 15-bit resolution. ±0.006% of FSR is equal to 1LSB in 14-bit resolution. (4) Error at input code 0000H (BTC). (5) Adjustable to zero with external trim potentiometer. Adjusting the gain potentiometer rotates the transfer function around the bipolar zero point. (6) Maximum represents the 3σ limit. Not tested for this parameter. (7) The bipolar worstcase code change is FFFFH to 0000H (BTC). (8) Minimum supply voltage for ±10V output swing is approximately ±13V. Output swing for ±12V supplies is at least ±9V. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® DAC725 2 CONNECTION DIAGRAM PIN DESCRIPTIONS PIN DESIGNATOR 1 CLR 2 3 VDD A2 4 A0 5 A1 6 D7 (D15) (MSB) 7 D6 (D14) 8 D5 (D13) 9 D4 (D12) CLR 1 28 GA (A) VDD 2 27 SJ (A) A2 3 26 ACOM (A) A0 4 25 VOUT (A) A1 5 24 WR (A) D7 (D15 ) 6 23 CS (A) D6 (D14 ) 7 22 –VCC D5 (D13 ) 8 21 +VCC D4 (D12 ) 9 20 CS (B) 10 D3 (D11) D3 (D11 ) 10 19 WR (B) 11 D2 (D10) D2 (D10 ) 11 18 GA (B) 12 D1 (D9) D1 (D9) 12 17 SJ (B) 13 D0 (D8) D0 (D8) 13 16 ACOM (B) 15 V OUT (B) 14 15 16 17 DCOM VOUT (B) ACOM (B) SJ (B) 18 19 20 GA (B) WR (B) CS (B) 21 +VCC 22 –VCC 23 CS (A) 24 25 26 27 WR (A) VOUT (A) ACOM (A) SJ (A) 28 GA (A) DCOM 14 High Byte Latch 8 D/A 16 Latch Low Byte Latch High Byte Latch 8 8 D/A 16 Latch Low Byte Latch 16Bit D/A 16Bit D/A 8 ABSOLUTE MAXIMUM RATINGS VDD to COMMON ........................................................................ 0V, +15V +VCC to COMMON ...................................................................... 0V, +18V –VCC to COMMON ...................................................................... 0V, –18V Digital Data Inputs to COMMON ...................................... –0.5V, VDD + 0.5 DC Current any Input ...................................................................... ±10mA Reference Out to COMMON ........................ Indefinite Short to COMMON VOUT ............................................................ Indefinite Short to COMMON External Voltage Applied to RF ......................................................... ±18V External Voltage Applied to D/A Output ............................................... ±5V Power Dissipation ........................................................................ 2000mW Storage Temperature ...................................................... –60°C to +150°C Lead Temperature (soldering, 10s) .................................................. 300°C DESCRIPTION Clear line. Sets the D/A register to 0000HEX, which gives bipolar zero on the D/A output. Logic supply (+5V). Latch enable for D/A latch (active low). Latch enable for “low byte” input (active low). Latch enable for “high byte” input (active low). Input for data bit 7 if enabling low byte (LB) latch, or data bit 15 if enabling the high byte (HB) latch. Input for data bit 6 if enabling LB latch, or data bit 14 if enabling HB latch. Data bit 5 (LB) or data bit 13 (HB). Data bit 4 (LB) or data bit 12 (HB). Data bit 3 (LB) or data bit 11 (HB). Data bit 2 (LB) or data bit 10 (HB). Data bit 1 (LB) or data bit 9 (HB). Data bit 0 (LB) or data bit 8 (HB). Digital common. Voltage output for DAC B. Analog common for DAC B. Summing junction of the internal op amp for DAC B. Gain adjust pin for DAC B. Write control line for DAC B. Chip select control line for DAC B. Positive supply voltage (+15V). Negative supply voltage (–15V). Chip select control line for DAC A. Write control line for DAC A. Voltage output for DAC A. Analog common for DAC A. Summing junction of the internal op amp for DAC A. Gain adjust pin for DAC A. NOTE: These devices are sensitive to electrostatic discharge. Appropriate I.C. handling procedures should be followed. PACKAGE INFORMATION Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. MODEL DAC725JP DAC725KP ORDERING INFORMATION MODEL DAC725JP DAC725KP LINEARITY ERROR max (% of FSR) TEMPERATURE RANGE ±0.012 ±0.006 0°C to +70°C 0°C to +70°C PACKAGE PACKAGE DRAWING NUMBER(1) 28-Pin Plastic DIP 28-Pin Plastic DIP 215 215 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. ® 3 DAC725 DISCUSSION OF SPECIFICATIONS Zero Drift Zero drift is a measure of change in the output with 0000H applied to the D/A converter inputs over the specified temperature range. This code corresponds to 0V analog output. DIGITAL INPUT CODES The DAC725 accepts positive-true binary twos complement input code, as shown in Table I. The data is loaded into either DAC, 8 bits at a time. The data may also be clocked into the device in a serial format. DIGITAL INPUT CODES ANALOG OUTPUT (Binary Two's Complement, Bipolar Operation, All Models) 7FFFH 0000H FFFFH 8000H + Full Scale Zero – 1LSB – Full Scale The maximum change in offset at tMIN or tMAX is referenced to the zero error at +25°C and is divided by the temperature change. This drift is expressed in FSR/°C. SETTLING TIME Settling time of the D/A is the total time required for the analog output to settle within an error band around its final value after a change in digital input. Refer to Figure 1 for typical values for this family of products. TABLE I. Digital Input Codes. Final-Value Error Band % of Full-Scale Range (±% of FSR) 1 ACCURACY Linearity This specification describes one of the most important measures of performance of a D/A converter. Linearity error is the deviation of the analog output from a straight line drawn through the end points (minus full-scale point and plus fullscale point). Differential Linearity Error Differential Linearity Error (DLE) of a D/A converter is the deviation from an ideal 1LSB change in the output when the input changes from one adjacent code to the next. A differential linearity error specification of ±1/2LSB means that the output step size can be between 1/2LSB and 3/2LSB when the input changes between adjacent codes. A negative DLE specification of –1LSB maximum (–0.006% for 14-bit resolution) insures monotonicity. 0.01 0.001 0.1 1 10 100 Settling Time (µs) FIGURE 1. Final-Value Error Band Versus Full-Scale Range Settling Time. Settling times are specified to ±0.003% of FSR (±1/2LSB for 14 bits) for two input conditions: a full-scale range change of 20V (±10V), and a 1LSB change at the “major carry,” the point at which the worst-case settling time occurs. This is the worst-case point since all of the input bits change when going from one code to the next. Monotonicity Monotonicity assures that the analog output will increase or remain the same for increasing input digital codes. The DAC725 is specified to be monotonic to 14 bits over the entire specification range. POWER SUPPLY SENSITIVITY Power supply sensitivity is a measure of the effect of a change in a power supply voltage on the D/A converter output. It is defined as a percent of FSR change in the output per percent of change in either the positive supply (+VCC), negative supply (–VCC) or logic supply (VDD) about the nominal power supply voltages (see Figure 2). It is specified for DC or low frequency changes. The typical performance curve in Figure 2 shows the effect of high frequency changes in power supply voltages. DRIFT Gain Drift Gain drift is a measure of the change in full-scale range output over temperature expressed in parts per million per degree centigrade (ppm/°C). Gain drift is established by: (1) testing the end point differences at tMIN, +25°C and tMAX, (2) calculating the gain error with respect to the +25°C value, and (3) dividing by the temperature change. The DAC725 is specified for Maximum Gain and Offset values at temperature. This tells the system designer the maximum that can be expected over temperature, regardless of room temperature values. ® DAC725 0.1 4 0.025 0.02 0.015 –15V Supply +15V Supply +5V Supply 0.01 0.005 DIGITAL INPUT CODE 16 Bits 15 Bits 14 Bits UNITS One LSB 7FFFH 8000H 305 +9.99969 –10 610 +9.99939 –10 1224 +9.99878 –10 µV V V BIPOLAR OUTPUT, ±10V TABLE II. Digital Input Codes. 0 1 10 100 1k 10k 100k Power Supply Ripple Frequency (Hz) INTERFACE LOGIC AND TIMING The control logic functions are chip select (CSA or CSB), write (WRA or WRB), latch enable (A0, A1, A2), and clear (CLR). These pins provide the control functions for the microprocessor interface. There is a write and a chip select for both DACA and for DACB channels. This allows the 8-bit data word to be latched from the data bus to the input latch or from the input latch to the DAC latch, of DACA, DACB, or both. FIGURE 2. Power Supply Rejection Versus Power Supply Ripple Frequency. OPERATING INSTRUCTIONS POWER SUPPLY CONNECTIONS For optimum performance and noise rejection, power supply decoupling capacitors should be added as shown in the Connection Diagram. 1µF to 10µF tantalum capacitors should be located close to the D/A converter. EXTERNAL ZERO AND GAIN ADJUSTMENT Zero and gain may be trimmed by installing external zero and gain potentiometers. Connect these potentiometers as shown in the Connection Diagram and adjust as described below. TCR of the potentiometers should be 100ppm/°C or less. The 3.9MΩ and 270kΩ resistors (±20% carbon or better) should be located close to the D/A converter to prevent noise pickup. If it is not convenient to use these high-value resistors, an equivalent “T” network, as shown in Figure 3, may be substituted in place of the 3.9MΩ resistor. A 0.001µF to 0.01µF low-leakage film capacitor should be connected from Gain Adjust to Analog Common to prevent noise pickup. Refer to Figure 4 for relationship of Offset and Gain adjustments. 180kΩ A1 A2 WR (A) CS (A) 1 1 1 0 0 0 X X 1 0 0 1 1 0 X X 0 1 0 1 0 1 X X 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 1 DESCRIPTION DAC latch enabled, Channel A Input latch high byte enabled, Channel A High byte flows through to DAC, Channel A Low byte latched from data bus, Channel A Low byte flows through to DAC, Channel A Serial input mode for byte latches No data is latched No data is latched “1” or “0” indicates TTL Logic Level Channel A shown. TABLE III. Truth Table of Data Transfers. 1LSB Analog Output 3.9MΩ A0 180kΩ 10kΩ Input = 8000H Full Scale Range % of FSR Error Per % of Change in VSUPPLY Gain Adjustment To adjust the gain of the DAC725, set the DAC to 7FFFH for both DACs. Adjust the gain of each DAC to obtain the full scale voltage of +9.99969V as shown in Table II. 0.03 + Full Scale Range of Gain Adjust Gain Adjust Rotates the Line Input = 7FFFH Input = 0000H Offset Adjust Translates the Line Range and Offset Adjust FIGURE 3. Equivalent Resistances. – Full Scale Zero Adjustment By loading the code 0000H, the DAC will force 0V. Offset is adjusted by using the circuit of Figure 5. An alternate method would be to use the CLR control to set the DAC to 0V. Zero calibration should be made before gain calibration. Digital Input FIGURE 4. Relationship of Zero and Gain Adjustments for the DAC725. ® 5 DAC725 The latch enable lines control which latch is being loaded. Line A1 in combination with WR and CS enables the high byte of the DAC channel to be latched through the byte latch. The A0 line, in conjunction with the WR and CS, latches the data for the low byte. When A2, CS, and WR are low at the same time, the data is latched through the D/A latch and the DAC changes output voltage. Each latch may be made transparent by maintaining its enable signal at logic “0”. OVER TEMP. INTERVAL tDW tCW tAW tWP tDH The serial data mode is activated when both A0 and A1 are at logic low simultaneously. The data (MSB first) is clocked in to pin 13 with clock pulses on the WR pin. The data is then latched through to the DAC as a complete 16-bit word selected by A2. DESCRIPTION ns, min Data valid to end of WR CS valid to end of WR A0, A1, A2 valid to end of WR Write pulse width Data hold after end of WR 80 80 80 80 0 t CW CS t AW A 0, A1, A2 The CLR line resets both input latches to all zeros and sets the DAC latch to 0000H. This is the binary code that gives a null, or zero, at the output of the DAC. t DW D0–D15, SI The maximum clock rate of the latches is 10MHz. The minimum time between the write (WR) pulses for successive enables is 20ns. In the serial input mode, the maximum rate at which data can be clocked into the input shift register is 10MHz. The timing of the control signals is given in Figure 6. t DH WR t WP FIGURE 6. Logic Timing Diagram. +VCC Gain Adjust (A) 270kΩ * 1 28 2 27 3 26 4 High Byte Latch 6 D/A 16 Latch 23 22 8 21 9 20 10 19 12 13 14 High Byte Latch +VCC Gain Adjust (B) 270kΩ * 18 8 D/A 16 Latch Low Byte Latch +VCC 24 8 7 11 * Offset Adjust (A) 25 16Bit D/A 16Bit D/A 0.0022µF 16 8 ® 6 * Offset Adjust (B) +VCC 15 FIGURE 5. Connections for Gain and Offset Adjust. –VCC 3.9MΩ 17 * 10kΩ to 100kΩ DAC725 –VCC 3.9MΩ 8 5 Low Byte Latch 0.0022µF ns, max INSTALLATION APPLICATIONS Because of the extremely high accuracy of the D/A converter, system design problems such as grounding and contact resistance become very important. For a 16-bit converter with a +10V full-scale range, 1LSB is 153µV. With a load current of 5mA, series wiring and connector resistance of only 30mΩ will cause the output to be in error by 1LSB. To understand what this means in terms of a system layout, the resistance of typical 1oz copper-clad printed circuit board material is approximately 1/2mΩ per square mil. In the example above, a 10mil-wide conductor 60mil long would cause a 1LSB error in R2 and R3 of Figure 7. WAVEFORM GENERATION The DAC725 has attributes that make it ideal for very low distortion waveform synthesis. Due to special design techniques, the feedthrough energy is much lower than that found in other D/A converters available today. In addition to the low feedthrough glitch energy, the input logic will operate with data rates of 10MHz. This makes the DAC725 ideal for waveform synthesis. PROGRAMMABLE POWER SUPPLIES The DAC725 is an excellent choice for programmable power supply applications. The DAC outputs may be programmed to track or oppose each other. If the load is floating, and can be driven differentially, the dynamic range will be 17 bits, because the full-scale range doubles for the same sized LSB. The clear line (CLR) sets both DAC outputs to zero, and would be used at power-up to bring the system up in a safe state. The CLR line could also be used if an over-power state is sensed. In Figure 7, lead and contact resistances are represented as R2 through R6. As long as the load resistance (RL) remains constant, the resistances of R2 and R3 will appear as gain errors when the output is sensed across the load. If the output is sensed at the DAC725 output terminal and the system analog common, R2 and R3 appear in series with RL. R4 has a current through it that varies by only 1% of the nominal 2mA current for all code combinations. This IR drop causes an offset error, and is calibrated out as an offset error. ISOLATION The current through the digital common varies directly with the digital code that is loaded into the DAC. The current is not the same for each code. If this IR drop is allowed to modulate the analog common, there may be code-dependent errors in the analog output. The DAC725 can accept serial input data, which means that only six optoisolators are needed for two DACs. The data is clocked into the input latch using the WR pin. The 16-bit data word is latched into the DAC selected by A2. When A0 and A1 are simultaneously low, the serial mode is enabled. The IR drop across R6 may cause accuracy problems if the analog commons of several circuits are “daisy chained” along the power supply analog common. All analog sense lines should be referenced to the system analog common. High Byte Low Byte 8 D/A Latch 8 0 to 2mA Typ High Byte Low Byte 16Bit D/A (A) R2 Out A R4 0 to 2mA Typ 8-Bit Data Bus 16 ≈ 2mA Constant Analog Common A 0 to 4mA Typ 8 D/A Latch 16 8 ≈ 2mA Constant Digital Common 16Bit D/A (B) System Analog Common R5 RL R3 Out B +VDD V DD Supply Analog Common B ±VCC Supply Digital Common +VCC R6 Analog Common –VCC FIGURE 7. System Wiring Example. ® 7 DAC725