® DAC714 16-Bit DIGITAL-TO-ANALOG CONVERTER With Serial Data Interface FEATURES: DESCRIPTION ● SERIAL DIGITAL INTERFACE The DAC714 is a complete monolithic digital-toanalog converter including a +10V temperature compensated reference, current-to-voltage amplifier, a high-speed synchronous serial interface, a serial output which allows cascading multiple converters, and an asynchronous clear function which immediately sets the output voltage to midscale. ● VOLTAGE OUTPUT: ±10V, ±5V, 0 to +10V ● ±1 LSB INTEGRAL LINEARITY ● 16-BIT MONOTONIC OVER TEMPERATURE ● PRECISION INTERNAL REFERENCE ● LOW NOISE: 120nV/√Hz Including Reference ● 16-LEAD PLASTIC AND CERAMIC SKINNY DIP AND PLASTIC SOIC PACKAGES The output voltage range is ±10V, ±5V, or 0 to +10V while operating from ±12V or ±15V supplies. The gain and bipolar offset adjustments are designed so that they can be set via external potentiometers or external D/A converters. The output amplifier is protected against short circuit to ground. The 16-pin DAC714 is available in a plastic 0.3" DIP, ceramic 0.3" CERDIP, and wide-body plastic SOIC package. The DAC714P, U, HB, and HC are specified over the –40°C to +85°C temperature range while the DAC714HL is specified over the 0°C to +70°C range. A0 Input Shift Register A1 SDI SDO 16 RFB2 CLK D/A Latch CLR 16 Reference Circuit Gain Adjust 16-Bit D/A Converter VOUT VREF OUT +10V RBPO Offset Adjust International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1994 Burr-Brown Corporation PDS-1252D 1 Printed in U.S.A. July, 1997 DAC714 SPECIFICATIONS At TA = +25°C, +VCC = +12V and +15V, –VCC = –12V, and –15V, unless otherwise noted. DAC714P, U PARAMETER MIN TYP DAC714HB MAX MIN TYP DAC714HC MAX MIN TYP DAC714HL MAX MIN TYP MAX UNITS ±1 ±2 ±1 ±1 LSB LSB LSB LSB Bits Bits % % % of FSR(2) % of FSR %FSR/%VCC ppm FSR/%VCC TRANSFER CHARACTERISTICS ACCURACY Linearity Error TMIN to TMAX Differential Linearity Error TMIN to TMAX Monotonicity Monotonicity Over Spec Temp Range Gain Error(3) TMIN to TMAX Unipolar/Bipolar Zero Error(3) TMIN to TMAX Power Supply Sensitivity of Gain ±4 ±8 ±4 ±8 14 13 REFERENCE VOLTAGE Voltage TMIN to TMAX Output Resistance Source Current Short Circuit to ACOM Duration 15 14 6 4 10 10 6 4 10 ±0.1 ±0.25 ±0.1 ±0.2 ±0.003 ±30 10 6 4 10 0.005 0.03 3.0 87 2 15 120 ±10 ±5 0.1 Indefinite +9.975 +9.960 1 2 10 6 4 10 2 +9.975 +9.960 V mA Ω 0.1 Indefinite +10.000 +10.025 +10.040 1 2 +9.975 +9.960 +10.000 +10.025 +10.040 1 2 Indefinite Indefinite Indefinite Indefinite 16 16 16 16 µs µs V/µs % % % dB nV–s nV–s nV/√Hz ±10 ±5 0.1 Indefinite +10.000 +10.025 +10.040 1 10 0.005 0.03 3.0 87 2 15 120 ±10 ±5 0.1 Indefinite +10.025 +10.040 ±0.1 ±0.25 ±0.1 ±0.2 ±0.003 ±30 0.005 0.03 3.0 87 2 15 120 ±10 ±5 +10.000 16 16 ±0.1 ±0.25 ±0.1 ±0.2 ±0.003 ±30 0.005 0.03 3.0 87 2 15 120 +9.975 +9.960 ±1 ±2 ±1 ±2 16 15 ±0.1 ±0.25 ±0.1 ±0.2 ±0.003 ±30 DYNAMIC PERFORMANCE Settling Time (to ±0.003%FSR, 5kΩ || 500pF Load)(4) 20V Output Step 1LSB Output Step(5) Output Slew Rate Total Harmonic Distortion 0dB, 1001Hz, fS = 100kHz –20dB, 1001Hz, fS = 100kHz –60dB, 1001Hz, fS = 100kHz SINAD: 1001Hz, fS = 100kHz Digital Feedthrough(5) Digital-to-Analog Glitch Impulse(5) Output Noise Voltage (includes reference) ANALOG OUTPUT Output Voltage Range +VCC, –VCC = ±11.4V Output Current Output Impedance Short Circuit to ACOM Duration ±2 ±4 ±2 ±4 V V Ω mA INTERFACE RESOLUTION DIGITAL INPUTS Serial Data Input Code Logic Levels(1) VIH VIL +2.0 (VCC –1.4) +2.0 0 +0.8 0 Binary Two’s Complement (VCC –1.4) +2.0 +0.8 0 Bits (VCC –1.4) +2.0 (VCC –1.4) +0.8 0 +0.8 V V IIH (VI = +2.7V) ±10 ±10 ±10 ±10 µA IIL (VI = +0.4V) ±10 ±10 ±10 ±10 µA +0.4 +5 V V +15 –15 +16.5 –16.5 V V 13 22 16 26 625 mA mA mW +70 +150 °C °C °C/W DIGITAL OUTPUT Serial Data VOL (ISINK = 1.6mA) VOH (ISOURCE = 500µA), TMIN to TMAX POWER SUPPLY REQUIREMENTS Voltage +VCC –VCC Current (No Load, ±15V Supplies)(6) +VCC –VCC Power Dissipation(7) TEMPERATURE RANGES Specification All Grades Storage Thermal Coefficient, θJA 0 +2.4 +11.4 –11.4 +0.4 +5 0 +2.4 +15 –15 +16.5 –16.5 +11.4 –11.4 13 22 16 26 625 –40 –60 +85 +150 75 +0.4 +5 0 +2.4 +15 –15 +16.5 –16.5 +11.4 –11.4 13 22 16 26 625 –40 –60 +85 +150 75 +0.4 +5 0 +2.4 +15 –15 +16.5 –16.5 +11.4 –11.4 13 22 16 26 625 –40 –60 +85 +150 75 0 –60 75 NOTES: (1) Digital inputs are TTL and +5V CMOS compatible over the specification temperature range. (2) FSR means Full Scale Range. For example, for ±10V output, FSR = 20V. (3) Errors externally adjustable to zero. (4) Maximum represents the 3σ limit. Not 100% tested for this parameter. (5) For the worst-case Binary Two’s Complement code changes: FFFF H to 0000H and 0000H to FFFFH. (6) During power supply turn on, the transient supply current may approach 3x the maximum quiescent specification. (7) Typical (i.e. rated) supply voltages times maximum currents. ® DAC714 2 PIN CONFIGURATION PIN DESCRIPTIONS Top View SOIC/DIP CLK 1 16 CLR A0 2 15 –VCC A1 3 14 Gain Adjust SDI 4 13 Offset Adjust DAC714 SDO 5 12 VREF OUT DCOM 6 11 RBPO +VCC 7 10 RFB2 ACOM 8 9 VOUT ELECTROSTATIC DISCHARGE SENSITIVITY PIN LABEL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK A0 A1 SDI SDO DCOM +VCC ACOM VOUT RFB2 RBPO VREF OUT Offset Adjust Gain Adjust –VCC CLR DESCRIPTION Serial Data Clock Enable for Input Register (Active Low) Enable for D/A Latch (Active Low) Serial Data Input Serial Data Output Digital Ground Positive Power Supply Analog Ground D/A Output ±10V Range Feedback Output Bipolar Offset Voltage Reference Output Offset Adjust Gain Adjust Negative Power Supply Clear ORDERING INFORMATION Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. BurrBrown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. PRODUCT PACKAGE DAC714P DAC714U DAC714HB DAC714HC DAC714HL Plastic DIP Plastic SOIC Ceramic DIP Ceramic DIP Ceramic DIP LINEARITY ERROR max at +25°C ±4 ±4 ±2 ±1 ±1 LSB LSB LSB LSB LSB TEMPERATURE RANGE –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C 0°C to +70°C PACKAGE INFORMATION ABSOLUTE MAXIMUM RATINGS(1) PRODUCT PACKAGE PACKAGE DRAWING NUMBER(1) DAC714P DAC714U DAC714H Plastic DIP Plastic SOIC Ceramic DIP 180 211 129 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. +VCC to Common .................................................................... 0V to +17V –VCC to Common .................................................................... 0V to –17V +VCC to –VCC ....................................................................................... 34V ACOM to DCOM ............................................................................... ±0.5V Digital Inputs to Common ............................................. –1V to (VCC –0.7V) External Voltage Applied to BPO and Range Resistors ..................... ±VCC VREF OUT ......................................................... Indefinite Short to Common VOUT ............................................................... Indefinite Short to Common SDO ............................................................... Indefinite Short to Common Power Dissipation .......................................................................... 750mW Storage Temperature ...................................................... –60°C to +150°C Lead Temperature (soldering, 10s) ................................................ +300°C NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 DAC714 TIMING SPECIFICATIONS TRUTH TABLE TA = –40°C to +85°C, +VCC = +12V or +15V, –VCC = –12V or –15V. SYMBOL PARAMETER MIN tCLK tCL tCH tA0S tA1S tAOH tA1H tDS tDH tDSOP tCP Data Clock Period Clock LOW Clock HIGH Setup Time for A0 Setup Time for A1 Hold Time for A0 Hold Time for A1 Setup Time for DATA Hold Time for DATA Output Propagation Delay Clear Pulsewidth 100 50 50 50 50 0 0 50 10 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns 140 200 A0 A1 CLK CLR DESCRIPTION 0 1 1→0→1 1 Shift Serial Data into SDI Load D/A Latch 1 0 1→0→1 1 1 1 1→0→1 1 No Change 0 0 1→0→1 1 Two Wire Operation(1) X X 1 1 No Change X X X 0 Reset D/A Latch NOTES: X = Don’t Care. (1) All digital input changes will appear at the output. TIMING DIAGRAMS Serial Data In tCLK tCH tCL CLK tA 0H tA 0S A0 tDS Serial Data Input MSB First tDH D15 SDI D14 D0 tA 1S Latch Data In D/A Latch A1 Serial Data Out tCLK tCH tCL CLK tA tA 0S 0H A0 Serial Data Out D15 SDO D14 tDSOP tDSOP Clear CLR ® DAC714 D0 4 tCP tA 1H TYPICAL PERFORMANCE CURVES POWER SUPPLY REJECTION vs POWER SUPPLY RIPPLE FREQUENCY LOGIC vs V LEVEL 1k 2.0 –VCC 100 I Digital Input (µA) [Change in FSR]/[Change in Supply Voltage] (ppm of FSR/ %) At TA = +25°C, VCC = ±15V, unless otherwise noted. +VCC 10 1 100 1k 10k 100k A0, A1 CLR 0 SDI –1.0 –2.0 –0.85 0.1 10 1.0 1M 0 0.85 1.7 2.55 3.4 4.25 5.1 5.95 6.8 V Digital Input Frequency (Hz) SETTLING TIME, +10V TO –10V ± FULL SCALE OUTPUT SWING ∆ Around –10V (µV) VOUT (V) 10 0 2000 +5V 1500 0V A1 (V) 2500 1000 500 0 –500 –1000 –1500 –2000 –10 –2500 Time (1µs/div) Time (10µs/div) VOUT SPECTRAL NOISE DENSITY SETTLING TIME, –10V TO +10V 1000 +5V 1500 0V A1 2000 1000 100 nV/√Hz ∆ Around +10V (µV) 2500 500 0 –500 10 –1000 –1500 –2000 1 –2500 1 Time (1µs/div) 10 100 1k 10k 100k 1M 10M Frequency (Hz) ® 5 DAC714 DISCUSSION OF SPECIFICATIONS DIGITAL FEEDTHROUGH When the A/D is not selected, high frequency logic activity on the digital inputs is coupled through the device and shows up as output noise. This noise is digital feedthrough. LINEARITY ERROR Linearity error is defined as the deviation of the analog output from a straight line drawn between the end points of the transfer characteristic. OPERATION DIFFERENTIAL LINEARITY ERROR The DAC714 is a monolithic integrated-circuit 16-bit D/A converter complete with 16-bit D/A switches and ladder network, voltage reference, output amplifier and a serial interface. Differential linearity error (DLE) is the deviation from 1LSB of an output change from one adjacent state to the next. A DLE specification of ±1/2LSB means that the output step size can range from 1/2LSB to 3/2LSB when the digital input code changes from one code word to the adjacent code word. If the DLE is more positive than –1LSB, the D/A is said to be monotonic. INTERFACE LOGIC The DAC714 has double-buffered data latches. The input data latch holds a 16-bit data word before loading it into the second latch, the D/A latch. This double-buffered organization permits simultaneous update of several D/A converters. All digital control inputs are active low. Refer to the block diagram shown in Figure 1. MONOTONICITY A D/A converter is monotonic if the output either increases or remains the same for increasing digital input values. Monotonicity of the C and L grades is guaranteed over the specification temperature range to 16 bits. All latches are level-triggered. Data present when the enable inputs are logic “0” will enter the latch. When the enable inputs return to logic “1”, the data is latched. The CLR input resets both the input latch and the D/A latch to 0000H (midscale). SETTLING TIME Settling time is the total time (including slew time) for the D/A output to settle to within an error band around its final value after a change in input. Settling times are specified to within ±0.003% of Full Scale Range (FSR) for an output step change of 20V and 1LSB. The 1LSB change is measured at the Major Carry (FFFFH to 0000H, and 0000H to FFFFH: BTC codes), the input transition at which worst-case settling time occurs. LOGIC INPUT COMPATIBILITY The DAC714 digital inputs are TTL compatible (1.4V switching level), low leakage, and high impedance. Thus the inputs are suitable for being driven by any type of 5V logic Family, such as CMOS. An equivalent circuit for the digital inputs is shown in Figure 2. The inputs will float to logic “0” if left unconnected. It is recommended that any unused inputs be connected to DCOM to improve noise immunity. TOTAL HARMONIC DISTORTION Total harmonic distortion is defined as the ratio of the square root of the sum of the squares of the values of the harmonics to the value of the fundamental frequency. It is expressed in % of the fundamental frequency amplitude at sampling rate fS. Digital inputs remain high impedance when power is off. INPUT CODING The DAC714 is designed to accept binary two’s complement (BTC) input codes with the MSB first which are compatible with bipolar analog output operation. For this configuration, a digital input of 7FFFH produces a plus full scale output, 8000H produces a minus full scale output, and 0000H produces bipolar zero output. SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) SINAD includes all the harmonic and outstanding spurious components in the definition of output noise power in addition to quantizing and internal random noise power. SINAD is expressed in dB at a specified input frequency and sampling rate, fS. INTERNAL REFERENCE The DAC714 contains a +10V reference. The reference output may be used to drive external loads, sourcing up to 2mA. The load current should be constant, otherwise the gain and bipolar offset of the converter will vary. DIGITAL-TO-ANALOG GLITCH IMPULSE The amount of charge injected into the analog output from the digital inputs when the inputs change state. It is measured at half scale at the input codes where as many as possible switches change state—from 0000H to FFFFH. ® DAC714 6 Gain Adjust VREF OUT +VCC – VCC 14 12 7 15 180Ω 15kΩ +10V Reference 10 RFB2 11 RBPO 13 Offset Adjust 9 VOUT 250Ω 10kΩ +2.5V 9750Ω 10kΩ –VCC D/A Switches CLK 1 A1 3 CLR 16 A0 2 SDI 4 SDO 5 DAC Latch 16 Shift Register 8 6 ACOM DCOM FIGURE 1. DAC714 Block Diagram. +VCC ESD Protection Circuit Range of Gain Adjust ≈ ±0.3% + Full Scale 6.8V Analog Output 1kΩ Digital Input 5pF –VCC FIGURE 2. Equivalent Circuit of Digital Inputs. All Bits Logic 0 Range of Offset Adjust OUTPUT VOLTAGE SWING The output amplifier of the DAC714 is designed to achieve a ±10V output range while operating on ±11.4V or higher power supplies. Offset Adj. Translates the Line ≈ ±0.3% Full Scale Range Bipolar Offset Gain Adjust Rotates the Line MSB on All Others Off All Bits Logic 1 – Full Scale Digital Input FIGURE 3. Relationship of Offset and Gain Adjustments. GAIN AND OFFSET ADJUSTMENTS Figure 3 illustrates the relationship of offset and gain adjustments for a bipolar connected D/A converter. Offset should be adjusted first to avoid interaction of adjustments. See Table I for calibration values and codes. These adjustments have a minimum range of ±0.3%. Offset Adjustment Apply the digital input code, 8000H, that produces the maximum negative output voltage and adjust the offset potentiometer or the offset adjust D/A converter for –10V (or 0V unipolar). ® 7 DAC714 DAC714 CALIBRATION VALUES DIGITAL INPUT CODE ANALOG OUTPUT (V) BINARY TWO’S BIPOLAR UNIPOLAR COMPLEMENT, BTC 20V RANGE 10V RANGE 1 16 DESCRIPTION 2 –VCC 15 14 –12V to –15V 7FFFH | 4000H | 0001H +9.999695 +9.999847 + Full Scale –1LSB 3 +5.000000 +7.500000 3/4 Scale 4 +0.000305 +5.000153 BPZ + 1LSB 0000H 0.000000 +5.000000 Bipolar Zero (BPZ) FFFFH | C000H | 8000H –0.000305 +4.999847 BPZ – 1LSB 13 DAC714 –5.000000 +2.500000 1/4 Scale –10.00000 0.000000 Minus Full Scale 5 12 6 DCOM 11 7 +VCC 10 8 ACOM 9 + 1µF +12V to +15V 1µF + TABLE I. Digital Input and Analog Output Voltage Calibration Values. FIGURE 4. Power Supply Connections. Gain Adjustment Apply the digital input that gives the maximum positive voltage output. Adjust the gain potentiometer or the gain adjust D/A converter for this positive full scale voltage. critical settling time may be able to use 0.01µF at –VCC as well as at +VCC. The capacitors should be located close to the package. The DAC714 has separate ANALOG COMMON and DIGITAL COMMON pins. The current through DCOM is mostly switching transients and are up to 1mA peak in amplitude. The current through ACOM is typically 5µA for all codes. INSTALLATION GENERAL CONSIDERATIONS Use separate analog and digital ground planes with a single interconnection point to minimize ground loops. The analog pins are located adjacent to each other to help isolate analog from digital signals. Analog signals should be routed as far as possible from digital signals and should cross them at right angles. A solid analog ground plane around the D/A package, as well as under it in the vicinity of the analog and power supply pins, will isolate the D/A from switching currents. It is recommended that DCOM and ACOM be connected directly to the ground planes under the package. Due to the high-accuracy of the DAC714 system design problems such as grounding and contact resistance become very important. A 16-bit converter with a 20V full-scale range has a 1LSB value of 305µV. With a load current of 5mA, series wiring and connector resistance of only 60mΩ will cause a voltage drop of 300µV. To understand what this means in terms of a system layout, the resistivity of a typical 1 ounce copper-clad printed circuit board is 1/2 mΩ per square. For a 5mA load, a 10 milliinch wide printed circuit conductor 60 milliinches long will result in a voltage drop of 150µV. If several DAC714s are used or if DAC714 shares supplies with other components, connecting the ACOM and DCOM lines to together once at the power supplies rather than at each chip may give better results. The analog output of DAC714 has an LSB size of 305µV (–96dB) in the bipolar mode. The rms noise floor of the D/A should remain below this level in the frequency range of interest. The DAC714’s output noise spectral density (which includes the noise contributed by the internal reference,) is shown in the Typical Performance Curves section. LOAD CONNECTIONS Since the reference point for VOUT and VREF OUT is the ACOM pin, it is important to connect the D/A converter load directly to the ACOM pin. Refer to Figure 5. Wiring to high-resolution D/A converters should be routed to provide optimum isolation from sources of RFI and EMI. The key to elimination of RF radiation or pickup is small loop area. Signal leads and their return conductors should be kept close together such that they present a small capture cross-section for any external field. Wire-wrap construction is not recommended. Lead and contact resistances are represented by R1 through R3. As long as the load resistance RL is constant, R1 simply introduces a gain error and can be removed by gain adjustment of the D/A or system-wide gain calibration. R2 is part of RL if the output voltage is sensed at ACOM. In some applications it is impractical to return the load to the ACOM pin of the D/A converter. Sensing the output voltage at the SYSTEM GROUND point is reasonable, because there is no change in DAC714 ACOM current, provided that R3 is a low-resistance ground plane or conductor. In this case you may wish to connect DCOM to SYSTEM GROUND as well. POWER SUPPLY AND REFERENCE CONNECTIONS Power supply decoupling capacitors should be added as shown in Figure 4. Best performance occurs using a 1 to 10µF tantalum capacitor at –VCC. Applications with less ® DAC714 8 DIGITAL INTERFACE GAIN AND OFFSET ADJUST Connections Using Potentiometers SERIAL INTERFACE The DAC714 has a serial interface with two data buffers which can be used for either synchronous or asynchronous updating of multiple D/A converters. A0 is the enable control for the input shift register. A1 is the enable for the D/A Latch. CLK is used to strobe data into the latches enabled by A0 and A1. A CLR function is also provided and when enabled it sets the shift register and the D/A Latch to 0000H (output voltage is midscale). GAIN and OFFSET adjust pins provide for trim using external potentiometers. 15-turn potentiometers provide sufficient resolution. Range of adjustment of these trims is at least ±0.3% of Full Scale Range. Refer to Figure 6. Using D/A Converters The GAIN ADJUST and OFFSET ADJUST circuits of the DAC714 have been arranged so that these points may be easily driven by external D/A converters. Refer to Figure 7. 12-bit D/A converters provide an OFFSET adjust resolution and a GAIN adjust resolution of 30µV to 50µV per LSB step. OUTPUT VOLTAGE RANGE CONNECTIONS Multiple DAC714s can be connected to the same CLK and data lines in two ways. The output of the serial shift register is available as SDO so that any number of DAC714s can be cascaded on the same input bit stream as shown in Figures 8 and 9. This configuration allows all D/A converters to be updated simultaneously and requires a minimum number of control signals. These configurations do require 16N CLK cycles to load any given D/A converter, where N is the number of D/A converters. The DAC714 output amplifier is connected internally to provide a 20V output range. For other ranges and configurations, see Figures 6 and 7. The DAC714 can also be connected in parallel as shown in Figure 10. This configuration allows any D/A converter in the system to be updated in a maximum of 16 CLK cycles. Nominal values of GAIN and OFFSET occur when the D/A converters outputs are at approximately half scale, +5V. VREF RBPO DAC714 10kΩ SDI RFB2 A0 A1 VREF 10kΩ 10kΩ CLR VOUT Bus Interface R1 RL DCOM Sense Output ACOM R2 R3 Alternate Ground Sense Connection To +VCC 0.01µF(1) 0.01µF System Ground Analog Power Supply To –VCC NOTE: (1) Locate close to DAC714 package. FIGURE 5. System Ground Considerations for High-Resolution D/A Converters. ® 9 DAC714 Internal +10V Reference VREF OUT 12 P1 1kΩ 180Ω R1 100Ω Gain Adjust 14 Offset Adjust R2 2MΩ 10kΩ to 100kΩ 13 15kΩ 10kΩ 9.75kΩ RFB2 9 IDAC 0-2mA –VCC R3 27kΩ 10 10kΩ 8 +VCC VOUT For no external adjustments, pins 13 and 14 are not connected. External resistors R1 - R3 are standard ±1% values. Range of adjustment at least ±0.3% FSR. ACOM FIGURE 6a. Manual Offset and Gain Adjust Circuits; Unipolar Mode (0V to +10V output range). Internal +10V Reference VREF OUT 12 Bipolar Offset 11 P2 1kΩ P1 1kΩ 180Ω 250Ω R1 100Ω Gain Adjust Offset Adjust 15kΩ 14 13 10kΩ 9.75kΩ 10 10kΩ RFB2 9 IDAC 0-2mA 8 R2 100Ω ACOM R3 27kΩ R4 10kΩ VOUT For no external adjustments, pins 13 and 14 are not connected. External resistors R1 - R4 are standard ±1% values. Range of adjustment at least ±0.3% FSR. FIGURE 6b. Manual Offset and Gain Adjust Circuits; Bipolar Mode (–5V to +5V output range). ® DAC714 10 Internal +10V Reference VREF OUT 12 Bipolar Offset 180Ω R1 200Ω 250Ω 10kΩ +10V 11 R2 1.3kΩ 10kΩ Gain Adjust –10V 14 Offset Adjust 5kΩ 13 15kΩ 9.75kΩ 10kΩ RFB2 10 R3 11.8kΩ Suggested Op Amps OPA177GP, GS or OPA604AP, AU R4 24.3kΩ RFB VREF A 10kΩ 0 to +10V IDAC 0-2mA Suggested Op Amps OPA177GP, GS: Single or OPA2604AP, AU: Dual 9 ±10V VOUT 0 to +10V RFB VREF B DAC714 For no external adjustments, pins 13 and 14 are not connected. External resistors R1 - R4 tolerance: ±1%. Range of adjustment at least ±0.3% FSR. Suggested D/As CMOS DAC7800: Dual: Serial Input, 12-bit Resolution DAC7801: Dual: 8-bit Port Input, 12-bit Resolution DAC7802: Dual: 12-bit Port Input, 12-bit Resolution DAC7528: Dual: 8-bit Port Input, 8-bit Resolution DAC7545: Dual: 12-bit Port Input, 12-bit Resolution DAC8043: Single: Serial Input, 12-bit Resolution BIPOLAR (complete) DAC813 (Use 11-bit resolution for 0V to +10V output. No op amps required). FIGURE 7. Gain and Offset Adjustment in the Bipolar Mode Using D/A Converters (–10V to +10V output range). ® 11 DAC714 4 Data 2 Data Latch 3 Update 1 CLK +5V 16 4 2 3 1 +5V 16 4 2 3 1 +5V 16 SDI A0 A1 DAC714 CLK CLR SDO 5 SDI A0 A1 DAC714 CLK CLR SDO 5 SDI A0 A1 DAC714 CLK CLR SDO 5 To other DACs FIGURE 8a. Cascaded Serial Bus Connection with Synchronous Update. DAC3 DAC2 DAC1 Clock(1) F E D C B A 9 8 7 6 5 4 Data 3 2 1 0 F E D C B A 9 8 7 6 5 4 3 Data Latch Update NOTE: (1) Maximum Clock Frequency is 5.26MHz. FIGURE 8b. Timing Diagram For Figure 8a. ® DAC714 12 2 1 0 F E D C B A 9 8 7 6 5 4 3 2 1 0 4 Data 2 Data Latch 3 Update 1 16 SDI A0 A1 DAC714 CLK CLR SDO 5 +5V 4 2 3 1 16 SDI A0 A1 DAC714 CLK CLR SDO 5 +5V 4 2 3 1 16 SDI A0 A1 DAC714 CLK CLR SDO 5 To other DACs +5V FIGURE 9a. Cascaded Serial Bus Connection with Asynchronous Update. DAC3 DAC2 DAC1 Data Latch(1) Data F E D C B A 9 8 7 6 5 4 3 2 1 0 F E D C B A 9 8 7 6 5 4 3 2 1 0 F E D C B A 9 8 7 6 5 4 3 2 1 0 Update NOTE: (1) Maximum Data Latch Frequency is 5.26MHz. FIGURE 9b. Timing Diagram For Figure 9a. ® 13 DAC714 Data Data Latch 1 Update 4 2 3 1 CLK 16 CLR 4 Data Latch 2 2 3 1 16 4 Data Latch 3 2 3 1 16 SDI A0 A1 DAC714 CLK CLR SDO 5 SDI A0 A1 DAC714 CLK CLR SDO 5 SDI A0 A1 DAC714 CLK CLR SDO 5 FIGURE 10a. Parallel Bus Connection. DAC1 DAC2 DAC3 Clock(1) F E D C B A 9 8 7 6 5 4 Data 3 2 1 0 F E D C B A 9 8 7 6 5 4 3 Data Latch 1 Data Latch 2 Data Latch 3 Update NOTE: (1) Maximum Clock Frequency is 10MHz. FIGURE 10b. Timing Diagram For Figure 10a. ® DAC714 14 2 1 0 F E D C B A 9 8 7 6 5 4 3 2 1 0