MP ® MPC100 C10 0 MPC 100 Wide Bandwidth 4 x 1 VIDEO MULTIPLEXER FEATURES The MPC100 consists of four identical monolithic integrated open-loop buffer amplifiers, which are connected internally at the output. The unidirectional transmission path consists of bipolar complementary buffers, which offer extremely high output-to-input isolation. The MPC100 multiplexer enables one of the four input channels to connect to the output. The output of the multiplexer is in a high-impedance state when no channel is selected. When one channel is selected with a digital “1” at the corresponding SEL-input, the component acts as a buffer with high input impedance and low output impedance. ● BANDWIDTH: 250MHz (1.4Vp-p) ● LOW INTERCHANNEL CROSSTALK: ≤60dB (30MHz, DIP); ≤70dB (30MHz, SO) ● LOW SWITCHING TRANSIENTS: +2.5/–1.2mV ● LOW DIFFERENTIAL GAIN/PHASE ERRORS: 0.05%, 0.01° ● LOW QUIESCENT CURRENT: One Channel Selected: ±4.6mA No Channel Selected: ±230µA The wide bandwidth of over 250MHz at 1.4Vp-p signal level, high linearity and low distortion, and low input voltage noise of 4nV/√Hz make this crosspoint switch suitable for RF and video applications. All performance is specified with ±5V supply voltage, which reduces power consumption in comparison with ±15V designs. The multiplexer is available in spacesaving SO-14 and DIP packages. Both are designed and specified for operation over the industrial temperature range (–40°C to +85°C.) APPLICATIONS ● VIDEO ROUTING AND MULTIPLEXING (CROSSPOINTS) ● RADAR SYSTEMS ● DATA ACQUISITION ● INFORMATION TERMINALS ● SATELLITE OR RADIO LINK IF ROUTING IN1 DESCRIPTION DB1 IN2 The MPC100 is a very wide bandwidth 4-to-1 channel video signal multiplexer which can be used in a wide variety of applications. MPC100 is designed for wide-bandwidth systems, including high-definition television and broadcast equipment. Although it is primarily used to route video signals, the harmonic and dynamic attributes of the MPC100 make it appropriate for other analog signal routing applications such as radar, communications, computer graphics, and data acquisition systems. DB2 VOUT IN3 DB3 IN4 DB4 SEL1 SEL2 SEL3 SEL4 TRUTH TABLE SEL1 SEL2 SEL3 SEL4 VOUT 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 HI-Z IN1 IN2 IN3 IN4 International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1991 Burr-Brown Corporation PDS-1133F Printed in U.S.A. March, 1995 SPECIFICATIONS At VCC = ±5V, RL = 10kΩ, RSOURCE = 50Ω, and TA = +25°C, unless otherwise noted. MPC100AP, AU PARAMETER CONDITIONS MIN TYP MAX UNITS +10 ±30 –80 –50 –50 ±3 ±30 mV µV/°C dB dB dB mV ±10 VCC = ±4.5V to ±5.5V VCC = +4.5V to +5.5V VCC = –4.5V to –5.5V +4 20 ±380 +1.0 –11.0 µA nA/°C nA/V µA/V µA/V Channel On Channel On Channel Off 0.88 1.0 1.0 MΩ pF pF fB = 20kHz to 10MHz S/N = 0.7/V N • √5MHz 4.0 98 nV/√Hz dB Gain Error ≤ 10% ±4.2 V 0.982 0.992 V/V V/V DC CHARACTERISTICS INPUT OFFSET VOLTAGE Initial vs Temperature vs Supply (Tracking) vs Supply (Non-tracking) vs Supply (Non-tracking) Initial Matching INPUT BIAS CURRENT Initial vs Temperature vs Supply (Tracking) vs Supply (Non-tracking) vs Supply (Non-tracking) INPUT IMPEDANCE Resistance Capacitance Capacitance INPUT NOISE Voltage Noise Density Signal-to-Noise Ratio INPUT VOLTAGE RANGE TRANSFER CHARACTERISTICS CHANNEL SELECTION INPUTS Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current SWITCHING CHARACTERISTICS SEL to Channel ON Time SEL to Channel OFF Time Switching Transient, Positive Switching Transient, Negative OUTPUT Voltage Resistance Resistance Capacitance RIN = 0, RSOURCE = 0 VCC = ±4.5V to ±5.5V VCC = +4.5V to +5.5V VCC = –4.5V to –5.5V Between the Four Channels –40 Voltage Gain RL = 1kΩ, VIN = ±2V RL = 10kΩ, VIN = ±2.8V 0.98 +2.0 0 V V µA µA VSEL = 5.0V VSEL = 0.8V 100 0.002 VI = –0.3V to +0.7V, f = 5MHz 90% Point of VO = 1Vp-p 10% Point of VO = 1Vp-p Measured While Switching Between Two Grounded Channels 0.25 0.25 +2.5 –1.2 µs µs mV mV ±2.98 11 900 1.5 V Ω MΩ pF VIN = ±3V, RL = 5kΩ One Channel Selected No Channel Selected No Channel Selected POWER SUPPLY Rated Voltage Derated Performance Quiescent Current VCC +0.8 150 5 ±2.8 ±4.5 One Channel Selected No Channel Selected TEMPERATURE RANGE Operating, AP, AU Storage, AP, AU Thermal Resistance, θJA AP, AU ±5 ±4.6 ±230 –40 –40 90 ±5.5 ±5 ±350 V V mA µA +85 +125 °C °C °C/W The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® MPC100 2 SPECIFICATIONS At VCC = ±5V, RL = 10kΩ, RSOURCE = 50Ω, and TA = +25°C, unless otherwise noted. MPC100AP, AU PARAMETER CONDITIONS MIN TYP MAX UNITS AC CHARACTERISTICS FREQUENCY DOMAIN LARGE SIGNAL BANDWIDTH (–3dB) VO = 5.0Vp-p, COUT = 1pF VO = 2.8Vp-p, COUT = 1pF VO = 1.4Vp-p, COUT = 1pF SMALL SIGNAL BANDWIDTH VO = 0.2Vp-p, COUT = 1pF DIFFERENTIAL PHASE GAIN FLATNESS PEAKING HARMONIC DISTORTION Second Harmonic Third Harmonic CROSSTALK MPC100AP All Hostile Off Isolation MPC100AU All Hostile Off Isolation MHz MHz MHz 450 MHz 450 ps f = 4.43MHz, VIN = 0.3Vp-p VDC = 0 to 0.7V VDC = 0 to 1.4V 0.05 0.06 % % f = 4.43MHz, VIN = 0.3Vp-p VDC = 0 to 0.7V VDC = 0 to 1.4V 0.01 0.02 Degrees Degrees VO = 0.2Vp-p, DC to 30MHz VO = 0.2Vp-p, DC to 100MHz 0.04 0.05 dB dB –53 –67 dBc dBc VI = 1.4Vp-p, Figures 4 and 8 f = 5MHz, f = 30MHz, f = 5MHz, f = 30MHz, f = 5MHz, f = 30MHz, f = 5MHz, f = 30MHz –82 –60 –70 –71 –78 –70 –75 –76 dB dB dB dB dB dB dB dB VO = 1.4Vp-p, Step 10% to 90% COUT = 1pF, ROUT = 22Ω 3.3 ns VO = 2Vp-p COUT = 1pF COUT = 22pF COUT = 47pF 650 460 320 V/µs V/µs V/µs GROUP DELAY TIME DIFFERENTIAL GAIN 70 140 250 f = 30MHz, VO = 1.4Vp-p, RL = 1kΩ TIME DOMAIN RISE TIME SLEW RATE ® 3 MPC100 CONNECTION DIAGRAM FUNCTIONAL DESCRIPTION Top View DIP/SO-14 IN1 1 GND 2 IN2 3 GND 4 IN3 5 GND 6 IN4 7 DB1 DB2 IN1 -IN4 Four analog input channels GND Analog input shielding grounds, connect to system ground SEL1 - SEL4 Channel selection inputs 14 SEL1 VOUT Analog output; tracks selected channel 13 SEL2 –VCC Negative supply voltage; typical –5VDC 12 –VCC +VCC Positive supply voltage; typical +5VDC 11 VOUT ELECTROSTATIC DISCHARGE SENSITIVITY 10 +VCC DB3 DB4 9 SEL3 8 SEL4 Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr-Brown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. MPC100 ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. ABSOLUTE MAXIMUM RATINGS Power Supply Voltage (±VCC) .............................................................. ±6V Analog Input Voltage (IN1 through IN4)(1) ................................ ±VCC, ±0.7V Logic Input Voltage ................................................... –0.6V to +VCC +0.6V Operating Temperature ..................................................... –40°C to +85°C Storage Temperature ...................................................... –40°C to +125°C Output Current .................................................................................. ±6mA Junction Temperature .................................................................... +175°C Lead Temperature (soldering, 10s) ................................................ +300°C Digital Input Voltages (SEL1 through SEL4)(1) ........... –0.5V to +VCC +0.7V NOTE: (1) Inputs are internally diode-clamped to ±VCC. PACKAGE/ORDERING INFORMATION PRODUCT TEMPERATURE RANGE PACKAGE PACKAGE DRAWING NUMBER(1) MPC100AP MPC100AU –40°C to +85°C –40°C to +85°C 14-Pin Plastic DIP SO-14 Surface Mount 010 235 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ® MPC100 4 TYPICAL PERFORMANCE CURVES At VCC = ±5V, RLOAD = 10kΩ, RSOURCE = 50Ω, and TA = +25°C, unless otherwise noted. INPUT BIAS CURRENT vs TEMPERATURE 5 4 4 3 3 2 2 Bias Current (µA) Voltage (mV) OFFSET VOLTAGE vs TEMPERATURE 5 1 0 –1 –2 1 0 –1 –2 –3 –3 –4 –5 –4 –5 –40 –20 0 20 40 60 80 100 –40 –20 0 Temperature (°C) 40 60 80 100 OUTPUT IMPEDANCE vs FREQUENCY 100 100k 30 Output Impedance (Ω) Input Impedance (Ω) INPUT IMPEDANCE vs FREQUENCY 1.0M 10k 1k 100 10 3 1 10k 100k 1M 10M 100M 1G 10k 100k 1M Frequency (Hz) 10M 100M 1G Frequency (Hz) TOTAL QUIESCENT CURRENT vs TEMPERATURE TOTAL QUIESCENT CURRENT vs TEMPERATURE 300 9 No Channel Selected 8 One Channel Selected 250 7 Supply Current (µA) Supply Current (mA) 20 Temperature (°C) 6 5 4 3 200 150 100 2 50 1 0 –40 0 –20 0 20 40 60 80 100 –40 Temperature (°C) –20 0 20 40 60 80 100 Temperature (°C) ® 5 MPC100 TYPICAL PERFORMANCE CURVES (CONT) At VCC = ±5V, RLOAD = 10kΩ, RSOURCE = 50Ω, and TA = +25°C, unless otherwise noted. TRANSFER FUNCTION INPUT VOLTAGE NOISE SPECTRAL DENSITY 100 5 4 Voltage Noise (nV/ Hz) Output Voltage (V) 3 2 1 0 –1 –2 –3 –4 –5 10 1 0.1 –5 –4 –3 –2 –1 0 1 2 3 4 5 100 1k 10k Input Voltage (V) 100k 1M 10M 100M Frequency (Hz) SWITCHING ENVELOPE (Video Signal) SWITCHING TRANSIENTS (Channel To Channel) 12 5V 10 Output Voltage (V) SEL1 Output Voltage (mV) +0.7V 0V –0.3V 8 Without bandwidth limiting lowpass filter. 6 SEL2 5V 4 2 0 –2 –4 Time (µs) 0 20 40 60 80 100 120 140 160 180 200 Time (ns) SMALL SIGNAL PULSE RESPONSE SWITCHING TRANSIENTS (Channel To Channel) Output Voltage (40mV/Div) 5V Output Voltage (mV) SEL1 SEL2 36MHz Low pass filter acc. Eureka Rec. EU95-PG03 in the signal path. 5V –4 0 20 40 60 80 Time (ns) COUT = 1pF, tRISE = tFALL = 2ns (Generator) VI = 0.2Vp-p 100 120 140 160 180 200 Time (ns) ® MPC100 0— 6 TYPICAL PERFORMANCE CURVES (CONT) At VCC = ±5VDC, RLOAD = 10kΩ, RSOURCE = 50Ω, and TA = +25°C, unless otherwise noted. LARGE SIGNAL PULSE RESPONSE Output Voltage (1V/Div) Output Voltage (40mV/Div) SMALL SIGNAL PULSE RESPONSE 0— 0— Time (ns) COUT = 47pF, tRISE = tFALL = 2ns (Generator) VI = 0.2Vp-p Time (ns) COUT = 1pF, tRISE = tFALL = 5ns (Generator) VI = 5Vp-p LARGE SIGNAL PULSE RESPONSE GROUP DELAY TIME vs FREQUENCY 2.5 Delay Time (ns) Output Voltage (1V/Div) 2 1.5 0— 1 0.5 Group Delay Time 0 ROUT 50Ω RI 150Ω –0.5 VI –1 DUT Out VOUT = 300mVPO –1.5 –2 –2.5 Time (ns) COUT = 47pF, tRISE = tFALL = 5ns (Generator) VI = 5Vp-p 1M 10M Frequency (Hz) BANDWIDTH vs COUT WITH RECOMMENDED ROUT 0.5 15 0.4 10 0.3 0.2 0 –15 –20 –25 Output (dB) Gain (dB) 5 –10 500M GAIN FLATNESS 20 –5 100M 1pF COUT ROUT f–3dB 500MHz 1p 0Ω 10p 22Ω 340MHz 10pF 22p 15Ω 250MHz 22pF 33p 12Ω 215MHz 33pF 47p 10Ω 130MHz dB 1M 10M 0.2Vp-p 0 –0.1 –0.2 47pF 100M 0.1 –0.3 RIN = 150Ω, RO1 = 1kΩ –0.4 COUT = 22pF, ROUT = 15Ω –0.5 300k 1G 1M 10M 100M 1G Frequency (Hz) Frequency (Hz) ® 7 MPC100 TYPICAL PERFORMANCE CURVES (CONT) At VCC = ±5V, RLOAD = 10kΩ, RSOURCE = 50Ω, and TA = +25°C, unless otherwise noted. BANDWIDTH vs RLOAD BANDWIDTH vs OUTPUT VOLTAGE 20 20 5Vp-p 15 10 2.8Vp-p 10 5 1.4Vp-p 5 0 Output (dBm) Output (dBm) 15 0.6Vp-p –5 –10 0.2Vp-p –15 0 –5 –10 –15 –20 COUT = 1pF, ROUT = 0Ω –20 COUT = 22pF, ROUT = 15Ω, VO = 2.8Vp-p –25 RIN = 150Ω –25 RL = 500Ω = 1kΩ = 10kΩ dB dB 300k 1M 10M 100M 1G 300k 1M Frequency (Hz) 10M 100M Frequency (Hz) 30MHz HARMONIC DISTORTION BANDWIDTH MATCHING (DB1...DB4) 20 10 10dB/Div Harmonic Distortion (dB) 15 2.8Vp-p 0 –5 –10 –15 –20 –25 COUT = 22pF, ROUT = 15Ω Frequency (Hz) VOUT = 2.8Vp-p, RL = 1kΩ, COUT = 1pF dB 300k 1M 10M 100M 1G Frequency (Hz) 30MHz HARMONIC DISTORTION 10dB/Div Harmonic Distortion (dB) Output (dBm) 5 Frequency (Hz) VOUT = 2.8Vp-p, R L = 10kΩ, COUT = 1pF ® MPC100 8 1G APPLICATIONS INFORMATION emitter followers applies no feedback, so their low frequency gain is slightly less than unity and somewhat dependent on loading. Unlike devices using MOS bilateral switching elements, the bipolar complementary buffers form an unidirectional transmission path and thus provide high output-to-input isolation. Switching stages compatible to TTL level digital signals are provided for each buffer to select the input channel. When no channel is selected, the output of the device is high-impedance and allows the user to wire more MPC100s together to form switch multi-channel matrices. The MPC100 operates from ±5V power supplies (±6V maximum). Do not attempt to operate with larger power supply voltages or permanent damage may occur. The buffer outputs are not current-limited or protected. If the output is shorted to ground, currents up to 18mA could flow. Momentary shorts to ground (a few seconds) should be avoided, but are unlikely to cause permanent damage. INPUT PROTECTION All pins on the MPC100 are internally protected from ESD by means of a pair of back-to-back reverse-biased diodes to either power supply as shown in Figure 1. These diodes will begin to conduct when the input voltage exceeds either power supply by about 0.7V. This situation can occur with loss of the amplifier’s power supplies while a signal source is still present. The diodes can typically withstand a continuous current of 30mA without destruction. To insure long term reliability, however, diode current should be externally limited to 10mA or less whenever possible. If one channel is selected with a digital “1” at the corresponding SEL-input, the MPC100 acts as a buffer amplifier with high input impedance and low output impedance. The truth table on the front page describes the relationship between the digital inputs (SEL1 to SEL4) and the analog inputs (IN1 to IN4), and which signal is selected at the output. The 2-4 address decoder and chip select logic is not integrated. The selected design increases the flexibility of address decoding in complex distribution fields, eases BUS-controlled channel selection, simplifies channel selection monitoring for the user, and lowers transient peaks. All of these characteristics make the multiplexer, in effect, a quad switchable high-speed buffer. It requires DC coupling and termination resistors when directly driven from a low impedance cable. High-current output amplifiers are recommended when driving low-impedance transmission lines or inputs. The internal protection diodes are designed to withstand 2.5kV (using Human Body Model) and will provide adequate ESD protection for most normal handling procedures. However, static damage can cause subtle changes in amplifier input characteristics without necessarily destroying the device. In precision buffer amplifiers, this may cause a noticeable degradation of offset voltage and drift. Therefore, static protection is strongly recommended when handling the MPC100. An advanced complementary bipolar process, consisting of pn-junction isolated high-frequency NPN and PNP transistors, provides wide bandwidth while maintaining low crosstalk and harmonic distortion. The single chip bandwidth of over 250MHz at an output voltage of 1.4Vp-p allows the design of large crosspoint or distribution fields in HDTV-quality with an overall system bandwidth of 36MHz. The buffer amplifiers also offer low differential gain (0.05%) and phase (0.01°) errors. These parameters are essential for video applications and demonstrate how well the signal path maintains a constant small-signal gain and phase for the low-level color subcarrier at 4.43MHz (PAL) or 3.58MHz (NSTC) as the brightness (luminance) signal is ramped through its specified range. The bipolar construction also ensures that the input impedance remains high and constant between ON and OFF states. The ON/ OFF input capacitance ratio is near unity, and does not vary with power supply voltage variations. The low output capacitance of 1.5pF when no channel is selected is a very important parameter for large distribution fields. Each parallel output capacitance is an additional load and reduces the overall system bandwidth. Static damage has been well recognized for MOSFET devices, but any semiconductor device deserves protection from this potentially damaging source. The MPC100 incorporates on-chip ESD protection diodes as shown in Figure 1. This eliminates the need for the user to add external protection diodes, performance. +VCC External Pin ESD Protection diodes internally connected to all pins. Internal Circuitry –VCC FIGURE 1. Internal ESD Protection. DISCUSSION OF PERFORMANCE Bipolar video crosspoint switches are virtually glitch-free when compared to signal switches using CMOS or DMOS devices. The MPC100 operates with a fast make-beforebreak switching action to keep the output switching transients small and short. Switching from one channel to another causes the signal to mix at the output for a short time, but it interferes only minimally with the input signals. The MPC100 video multiplexer allows the user to connect any one of four analog input channels (IN1-IN4) to the output of the component and to switch between channels within less than 0.5µs. It consists of four identical unity-gain buffer amplifiers, which are connected together internally at the output. The open loop buffers consisting of complementary ® 9 MPC100 The transient peaks remain less than +2.5mV and –1.2mV. Subsequent equipment might interpret large negative output glitches as synchronization pulses. To remove this problem, the output must be clamped during the switching dead time. With the MPC100, the generated output transients are extremely small and clamping is unnecessary. The switching time between two channels is less than 0.5µs. This short time period allows easy switching during the vertical blanking time. The signal envelope during the transition from one channel to another rises and falls symmetrically and shows less overshooting or DC settling transients. • Bypass power supplies very close to the device pins. Use tantalum chip capacitors (approximately 2.2µF), a parallel 470pF ceramic chip capacitor may be added if desired. Surface-mount types are recommended due to their low lead inductance. • PC board traces for signal and power lines should be wide to reduce impedance or inductance. • Make short and low inductance traces. The entire physical circuit layout should be as small as possible. • Use a low-impedance ground plane on the component side to ensure that low-impedance ground is available throughout the layout. Grounded traces between the input traces are essential to achieve high interchannel crosstalk rejection. Refer to the suggested layout shown in Figure 6. Power consumption is a serious problem when designing large crosspoint fields with high component density. Most of the buffers are always in off-state. One important design goal was to attain low off-state quiescent current when no channel is selected. The low supply current of ±230µA in off-state and ±4.6mA when one channel is selected, as well as the reduced ±5V supply voltage, conserves power, simplifies the power supply design, and results in cooler, more reliable operation. • Do not extend the ground plane under high-impedance nodes sensitive to stray capacitances, such as the buffer’s input terminals. • Sockets are not recommended because they add significant inductance and parasitic capacitance. If sockets are required, use zero-profile solderless sockets. CIRCUIT LAYOUT The high-frequency performance of the MPC100 can be greatly affected by the physical layout of the circuit. The following tips are offered as suggestions, not as absolutes. Oscillations, ringing, poor bandwidth and settling, higher crosstalk, and peaking are all typical problems which plague high-speed components when they are used incorrectly. • Use low-inductance and surface-mounted components to achieve the best AC-performance. • A resistor (100Ω to 200Ω) in series with the input of the buffers may help to reduce peaking. Place the resistor as close as possible to the pin. • Plug-in prototype boards and wire-wrap boards will not function well. A clean layout using RF techniques is essential. SEL1 (14) IN1 DB1 (1) GND (2) +VCC = +5V (10) SEL2 (13) IN2 (3) VOUT (11) DB2 GND SEL3 (4) (9) IN3 DB3 (5) GND SEL1 (6) (8) IN4 DB4 (7) NOTE: DB = Diamond Buffer FIGURE 2. Simplified Circuit Diagram. ® MPC100 10 –VCC = –5V (12) 10 0 150Ω DB1 SEL1 SEL2 SEL3 SEL4 GND 50Ω 150Ω IN 2 VI 50Ω 0 0 1 0 –10 Crosstalk (dB) IN1 DB2 15Ω GND 180Ω 50Ω 50Ω BUF601 VO 22pF IN3 DB3 VI = 1.4Vp-p Crosstalk = 20log VO VI GND –20 –30 –40 –50 –60 MPC100AU MPC100AP –70 –80 150Ω DB4 IN3 is connected to GND IN4 –90 MPC100 1M 10M 100M 300M Frequency (Hz) FIGURE 3. Channel Crosstalk—Grounded Input. 10 150Ω 0 DB1 SEL1 SEL2 SEL3 SEL4 50Ω 150Ω IN 2 VI 50Ω 0 0 1 0 –10 Crosstalk (dB) IN1 GND DB2 15Ω GND 180Ω 50Ω 50Ω BUF601 VO 22pF 200Ω IN 3 DB3 VI = 1.4Vp-p Crosstalk = 20log VO VI MPC100AP –20 –30 –40 –50 –60 GND MPC100AU –70 150Ω DB4 –80 IN3 is connected with 150Ω + 50Ω to GND IN4 –90 MPC100 1M 10M 100M 300M Frequency (Hz) FIGURE 4. Channel Crosstalk—150Ω Input Resistor. 10 0 150Ω DB1 SEL1 SEL2 SEL3 SEL4 GND 50Ω 150Ω VI 50Ω IN2 0 0 0 0 –10 Crosstalk (dB) IN1 DB2 180Ω GND 50Ω 50Ω BUF601 VO 150Ω IN3 VI = 1.4Vp-p V Crosstalk = 20log O VI DB3 –20 MPC100AU –30 –40 –50 –60 –70 GND –80 150Ω MPC100AP –90 DB4 IN4 1M 10M 100M 300M MPC100 Frequency (Hz) FIGURE 5. Off Isolation. ® 11 MPC100 2.2µ 470p –5V IN13 75Ω 75Ω 75Ω 150Ω 150Ω 150Ω 1 14 2 13 3 12 4 11 5 10 6 9 22Ω IN16 75Ω 150Ω 7 8 MPC100 2.2µ 470p +5V 2.2µ 0.1µF 16 470p VCC 15 14 IN13 75Ω 150Ω 1 14 2 13 13 12 75Ω 150Ω 11 10 3 12 9 75Ω 150Ω 75Ω 150Ω 4 11 5 10 6 9 22Ω 7 Y0 A0 Y1 A1 1 A0 2 A1 3 A3 74HC 237 CS1 6 Y2 Y3 Y4 CS2 A3 CS 5 +5V Y5 Y6 Y7 LE GND 4 IN16 7 8 MPC100 2.2µ 470p 2.2µ 470p IN13 75Ω 150Ω 1 14 2 13 3 12 +5V 0.1µF 75Ω 150Ω 16 VCC 4 11 5 10 22Ω 15 14 75Ω 150Ω 13 6 9 7 8 12 IN16 11 75Ω 150Ω 10 9 MPC100 7 2.2µ Y0 A0 Y1 A1 1 2 3 A2 74HC 237 CS2 5 Y2 Y3 Y4 CS1 6 Y5 Y6 Y7 GND LE 4 470p 2.2µ 470p IN13 75Ω 150Ω 1 14 2 13 3 12 +5V 75Ω 75Ω 150Ω 150Ω 4 11 5 10 2.2µ 10n 22Ω 150Ω 3 2 7 + OPA623 4 – 75Ω 6 Out –5V 220Ω 6 9 2.2µ 220Ω IN16 75Ω 150Ω 7 8 MPC100 2.2µ 470p +5V FIGURE 6. Video Distribution Field. ® MPC100 12 10n +5V 2.2µ +5V 0.1µ 10 470p BUF600 +5V In 180Ω 4 1 +1 150Ω 8 1 DB1 5 –5V 75Ω 150Ω 150Ω 13 14 Y1 9 13 Y2 3 8 12 Y3 5 1 A0 2 74HC 237 A1 A2 3 150Ω CS1 DB2 11 4 75Ω R-2R Ladder Network 15 Y0 2 75Ω 150Ω 4 8 5 LE GND CS2 14 5 +5V 150Ω 3 + 7 OPA623 2 4 – DB3 75Ω 6 Out –5V 390Ω 6 75Ω 390 Ω 75Ω 150Ω 7 DB4 MPC100 12 2.2µ 470p CS A1 A0 2 3 4 0 0 0 2 1 0 0 0 0 0 1 1 0 1 0 0 0 1 0 0.5 0 0 1 0 0 1 1 0.25 0 0 0 1 1 X X 0 0 0 0 0 GAIN SEL1 –5V FIGURE 7. Digital Gain Control. +5V 0.1µ 16 +5V 4 8 5 VCC LE GND CS2 2.2µ 10 470p 15 Y0 1 14 Y1 2 13 Y2 3 12 Y3 5 A0 A1 A2 14 In1 150Ω 1 DB1 50Ω CS1 13 9 2 8 In2 150Ω 3 DB2 11 4 In3 12 Bit 10MHz A/D Converter +5V 50Ω 150Ω 150Ω 3 + 2 5 – DB3 220Ω 50Ω 7 OPA620 6 Signal Input 4 –5V 6 220Ω ADS804 In4 150Ω 7 DB4 50Ω MPC100 12 2.2µ 470p –5V FIGURE 8. High Speed Data Acquisition System. ® 13 MPC100 150Ω R 1 DB1 –5V +5V 2.2µ 2.2µ 2 CH1 G 150Ω 470p 3 10n 12 DB2 B 4 150Ω 11 75Ω 150Ω 5 10 DB3 75Ω 6 OPA623 R 4 – 390Ω 470p 6 150Ω 2 2.2µ 7 3 + 2.2µ 390Ω 10n +5V 7 DB4 –5V MPC100 9 150Ω R 1 10 13 14 DB1 –5V +5V 2.2µ 2.2µ 2 CH2 G 150Ω 470p 3 10n 12 DB2 B 4 75Ω 150Ω 150Ω 11 5 10 DB3 2 2.2µ 7 3 + OPA623 75Ω 6 G 4 – 390Ω 2.2µ 470p 6 390Ω 10n 150Ω +5V 7 DB4 –5V MPC100 9 R 10 13 +5V 14 5 16 CS1 CS VCC A0 1 15 Y0 A0 CH3 G 74HC 237 14 Y1 B 75Ω 9 150Ω 1 10 13 13 Y2 A9 3 12 Y3 LE 4 CS2 GND 5 8 14 DB1 –5V 2.2µ 2 3 470p DB2 4 R 150Ω 5 CH4 G DB3 10n 12 150Ω 11 10 2.2µ 7 3 + 2 OPA623 75Ω 6 B 4 – 390Ω 2.2µ 470p 6 390Ω B 10n 150Ω 7 +5V DB4 –5V 75Ω MPC100 FIGURE 9. Distribution Field for High Resolution Graphic Cards, Cameras. ® MPC100 14 A1 +5V 2.2µ 150Ω A1 2 Out 50Ω VI In RO1 RI 150Ω ROUT RO1 DUT RB 51Ω VO +1 400MHz Scope 50Ω BOUT RIN = 50Ω 50Ω COUT DB1 to DB4 RIN = 50Ω BUF601 Pulse Generator FIGURE 10. Test Circuit Pulse Response. MPC100 OPA623 VIN 75Ω Generator 150Ω 150Ω 4 DUT RIN = 75Ω 3 75Ω 10kΩ + 75Ω 8 Video Analyzer 75Ω – RIN = 75Ω 390Ω DB1 to DB4 4.43MHz 390Ω VDC FIGURE 11. Test Circuit Differential Gain and Phase. Out 50Ω Generator VI In RO1 RI 150Ω ROUT RO1 DUT +1 RB 51Ω VO Spectrum Analyzer 50Ω BOUT RIN = 50Ω 50Ω COUT DB1 to DB4 RIN = 50Ω BUF601 FIGURE 12. Test Circuit Frequency Response. MPC100 SEL Inputs MPC100 SEL Inputs SER In 2 1 3 5 4 5 6 D 3 7 1 7 14 13 12 11 Parallel Out HC4094 1 15 3 5 MPC100 SEL Inputs 7 SER 3 Out 1 3 5 4 5 6 MPC100 SEL Inputs 7 1 7 14 13 12 11 Parallel Out HC4094 2 3 1 15 3 5 MPC100 SEL Inputs 7 1 3 5 4 5 6 MPC100 SEL Inputs 7 1 7 14 13 12 11 Parallel Out HC4094 2 SER 3 ••• Out 3 1 3 5 7 SER 3 Out 15 Clock STR OE FIGURE 13. Serial Bus-Controlled Distribution Field. ® 15 MPC100