® OPA 177 OPA177 OPA 177 Precision OPERATIONAL AMPLIFIER FEATURES APPLICATIONS ● LOW OFFSET VOLTAGE: 25µV max ● LOW DRIFT: 0.3µV/°C ● PRECISION INSTRUMENTATION ● DATA ACQUISITION ● HIGH OPEN-LOOP GAIN: 130dB min ● LOW QUIESCENT CURRENT: 1.5mA typ ● TEST EQUIPMENT ● BRIDGE AMPLIFIER ● REPLACES INDUSTRY-STANDARD OP AMPS: OP-07, OP-77, OP-177, AD707, ETC. ● THERMOCOUPLE AMPLIFIER DESCRIPTION The OPA177 precision bipolar op amp feature very low offset voltage and drift. Laser-trimmed offset, drift and input bias current virtually eliminate the need for costly external trimming. The high performance and low cost make them ideally suited to a wide range of precision instrumentation. electric effects in input interconnections. It provides an effective alternative to chopper-stabilized amplifiers. The low noise of the OPA177 maintains accuracy. OPA177 performance gradeouts are available. Packaging options include 8-pin plastic DIP and SO-8 surface-mount packages. The low quiescent current of the OPA177 dramatically reduce warm-up drift and errors due to thermoV+ 7 Trim 1 14kΩ Trim 8 25Ω VO 6 30Ω +In 3 –In 2 500Ω 500Ω 20µA V– 4 International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1990 Burr-Brown Corporation PDS-1081E Printed in U.S.A. August, 1997 OPA177 SPECIFICATIONS At VS = ±15V, TA = +25°C, unless otherwise noted. OPA177F PARAMETER CONDITION OFFSET VOLTAGE Input Offset Voltage Long-Term Input Offset(1) Voltage Stability Offset Adjustment Range Power Supply Rejection Ratio RP = 20kΩ VS = ±3V to ±18V MIN 115 INPUT BIAS CURRENT Input Offset Current Input Bias Current NOISE Input Noise Voltage Input Noise Current INPUT IMPEDANCE Input Resistance 1Hz to 100Hz(2) 1Hz to 100Hz Differential Mode(3) Common-Mode TYP MAX 10 0.3 25 ±3 125 OPA177G MIN 110 TYP MAX UNITS 20 0.4 60 µV µV/Mo ✻ 120 mV dB 0.3 0.5 1.5 ±2 ✻ ✻ 2.8 ±2.8 nA nA 85 4.5 150 ✻ ✻ ✻ nVrms pArms 26 45 200 18.5 ✻ ✻ MΩ GΩ INPUT VOLTAGE RANGE Common-Mode Input Range(4) Common-Mode Rejection VCM = ±13V ±13 130 ±14 140 ✻ 115 ✻ ✻ V dB OPEN-LOOP GAIN Large Signal Voltage Gain RL ≥ 2kΩ VO = ±10V(5) 5110 12,000 2000 6000 V/mV RL ≥ 10kΩ RL ≥ 2kΩ RL ≥ 1kΩ ±13.5 ±12.5 ±12 ±14 ±13 ±12.5 60 ✻ ✻ ✻ ✻ ✻ ✻ ✻ V V V Ω RL ≥ 2kΩ G = +1 0.1 0.4 0.3 0.6 ✻ ✻ ✻ ✻ V/µs MHz OUTPUT Output Voltage Swing Open-Loop Output Resistance FREQUENCY RESPONSE Slew Rate Closed-Loop Bandwidth POWER SUPPLY Power Consumption Supply Current VS = ±15V, No Load VS = ±3V, No Load VS = ±15V, No Load 40 3.5 1.3 60 4.5 2 ✻ ✻ ✻ ✻ ✻ ✻ mW mW mA 15 0.1 40 0.3 20 0.7 100 1.2 µV µV/°C At VS = ±15V, –40°C ≤ TA ≤ +85°C, unless otherwise noted. OFFSET VOLTAGE Input Offset Voltage Average Input Offset Voltage Drift Power Supply Rejection Ratio VS = ±3V to ±18V 110 INPUT BIAS CURRENT Input Offset Current Average Input Offset Current Drift(6) Input Bias Current Average Input Bias Current Drift(6) INPUT VOLTAGE RANGE Common-Mode Input Range Common-Mode Rejection OPEN-LOOP GAIN Large Signal Voltage Gain OUTPUT Output Voltage Swing POWER SUPPLY Power Consumption Supply Current 120 106 115 dB 0.5 1.5 2.2 40 ✻ ✻ 4.5 85 nA pA/°C 0.5 8 ±4 40 ✻ 15 ±6 60 nA pA/°C VCM = ±13V ±13 120 ±13.5 140 ✻ 110 ✻ ✻ V dB RL ≥ 2kΩ, VO = ±10V 2000 6000 1000 4000 V/mV RL ≥ 2kΩ ±12 ±13 ✻ ✻ V VS = ±15V, No Load VS = ±15V, No Load 60 2 75 25 ✻ ✻ ✻ ✻ mW mA ✻ Same as specification for product to left. NOTES: (1) Long-Term Input Offset Voltage Stability refers to the averaged trend line of VOS vs time over extended periods after the first 30 days of operation. Excluding the initial hour of operation, changes in VOS during the first 30 operating days are typically less than 2µV. (2) Sample tested. (3) Guaranteed by design. (4) Guaranteed by CMRR test condition. (5) To insure high open-loop gain throughout the ±10V output range, AOL is tested at –10V ≤ VO ≤ 0V, 0V ≤ VO ≤ +10V, and –10V ≤ VO ≤ +10V. (6) Guaranteed by end-point limits. ® OPA177 2 PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Top View Power Supply Voltage ....................................................................... ±22V Differential Input Voltage ................................................................... ±30V Input Voltage ....................................................................................... ±VS Output Short Circuit ................................................................. Continuous Operating Temperature: Plastic DIP (P), SO-8 (S) .............................................. –40°C to +85°C θJA (PDIP) ................................................................................. 100°C/W θJA (SOIC) ................................................................................. 160°C/W Storage Temperature: Plastic DIP (P), SO-8 (S) ............................................ –65°C to +125°C Junction Temperature .................................................................... +150°C Lead Temperature (soldering, 10s) P packages ........................... +300°C (soldering, 3s) S package ............................... +260°C DIP/SOIC Offset Trim 1 8 Offset Trim –In 2 7 V+ +In 3 6 VO V– 4 5 No Internal Connection PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER(1) OPA177FP OPA177GP OPA177GS 8-Pin Plastic DIP 8-Pin Plastic DIP SO-8 Surface-Mount 006 006 182 TEMPERATURE RANGE –40°C to +85°C –40°C to +85°C –40°C to +85°C ELECTROSTATIC DISCHARGE SENSITIVITY Any integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. ESD can cause damage ranging from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. Burr-Brown’s standard ESD test method consists of five 1000V positive and negative discharges (100pF in series with 1.5kΩ) applied to each pin. Failure to observe proper handling procedures could result in small changes to the OPA177’s input bias current. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 OPA177 TYPICAL PERFORMANCE CURVES At TA = +25°C, VS = ±15V, unless otherwise noted. TOTAL HARMONIC DISTORTION AND NOISE vs FREQUENCY MAXIMUM VOUT vs IOUT (Negative Swing) 1 –17.5 A = 20dB, 3Vrms, 10kΩ load Inverting Noninverting VS = ±18V –12.5 VS = ±15V –10 VS = ±12V VOUT (V) THD + N (%) 0.1 –15 –7.5 0.01 –5 VS = ±15V –2.5 30kHz low pass filtered 0.001 0 1k 10k 100k 0 –2 –4 –6 Frequency (Hz) MAXIMUM VOUT vs IOUT (Positive Swing) –10 –12 WARM-UP OFFSET VOLTAGE DRIFT 3 17.5 Offset Voltage Change (µV) 15 VS = ±18V 12.5 VOUT (V) –8 –IOUT (mA) VS = ±15V 10 VS = ±12V 7.5 5 2.5 2 1 0 –1 –2 VS = ±15V –3 0 0 6 12 18 24 30 0 36 15 30 45 60 75 90 105 120 Time from Power Supply Turn-On (s) IOUT (mA) OFFSET VOLTAGE CHANGE DUE TO THERMAL SHOCK CLOSED-LOOP RESPONSE vs FREQUENCY 30 100 Device Immersed in 70°C Inert Liquid 80 Closed-Loop Gain (dB) Absolute Change in Input Offset Voltage (µV) 25 20 15 10 Plastic DIP 5 60 40 20 0 0 –20 0 10 20 30 40 50 60 70 80 10 Time (s) 1k 10k 100k Frequency (Hz) ® OPA177 100 4 1M 10M TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VS = ±15V, unless otherwise noted. CMRR vs FREQUENCY OPEN-LOOP GAIN/PHASE vs FREQUENCY 160 0 Gain 140 45 100 Phase 80 90 60 40 135 130 CMRR (dB) 120 Phase Shift (Degrees) Open-Loop Gain (dB) 140 150 110 100 90 20 0 0.01 180 0.1 1 10 100 1k 10k 100k 80 1 1M 100 10k POWER SUPPLY REJECTION vs FREQUENCY INPUT BIAS AND INPUT OFFSET CURRENT vs TEMPERATURE Input Bias and Input Offset Current (nA) 110 90 70 1 10 100 1k 10k 100k 2 1 IB I OS 0 –1 –2 –40 50 –15 10 35 60 85 Temperature (°C) Frequency (Hz) TOTAL NOISE vs BANDWIDTH (0.1Hz to Frequency Indicated) INPUT NOISE VOLTAGE DENSITY vs FREQUENCY 1k Input Noise Voltage (nV/√Hz) 10 RMS Noise (µV) 1k Frequency (Hz) 130 0.1 10 Frequency (Hz) 150 Power Supply Rejection (dB) 120 1 0.1 RS1 = RS2 = 200kΩ Thermal noise of source resistors included. 100 RS = 0 10 1 0.01 100 1k 10k 1 100k 10 100 1k 10k Frequency (Hz) Bandwidth (Hz) ® 5 OPA177 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VS = ±15V, unless otherwise noted. MAXIMUM OUTPUT SWING vs FREQUENCY POWER CONSUMPTION vs POWER SUPPLY 100 G = +1 R L = 2kΩ 28 24 Power Consumption (mW) Peak-to-Peak Amplitude (V) 32 20 16 12 8 10 4 1 0 1k 10k 100k 1M 0 10 Frequency (Hz) 30 40 OUTPUT SHORT-CIRCUIT CURRENT vs TIME MAXIMUM OUTPUT VOLTAGE vs LOAD RESISTANCE 40 Output Short-Circuit Current (mA) 20 Maximum Output (V) 20 Total Supply Voltage (V) Positive Output 15 Negative Output 10 5 35 30 ISC + 25 20 ISC – 15 0 100 1k 0 10k Load Resistance to Ground ( Ω) ® OPA177 1 2 3 Time from Output Being Shorted (min) 6 4 APPLICATIONS INFORMATION V+ The OPA177 is unity-gain stable, making it easy to use and free from oscillations in the widest range of circuitry. Applications with noisy or high impedance power supply lines may require decoupling capacitors close to the device pins. In most cases 0.1µF ceramic capacitors are adequate. The OPA177 has very low offset voltage and drift. To achieve highest performance, circuit layout and mechanical conditions must be optimized. Offset voltage and drift can be degraded by small thermoelectric potentials at the op amp inputs. Connections of dissimilar metals will generate thermal potential which can mask the ultimate performance of the OPA177. These thermal potentials can be made to cancel by assuring that they are equal in both input terminals. VIN 3 8 VOUT OPA177 Trim Range is approximately ±3.0mV FIGURE 1. Optional Offset Nulling Circuit. NOISE PERFORMANCE The noise performance of the OPA177 is optimized for circuit impedances in the range of 2kΩ to 50kΩ. Total noise in an application is a combination of the op amp’s input voltage noise and input bias current noise reacting with circuit impedances. For applications with higher source impedance, the OPA627 FET-input op amp will generally provide lower noise. For very low impedance applications, the OPA27 will provide lower noise. 1. Keep connections made to the two input terminals close together. 2. Locate heat sources as far as possible from the critical input circuitry. 3. Shield the op amp and input circuitry from air currents such as cooling fans. OFFSET VOLTAGE ADJUSTMENT The OPA177 has been laser-trimmed for low offset voltage and drift so most circuits will not require external adjustment. Figure 1 shows the optional connection of an external potentiometer to adjust offset voltage. This adjustment should not be used to compensate for offsets created elsewhere in a system since this can introduce excessive temperature drift. INPUT BIAS CURRENT CANCELLATION The input stage base current of the OPA177 is internally compensated with an equal and opposite cancellation current. The resulting input bias current is the difference between the input stage base current and the cancellation current. This residual input bias current can be positive or negative. INPUT PROTECTION The inputs of the OPA177 are protected with 500Ω series input resistors and diode clamps as shown in the simplified circuit diagram. The inputs can withstand ±30V differential inputs without damage. The protection diodes will, of course, conduct current when the inputs are overdriven. This may disturb the slewing behavior of unity-gain follower applications, but will not damage the op amp. When the bias current is cancelled in this manner, the input bias current and input offset current are approximately the same magnitude. As a result, it is not necessary to balance the DC resistance seen at the two input terminals (Figure 2). A resistor added to balance the input resistances may actually increase offset and noise. R2 R1 20kΩ 1 2 R2 Op Amp R1 RB = R2 || R1 OPA177 No bias current cancellation resistor needed (a) (b) Conventional op amp with external bias current cancellation resistor. OPA177 with no external bias current cancellation resistor. FIGURE 2. Input Bias Current Cancellation. ® 7 OPA177