OPA ® OPA4658 465 OPA 8 465 8 Quad Wideband, Low Power Current Feedback OPERATIONAL AMPLIFIER FEATURES APPLICATIONS ● GAIN BANDWIDTH: 900MHz at G = 2 ● GAIN OF 2 STABLE ● LOW POWER: 50mW PER AMP ● MEDICAL IMAGING ● HIGH-RESOLUTION VIDEO ● HIGH-SPEED SIGNAL PROCESSING ● LOW DIFF GAIN/PHASE ERRORS: 0.015%/0.02° ● HIGH SLEW RATE: 1700V/µs ● COMMUNICATIONS ● PULSE AMPLIFIERS ● ADC/DAC GAIN AMPLIFIER ● PACKAGE: 14-Pin DIP and SO-14 ● MONITOR PREAMPLIFIER ● CCD IMAGING AMPLIFIER DESCRIPTION The OPA4658 is a quad ultra-wideband, low power current feedback video operational amplifier featuring high slew rate and low differential gain/phase error. The current feedback design allows for superior large signal bandwidth, even at high gains. The low differential gain/phase errors, wide bandwidth and low quiescent current make the OPA4658 a perfect choice for numerous video, imaging and communications applications. The OPA4658 is internally compensated for stability in gains of 2 or greater. The OPA4658 is also available in dual (OPA2658) and single (OPA658) configurations. +VS Current Mirror IBIAS V+ V– Buffer VOUT CCOMP IBIAS Current Mirror –VS NOTE: Diagram reflects only one-fourth of the OPA4658. International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1994 Burr-Brown Corporation PDS-1270C 1 OPA4658 Printed in U.S.A. March, 1998 SPECIFICATIONS At TA = +25°C, VS = ±5V, RL = 100Ω, CL = 2pF, RFB = 402Ω, unless otherwise noted. OPA4658P, U PARAMETER CONDITION FREQUENCY RESPONSE Closed-Loop Bandwidth(2) Slew Rate(3) At Minimum Specified Temperature Settling Time: 0.01% 0.1% 1% Spurious Free Dynamic Range Third-Order Intercept Point Differential Gain Differential Phase Crosstalk OFFSET VOLTAGE Input Offset Voltage Over Temperature Power Supply Rejection INPUT BIAS CURRENT Non-Inverting Over Temperature Inverting Over Temperature NOISE Input Voltage Noise Density f = 100Hz f = 10kHz f = 1MHz fB = 100Hz to 200MHz Inverting Input Bias Current Noise Density: f = 10MHz Non-Inverting Input Current Noise Density: f = 10MHz Noise Figure (NF) INPUT VOLTAGE RANGE Common-Mode Input Range Over Temperature Common-Mode Rejection MIN G = +2 G = +5 G = +10 G = +2, 2V Step 55 VCM = 0V VCM = 0V RS = 100Ω RS = 50Ω ±2.5 45 VCM = ±1V INPUT IMPEDANCE Non-Inverting Inverting OPEN-LOOP TRANSIMPEDANCE Open-Loop Transimpedance Over Temperature OUTPUT Voltage Output Over Temperature Voltage Output Over Temperature Voltage Output Over Temperature Output Current, Sourcing Over Temperature Range Output Current, Sinking Over Temperature Range Short Circuit Current Output Resistance POWER SUPPLY Specified Operating Voltage Operating Voltage Range Quiescent Current Over Temperature TEMPERATURE RANGE Specification: P, U, UB Thermal Resistance, θJA P U OPA4658UB MAX 450 195 130 1700 1500 20 15.1 4.8 66 57 38 0.015 0.02 –74 –85 G = +2, 2V Step G = +2, 2V Step G = +2, 2V Step f = 5MHz, G = +2, VO = 2Vp-p f = 20MHz, G = +2, VO = 2Vp-p f = 10MHz G = +2, NTSC, VO = 1.4Vp-p, RL = 150Ω G = +2, NTSC, VO = 1.4Vp-p, RL = 150Ω Input Referred, 5MHz, Three Active Channels Input Referred, 5MHz, Channel-to-Channel VS = ±4.5 to ±5.5V TYP MIN 1000 900 ±1.5 ±5 70 ±5.5 ±8 ±6.5 ±10 ±1.1 ±30 ±30 ±80 ±35 ±75 58 TYP MAX ✻(1) ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ UNITS MHz MHz MHz V/µs V/µs ns ns ns dBc dBc dBm % degrees dB dB ±2 ±4 75 ±5 ±8 mV mV dB ✻ ✻ ✻ ✻ ±18 ±35 ✻ ✻ µA µA µA µA 16 3.6 3.2 45 ✻ ✻ ✻ ✻ nV/√Hz nV/√Hz nV/√Hz µVrms 32 ✻ pA/√Hz 12 9.5 11 ✻ ✻ ✻ pA/√Hz dBm dBm ✻ ✻ V V dB ✻ ✻ kΩ ||pF Ω ±2.9 ✻ ✻ 52 500 || 1 25 VO = ±2V, RL = 100Ω VO = ±2V, RL = 100Ω 150 100 350 290 200 150 360 300 kΩ kΩ No Load ±2.7 ±2.5 ±2.7 ±2.5 ±2.2 ±2.0 80 70 60 35 ±3.0 ±2.75 ±3.0 ±2.7 ±2.7 ±2.5 120 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ V V V V V V mA mA mA mA mA Ω RL = 250Ω RL = 100Ω 80 ✻ ✻ 150 0.1 1MHz, G = +2 ±4.5 All Channels, VS = ±5V ±5 ±19 ±20 –40 75 75 ✻ ✻ ±5.5 ±31 ±34 ✻ ±13 +85 ✻ ±20 ±21 ✻ ±23 ±26 ✻ ✻ ✻ V V mA mA °C °C/W °C/W NOTES: (1) An asterisk (✻) specifies the same value as the grade to the left. (2) Bandwidth can be affected by a non-optimal PC board layout. Refer to the demonstration board layout for details. (3) Slew rate is rate of change from 10% to 90% of output voltage step. ® OPA4658 2 PACKAGE INFORMATION ABSOLUTE MAXIMUM RATINGS Supply .......................................................................................... ±5.5VDC Internal Power Dissipation(1) ....................... See Applications Information Differential Input Voltage .............................................................. Total VS Input Voltage Range .................................... See Applications Information Storage Temperature Range: P, U, UB ........................ –40°C to +125°C Lead Temperature (soldering, 10s) .............................................. +300°C (soldering, SOIC 3s) ...................................................................... +260°C Junction Temperature (TJ ) ............................................................ +175°C PRODUCT OPA4658P OPA4658U, UB OPA4658P OPA4658U, UB PIN CONFIGURATION 1 14 Output 4 2 13 –Input 4 +Input 1 3 12 +Input 4 +VS 4 11 –VS +Input 2 5 10 +Input 3 –Input 2 6 9 –Input 3 Output 2 7 8 Output 3 010 235 PACKAGE TEMPERATURE RANGE 14-Pin Plastic DIP SO-14 Surface Mount –40°C to +85°C –40°C to +85°C NOTE: (1) The "B" grade of the SOIC package will be marked with a "B" by pin 8. Refer to mechanical section for the location. DIP/SO-14 –Input 1 14-Pin Plastic DIP SO-14 Surface Mount ORDERING INFORMATION(1) PRODUCT Output 1 PACKAGE DRAWING NUMBER(1) NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. NOTE: (1) Packages must be derated based on specified θJA. Maximum TJ must be observed. Top View PACKAGE ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 OPA4658 TYPICAL PERFORMANCE CURVES At TA = +25°C, VS = ±5V, RL = 100Ω, CL = 2pF, RFB = 402Ω, unless otherwise noted. SUPPLY CURRENT vs TEMPERATURE (Total of All Four Op Amps) PSRR AND CMRR vs TEMPERATURE 85 21 PSRR Supply Current (±mA) PSRR , CMRR (dB) 80 75 70 65 60 PSR+ 55 PSR– 50 CMRR 45 –75 –50 –25 0 25 50 75 100 20 19 18 17 –75 125 –50 –25 Temperature (°C) 0 25 50 75 100 125 Temperature (°C) OUTPUT SWING vs TEMPERATURE OUTPUT CURRENT vs TEMPERATURE 4 60 Output Swing (V) IO+ 50 I O– 2 0 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 Temperature (°C) Temperature (°C) NON-INVERTING INPUT BIAS CURRENT vs TEMPERATURE INVERTING INPUT BIAS CURRENT vs TEMPERATURE 10 100 125 100 125 8 8 6 4 2 –75 ±VO RL = 100Ω 1 45 40 –75 Non-Inverting Input Bias Current IB+ (µA) 3 55 Inverting Input Bias Current IB– (µA) Output Current (mA) ±VO RL = 250Ω –50 –25 0 25 50 75 100 4 2 0 –75 125 –50 –25 0 25 50 Temperature (°C) Temperature (°C) ® OPA4658 6 4 75 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VS = ±5V, RL = 100Ω, CL = 2pF, RFB = 402Ω, unless otherwise noted. OPEN-LOOP TRANSIMPEDANCE AND PHASE vs FREQUENCY OPEN-LOOP GAIN AND PHASE vs FREQUENCY 60 Transimpedance –45 Phase 103 –90 102 –135 101 1 1k 10k 100k 1M 10M Frequency (Hz) 100M Open-Loop Gain (dB) 104 Gain 40 0 Open-Loop Phase (°) Transimpedance (Ω) 105 20 –45 0 –90 –20 –135 –180 –40 –180 –225 –60 –225 1k 1G 10k 100k 10M 100M 1G CLOSED-LOOP BANDWIDTH (G = +5) CLOSED-LOOP BANDWIDTH (G = +2) 20 9 SO-14 Bandwidth = 458MHz (Dashed Line) 17 Bandwidth = 205MHz 6 14 3 Gain (dB) Gain (dB) 1M Frequency (Hz) 12 0 –3 DIP Bandwidth = 435M (Solid Line) –6 11 8 5 –9 – 12 2 1M 10M 100M 1G 1M 10G 10M 100M 1G Frequency (Hz) Frequency (Hz) CLOSED-LOOP BANDWIDTH (G = +10) COMMON-MODE REJECTION vs INPUT COMMON-MODE VOLTAGE 26 55 Bandwidth = 134MHz Common-Mode Rejection (dB) 23 20 Gain (dB) 0 Phase Open-Loop Phase (°) 106 17 14 11 8 5 2 50 45 40 35 30 1M 10M 100M 1G –4 Frequency (Hz) –3 –2 –1 0 1 2 3 4 Common-Mode Voltage (V) ® 5 OPA4658 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VS = ±5V, RL = 100Ω, CL = 2pF, RFB = 402Ω, unless otherwise noted. SMALL SIGNAL TRANSIENT RESPONSE (G = +2) RECOMMENDED ISOLATION RESISTANCE vs CAPACITIVE LOAD 160 40 G = +2 120 Output Voltage (mV) Isolation Resistance 35 30 RISO 25 20 CL 402Ω 15 1kΩ 402Ω 80 40 0 –40 –80 –120 –160 10 10 20 Time (5ns/div) 30 40 50 60 70 80 90 100 Capacitive Load (pf) LARGE SIGNAL TRANSIENT RESPONSE (G = +2) 5MHz HARMONIC DISTORTION vs OUTPUT SWING (G = +2) 1.6 –50 Harmonic Distortion (dBc) Output Voltage (V) 1.2 0.8 0.4 0 –0.4 –0.8 2fO –60 3fO –70 –80 –90 –1.2 –1.6 –100 Time (5ns/div) 0 1 2 3 4 Output Swing (Vp-p) 10MHz HARMONIC DISTORTION vs OUTPUT SWING (G = +2) HARMONIC DISTORTION vs FREQUENCY (G = +2, VO = 2Vp-p) –40 –50 Harmonic Distortion (dBc) Harmonic Distortion (dBc) 2fO –60 3fO –70 –80 –90 1 2 3 4 2fO –80 1M 10M Frequency (Hz) Output Swing (Vp-p) ® OPA4658 3fO –100 100k –100 0 –60 6 100M TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VS = ±5V, RL = 100Ω, CL = 2pF, RFB = 402Ω, unless otherwise noted. HARMONIC DISTORTION vs TEMPERATURE (G = +2, VO = 2Vp-p, fO = 5MHz) HARMONIC DISTORTION vs GAIN (fO = 5MHz, VO = 2Vp-p) –50 Harmonic Distortion (dBc) Harmonic Distortion (dBc) –60 2fO –65 3fO –55 2fO –60 3fO –65 –70 –70 –40 –20 0 20 40 60 80 2 100 Temperature (°C) 3 4 5 6 7 8 9 10 Non-Inverting Gain (V/V) ® 7 OPA4658 APPLICATIONS INFORMATION For non-inverting operation, the input signal is applied to the non-inverting (high impedance buffer) input. The output (buffer) error current (IE) is generated at the low impedance inverting input. The signal generated at the output is fed back to the inverting input such that the overall gain is (1 + RFB/RFF). Where a voltage-feedback amplifier has two symmetrical high impedance inputs, a current feedback amplifier has a low inverting (buffer output) impedance and a high non-inverting (buffer input) impedance. The closed-loop gain for the OPA4658 can be calculated using the following equations: R – FB R FF Inverting Gain = 1 (1) 1+ Loop Gain THEORY OF OPERATION Conventional op amps depend on feedback to drive their inputs to the same potential, however the current feedback op amp’s inverting and non-inverting inputs are connected by a unity gain buffer, thus enabling the inverting input to automatically assume the same potential as the non-inverting input. This results in very low impedance at the inverting input to sense the feedback as an error current signal. DISCUSSION OF PERFORMANCE The OPA4658 is a low-power, unity gain stable, current feedback operational amplifier which operates on ±5V power supply. The current feedback architecture offers the following important advantages over voltage feedback architectures: (1) the high slew rate allows the large signal performance to approach the small signal performance, and (2) there is very little bandwidth degradation at higher gain settings. The current feedback architecture of the OPA4658 provides the traditional strength of excellent large signal response plus wide bandwidth, making it a good choice for use in high resolution video, medical imaging and DAC I/V Conversion. The low power requirements make it an excellent choice for numerous portable applications. R FB 1 + R FF Non−Inverting Gain = 1 1+ Loop Gain (2) TO where Loop Gain = R FB R FB + R S 1 + R FF At higher gains the small value inverting input impedance causes an apparent loss in bandwidth. This can be seen from the equation: ƒ ( A = +2 ) BW x (1. 25) V (3) ƒ ACTUAL BW ≈ RS R FB 1 + × 1 + R FF R FB [ DC GAIN TRANSFER CHARACTERISTICS The circuit in Figure 1 shows the equivalent circuit for calculating the DC gain. When operating the device in the inverting mode, the input signal error current (IE) is amplified by the open loop transimpedance gain (TO). The output signal generated is equal to TO x IE. Negative feedback is applied through RFB such that the device operates at a gain equal to –RFB/RFF. ] This loss in bandwidth at high gains can be corrected without affecting stability by lowering the value of the feedback resistor from the specified value of 402Ω. OFFSET VOLTAGE AND NOISE The output offset is the algebraic sum of the input offset voltage and bias current errors. The output offset for noninverting operation is calculated by the following equation: CC + IE RFF RS LS TO – VN R (4) Output Offset Voltage = ±Ib N × R N 1 + F B ± R FF R FB V IO 1 + ±Ib I × R FB R FF VO If all terms are divided by the gain (1 + RFB/RFF) it can be observed that input referred offsets improve as gain increases. The effective noise at the output can be determined by taking (50Ω) C1 VI RFB RFF IbI RFB IbN RN VIO FIGURE 1. Equivalent Circuit. FIGURE 2. Output Offset Voltage Equivalent Circuit. ® OPA4658 8 The feedback resistor value acts as the frequency response compensation element for a current feedback type amplifier. The 402Ω used in setting the specification achieves a nominal maximally flat butterworth response while assuming a 2pF output pin parasitic. Increasing the feedback resistor will over compensate the amplifier, rolling off the frequency response, while decreasing it will decrease phase margin, peaking up the frequency response. the root sum of the squares of equation (4) and applying the spectral noise values found in the Typical Performance Curve graph section. This applies to noise from the op amp only. Note that both the noise figure (NF) and the equivalent input offset voltages improve as the closed loop gain increases (by keeping RFB fixed and reducing RFF with RN = 0Ω). INCREASING BANDWIDTH AT HIGH GAINS The closed-loop bandwidth can be extended at high gains by reducing the value of the feedback resistor RFB. This bandwidth reduction is caused by the feedback current being split between RS and RFF (refer to Figure 1). As the gain increases (for a fixed RFB), more feedback current is shunted through RFF, which reduces closed-loop bandwidth. d) Connections to other wideband devices on the board may be made with short direct traces or through on-board transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50 to 100 mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RISO from the plot of recommended RISO vs capacitive load. Low parasitic loads may not need an RISO since the OPA4658 is nominally compensated to operate with a 2pF parasitic load. If a long trace is required and the 6dB signal loss intrinsic to doubly terminated transmission lines is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is not necessary on board, and in fact a higher impedance environment will improve distortion as shown in the distortion vs load plot. With a characteristic impedance defined based on board material and desired trace dimensions, a matching series resistor into the trace from the output of the amplifier is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device; the total effective impedance should match the trace impedance. Multiple destination devices are best handled as separate transmission lines, each with their own series and shunt terminations. If the 6dB attenuation loss of a doubly terminated line is unacceptable, a long trace can be series-terminated at the source end only. This will help isolate the line capacitance from the op amp output, but will not preserve signal integrity as well as a doubly terminated line. If the shunt impedance at the destination end is finite, there will be some signal attenuation due to the voltage divider formed by the series and shunt impedances. e) Socketing a high speed part like the OPA4658 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket creates an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable response. Best results are obtained by soldering the part onto the board. If socketing for the DIP package is desired, high frequency flush mount pins (e.g., McKenzie Technology #710C) can give good results. CIRCUIT LAYOUT AND BASIC OPERATION Achieving optimum performance with a high frequency amplifier like the OPA4658 requires careful attention to layout parasitics and selection of external components. Recommendations for PC board layout and component selection include: a) Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability; on the noninverting input it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes. Otherwise, ground and power planes should be unbroken elsewhere on the board. b) Minimize the distance (< 0.25") from the two power pins to high frequency 0.1µF decoupling capacitors. At the pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. Larger (2.2µF to 6.8µF) decoupling capacitors, effective at lower frequencies, should also be used. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. c) Careful selection and placement of external components will preserve the high frequency performance of the OPA4658. Resistors should be a very low reactance type. Surface mount resistors work best and allow a tighter overall layout. Metal film or carbon composition axially-leaded resistors can also provide good high frequency performance. Again, keep their leads as short as possible. Never use wirewound type resistors in a high frequency application. Since the output pin and the inverting input pin are most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the package pins. Other network components, such as noninverting input termination resistors, should also be placed close to the package. ® 9 OPA4658 max = (±VS)2 /4RL. Note that it is the voltage across the output transistor, and not the load, that determines the power dissipated in the output stage. The short-circuit condition represents the maximum amount of internal power dissipation that can be generated. The variation of output current with temperature is shown in the Typical Performance Curves. ESD PROTECTION ESD damage has been well recognized for MOSFET devices, but any semiconductor device is vulnerable to this potentially damaging source. This is particularly true for very high speed, fine geometry processes. ESD damage can cause subtle changes in amplifier input characteristics without necessarily destroying the device. In precision operational amplifiers, this may cause a noticeable degradation of offset voltage and drift. Therefore, ESD handling precautions are strongly recommended when handling the OPA4658. CAPACITIVE LOADS The OPA4658’s output stage has been optimized to drive low resistive loads. Capacitive loads, however, will decrease the amplifier’s phase margin which may cause high frequency peaking or oscillations. Capacitive loads greater than 5pF should be buffered by connecting a small resistance, usually 5Ω to 25Ω, in series with the output as shown in Figure 4. This is particularly important when driving high capacitance loads such as flash A/D converters. OUTPUT DRIVE CAPABILITY The OPA4658 has been optimized to drive 75Ω and 100Ω resistive loads. The device can drive 2Vp-p into a 75Ω load. This high-output drive capability makes the OPA4658 an ideal choice for a wide range of RF, IF, and video applications. In many cases, additional buffer amplifiers are unneeded. In general, capacitive loads should be minimized for optimum high frequency performance. Coax lines can be driven if the cable is properly terminated. The capacitance of coax cable (29pF/foot for RG-58) will not load the amplifier when the coaxial cable or transmission line is terminated with its characteristic impedance. Many demanding high-speed applications such as ADC/DAC buffers require op amps with low wideband output impedance. For example, low output impedance is essential when driving the signal-dependent capacitances at the inputs of flash A/D converters. As shown in Figure 3, the OPA4658 maintains very low closed-loop output impedance over frequency. Closed-loop output impedance increases with frequency since loop gain is decreasing with frequency. 402Ω 402Ω 1/4 OPA4658 (RS typically 5Ω to 25Ω) RS 100 Output Impedance (Ω) G = +2 50Ω 10 RL CL 1 FIGURE 4. Driving Capacitive Loads. 0.1 0.01 COMPENSATION The OPA4658 is internally compensated and is stable in gains of two or greater, with a phase margin of approximately 66° in a gain of +2V/V. (Note that, from a stability standpoint, an inverting gain of –1V/V is equivalent to a noise gain of 2.) Gain and phase response for other gains are shown in the Typical Performance Curves. The high-frequency response of the OPA4658 in a good layout is very flat with frequency. 0.001 10k 100k 1M Frequency (Hz) 10M 100M FIGURE 3. Closed-Loop Output Impedance vs Frequency. THERMAL CONSIDERATIONS The OPA4658 does not require a heat sink for operation in most environments. At extreme temperatures and under full load conditions a heat sink may be necessary. DISTORTION The internal power dissipation is given by the equation PD = PDQ + PDL, where PDQ is the quiescent power dissipation and PDL is the power dissipation in the output stage due to the load. (For ±VS = ±5V, PDQ = 10V x 34mA = 340mW, max). For the case where the amplifier is driving a grounded load (RL) with a DC voltage (±VOUT) the maximum value of PDL occurs at ±V OUT = ±V S/2, and is equal to PDL, The OPA4658’s Harmonic Distortion characteristics into a 100Ω load are shown vs frequency and power output in the Typical Performance Curves. Distortion can be further improved by increasing the load resistance as illustrated in Figure 5. Remember to include the contribution of the feedback resistance when calculating the effective load resistance seen by the amplifier. ® OPA4658 10 channel or channels. Crosstalk is inclined to occur in most multichannel integrated circuits. In quad devices, the effect of crosstalk is measured by driving three channels and observing the output of the undriven channel over various frequencies. The magnitude of this effect is referenced in terms of channelto-channel isolation and expressed in decibels. Input referred points to the fact that there is a direct correlation between gain and crosstalk, therefore at increased gain, crosstalk also increases by a factor equal to that of the gain. Figure 7 illustrates the measured effect of crosstalk in the OPA4658U. –50 Harmonic Distortion (dBc) G = +2 –60 2fO –70 3fO –80 –90 –100 10 100 1k 10 Load Resistance (Ω) 0 FIGURE 5. 5MHz Harmonic Distortion vs Load Resistance. Isolation (dB) –20 The third-order intercept is an important parameter for many RF amplifier applications. Figure 6 shows the OPA4658’s two tone, third-order intercept vs frequency. This curve is particularly useful for determining the magnitude of the third harmonic as a function of frequency, load resistance, and gain. For example, assume that the application requires the OPA4658 to operate in a gain of +2V/V and drive 2Vp-p into 100Ω at a frequency of 10MHz. Referring to Figure 6 we find that the intercept point is +38dBm. The magnitude of the third harmonic can now be easily calculated from the expression: –30 –40 –50 –60 –70 –80 –90 1M 10M 100M Frequency (Hz) FIGURE 7. Channel-to-Channel Isolation (three active channels). Third Harmonic (dBc) = 2(OPI3P – PO) DIFFERENTIAL GAIN AND PHASE where OPI3P = third-order output intercept, dBm PO = output level, dBm Differential Gain (DG) and Differential Phase (DP) are critical specifications for video applications. DG is defined as the percent change in closed-loop gain over a specified change in output voltage level. DP is defined as the change in degrees of the closed-loop phase over the same output voltage change. Both DG and DP are specified at the NTSC sub-carrier frequency of 3.58MHz and the PAL subcarrier of 4.43MHz. All NTSC measurements were performed using a Tektronix model VM700A Video Measurement Set. For this case OPI3P = 38dBm, PO = 7dBm, and the third Harmonic = 2(38 – 7) = 62dB below the fundamental. The OPA4658’s low distortion makes the device an excellent choice for a variety of RF signal processing applications. CROSSTALK Crosstalk is the undesired result of the signal of one channel mixing with and reproducing itself in the output of another DG and DP of the OPA4658 were measured with the amplifier in a gain of +2V/V with 75Ω input impedance and the output back-terminated in 75Ω. The input signal selected from the generator was a 0V to 1.4V modulated ramp with sync pulse. With these conditions the test circuit shown in Figure 8 delivered a 100IRE modulated ramp to the 75Ω input of the video analyzer. The signal averaging feature of the analyzer (G = +2, RL = 100Ω, RFB = 402Ω) 70 Third Order Intercept Point (dBm) G = +2 –10 G = +2 60 50 75Ω 1/4 OPA4658 40 75Ω 30 20 100k 75Ω 402Ω 75Ω 1M 10M 402Ω 100M TEK TSG 130A TEK VM700A Frequency (Hz) FIGURE 6. Third Order Intercept Point vs Frequency. FIGURE 8. Configuration for Testing Differential Gain/Phase. ® 11 OPA4658 was used to establish a reference against which the performance of the amplifier was measured. Signal averaging was also used to measure the DG and DP of the test signal in order to eliminate the generator’s contribution to measured amplifier performance. Typical performance of the OPA4658 is 0.015% differential gain and 0.02° differential phase to both NTSC and PAL standards. Noise Figure (dB) 40 NOISE FIGURE NF = 10LOG 1 + 30 en2 + (InRs)2 4KTRS 20 10 The OPA4658’s voltage and current noise spectral densities are specified in the Typical Performance Curves. For RF applications, however, Noise Figure (NF) is often the preferred noise specification since it allows system noise performance to be more easily calculated. The OPA4658’s Noise Figure vs Source Resistance is shown in Figure 9. 0 10 100 1k 10k 100k Source Resistance (Ω) FIGURE 9. Noise Figure vs Source Resistance. SPICE MODELS Computer simulation using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for Video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. SPICE models using MicroSim Corporation’s PSpice are available for the OPA4658. Evaluation PC boards are also available. Contract Burr-Brown applications departments to receive a SPICE Diskette. DEMONSTRATION BOARD PACKAGE PRODUCT DEM-OPA465xP 8-Pin DIP OPA4658P DEM-OPA465xU SO-8 OPA4658U OPA4658UB TYPICAL APPLICATIONS 402Ω 402Ω 75Ω Transmission Line 75Ω 1/4 OPA4658 V OUT Video Input 75Ω 75Ω FIGURE 10. Low Distortion Video Amplifier. ® OPA4658 12 FIGURE 11. Circuit Detail for the PC Board Layout of Figure 12. 13 ® OPA4658 +InD –InD +InC –InC J10 J11 J9 J8 R22 R25 R19 R16 R23 R26 R20 R17 R24 R31 R21 R32 R27 4 1/4 OPA4658 8 C4 2.2µF C3 0.1µF 1/4 14 OPA4658 12 11 13 10 9 C1 0.1µF C2 2.2µF R18 C8 R28 U1 OPA465xP C7 R15 J12 J7 OutD OutC 2 1 2 1 P2 P1 –5V GND GND +5V +InA –InA +InB –InB J3 J2 J4 J5 R5 R5 R8 R11 R6 R3 R9 R12 R7 R29 R10 R30 3 2 5 6 1/4 OPA4658 R4 1/4 OPA4658 R13 1 7 C5 C6 R1 R14 J1 J6 OutA OutB DEM-OPA465xP Demonstration Board Layout (A) (B) (C) (D) FIGURE 12a. Board Silkscreen (Bottom). 12b. Board Silkscreen (Top). 12c. Board Layout (Solder Side). 12d. Board Layout (Component Side). ® OPA4658 14