® OPA642 OP OPA 642 A64 OPA 2 658 Wideband, Low Distortion, Low Gain OPERATIONAL AMPLIFIER FEATURES APPLICATIONS ● LOW DISTORTION: –95dBc at 5MHz ● GAIN OF +1 BANDWIDTH: 400MHz ● ADC/DAC BUFFER AMPLIFIER ● LOW DISTORTION IF AMPLIFIER ● AVAILABLE IN SOT23-5 PACKAGE ● HIGH OPEN LOOP GAIN: 95dB ● HIGH COMMON-MODE REJECTION: 90dB ● HIGH RESOLUTION IMAGING ● MEDICAL IMAGING ● LOW NOISE PREAMPLIFIER ● HIGH CMR DIFFERENCING AMPLIFIER ● TEST INSTRUMENTATION ● FAST 12-BIT SETTLING: 13ns (0.01%) ● LOW NOISE: 2.7nV/√Hz ● HIGH OUTPUT CURRENT: ±60mA ● VERY LOW DIFF GAIN/PHASE ERROR: 0.007%/0.008° ● PROFESSIONAL AUDIO DESCRIPTION feedback op amps. Fast settling time, excellent differential gain/phase performance, low voltage noise and high output current drive make the OPA642 ideal for most high dynamic range applications. The OPA642 provides a level of speed and dynamic range previously unattainable in a monolithic op amp. Using a unity gain stable voltage feedback architecture with two internal gain stages, the OPA642 achieves exceptionally low harmonic distortion over a wide frequency range. The “classic” differential input provides all the familiar benefits of precision op amps, such as bias current cancellation and very low inverting current noise compared with wideband current Unity gain stability makes the OPA642 particularly suitable for low gain differential amplifiers, transimpedance amplifiers, gain of +2 video line drivers, wideband integrators and low distortion ADC buffers. Where higher gain or even lower harmonic distortion is required, consider the OPA643—a higher gainbandwidth and lower noise version of the OPA642 +5V 5kΩ REFT 0.1µF +5V clk 1Vp-p 5MHz 2Vp-p 0.1µF ADS804 10MSPS 24Ω Analog Input OPA642 100pF –5V 402Ω 12-Bit 10MSPS Measured 80dB SFDR 5kΩ REFB 0.1µF 402Ω High Dynamic Range 10MSPS Digitizer International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1993 Burr-Brown Corporation 1 PDS-1190F OPA642 Printed in U.S.A. February, 1998 SPECIFICATIONS ELECTRICAL At TA = +25°C, VS = ±5V, RL = 100Ω, RF = 402Ω, unless otherwise noted. RF = 25Ω for a gain of +1. OPA642P, U, N PARAMETER CONDITIONS OFFSET VOLTAGE Input Offset Voltage Average Drift Power Supply Rejection (PSR) TYP MAX ±4 65 ±1.5 4 85 VCM = 0V 25 VCM = 0V 0.1 45 70 2.0 3.0 VS = ±4.5 to ±5.5V INPUT BIAS CURRENT Input Bias Current Over Specified Temperature Input Offset Current Over Specified Temperature NOISE Input Voltage Noise Noise Density: f ≥ 1MHz Integrated Voltage Noise, BW = 100Hz to 100MHz Input Bias Current Noise Density f ≥ 1MHz INPUT VOLTAGE RANGE Common-Mode Input Range Over Temperature Common-Mode Rejection (CMR) VCM = ±0.5V ±2.75 ±2.5 65 INPUT IMPEDANCE Differential Common-Mode OPEN-LOOP GAIN Open-Loop Voltage Gain (AOL) Over Specified Temperature Diff. Gain Error at 3.58MHz, G = +2V/V Diff. Phase Error at 3.58MHz, G = +2V/V OUTPUT Voltage Output Over Specified Temperature Voltage Output Over Specified Temperature Current Output, +25°C Over Specified Temperature Closed-Loop Output Resistance VO = ±2V, RL = 100Ω 80 80 Gain = +1V/V Gain = +2V/V Gain = +5V/V Gain = +10V/V G = +1, 2V Step G = +1, 2V Step G = +1, 1V Step G = +1, 1V Step G = +1, 1V Step G = +1, f = 5MHz VO = 2Vp-p, RL = 100Ω VO = 0V to 1.4V, RL = 150Ω VO = 0V to 1.4V, RL = 150Ω No Load ±3.0 RL = 100Ω ±2.5 ±40 ±35 0.1MHz, G = +1V/V POWER SUPPLY Specified Operating Voltage Operating Voltage Range Quiescent Current Over Specified Temperature TEMPERATURE RANGE Specification: P, U, N, PB, UB, NB Thermal Resistance P, PB 8-Pin DIP U, UB 8-Pin SO-8 N, NB 5-Pin SOT23-5 TYP MAX UNITS ±1.0 73 ±0.5 2 95 mV µV/°C dB ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ µA µA µA µA 2.7 27 ✻ ✻ nV/√Hz µVrms 2.8 ✻ pA/√Hz ✻ ✻ V V dB ✻ ✻ kΩ || pF kΩ || pF 98 dB dB 400 150 45 21 210 380 340 13 11.5 3.5 92 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ 95 MHz MHz MHz MHz MHz V/µs V/µs ns ns ns dBc 0.007 0.008 ✻ ✻ % degrees ✻ V V V V mA mA Ω ±3.0 ✻ ✻ 80 90 TMIN to TMAX Ambient θJA, Junction-to-Ambient 95 85 ✻ ±3.5 ✻ ±2.75 ✻ ±50 ±40 ±60 ±4.5 ±5 ±20 –40 100 125 150 NOTE: (1) Slew rate is rate of change from 10% to 90% of output voltage step. ® 2 ✻ ✻ ±65 ✻ 0.01 ✻ Indicates same specification as for OPA642P, U, N. OPA642 MIN 11 || 1 650 || 1 FREQUENCY RESPONSE Closed-Loop Response Gain Bandwidth Product (GBP) Slew Rate(1) At Minimum Specified Temperature Settling Time: 0.01% 0.1% 1% Spurious Free Dynamic Range (SFDR) OPA642PB, UB, NB MIN ✻ ±5.5 ±25 ±26 ✻ ±16 +85 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ V V mA mA °C °C/W °C/W °C/W °C/W ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION Supply .......................................................................................... ±6.0VDC Internal Power Dissipation(1) .................................. See Thermal Analysis Differential Input Voltage .................................................................. ±1.2V Input Voltage Range ............................................................................ ±VS Storage Temperature Range: P, PB, U, UB, N, NB ..... –40°C to +125°C Lead Temperature (soldering, 10s) .............................................. +300°C (soldering, SO-8 3s) ....................................... +260°C Junction Temperature (TJ ) ............................................................ +175°C NOTE: (1) Packages must be derated based on specified θ TJ must be observed. JA. Top View DIP/SO-8 NC 1 8 +VS2(1) Inverting Input 2 7 +VS1 Non-Inverting Input 3 6 Output –VS1 4 5 –VS2(1) Maximum ELECTROSTATIC DISCHARGE SENSITIVITY SOT23-5 Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. BurrBrown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. Output 1 –VS 2 Non-Inverting Input 3 5 +VS 4 Inverting Input NOTE: (1) Making use of all four power supply pins is recommended, although not required. Using these four pins, instead of just pins 4 and 7, will lower the power supply impedance improving distortion. PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER(1) OPA642U OPA642UB OPA642N SO-8 Surface Mount SO-8 Surface Mount 5-pin SOT23-5 182 182 331 –40°C to +85°C –40°C to +85°C –40°C to +85°C OPA642U OPA642UB A42 OPA642NB 5-pin SOT23-5 331 –40°C to +85°C A42B OPA642P OPA642PB 8-Pin Plastic DIP 8-Pin Plastic DIP 006 006 –40°C to +85°C –40°C to +85°C OPA642P OPA642PB TEMPERATURE RANGE PACKAGE MARKING(2) ORDERING NUMBER(3) OPA642U OPA642UB OPA642N-250 OPA642N-3k OPA642NB-250 OPA642NB-3k OPA642P OPA642PB NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) The “B” grade of the SO-8 and DIP packages will be marked with a “B” by pin 8. The “B” grade of the SOT23-5 will be marked with a “B” near pins 3 and 4. (3) The SOT23-5 is only available on a 7" tape and reel (e.g. ordering 250 pieces of “OPA642N-250” will get a single 250 piece tape and reel. Ordering 3000 pieces of “OPA642N-3k” will get a single 3000 piece tape and reel). Please refer to Appendix B of Burr-Brown IC Data Book for detailed Tape and Reel Mechanical information. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 OPA642 TYPICAL PERFORMANCE CURVES At TA = +25°C, VS = ±5V, RL = 100Ω, RF = 402Ω, G = +2, unless otherwise noted. RF = 25Ω for a gain of +1. SMALL SIGNAL FREQUENCY RESPONSE VO = 0.1Vp-p G = +1 G = +2 0 –6 –9 –12 –15 G = +5 –21 10MHz 100MHz 3 0 VO = 2Vp-p –3 –9 VO = 4Vp-p –12 –15 –18 G = +10 –24 0.5MHz VO = 1Vp-p 6 –3 –18 G = +2 9 Gain (3dB/div) Normalized Gain (3dB/div) 3 –21 0.5MHz 500MHz 10MHz Frequency SMALL SIGNAL TRANSIENT RESPONSE (G = +1, RL = 100Ω) LARGE SIGNAL TRANSIENT RESPONSE (G = +1, RL = 100Ω) 200 2.0 160 1.6 120 1.2 80 40 0 –40 –80 0.4 0 –0.4 –0.8 –1.2 –160 –1.4 –200 500MHz 0.8 –120 –2.0 Time (5ns/div) Time (5ns/div) FREQUENCY RESPONSE vs CAPACITIVE LOAD RS vs CAPACITIVE LOAD 12 Gain to Capacitive Load (3dB/div) 30 25 20 RS (Ω) 100MHz Frequency Output Voltage (V) Output Voltage (mV) LARGE SIGNAL FREQUENCY RESPONSE 12 6 15 10 5 G = +2 9 CL = 10pF 6 3 0 CL = 22pF RS VIN –3 OPA642 –6 402Ω VO CL 1kΩ –9 –12 CL = 47pF 402Ω –15 (1kΩ is optional) CL = 100pF –18 0 1 10 0 100 ® OPA642 100MHz Frequency (20MHz/div) Capacitive Load (pF) 4 200MHz TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VS = ±5V, RL = 100Ω, RF = 402Ω, G = +2, unless otherwise noted. RF = 25Ω for a gain of +1. 5MHz 3RD HARMONIC DISTORTION 5MHz 2ND HARMONIC DISTORTION –65 –65 G = +2 RL = 100Ω G = +2 3rd Harmonic Distortion (dBc) 2nd Harmonic Distortion (dBc) –70 –75 –80 RL = 200Ω –85 RL = 500Ω –90 –95 –70 –75 –80 RL = 100Ω, 200Ω, or 500Ω –85 –90 –95 –100 –100 0.1 1 0.1 10 10MHz 2ND HARMONIC DISTORTION 10 10MHz 3RD HARMONIC DISTORTION –60 –60 G = +2 G = +2 RL = 100Ω –65 3rd Harmonic Distortion (dBc) 2nd Harmonic Distortion (dBc) 1 Output Voltage Swing (Vp-p) Output Voltage Swing (Vp-p) –70 –75 RL = 200Ω –80 RL = 500Ω –85 –90 –95 –65 –70 –75 –80 –85 RL = 500Ω –90 RL = 200Ω –95 RL = 100Ω –100 –100 0.1 1 10 0.1 Output Voltage Swing (Vp-p) 20MHz 2ND HARMONIC DISTORTION 10 20MHz 3RD HARMONIC DISTORTION –50 –50 G = +2 G = +2 –55 –60 3rd Harmonic Distortion (dBc) 2nd Harmonic Distortion (dBc) 1 Output Voltage Swing (Vp-p) RL = 200Ω –65 RL = 100Ω –70 –75 –80 RL = 500Ω –85 –90 –55 –60 –65 –70 RL = 200Ω –75 RL = 100Ω –80 RL = 500Ω –85 –90 0.1 1 10 0.1 Output Voltage Swing (Vp-p) 1 10 Output Voltage Swing (Vp-p) ® 5 OPA642 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VS = ±5V, RL = 100Ω, RF = 402Ω, G = +2, unless otherwise noted. RF = 25Ω for a gain of +1. 3RD HARMONIC DISTORTION vs FREQUENCY 2ND HARMONIC DISTORTION vs FREQUENCY –40 –40 VO = 2Vp-p G=8 3rd Harmonic Distortion (dBc) 2nd Harmonic Distortion (dBc) VO = 2Vp-p –50 –60 –70 G=2 G=4 –80 –90 G=1 –50 –60 G=8 –70 –80 G=4 G=2 –90 G=1 –100 –100 0.1 1 10 0.1 20 1 10 Frequency (MHz) Frequency (MHz) INPUT VOLTAGE AND CURRENT NOISE DENSITY TWO-TONE, THIRD ORDER INTERMODULATION INTERCEPT 20 50 100 Intercept (dBm) voltage Noise nV/√Hz 45 10 Current Noise 2.8pA/√Hz Voltage Noise 2.7nV/√Hz 40 35 Pi 50Ω 30 50Ω PO 50Ω 402Ω 25 402Ω 20 1 102 103 104 105 106 107 5 –60 Phase 70 –90 60 –120 50 –150 Gain 40 –180 30 –210 20 –240 10 –270 0 –300 –10 Open-Loop Phase (30°/div) –30 –330 102 103 104 105 106 107 108 109 Frequency (Hz) Differential Gain Error (%) 0 90 0.006 0.004 0.002 –0.000 –0.002 –0.004 Differential Phase Error (°) OPEN-LOOP GAIN AND PHASE 100 80 10 15 20 25 0.008 0.006 0.004 0.002 0 35 40 0.7 ® 6 1.4 DC Offset (V) 0.000 0 0.7 DC Offset (V) OPA642 30 Frequency (MHz) Frequency (Hz) Open-Loop Gain (dB) OPA642 1.4 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VS = ±5V, RL = 100Ω, RF = 402Ω, G = +2, unless otherwise noted. RF = 25Ω for a gain of +1. CMR AND PSR vs FREQUENCY 100 90 PSR 10 Output Impedance (Ω) Rejection Ratio (dB) CLOSED-LOOP OUTPUT IMPEDANCE CMR 80 70 60 50 40 1 0.1 0.01 30 0.001 20 102 103 104 105 106 107 108 0 1 10 100 Frequency (MHz) DIFFERENTIAL AND COMMON-MODE INPUT IMPEDANCE COMMON-MODE REJECTION vs INPUT COMMON-MODE VOLTAGE 1000 500 100 Common-Mode Rejection (dB) Common-Mode Input Impedance (kΩ) 0.1 Frequency (Hz) 100 Differential Input 10 1 90 80 70 60 102 103 104 105 106 107 108 –5 –4 –3 –2 –1 0 1 2 3 4 Frequency (Hz) Common-Mode Voltage (V) AOL, PSR AND CMR vs TEMPERATURE OUTPUT AND QUIESCENT CURRENT vs TEMPERATURE 80 110 5 IO+ 70 100 Output Current (mA) AOL, PSR, CMR (dB) PSR+ AOL PSR– CMR 90 60 IO– 50 40 30 ICC 20 10 80 0 –75 –50 –25 0 25 50 75 100 –50 125 –25 0 25 50 75 100 125 Ambient Temperature (°C) Temperature (°C) ® 7 OPA642 BUFFERING HIGH PERFORMANCE ADC’S To achieve full performance from a high dynamic range A/D converter, considerable care must be exercised in the design of the input amplifier interface circuit. The example circuit on the front page shows a typical AC-coupled interface to a very high dynamic range converter. The frequency domain application allows the OPA642 to be operated in its most linear region, using a signal range which swings symmetrically around ground (0V). The 2Vp-p swing is then level-shifted through the blocking capacitor to a DC reference level, which is created by a well-decoupled resistive divider off the converter’s internal reference voltages. To have a negligible effect on the rated spurious-free dynamic range (SFDR) of the converter, the amplifier’s SFDR should be at least 10dB greater. In the front page example, the insertion of the OPA642 has an immeasurable effect on the distortion of the ADS804, which achieves 80dB SFDR at 5MHz Nyquist input signal. APPLICATIONS INFORMATION WIDEBAND VOLTAGE FEEDBACK OPERATION The OPA642’s combination of speed and dynamic range is easily achieved in a wide variety of application circuits, providing that simple principles of good design practice are observed. For example, good power supply decoupling, as shown in Figure 1, is essential to achieve the lowest possible harmonic distortion and smooth frequency response. Proper PC board layout and careful component selection will maximize the performance of the OPA642 in all applications, as discussed in the remaining sections of this data sheet. Figure 1 shows the gain of +2 configuration used as the basis for most of the Typical Performance Curves. Most of the curves were characterized using signal sources with 50Ω driving impedance, and with measurement equipment presenting 50Ω shunt load impedance. In Figure 1, the 50Ω shunt resistor at the VI terminal matches the source impedance of the test generator, while the 50Ω series resistor at the VO terminal provides a matching resistor for the measurement equipment load. Generally, data sheet specifications refer to the voltage swing at the output pin (VO in Figure 1). The 100Ω load from the series and shunt matching resistances, combined with the 804Ω total feedback network load, presents the OPA642 with an effective load of approximately 90Ω. To achieve the lowest possible distortion in the 8-pin SO-8 or DIP package, the addition of 0.1µF decoupling capacitors on pins 5 and 8 is required. These are shown in Figure 1. Although pins 5 and 8 are internally connected to pins 4 and 7 respectively (the standard supply pins for 8-pin op amps), the additional capacitors help to decouple the package lead inductances and improve second harmonic suppression at 5MHz by approximately 4dB. The much shorter bond wires and supply leads of the SOT23-5 package give the best distortion performance while requiring only two power supply connections. Successful application of the OPA642 for ADC buffering requires careful selection of the series resistor at the amplifier output, along with the additional shunt capacitor at the ADC input. To some extent, selection of this RC network will be determined empirically for each model of converter. Many high performance CMOS ADCs, like the ADS804, perform better with the shunt capacitor at the input pin. This capacitor provides a low source impedance for the transient currents produced by the sampling process. Improved SFDR is obtained by adding the capacitor, whose value is often recommended in the converter data sheet. The external capacitor, in combination with the built-in capacitance of the A/D input, presents a significant capacitive load to the OPA642. Without a series isolation resistor, the result could be undesirable peaking or loss of stability in the amplifier. Since the DC bias current of the CMOS A/D input is negligible, the resistor has no effect on overall gain or offset accuracy. Refer to the plot of “RS vs Capacitive Load” in the Typical Performance Curves to obtain a good starting value for the series resistor. This will ensure flat frequency response to the ADC input. Increasing the external capacitor value will allow the series resistor to be reduced or, keeping this resistor fixed, will band-limit the signal and reduce high frequency noise to the input of the converter. +VS 2.2µF + 0.1µF 50Ω Source VI 0.1µF 3 7 8 50Ω 6 OPA642 VO 50Ω 50Ω Load 5 0.1µF 2 4 0.1µF Gain, VO VI =1+ RF RG RF 402Ω RG 402Ω 2.2µF + –VS VIDEO LINE DRIVING Most video distribution systems are designed with 75Ω series resistors to drive a matched 75Ω cable. In order to deliver a net gain of 1 to the 75Ω matched load, the amplifier FIGURE 1. Gain of +2, High Frequency Application and Characterization Circuit [P or U Package]. ® OPA642 8 packaged together as a dual voltage feedback op-amp—the OPA2650. This approach saves board space, cost and power compared to using two additional OPA642 devices, and still achieves very good noise and distortion performance due to the moderate loading on the input amplifiers. In this circuit, the common mode gain to the output is always one due to the four matched 1kΩ resistors, while the differential gain is set by (1 + 2RF1/RG)—which is equal to 2 using the values in Figure 3. The differential to single-ended conversion is still performed by the OPA642 output stage. The high impedance inputs allow the V1 and V2 sources to be terminated or impedance matched as required without further loading by the differential amplifier. If the V1 and V2 inputs are already truly differential, such as the output from a signal transformer, then a single matching termination resistor may be used between them. Remember, however, that a defined DC signal path must always exist for the V1 and V2 inputs; for the transformer case, a center-tapped secondary connected to ground would provide an optimum DC operating point. is typically set up for a voltage gain of +2, compensating for the 6dB attenuation of the voltage divider formed by the series and shunt 75Ω resistors at either end of the cable. The circuit of Figure 1 applies to this requirement if all references to 50Ω resistors are replaced by 75Ω values. Often, the amplifier gain is further increased to 2.2, which recovers the additional DC loss of a typical long cable run. This change would require the gain resistor (RG) in Figure 1 to be reduced from 402Ω to 335Ω. In either case, both the gain flatness and the differential gain/phase performance of the OPA642 will provide exceptional results in video distribution applications. Differential Gain and Phase measure the change in overall small-signal gain and phase for the color subcarrier frequency (3.58MHz in NTSC systems) vs changes in the large-signal output level (which represents luminance information in a composite video signal). The OPA642, with the typical 150Ω load of a single matched video cable, shows less than 0.01%/0.01° differential gain/phase errors over the standard luminance range for a positive video (negative sync) signal. Similar performance would be observed for negative video signals. In practice, similar performance is achieved even with two video loads due to the linear high-frequency output impedance of the OPA642. +5V Power Supply De-coupling Not Shown R1 SINGLE OP-AMP DIFFERENTIAL AMPLIFIER The voltage feedback architecture of the OPA642, with its high CMR, will provide exceptional performance in differential amplifier configurations. Figure 2 shows a typical configuration. The starting point for this design is the selection of the RF value in the range of 200Ω to 2kΩ. Lower values reduce the required RG increasing the load on the V2 source and on the OPA642 output. Higher values increase output noise and exacerbate the effects of parasitic board and device capacitances. Following the selection of RF, RG must be set to achieve the desired inverting gain for V2. Remember that the bandwidth will be set approximately by the gain bandwidth product (GBP) divided by the noise gain (1+ RF/RG). For accurate differential operation (i.e. good CMR), the ratio R2/R1 must be set equal to RF/RG. Usually, it is best to set the absolute values of R2 and R1 equal to RF and RG respectively; this equalizes the divider resistances and cancels the effect of input bias currents. However, it is sometimes useful to scale the values of R2 and R1 in order to adjust the loading on the driving source V1. In most cases, the achievable low frequency CMR will be limited by the accuracy of the resistor values. The 90dB CMR of the OPA642 itself will not determine the overall circuit CMR unless the resistor ratios are matched to better than 0.003%. If it is necessary to trim the CMR, then R2 is the suggested adjustment point. V1 R2 OPA642 VO = RF RG when V2 RF RG (V1 – V2) R2 R1 = RF RG –5V FIGURE 2. High Speed, Single Amplifier Differential Amplifier. V1 Power Supplies and De-coupling Not Shown 1/2 OPA2650 RG 1kΩ RF1 500Ω 1kΩ RF1 500Ω 1kΩ OPA642 VO 1kΩ THREE OP AMP DIFFERENCING (Instrumentation Topology) The primary drawback of the single op-amp differential amplifier is its relatively low input impedances. Where a high impedance is required at the differential input, a standard instrumentation amplifier (INA) topology may be built using the OPA642 as the differencing stage. Figure 3 shows an example of this, in which the two input amplifiers are 1/2 OPA2650 1kΩ VO = 2 (V1 – V2) V2 FIGURE 3. Wideband 3-Op Amp Differencing Amplifier. ® 9 OPA642 DAC TRANSIMPEDANCE AMPLIFIER High frequency DDC DACs require a low distortion output amplifier to retain their SFDR performance into real-world loads. A single-ended output drive implementation is shown in Figure 4. In this circuit, only one side of the complementary output drive signal is used. The diagram shows the signal output current connected into the virtual ground summing junction of the OPA642, which is set up as a transimpedance stage or “I-V converter”. The unused current output of the DAC is connected to ground. If the DAC requires its outputs terminated to a compliance voltage other than ground for operation, then the appropriate voltage level may be applied to the non-inverting input of the OPA642. The DC gain for this circuit is equal to RF. At high frequencies, the DAC output capacitance will produce a zero in the noise gain for the OPA642 that may cause peaking in the closed-loop frequency response. CF is added across RF to compensate for this noise gain peaking. To achieve a flat transimpedance frequency response, this pole in the feedback network should be set to: Figure 5 shows an example Sallen-Key low pass filter, in which the OPA642 is set up to deliver a low frequency gain of +2. The filter component values have been selected to achieve a maximally flat Butterworth response with a 5MHz –3dB bandwidth. The resistor values have been slightly adjusted to compensate for the effects of the 150MHz bandwidth provided by the OPA642 in this configuration. This filter may be combined with the ADC driver suggestions to provide moderate (2-pole) Nyquist filtering, limiting noise and out of band components into the input of an ADC. This filter will deliver the exceptionally low harmonic distortion required by high SFDR A/D converters such as the ADS804 (12-bit, 10MSPS, 80dB SFDR). 150pF 124Ω 505Ω VI 100pF OPA642 VO 1 / 2πR F C F = GBP / ( 4πR F C D ) 402Ω which will give a corner frequency ƒ-3dB of approximately: 402Ω ƒ –3dB = GBP / 2πR F C D FIGURE 5. 5MHz Butterworth Low Pass Active Filter. OPERATING SUGGESTIONS OPA642 High Speed DAC VO = IO RF OPTIMIZING RESISTOR VALUES Since the OPA642 is a unity gain stable voltage feedback op amp, a wide range of resistor values may be used for the feedback and gain setting resistors. The primary limits on these values are set by dynamic range (noise and distortion) and parasitic capacitance considerations. For a non-inverting unity gain follower application, the feedback connection should be made with a 25Ω resistor—not a direct short. This will isolate the inverting input capacitance from the output pin and improve the frequency response flatness. Usually, the feedback resistor value should be between 200Ω and 1kΩ. Below 200Ω, the feedback network will present additional output loading which can degrade the harmonic distortion performance of the OPA642. Above 1kΩ, the typical parasitic capacitance (approximately 0.2pF) across the feedback resistor may cause unintentional band-limiting in the amplifier response. RF CF IO CD GBP → Gain Bandwidth Product for the OPA642 IO FIGURE 4. Wideband, Low Distortion DAC Transimpedance Amplifier. A good rule of thumb is to target the parallel combination of RF and RG (Figure 1) to be less than about 200Ω. The combined impedance RF || RG interacts with the inverting input capacitance, placing an additional pole in the feedback network and thus a zero in the forward response. Assuming a 2pF total parasitic on the inverting node, holding RF || RG < 200Ω will keep this pole above 400MHz. By itself, this constraint implies that the feedback resistor RF can increase to several kΩ at high gains. This is acceptable as long as the pole formed by RF and any parasitic capacitance appearing in parallel is kept out of the frequency range of interest. ACTIVE FILTERS Most active filter topologies will deliver exceptional performance using the broad bandwidth and unity gain stability of the OPA642. Topologies employing capacitive feedback require a unity gain stable voltage feedback op amp. SallenKey filters simply use the op amp as a non-inverting gain stage inside an RC network. Either current or voltage feedback op amps may be used in Sallen-Key implementations. ® OPA642 10 DRIVING CAPACITIVE LOADS One of the most demanding, and yet very common, load conditions for an op amp is capacitive loading. A high speed, high open-loop gain, amplifier like the OPA642 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. In simple terms, the capacitive load reacts with the open-loop output resistance of the amplifier to introduce an additional pole into the loop and thereby decrease the phase margin. This issue has become a popular topic of application notes and articles, and several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. In the inverting configuration, an additional design consideration must be noted. RG becomes the input resistor and therefore the load impedance to the driving source. If impedance matching is desired, RG may be set equal to the required termination value. However, at low inverting gains the resultant feedback resistor value can present a significant load to the amplifier output. For example, an inverting gain of 2 with a 50Ω input matching resistor (= RG) would require a 100Ω feedback resistor, which would contribute to output loading in parallel with the external load. In such a case, it would be preferable to increase both the RF and RG values, and then achieve the input matching impedance with a third resistor to ground. The total input impedance becomes the parallel combination of RG and the additional shunt resistor. BANDWIDTH VS GAIN Voltage feedback op amps exhibit decreasing closed-loop bandwidth as the signal gain is increased. In theory, this relationship is described by the Gain Bandwidth Product (GBP) shown in the specifications. Ideally, dividing GBP by the non-inverting signal gain (also called the Noise Gain, or NG) will predict the closed-loop bandwidth. In practice, this only holds true when the phase margin approaches 90°, as it does in high gain configurations. At low signal gains, most amplifiers will exhibit a more complex response with lower phase margin. The OPA642 is optimized to give a maximally flat second order Butterworth response in a gain of 2. In this configuration, the OPA642 has approximately 60° of phase margin and will show a typical –3dB bandwidth of 150MHz. When the phase margin is 60°, the closed-loop bandwidth is approximately √2 greater than the value predicted by dividing GBP by the noise gain. Increasing the gain will cause the phase margin to approach 90° and the bandwidth to more closely approach the predicted value of (GBP/NG). At a gain of +10, the 21MHz bandwidth shown in the Typical Specifications agrees with that predicted using the simple formula and the typical GBP of 210MHz. The Typical Performance Curves show the recommended RS vs Capacitive Load and the resulting frequency response at the load. The criterion for setting the recommended resistor is maximum bandwidth, flat frequency response at the load. Since there is now a passive low pass filter between the output pin and the load capacitance, the response at the output pin itself is typically somewhat peaked, and becomes flat after the rolloff action of the RC network. This is not a concern in most applications, but can cause clipping if the desired signal swing at the load is very close to the amplifier’s swing limit. Such clipping would be most likely to occur in pulse response applications where the frequency peaking is manifested as an overshoot in the step response. Parasitic capacitive loads greater than 2pF can begin to degrade the performance of the OPA642. Long PC board traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. Always consider this effect carefully, and add the recommended series resistor as close as possible to the OPA642 output pin (see Board Layout Guidelines). OUTPUT DRIVE CAPABILITY The OPA642 has been optimized to drive the demanding load of a doubly terminated transmission line. When a 50Ω line is driven, a series 50Ω into the cable and a terminating 50Ω load at the end of the cable are used. Under these conditions, the cable’s impedance will appear resistive over a wide frequency range, and the total effective load on the OPA642 is 100Ω in parallel with the resistance of the feedback network. The Specifications show a guaranteed ±2.5V swing into a such a load—which will then be reduced to a ±1.25V swing at the termination resistor. The guaranteed ±35mA output drive over temperature provides adequate current drive margin for this load. Higher voltage swings (and lower distortion) are achievable when driving higher impedance loads. DISTORTION PERFORMANCE The OPA642 is capable of delivering an exceptionally low distortion signal at high frequencies and low gains. The distortion plots in the Typical Performance Curves show the typical distortion under a wide variety of conditions. Most of these plots are limited to 100dB dynamic range. The OPA642’s distortion does not rise above –100dBc until either the signal level exceeds 0.5V and/or the fundamental frequency exceeds 500kHz. Distortion in the audio band is ≤ –120dBc. Generally, until the fundamental signal reaches very high frequencies or powers, the second harmonic will dominate the distortion with negligible third harmonic component. Focusing then on the second harmonic, increasing the load impedance improves distortion directly. Remember that the total load includes the feedback network—in the non-inverting A single video load typically appears as a 150Ω load (using standard 75Ω cables) to the driving amplifier. The OPA642 provides adequate voltage and current drive to support up to 3 parallel video loads (50Ω total load) for an NTSC signal. With only one load, the OPA642 achieves an exceptionally low 0.007%/0.008° dG/dP error. ® 11 OPA642 model, all the noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz. configuration this is sum of RF + RG, while in the inverting configuration this is just RF (Figure 1). Increasing output voltage swing increases harmonic distortion directly. A 6dB increase in output swing will generally increase the second harmonic 12dB and the third harmonic 18dB. Increasing the signal gain will also increase the second harmonic distortion. Again a 6dB increase in gain will increase the second and third harmonic by 6dB even with a constant output power and frequency. And finally, the distortion increases as the fundamental frequency increases due to the rolloff in the loop gain with frequency. Conversely, the distortion will improve going to lower frequencies down to the dominant open-loop pole at approximately 3kHz. Starting from the –90dBc second harmonic for 2Vp-p into 500Ω, G = +2 distortion at 1MHz (from the Typical Performance Curves), the second harmonic distortion at 20kHz should be approximately –90dB – 20log (1MHz/20kHz) = –124dBc. The total output spot noise voltage can be computed as the square root of the squared contributing terms to the output noise voltage. This computation is adding all the contributing noise powers at the output by superposition, then taking the square root to get back to a spot noise voltage. Equation 1 shows the general form for this output noise voltage using the terms shown in Figure 6. Eq. 1 EO = 2 NI ) + ( I BN R S ) + 4kTR S G N 2 + ( I BI R F ) + 4kTR F G N 2 2 ENI EO OPA642 RS The OPA642 has an extremely low third order harmonic distortion. This also gives an exceptionally good two-tone, third-order intermodulation intercept as shown in the Typical Performance Curves. This intercept curve is defined at the 50Ω load when driven through a 50Ω matching resistor to allow direct comparisons to RF MMIC devices. This network attenuates the voltage swing from the output pin to the load by 6dB. If the OPA642 drives directly into the input of a high impedance device, such as an ADC, this 6dB attenuation is not taken. Under these conditions, the intercept will increase by a minimum 6dBm. The intercept is used to predict the intermodulation spurious for two closely spaced frequencies. If the two test frequencies, f1 and f2, are specified in terms of average and delta frequency, fO = (f1 + f2)/2 and ∆f = |f2 – f2 | /2, the two, third-order, close-in spurious tones will appear at fO ± (3 • ∆f). The difference between two equal test tone power levels and these intermodulation spurious power levels is given by 2 • (IM3 – PO) where IM3 is the intercept taken from the Typical Performance Curve and PO is the power level in dBm at the 50Ω load for one of the two closely spaced test frequencies. For instance, at 10MHz the OPA642 at a gain of +2 has an intercept of 46dBm at a matched 50Ω load. If the full envelope of the two frequencies needs to be 2Vp-p, this requires each tone to be 4dBm. The third-order intermodulation spurious tones will then be 2 • (46 – 4) = 84dBc below the test tone power level (–80dBm). If this same 2Vp-p two-tone envelope were delivered directly into the input of an ADC without the matching loss or loading of the 50Ω network, the intercept would increase to at least 52dBm. With the same signal and gain conditions but now driving directly into a light load, the spurious tones will then be at least 2 • (52 – 4) = 96dBc below the 1Vp-p test tone signal levels. IBN ERS RF √ 4kTRS RG 4kT RG IBI √ 4kTRF 4kT = 1.6E –20J at 290°K FIGURE 6. Op Amp Noise Analysis Model. Dividing this expression by the noise gain (GN = 1 + RF/RG) will give the equivalent input referred spot noise voltage at the non-inverting input as shown in Equation 2. Eq. 2 E N = E NI + ( I BN R S ) 2 2 2 I R 4kTR F + 4kTR S + BI F + G GN N Evaluating these two equations for the OPA642 circuit shown in Figure 1 will give a total output spot noise voltage of 6.7nV/√Hz and an equivalent input spot noise voltage of 3.35nV/√Hz. Narrowband communications systems are more commonly concerned with the noise figure for the amplifier. The total input referred voltage noise expression (Eq. 2), may be used to calculate the noise figure. Equation 3 shows this noise figure expression using the EN of Eq. 2 for the non-inverting configuration where the input terminating resistor RT has been set to match the source impedance (as shown in Figure 1). E 2 NF = 10 log 2 + N kTRs Eq. 3 Evaluating Equation 3 for the circuit of Figure 1 gives a Noise Figure = 17.6dB. Input transformer coupling can be used to reduce this noise figure. A broadband pulse transformer can provide both a noiseless voltage gain and a more optimum source impedance to minimize the noise figure. Figure 7 shows an example built from the circuit of Figure 1, in which the transformer turns ratio has been set to the NOISE PERFORMANCE The OPA642 complements its ultra-low harmonic distortion with low input noise terms. Both the input referred voltage noise, and the two input referred current noise terms combine to give a low output noise under a wide variety of operating conditions. Figure 6 shows the op amp noise analysis model with all the noise terms included. In this ® OPA642 (E 12 closest integer for minimum noise figure. This optimum turns ratio is calculated by Eq. 4 ( the offset control is best applied as an inverting summing signal. If the signal path is intended to be inverting, applying the offset control to the non-inverting input can be considered. For a DC coupled signal, the DC offset signal can, in some configurations, set up a DC current back into the source that must be considered. An adjustment placed on the inverting op amp input can also change the noise gain and frequency response flatness. Figure 8 shows one example of an offset adjustment for a DC coupled signal path that will have minimum impact on the signal frequency response. In this case, the input is brought in to an inverting gain resistor with the DC adjustment an additional current summed into the inverting node. The resistor network setting this current is much larger than the signal path resistors. This will insure that this adjustment has minimal impact on the loop gain and hence the frequency response. ) N OPT = Nearest Integer E N / I BN • ( R S / 2 ) This optimum will depend strongly on the amplifier and configuration selected. AV = 7V/V [16.9dB] RS = 50Ω 1:7 Supply Decoupling Not Shown 50Ω 2.4kΩ OPA642 50Ω Load 402Ω +5V 6.3dB Noise Figure Supply Decoupling Not Shown 402Ω 0.1µF 328Ω OPA642 VO FIGURE 7. Reduced Noise Figure Circuit. DC OFFSET CONTROL The OPA642 can provide excellent DC signal accuracy due to its high open-loop gain, high common-mode rejection, high power supply rejection, and low input offset voltage and bias current offset errors. The high grade (B) version of any package type provides less than 1mV input offset voltage. To take full advantage of this low input offset voltage, a careful attention to input bias current cancellation is also required. The high speed input stage for the OPA642 has a relatively high input bias current (25µA typ into the pins) but with a very close match between the two input currents—typically 100nA input offset current. The total output offset voltage may be considerably reduced by matching the source impedances looking out of the two inputs. For example, one way to add bias current cancellation to the circuit of Figure 1 would be to insert a 175Ω series resistor into the non-inverting input from the 50Ω terminating resistor. When the 50Ω source resistor is DC coupled, this will increase the source impedance for the non-inverting input bias current to 200Ω. Since this is now equal to the impedance looking out of the inverting input (RF || RG), the circuit will cancel the gains for the bias currents to the output leaving only the offset current times the feedback resistor as a residual DC error term at the output. Using a 402Ω feedback resistor, this output error will now be less than 3µA • 402Ω = 1.2mV. –5V +5V RG 500Ω RF 1kΩ VI 5kΩ 20kΩ ±200mV Output Adjustment 10kΩ 0.1µF 5kΩ VO VI =– RF RG = –2 –5V FIGURE 8. DC Coupled, Inverting Gain of –2, with Output Offset Adjustment. THERMAL ANALYSIS The OPA642 will not require heatsinking under most operating conditions. Maximum desired junction temperature will set a maximum allowed internal power dissipation as described below. In no case should the maximum junction temperature be allowed to exceed 175°C. Operating junction temperature (T J ) is given by TA + PD • θJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL will depend on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 either supply voltage (for equal bipolar supplies). Under this condition PDL = VS2/(4 • RL) where RL includes feedback network loading. A fine scale output offset null, or DC operating point adjustment, is sometimes required. Numerous techniques are available for introducing a DC offset control into an op amp circuit. Most of these techniques eventually reduce to setting up a DC current through the feedback resistor. One key consideration to selecting a technique is to insure that it has a minimal impact on the desired signal path frequency response. If the signal path is intended to be non-inverting, ® 13 OPA642 the output and inverting input pins. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal film or surface mount resistors have approximately 0.2pF in shunt with the resistor. For resistor values > 1.5kΩ, this parasitic capacitance can add a pole and/or zero below 500MHz that can effect circuit operation. Keep resistor values as low as possible consistent with load driving considerations. The 402Ω feedback used in the typical performance specifications is a good starting point for design. Note that a 25Ω feedback resistor, rather than a direct short is suggested for the unity gain follower application. This effectively isolates the inverting input capacitance from the output pin that would otherwise cause a slight peaking in the gain of +1 frequency response. Note that it is the power in the output stage and not into the load that determines internal power dissipation. As a worst case example, compute the maximum TJ using an OPA642N (SOT23-5 package) in the circuit of Figure 1 operating at the maximum specified ambient temperature of +85°C. PD = 10V • 26mA +5^2 /(4 • (100Ω || 804Ω)) = 330mW. Maximum TJ = +85°C + 0.33W • 150°C/W = 135°C. BOARD LAYOUT GUIDELINES Achieving optimum performance with a high frequency amplifier like the OPA642 requires careful attention to board layout parasitics and external component types. Recommendations that will optimize performance include: a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability: on the noninverting input, it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Ground and power planes should be unbroken elsewhere on the board. d) Connections to other wideband devices on the board may be made with short direct traces or through on-board transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50 to 100mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the plot of recommended RS vs Capacitive Load. Low parasitic capacitive loads (< 5pF) may not need an RS since the OPA642 is nominally compensated to operate with a 2pF parasitic load. Higher parasitic cap. loads without an RS are allowed as the signal gain increases (increasing the unloaded phase margin). If a long trace is required, and the 6dB signal loss intrinsic to a doubly terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is normally not necessary on board, and in fact a higher impedance environment will improve distortion as shown in the Distortion vs Load plots. With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the OPA642 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device: this total effective impedance should be set to match the trace impedance. Multiple destination devices are best handled as separate transmission lines, each with their own series and shunt terminations. If the 6dB attenuation of a doubly terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of RS vs Capacitive load. This will not preserve signal integrity as well as a doubly terminated line. If the input impedance of the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. b) Minimize the distance (< 0.25") from the power supply pins to high frequency 0.1uF decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The primary power supply connections (on pins 4 and 7) should always be decoupled with these capacitors. Optional output stage power supply connections on pins 5 and 8 may be used to get a slight improvement in harmonic distortion and settling time (for the 8-pin packaged parts). Place additional 0.1µF decoupling capacitors very near to these pins to improve performance. Larger (2.2µF to 6.8µF) decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. c) Careful selection and placement of external components will preserve the high frequency performance of the OPA642. Resistors should be a very low reactance type. Surface mount resistors work best and allow a tighter overall layout. Metal film and carbon composition axially leaded resistors can also provide good high frequency performance. Again, keep their leads and PC board trace length as short as possible. Never use wirewound type resistors in a high frequency application. Since the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as noninverting input termination resistors, should also be placed close to the package. Where double side component mounting is allowed, place the feedback resistor directly under the package on the other side of the board between ® OPA642 14 e) Socketing a high speed part like the OPA642 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA642 onto the board. If socketing for the DIP package is desired, high frequency flush mount pins (e.g., McKenzie Technology #710C) can give good results. 50Ω Source Power Supply Decoupling Not Shown D2 50Ω 50Ω OPA642 D1 50Ω INPUT AND ESD PROTECTION The OPA642 is built using a very high speed complementary bipolar process. The internal junction breakdown voltages are relatively low due to these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Rating table. All device pins are protected with internal ESD protection diodes to the power supplies as shown in Figure 9. –5V 301Ω 301Ω D1, D2 → IN5911 (or equivalent) FIGURE 10. Gain of +2 with Input Protection. DESIGN-IN TOOLS DEMONSTRATION BOARDS Several PC boards are available in the initial evaluation of circuit performance using the OPA642 in its three package styles. Two partially assembled boards are available for sale to support the DIP (P suffix) and SO-8 (U-suffix) packages. These boards come partially assembled with power supply and I/O connectors but do not have the amplifier or resistor networks loaded. Both boards are configured for low distortion, non-inverting amplifier operation. Order these boards by the following part numbers from your local BurrBrown distributor: +V CC External Pin +5V 174Ω Internal Circuitry –V CC FIGURE 9. Internal ESD Protection. DEM-OPA64XP-N for the OPA642P and OPA642PB (8-pin DIP package) DEM-OPA64XU-N for the OPA642U and OPA642UB (8-pin SO package) These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher currents are possible (e.g. in systems with ±15V supply parts driving into the OPA642), current limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible since high values degrade both noise performance and frequency response. The SOT23-5 package version of the OPA642 may be evaluated using a single unpopulated board used for numerous SOT23-5 packaged amplifiers available from Burr-Brown. This board is available from the Burr-Brown Literature department as an unpopulated board attached to a descriptive document. This board, the DEM-OPA6xxN, is available free by requesting literature number MKT-348. High input overdrive signals can also cause significant differential voltage between the + and – inputs. Where this voltage can exceed the maximum rated voltage of ±1.2V, external Schottky protection diodes should be added across the two inputs. Again, the capacitance added by these diodes can degrade the noise and AC performance and should be used only where necessary. Figure 9 shows a fully featured input protection circuit for the OPA642. This is the circuit of Figure 1 with additional limiting resistors into the inputs and Schottky clamp diodes across the inputs. These resistor values have been selected to limit the degradation in noise and frequency response, achieve DC bias current cancellation, and limit the current that will flow under overdrive conditions. MACROMODELS AND APPLICATIONS SUPPORT Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model for the OPA642 is available through either the Burr-Brown web page (http://www.burr-brown.com) or as a disk from the Burr-Brown Applications Department (1-800548-6132). The application department is also available for design assistance at this number. These models do a good job of predicting small signal AC and transient performance under a wide variety of operating conditions. They do not do as good a job in predicting the harmonic distortion or dG/dP characteristics. These models do not attempt to distinguish between the package types in their small signal AC performance. ® 15 OPA642