OPA 693 OPA6 93 OPA693 SBOS285 – OCTOBER 2003 Ultra-Wideband, Fixed Gain Video BUFFER AMPLIFIER with Disable FEATURES DESCRIPTION ● VERY HIGH BANDWIDTH (G = +2): 700MHz ● FLEXIBLE SUPPLY RANGE: +5V to +12V Single Supply ±2.5V to ±6V Dual Supplies ● INTERNALLY FIXED GAIN: +2 or ±1 ● LOW SUPPLY CURRENT: 13mA ● LOW DISABLED CURRENT: 120µA ● HIGH OUTPUT CURRENT: ±120mA ● OUTPUT VOLTAGE SWING: ±4.1V ● SOT23-6 AVAILABLE The OPA693 provides an easy to use, broadband, fixed gain buffer amplifier. Depending on the external connections, the internal resistor network may be used to provide either a fixed gain of +2 video buffer or a gain of ±1 voltage buffer. Operating on a low 13mA supply current, the OPA693 offers a slew rate (2500V/µs) and bandwidth (> 700MHz) normally associated with a much higher supply current. A new output stage architecture delivers high output current with a minimal headroom and crossover distortion. This gives exceptional single-supply operation. Using a single +5V supply, the OPA693 can deliver a 2.5VPP swing with over 90mA drive current and 500MHz bandwidth at a gain of +2. This combination of features makes the OPA693 an ideal RGB line driver or single-supply undersampling Analog-to-Digital Converter (ADC) input driver. APPLICATIONS ● ● ● ● ● ● The OPA693’s low 13mA supply current is precisely trimmed at 25°C. This trim, along with low drift over temperature, ensures lower maximum supply current than competing products that report only a room temperature nominal supply current. System power may be further reduced by using the optional disable control pin. Leaving this disable pin open, or holding it HIGH, gives normal operation. This optional disable allows the OPA693 to fit into existing video buffer layouts where the disable pin is unconnected to get improved performance with no board changes. If pulled LOW, the OPA693 supply current drops to less than 170µA while the output goes into a high impedance state. This feature may be used for power savings. BROADBAND VIDEO LINE DRIVERS MULTIPLE LINE VIDEO DA PORTABLE INSTRUMENTS ADC BUFFERS HIGH FREQUENCY ACTIVE FILTERS HFA1112 IMPROVED DROP-IN OPA693 RELATED PRODUCTS SINGLES DUALS TRIPLES OPA690 OPA2690 OPA3690 Current Feedback OPA691 OPA2691 OPA3691 Fixed Gain OPA692 — OPA3692 > 900MHz OPA695 — — Voltage Feedback The low gain stable current-feedback architecture used in the OPA693 is particularly suitable for high full-power bandwidth cable driving requirements. Where the additional flexibility of an op amp is required, consider the OPA695 ultra-wideband current feedback op amp. Where a unity gain stable voltage feedback op amp with very high slew rate is required, consider the OPA690. OPA693 1 300Ω 8 DIS 75Ω 300Ω Video In 2 7 3 6 4 5 Video Out +5V RG-59 75Ω 75Ω −5V 75Ω Video Out RG-59 75Ω SO-8 G = +2 700MHz, 2-Output Component Video DA Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2002-2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) Power Supply ............................................................................... ±6.5VDC Internal Power Dissipation(2) ............................ See Thermal Information Differential Input Voltage .................................................................. ±1.2V Input Voltage Range ............................................................................ ±VS Storage Temperature Range: D, DVB ........................... –40°C to +125°C Lead Temperature (soldering, 10s) .............................................. +300°C Junction Temperature (TJ ) ........................................................... +150°C ESD Rating (Human Body Model) .................................................. 2000V (Charge Device Model) ............................................... 1000V (Machine Model) ............................................................ 100V This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTES:: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. (2) Packages must be derated based on specified θJA. Maximum TJ must be observed. PACKAGE/ORDERING INFORMATION SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY OPA693ID OPA693IDR OPA693IDBVT OPA693IDBVR Rails, 100 Tape and Reel, 2500 Tape and Reel, 250 Tape and Reel, 3000 PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR(1) OPA693 SO-8 D –40°C to +85°C OPA693D " " " " " OPA693 SOT23-6 DBV –40°C to +85°C C59 " " " " " NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. PIN CONFIGURATION Top View SO Top View SOT23 Output 1 6 +VS 5 DIS 4 −IN RF 300Ω NC 1 RG −IN 2 +IN 3 RF 300Ω 8 2 +IN 3 DIS 7 +VS 6 Output 300Ω −VS RG 300Ω 6 −VS 4 5 5 4 NC C59 NC = No Connection 1 2 3 Pin Orientation/Package Marking 2 OPA693 www.ti.com SBOS285 ELECTRICAL CHARACTERISTICS: VS = ±5V Boldface limits are tested at 25°C. G = +2 (–IN grounded) and RL = 100Ω (see Figure 1 for AC performance only), unless otherwise noted. OPA693ID, IDBV MIN/MAX OVER TEMPERATURE(1) TYP PARAMETER +25°C 0°C to 70°C –40°C to +85°C MHz typ 700 510 490 480 MHz min B G = –1 700 510 490 480 MHz typ C B CONDITIONS +25°C G = +1 1400 G = +2 UNITS MIN/ TEST MAX LEVEL(2 ) AC PERFORMANCE (see Figure 1) Small-Signal Bandwidth (VO < 1.0VPP) Bandwidth for 0.2dB Gain Flatness C G = +2, VO < 1.0VPP, RL = 150Ω 400 122 112 108 MHz min Peaking at a Gain of +1 VO < 1.0VPP 2.5 3.8 4.8 5.2 dB max B Large-Signal Bandwidth G = +2, VO = 4VPP 400 MHz typ C Slew Rate Rise-and-Fall Time Settling Time to 0.02% Settling Time to 0.1% Harmonic Distortion 2nd-Harmonic 3rd-Harmonic G = +2, 4V Step 2500 2200 2100 2000 V/µs min B G = +2, VO = 0.5V Step 0.6 0.8 0.8 0.8 ns max B G = +2, VO = 5V Step 1.2 1.3 1.3 1.4 ns max B G = +2, VO = 2V Step 16 ns typ C G = +2, VO = 2V Step 12 ns typ C G = +2, f = 10MHz, VO = 2VPP RL = 100Ω –69 –66 –65 –64 dBc max B RL ≥ 500Ω –82 –80 –79 –78 dBc max B RL = 100Ω –83 –80 –70 –69 dBc max B RL ≥ 500Ω –96 –86 –85 –82 dBc max B Input Voltage Noise f > 1MHz 1.8 2 2.7 2.9 nV/√Hz max B Noninverting Input Current Noise f > 1MHz 18 19 21 22 pA/√Hz max B Inverting Input Current Noise (internal) f > 1MHz 22 24 26 27 pA/√Hz max B NTSC, RL = 150Ω 0.03 % typ C NTSC, RL = 37.5Ω 0.03 % typ C NTSC, RL = 150Ω 0.01 deg typ C NTSC, RL = 37.5Ω 0.1 deg typ C G = +1 ±0.2 % typ C G = +2 ±0.3 ±0.9 ±1.0 ±1.1 % max A G = –1, RS = 0Ω ±0.2 ±0.8 ±0.9 ±1.0 % max B VO = ±2, RL = 100Ω, G = +2 0.0016 % typ C Differential Gain Differential Phase DC PERFORMANCE(3) Gain Error DC Linearity Internal RF and RG Maximum 300 341 345 346 Ω max A Minimum 300 264 260 259 Ω min A 0.03 0.03 %/C° max B ±2.3 ±2.5 mV max A ±5 ±8 µV/°C max B Average Drift Input Offset Voltage VCM = 0V Average Offset Voltage Drift VCM = 0V Noninverting Input Bias Current VCM = 0V Average Noninverting Input Bias Current Drift VCM = 0V Inverting Input Bias Current (internal) VCM = 0V Average Inverting Input Bias Current Drift VCM = 0V ±0.3 +15 ±20 ±2.0 ±35 ±50 ±43 ±45 µA max A 170 170 nA/°C max B ±52 ±54 µA max A 50 60 nA°C max B ±3.2 ±3.2 INPUT ±3.4 Common-Mode Input Range Noninverting Input Impedance ±3.3 300 || 1.2 V min B kΩ || pF typ C OUTPUT No Load ±4.1 ±3.8 V min A ±3.8 ±3.9 ±3.7 ±3.9 100Ω Load ±3.7 ±3.6 V min A Current Output, Sourcing +120 +90 +80 +70 mA min A Current Output, Sinking –120 –90 –80 –70 mA min A Ω typ C Voltage Output Swing Closed-Loop Output Impedance G = +2, f = 100kHz 0.18 (1) Junction temperature = ambient temperature for low temperature limit and +25°C specifications. Junction temperature = ambient temperature +20°C at high temperature limit specifications. (2) Test Levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (3) Current is considered positive out-of-node. VCM is the input common-mode voltage. OPA693 SBOS285 www.ti.com 3 ELECTRICAL CHARACTERISTICS: VS = ±5V (Cont.) Boldface limits are tested at 25°C. G = +2 (–IN grounded) and RL = 100Ω (see Figure 1 for AC performance only), unless otherwise noted. OPA693ID, IDBV MIN/MAX OVER TEMPERATURE(1) TYP PARAMETER CONDITIONS +25°C +25°C 0°C to 70°C –40°C to +85°C UNITS –170 –186 –192 µA max A µs typ C MIN/ TEST MAX LEVEL(2 ) DISABLE/POWER DOWN (DIS Pin) Power-Down Supply Current (+VS) VDIS = 0V –70 VIN = +1VDC 3 Enable Time VIN = +1VDC 25 ns typ C Off Isolation G = +2, 5MHz 70 dB typ C 4 pF typ C Turn-On Glitch G = +2, RL = 150Ω, VIN = 0VDC ±100 mV typ C Turn-Off Glitch G = +2, RL = 150Ω, VIN = 0VDC ±20 mV typ C Enable Voltage +VS = +5V 3.3 3.5 3.6 3.7 V min A Disable Voltage +VS = +5V 1.8 1.7 1.6 1.5 V max A Control Pin Input Bias Current VDIS = 0V 75 130 143 149 µA max A V typ C ±6 ±6 ±6 V max A Disable Time Output Capacitance in Disable POWER SUPPLY ±5 Specified Operating Voltage Maximum Operating Voltage Range Max Quiescent Current VS = ±5V 13 13.3 13.7 14.1 mA max A Min Quiescent Current VS = ±5V 13 12.5 11.6 11.0 mA min A Input Referred 58 54 52 51 dB min A –40 to +85 °C typ C 125 °C/W typ C 150 °C/W typ C Power-Supply Rejection Ratio (+PSRR) TEMPERATURE RANGE Specification: D, DBV Thermal Resistance, θJA D SO-8 DBV SOT23-6 (1) Junction temperature = ambient temperature for low temperature limit and +25°C specifications. Junction temperature = ambient temperature +20°C at high temperature limit specifications. (2) Test Levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (3) Current is considered positive out-of-node. VCM is the input common-mode voltage. 4 OPA693 www.ti.com SBOS285 ELECTRICAL CHARACTERISTICS: VS = +5V Boldface limits are tested at +25°C. G = +2 (–IN grounded though 0.001µF) and RL = 100Ω to VS/2 (see Figure 4 for AC performance only), unless otherwise noted. OPA693ID, IDBV TYP PARAMETER CONDITIONS +25°C MIN/MAX OVER TEMPERATURE +25°C(1) 0°C to 70°C –40°C to +85°C UNITS MHz typ 400 390 380 MHz min B MHz typ C B MIN/ TEST MAX LEVEL(2 ) AC PERFORMANCE (see Figure 4) Small-Signal Bandwidth (VO < 1.0VPP) Bandwidth for 0.2dB Gain Flatness G = +1 634 G = +2 526 G = –1 512 C G = +2, VO < 1.0VPP 210 110 100 96 MHz min Peaking at a Gain of +1 VO < 1.0VPP 1.9 2.6 3.6 3.9 dB max B Large-Signal Bandwidth G = +2, VO = 2VPP 400 MHz typ C Slew Rate Rise-and-Fall Time G = +2, 2V Step 1500 V/µs min B G = +2, VO = 0.5V Step 0.8 1200 1100 1000 ns typ C G = +2, VO = 2V Step 1.0 ns typ C Settling Time to 0.02% G = +2, VO = 2V Step 16 ns typ C Settling Time to 0.1% G = +2, VO = 2V Step 12 ns typ C Harmonic Distortion 2nd-Harmonic G = +2, f = 10MHz, VO = 2VPP RL = 100Ω to VS /2 –66 –62 –62 –61 dBc max B RL ≥ 500Ω to VS /2 –75 –69 –68 –68 dBc max B RL = 100Ω to VS /2 –70 –64 –63 –62 dBc max B RL ≥ 500Ω to VS /2 –69 –63 –62 –61 dBc max B Input Voltage Noise f > 1MHz 1.8 2 2.7 2.9 nV/√Hz max B Noninverting Input Current Noise f > 1MHz 18 19 21 22 pA/√Hz max B Inverting Input Current Noise f > 1MHz 22 24 26 27 pA/√Hz max B G = +1 ±0.2 % typ C G = +2 ±0.5 ±1.2 ±1.3 ±1.4 % max A G = –1 ±0.4 ±1.1 ±1.2 ±1.3 % max B Maximum 300 341 345 346 Ω max B Minimum 300 264 260 259 Ω min B 0.03 0.03 0.03 %/C° max B ±0.3 ±2.5 ±2.8 ±3.0 mV max A ±5 ±8 µV/°C max B +5 ±25 ±33 ±35 µA max A ±170 ±170 nA/°C max B ±52 ±54 µA max A ±50 ±60 nA°C max B 3rd-Harmonic DC PERFORMANCE(3) Gain Error Internal RF and RG Average Drift Input Offset Voltage VCM = 2.5V Average Offset Voltage Drift VCM = 2.5V Noninverting Input Bias Current VCM = 2.5V Average Noninverting Input Bias Current Drift VCM = 2.5V Inverting Input Bias Current VCM = 2.5V Average Inverting Input Bias Current Drift VCM = 2.5V ±20 ±50 INPUT Least Positive Input Voltage 1.6 1.7 1.8 1.8 V max B Most Positive Input Voltage 3.4 3.3 3.2 3.2 V min B kΩ || pF typ C Noninverting Input Impedance 300 || 1.2 OUTPUT Most Positive Output Voltage Least Positive Output Voltage No Load 4.1 3.9 3.9 3.8 V min A RL = 100Ω 3.9 3.8 3.8 3.7 V min A No Load 0.9 1.1 1.1 1.2 V max A RL = 100Ω 1.1 1.2 1.2 1.3 V max A Current Output, Sourcing +120 +90 +80 +70 mA min A Current Output, Sinking –120 –90 –80 –70 mA min A Ω typ C Output Impedance G = +2, f = 100kHz 0.18 (1) Junction temperature = ambient temperature for low temperature limit and +25°C specifications. Junction temperature = ambient temperature +10°C at high temperature limit specifications. (2) Test Levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (3) Current is considered positive out-of-node. VCM is the input common-mode voltage. OPA693 SBOS285 www.ti.com 5 ELECTRICAL CHARACTERISTICS: VS = +5V (Cont.) Boldface limits are tested at +25°C. G = +2 (–IN grounded though 0.001µF) and RL = 100Ω to VS/2 (see Figure 4 for AC performance only), unless otherwise noted. OPA693ID, IDBV TYP PARAMETER MIN/MAX OVER TEMPERATURE CONDITIONS +25°C(1) +25°C 0°C to 70°C –40°C to +85°C –155 –172 –180 UNITS MIN/ TEST MAX LEVEL(2 ) DISABLE/POWER DOWN (DIS Pin) Power-Down Supply Current (+VS) µA typ A dB typ C pF typ C mV typ B VDIS = 0 –95 G = +2, 5MHz 65 4 Turn-On Glitch G = +2, RL = 150Ω, VIN = 2.5V ±20 Turn-Off Glitch G = +2, RL = 150Ω, VIN = 2.5V ±20 mV typ B V min B Off Isolation Output Capacitance in Disable Enable Voltage 3.3 Disable Voltage Control Pin Input Bias Current (DIS ) VDIS = 0 3.5 3.6 3.7 1.8 1.7 1.6 1.5 V max B 80 137 153 160 µA typ A V typ C +12 +12 +12 V max A POWER SUPPLY Specified Single-Supply Operating Voltage 5 Maximum Single-Supply Operating Voltage Maximum Quiescent Current VS = +5V 11.5 12.0 12.5 12.9 mA max A Minimum Quiescent Current VS = +5V 11.5 11.0 9.5 9.2 mA min A Input Referred 57 dB typ C –40 to +85 °C typ C 125 °C/W typ C 150 °C/W typ C Power-Supply Rejection Ratio (+PSRR) TEMPERATURE RANGE Specification: D, DBV Thermal Resistance, θJA D SO-8 DBV SOT23-6 (1) Junction temperature = ambient temperature for low temperature limit and +25°C specifications. Junction temperature = ambient temperature +10°C at high temperature limit specifications. (2) Test Levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (3) Current is considered positive out-of-node. VCM is the input common-mode voltage. 6 OPA693 www.ti.com SBOS285 TYPICAL CHARACTERISTICS: VS = ±5V At TA = +25°C, G = +2, and RL = 100Ω, unless otherwise specified. LARGE-SIGNAL FREQUENCY RESPONSE SMALL-SIGNAL FREQUENCY RESPONSE 8 3 VO = 1VPP G = +1 G = +2 RL = 100Ω 7 6 1 G = +2 0 −1 G = −1 −2 4 2 −4 1 −5 0 −6 −1 100 1000 VO = 2VPP 3 −3 10 VO = 1VPP 5 Gain (dB) Normalized Gain (dB) 2 VO = 7VPP VO = 4VPP See Figure 1 0 2000 200 Frequency (MHz) FREQUENCY RESPONSE FLATNESS vs LOAD Normalized Gain (dB) 0.1 RL = 200Ω 0 −0.1 RL = 75Ω RL = 100Ω −0.3 See Figure 1 −0.4 RL = 100Ω 0.75 G = +1 0.50 G = −1 0.25 0 −0.25 G = +2 −0.50 −0.75 −1.00 0 100 200 Frequency (MHz) 300 400 0 50 GAIN OF +2 PULSE RESPONSE 150 200 GAIN OF +1 PULSE RESPONSE 3 RL = 100Ω RL = 100Ω Large Signal 2 Large Signal 2 1 1 Output (V) Small Signal 0 −1 Small Signal 0 −1 −2 −2 See Figure 1 See Figure 2 −3 −3 Time (2ns/div) Time (2ns/div) OPA693 SBOS285 100 Frequency (MHz) 3 Output (V) 1000 DEVIATION FROM LINEAR PHASE RL = 150Ω −0.2 800 1.00 G = +2 VO = 1VPP Deviation from Linear Phase (°) 0.2 400 600 Frequency (MHz) www.ti.com 7 TYPICAL CHARACTERISTICS: VS = ±5V (Cont.) At TA = +25°C, G = +2, and RL = 100Ω, unless otherwise specified. 10MHz HARMONIC DISTORTION vs LOAD RESISTANCE −60 −60 Harmonic Distortion (dBc) −65 −70 2nd Harmonic −75 −80 −85 3rd Harmonic G = +2 f = 10MHz VO = 2VPP See Figure 1 −90 −95 −100 50 3rd Harmonic −80 −85 G = +2 RL = 100Ω VO = 2VPP See Figure 1 −90 500 2.5 3.0 3.5 10MHz HARMONIC DISTORTION vs OUTPUT VOLTAGE −60 G = +2 RL = 100Ω f = 10MHz See Figure 1 −65 2nd Harmonic −80 3rd Harmonic −85 −90 −70 See Figure 1 −100 0.5 6.0 2nd Harmonic −75 −80 3rd Harmonic −85 −90 1 10 −100 0.5 50 1 G = –1 HARMONIC DISTORTION vs FREQUENCY G = +1 HARMONIC DISTORTION vs FREQUENCY RL = 100Ω VO = 2VPP See Figure 2 −50 2nd Harmonic 3rd Harmonic −75 RL = 100Ω VO = 2VPP See Figure 3 −55 Harmonic Distortion (dBc) −60 5 Output Voltage (VPP) Frequency (MHz) Harmonic Distortion (dBc) 5.5 −95 −95 −80 −85 −90 −95 −60 2nd Harmonic −65 −70 3rd Harmonic −75 −80 −85 −90 −95 −100 −100 0.5 1 10 0.5 50 Frequency (MHz) 8 5.0 G = +2 HARMONIC DISTORTION vs FREQUENCY −75 −70 4.5 Supply Voltage (±V) −70 −65 4.0 Load Resistance (Ω) RL = 100Ω VO = 2VPP −65 −75 −100 100 −60 2nd Harmonic −70 −95 Harmonic Distortion (dBc) Harmonic Distortion (dBc) −65 Harmonic Distortion (dBc) 10MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE 1 10 50 Frequency (MHz) OPA693 www.ti.com SBOS285 TYPICAL CHARACTERISTICS: VS = ±5V (Cont.) At TA = +25°C, G = +2, and RL = 100Ω, unless otherwise specified. 2-TONE, 3RD-ORDER INTERMODULATION INTERCEPT INPUT VOLTAGE vs CURRENT NOISE DENSITY 60 100 +5V Inverting Current Noise (internal) 22pA/√Hz Noninverting Current Noise 17.8pA/√Hz 10 Voltage Noise 50Ω Intercept Point (+dBm) Voltage Noise (nV/√Hz) Current Noise (pA/√Hz) PI PO OPA693 RF 300Ω 50 500Ω RG 300Ω −5V 40 +5V PI 30 50Ω PO OPA693 50Ω RF 300Ω 1.8nV/√Hz 50Ω RG 300Ω −5V 20 1 100 1k 10k 100k 1M 0 10M 25 50 Frequency (MHz) −10 −10 −20 VSWR < 1.2:1 G = −1 See Figure 3 −40 −50 G = +2 See Figure 1 125 150 175 200 No Output Trim Capacitor −20 VSWR < 1.2:1 −30 −40 50Ω OPA693 −50 G = +2 See Figure 1 −60 −70 With Trim Capacitor −60 10 60 100 1000 10 SMALL-SIGNAL FREQUENCY RESPONSE vs CAPACITIVE LOAD 9 Gain to Cap. Load (dB) RS VO OPA693 50Ω 300Ω CL 1kΩ 3 CL = 100pF CL = 10pF 0 CL = 50pF CL = 20pF −3 −6 300Ω 1kΩ is optional −9 0 10 100 Capacitive Load (pF) OPA693 SBOS285 G = +2 Optimized RS 6 VIN 1 1000 RECOMMENDED RS vs CAPACITIVE LOAD 30 10 100 Frequency (MHz) 40 20 S22 1.8pF Frequency (MHz) G = +2 < 0.1dB Peaking 50 RS (Ω) 100 OUTPUT RETURN LOSS vs FREQUENCY (S22) 0 Return Loss (dB) Return Loss (dB) INPUT RETURN LOSS vs FREQUENCY (S11) 0 −30 75 Frequency (MHz) www.ti.com 10 100 Frequency (MHz) 1000 9 TYPICAL CHARACTERISTICS: VS = ±5V (Cont.) At TA = +25°C, G = +2, and RL = 100Ω, unless otherwise specified. CLOSED-LOOP OUTPUT IMPEDANCE PSRR vs FREQUENCY 10 –PSRR +5V 60 +PSRR 55 Output Impedance (Ω) 50 45 40 35 30 OPA693 50Ω –5V 300Ω 1 300Ω 25 0.1 20 1k 10k 100k 1M 10M 10k 100M 100k 1M OUTPUT VOLTAGE AND CURRENT LIMITATIONS 150 1W Internal Power Boundary 2 50Ω Load Line 1 20Ω Load Line 0 −1 −2 −3 1W Internal Power Boundary −4 −5 −250 −200 −150 −100 −50 0 50 IO (mA) 130 120 14 Supply Current Right Scale 13 Sourcing Output Current Left Scale 12 Sinking Output Current 110 11 100 100 150 10 –50 200 250 –25 0 25 50 75 100 125 Ambient Temperature (°C) NONINVERTING OVERDRIVE RECOVERY INVERTING OVERDRIVE RECOVERY 6 4 15 140 100Ω Load Line Output Current (mA) 3 100M SUPPLY AND OUTPUT CURRENT vs TEMPERATURE 5 4 10M Frequency (Hz) Frequency (Hz) VO (V) ZO 6 G = +2 RL = 100Ω 4 G = −1 RL = 100Ω Input/Output (V) Input/Output (V) Output 2 Input 0 −2 −4 2 Output Input 0 −2 −4 See Figure 1 See Figure 3 −6 −6 Time (50ns/div) 10 Time (50ns/div) OPA693 www.ti.com SBOS285 Supply Current (mA) Power-Supply Rejection Ratio (dB) 65 TYPICAL CHARACTERISTICS: VS = ±5V (Cont.) At TA = +25°C, G = +2, and RL = 100Ω, unless otherwise specified. SETTLING TIME DISABLED FEEDTHRU vs FREQUENCY −20 20 G = +2 RL = 100Ω 2V → 0V Output Step 10 −30 −40 5 Gain (dB) Input/Output (5mV/div) 15 Input 0 −5 G = +2 RL = 100Ω VDIS = 0V Output Forward and Reverse −50 −60 −70 −80 −10 −15 −90 See Figure 1 −100 −20 0 2 4 6 8 10 12 Time (2ns/div) 14 16 18 20 See Figure 1 10 100 Frequency (MHz) COMMON-MODE INPUT AND OUTPUT SWING vs SUPPLY VOLTAGE TYPICAL DC DRIFT OVER TEMPERATURE 1.0 6 16 8 0 0 VIO −8 IB− (internal) Input/Output Range (±V) 0.5 Input Bias Currents (µA) Input Offset Voltage (mV) IB+ −0.5 −16 –25 5 4 Output 3 Input 2 1 −1.0 –50 0 25 50 75 100 0 125 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 Supply Voltages (±V) Ambient Temperature (°C) LARGE-SIGNAL DISABLE/ENABLE RESPONSE COMPOSITE VIDEO dG/dP 7 0.12 No Pull-Down With 1.0kΩ Pull-Down +5V Video In DIS 5 OPA693 75Ω 0.08 dP Optional 1.0kΩ Pull-Down −5V 0.06 6 Video Loads 4 VDIS/VOUT (V) 0.10 dG/dP (%/°) 1000 dP 0.04 2 1 VOUT 0 dG G = +2 VIN = 1VDC RL = 100Ω −1 dG 0.02 VDIS 3 −2 See Figure 1 −3 0 1 2 3 Time (500ns/div) 4 Number of 150Ω Loads OPA693 SBOS285 www.ti.com 11 TYPICAL CHARACTERISTICS: VS = +5V At TA = +25°C, G = +2, and RL = 100Ω to VS/2, unless otherwise specified. SMALL-SIGNAL FREQUENCY RESPONSE 3 G = +1 1 6 G = +2 −1 5 Gain (dB) 0 G = −1 −2 2 1 −5 0 −6 −1 10 100 1000 VO = 2VPP See Figure 4 0 200 SMALL-SIGNAL BANDWIDTH vs SINGLE-SUPPLY VOLTAGE 800 RL = 150Ω −0.1 −0.2 RL = 75Ω 700 650 600 550 500 450 RL = 100Ω See Figure 4 See Figure 4 −0.4 400 0 50 100 150 4 200 5 6 7 8 9 10 11 12 Single-Supply Voltage (V) Frequency (MHz) GAIN OF +2 PULSE RESPONSE GAIN OF +1 PULSE RESPONSE 4.5 4.5 RL = 100Ω 4.0 RL = 100Ω Large Signal Large Signal 3.5 3.5 Small Signal 3.0 Small Signal Output (V) Output (V) 1000 G = +2 VO = 0.5VPP RL = 100Ω 750 −0.3 2.5 2.0 1.5 3.0 2.5 2.0 1.5 1.0 See Figure 4 0.5 See Figure 5 0.5 Time (2ns/div) 12 800 FREQUENCY RESPONSE FLATNESS vs LOAD RL = 200Ω 1.0 600 Frequency (MHz) 0 4.0 400 Frequency (MHz) G = +2 VO = 1VPP 0.1 VO = 3VPP 3 −4 1 VO = 1VPP 4 −3 0.2 G = +2 RL = 100Ω 7 Small-Signal BW (MHz) Normalized Gain (dB) 2 Normalized Gain (dB) LARGE-SIGNAL FREQUENCY RESPONSE 8 VO = 1VPP Time (2ns/div) OPA693 www.ti.com SBOS285 TYPICAL CHARACTERISTICS: VS = +5V (Cont.) At TA = +25°C, G = +2, and RL = 100Ω to VS/2, unless otherwise specified. HARMONIC DISTORTION vs FREQUENCY G = +2 RL = 100Ω VO = 2VPP Harmonic Distortion (dBc) −60 −65 2nd Harmonic −75 −80 −85 −65 −70 2nd Harmonic −75 −80 −85 3rd Harmonic −90 −90 See Figure 4 −95 0.5 See Figure 4 −95 1 10 −55 0.1 50 1 3 Frequency (MHz) Output Voltage (VPP) HARMONIC DISTORTION vs LOAD RESISTANCE 2-TONE, 3RD-ORDER INTERMODULATION INTERCEPT 50 2nd Harmonic −65 G = +2 f = 10MHz 1kΩ PI −70 3rd Harmonic −75 +5V 45 Intercept Point (+dBm) −60 Harmonic Distortion (dBc) G = +2 RL = 100Ω f = 10MHz −60 3rd Harmonic −70 HARMONIC DISTORTION vs OUTPUT VOLTAGE −55 Harmonic Distortion (dBc) −55 −80 −85 −90 40 50Ω 35 1kΩ PO OPA693 RF 300Ω 500Ω RG 300Ω 30 +5V 1kΩ 25 PI 50Ω 20 50Ω 1kΩ PO OPA693 RF 300Ω 50Ω RG 300Ω 15 See Figure 4 −95 10 50 100 500 25 50 75 100 125 150 175 200 Frequency (MHz) Load Resistance (Ω) OPA693 SBOS285 0 www.ti.com 13 APPLICATION INFORMATION WIDEBAND BUFFER OPERATION The OPA693 gives the exceptional AC performance of a wideband current-feedback op amp with a highly linear output stage. It features internal RF and RG resistors, making it a simple matter to select a gain of +2, +1 or –1 with no external resistors. Requiring only 13mA supply current, the OPA693’s output swings to within 1V of either supply with > 700MHz small signal bandwidth and > 300MHz delivering 7VPP into a 100Ω load. This low output headroom in a very high-speed amplifier gives remarkable single +5V operation. The OPA693 delivers 2VPP swing with > 500MHz bandwidth operating on a single +5V supply. The primary advantage of a current-feedback fixed gain video buffer, as opposed to a slew-enhanced low-gain stable voltage-feedback implementation, is a higher slew rate with lower quiescent power and output noise. Figure 1 shows the DC-coupled, gain of +2V/V, dual powersupply circuit configuration used as the basis for the ±5V Electrical Characteristics table and Typical Characteristics curves. For test purposes, the input impedance is set to 50Ω with a resistor to ground and the output impedance is set to 50Ω with a series output resistor. Voltage swings reported in the specifications are taken directly at the input and output pins while load powers (dBm) are defined at a matched 50Ω load. For the circuit of Figure 1, the total effective load will be 100Ω || 600Ω = 85.7Ω. The disable control line (DIS) is typically left open to ensure normal amplifier operation. In addition to the usual power supply decoupling capacitors to ground, a 0.01µF capacitor can be included between the two power-supply pins. This optional added capacitor will typically improve the 2nd harmonic distortion performance by 3dB to 6dB. +5V + 0.1µF 6.8µF 50Ω Source DIS VI 50Ω 50Ω OPA693 VO 50Ω Load RF 300Ω RG 300Ω 0.1µF + 6.8µF −5V Figure 1. DC-Coupled, G = +2, Bipolar-Supply, Specification and Test Circuit. 14 Figure 2 shows the DC-coupled, gain of +1V/V buffer configuration used as a starting point for the gain of +1V/V Typical Characteristic curves. In this case, the inverting input resistor, RG, is left open giving a very broadband gain of +1 performance. While the test circuit shows a 50Ω input resistor, a buffer application is typically transforming from a source that cannot drive a heavy load to a 100Ω load, such as shown in Figure 2. The noninverting input impedance of the OPA693 is typically 100kΩ || 2pF. Driving directly into the noninverting input will provide this very light load to the source. However, the source must still provide the noninverting input bias current required by the input stage to operate. An alternative approach to a gain of +1 buffer is described in the Wideband Unity Gain Buffers section of this data sheet. +5V + 0.1µF 6.8µF 50Ω Source DIS VI 50Ω 50Ω OPA693 VO 50Ω Load RF 300Ω RG 300Ω 0.1µF + 6.8µF Open −5V Figure 2. DC-Coupled, G = +1V/V, Bipolar-Supply, Specification and Test Circuit. Figure 3 shows the DC-coupled, gain of –1V/V buffer configuration used as a starting point for the gain of –1V/V Typical Characteristic curves. The input impedance is set to 50Ω using the parallel combination of an external 60.4Ω resistor and the internal 300Ω RG resistor. The noninverting input is tied directly to ground. Since the internal design for the OPA693 is current-feedback, trying to get improved DC accuracy by including a resistor on the noninverting input to ground is ineffective. Using a direct short to ground on the noninverting input reduces both the contribution of the DC bias current and noise current to the output error. While the external 60.4Ω is used here to match to the 50Ω source from the test equipment, the maximum input impedance in this configuration is limited to the 300Ω RG resistor even with the RM resistor removed. Unlike the noninverting unity gain buffer application, removing RM does not strongly impact the DC operating point because the short on the noninverting input of Figure 3 provides the DC operating voltage. This application of the OPA693 provides a very broadband, highoutput, signal inverter. OPA693 www.ti.com SBOS285 +5V +VS 0.1µF + 6.8µF 50Ω Source DIS VO OPA693 +5V RG 300Ω 6.8µF 604Ω 1000pF DIS VI 50Ω 60.4Ω VO 604Ω 100Ω OPA693 50Ω Load 50Ω Source + 0.1µF VS/2 RF 300Ω RF 300Ω VI RG 300Ω RM 60.4Ω 0.1µF −5V + 6.8µF 1000pF Figure 3. DC-Coupled, G = –1V/V, Bipolar-Supply Specification and Test Circuit. Figure 4. AC-Coupled, G = +2V/V, Single-Supply Specification and Test Circuit. SINGLE-SUPPLY OPERATION While the circuit of Figure 4 shows +5V single-supply operation, this same circuit may be used for single supplies ranging as high as +12V nominal. The noninverting input bias resistors are relatively low in Figure 4 to minimize output DC offset due to noninverting input bias current. At higher signalsupply voltage, these should be increased to limit the added supply current drawn through this path. The OPA693 may be used over a single-supply range of +5V to +12V. Though not a rail-to-rail output design, the OPA693 requires minimal input and output voltage headroom compared to other very-wideband video buffer amplifiers. As shown in the single +5V Typical Characteristic curves, the OPA693 provides > 300MHz bandwidth driving a 3VPP swing into a 100Ω load. The key requirement of broadband singlesupply operation is to maintain input and output signal swings within the useable voltage ranges at both the input and the output. The circuit of Figure 4 shows the AC-coupled, gain of +2V/V, video buffer circuit used as the basis for the Electrical Characteristics table and Typical Characteristics curves. The circuit of Figure 4 establishes an input midpoint bias using a simple resistive divider from the +5V supply (two 604Ω resistors). The input signal is then AC-coupled into this midpoint voltage bias. The input voltage can swing to within 1.7V of either supply pin, giving a 1.6VPP input signal range centered between the supply pins. The input impedance matching resistor (60.4Ω) used for testing is adjusted to give a 50Ω input match when the parallel combination of the biasing divider network is included. The gain resistor (RG) is AC-coupled, giving the circuit a DC gain of +1, which puts the input DC bias voltage (2.5V) on the output as well. Again, on a single +5V supply, the output voltage can swing to within 1V of either supply pin while delivering more than 90mA output current. A demanding 100Ω load to a midpoint bias is used in this characterization circuit. The new output stage used in the OPA693 can deliver large bipolar output current into this midpoint load with minimal crossover distortion, as shown by the +5V supply, 3rd-harmonic distortion plots. Figure 5 shows the AC-coupled, G = +1V/V, single-supply specification and test circuit. In this case, the gain setting resistor, RG, is simply left open to get a gain of +1V for AC signals. Once again, the noninverting input is DC biased at mid-supply, putting that same VS/2 at the output pin. The signal is AC-coupled into this midpoint with an added termination resistor on the source side of the blocking capacitor. VS + 0.1µF 50Ω Source 1000pF 6.8µF 604Ω DIS VI 60.4Ω 604Ω OPA693 VO 100Ω VS/2 RF 300Ω RG 300Ω Open Figure 5. AC-Coupled, G = +1V/V, Single-Supply Specification and Test Circuit. OPA693 SBOS285 +5V www.ti.com 15 SINGLE-SUPPLY ADC INTERFACE Most modern, high-performance ADCs (such as the Texas Instruments ADS8xx series) operate on a single +5V (or lower) power supply. It has been a considerable challenge for single-supply op amps to deliver a low distortion input signal at the ADC input for signal frequencies exceeding 5MHz. The high slew rate, exceptional output swing, and high linearity of the OPA693 make it an ideal single-supply ADC driver. Figure 6 shows an example input interface to a very high-performance, 10-bit, 75MSPS CMOS converter. The OPA693 in the circuit of Figure 6 provides > 500MHz bandwidth at an operating gain of +2V/V delivering 1VPP at the output for a 0.5VPP input. This broad bandwidth provides adequate margin to deliver low distortion to the maximum 20Mhz analog input frequency intended for the circuit of Figure 6. A 40MHz low-pass filter is provided as part of the converter interface to both limit broadband noise and reduce harmonics as the signal frequency exceeds 15MHz. The noninverting input bias voltage is referenced to the midpoint of the ADC signal range by dividing off the top and bottom of the internal ADC reference ladder. This circuit creates an additional input offset voltage as the difference in the two input bias currents times the impedance to ground at VI. Figure 8 shows a comparison of small-signal frequency response for the unity gain buffer of Figure 2 compared to the improved approach shown in Figure 7. +5V DIS OPA693 RG 300Ω VO RO 50Ω RF 300Ω VI RM 50Ω −5V Figure 7. Improved Unity Gain Buffer. 2 G = +1, Figure 2 WIDEBAND UNITY GAIN BUFFER WITH IMPROVED FLATNESS Normalized Gain (dB) 1 As shown in the Typical Characteristic curves, the unity gain buffer configuration of Figure 2 shows a peaking in the frequency response exceeding 2dB. This gives the slight amount of overshoot and ringing apparent in the gain of +1V/V pulse response curves. A similar circuit that holds a flatter frequency response, giving improved pulse fidelity, is shown in Figure 7. This circuit removes the peaking by bootstrapping out any parasitic effects on RG. The input impedance is still set by RM as the apparent impedance looking into RG is very high. RM may be increased to show a higher input impedance, but larger values will start to impact DC output offset voltage. 0 −1 G = +1, Figure 7 −2 −3 −4 −5 −6 10 100 1000 Frequency (MHz) Figure 8. Buffer Frequency Response Comparison. +5V +5V RF 300Ω RG 300Ω 1000pF Clock 50Ω Input OPA693 1VPP 0.5VPP 100pF ADS828 10-Bit 75MSPS Input 1000pF CM DIS 2kΩ +3.5V REFT 0.1µF +2.5V DC Bias 2kΩ +1.5V REFB 0.1µF Figure 6. Wideband, AC-Coupled, Single-Supply ADC Driver. 16 OPA693 www.ti.com SBOS285 WIDEBAND, DC-COUPLED, SINGLE-TO-DIFFERENTIAL CONVERSION The frequency response shown in Figure 7 for the improved gain of +1V/V buffer closely matches the inverting gain of –1V/V frequency response. Combining two OPA693s to give a +1 and –1 response will give a very broadband, DCcoupled, single-ended input to differential output conversion. Figure 9 shows this implementation where the input match is now set by RM in parallel with the RG resistor of the inverting stage. This circuit is essentially providing a DC to 700MHz 1:1 transformer operation. A 50Ω input match is shown, but this may be increased by increasing RM. For instance, targeting a 200Ω input impedance requires an RM = 600Ω to get the parallel combination of RM and RG = 200Ω. shows an example gain of +2 line driver using the OPA693 that incorporates a 40MHz low-pass Butterworth response with just a few external components. The filter resistor values have been adjusted slightly here from an ideal filter analysis to account for parasitic effects. +5V 22pF 100Ω 226Ω VI 50Ω 22pF VO OPA693 0Ω Source RF 300Ω RG 300Ω +5V 50Ω −5V DIS OPA693 RG 300Ω +VI Figure 10. Line Driver with 40 MHz Low-Pass Active Filter. RF 300Ω This type of filter depends on a low output impedance from the amplifier through very high frequencies to continue to provide an increasing attenuation with frequency. As the amplifier output impedance rises with frequency, any input signal or noise starts to feed directly through to the output via the feedback capacitor. Since the OPA693 used in Figure 10 has a 700MHz bandwidth, the active filter will continue to roll off through frequencies exceeding 200MHz. Figure 11 shows the frequency response for the filter of Figure 10, where the desired 40MHz cutoff is achieved and a 40dB/dec rolloff is held through very high frequencies. VI RM 60.4Ω −5V RG 300Ω +5V 2VI RF 300Ω −VI OPA693 DIS −5V 3 0 −3 Figure 9. DC → 700MHz, Single-to-Differential Conversion. The extremely wide bandwidth of the OPA693 allows a wide range of active filter topologies to be implemented with minimal amplifier bandwidth interaction in the filter shape. Sallen-Key filters, using either a gain of 1 or gain of 2 amplifier, may be easily implemented with no external gain setting elements. In general, given a desired filter WO, the amplifier should have at least 20X that WO to minimize filter interaction with the amplifier frequency response. Figure 10 Gain (dB) HIGH-FREQUENCY ACTIVE FILTERS −6 −15 −18 −21 −24 −27 −30 1 10 100 1000 Frequency (MHz) Figure 11. 40MHz Low-Pass Active Filter Response. OPA693 SBOS285 −9 −12 www.ti.com 17 DESIGN-IN TOOLS DEMONSTRATION BOARDS Two printed circuit (PC) boards are available to assist in the initial evaluation of the circuit performance using the OPA693 in its two package styles. Both are available free as unpopulated PC boards delivered with descriptive documentation. The summary information for these boards is shown in Table I. PRODUCT PACKAGE DEMO BOARD PART NUMBER LITERATURE REQUEST NUMBER SO-8 DEM-OPA68xU SBOU009 SOT23-6 DEM-OPA6xxN SBOU010 OPA693ID OPA693IDBV TABLE I. Demo Board Ordering Information. To request either of these boards, check the Texas Instruments web site at www.ti.com. OPERATING SUGGESTIONS GAIN SETTING Setting the gain for the OPA693 is very easy. For a gain of +2, ground the –IN pin and drive the +IN pin with the signal. For a gain of +1, either leave the –IN pin open and drive the +IN pin or drive both the +IN and –IN pins as shown in Figure 7. For a gain of –1, ground the +IN pin and drive the –IN pin with the input signal. An external resistor may be used in series with the –IN pin to reduce the gain. However, since the internal resistors (RF and RG) have a tolerance and temperature drift different than the external resistor, the absolute gain accuracy and gain drift over temperature will be relatively poor compared to the previously described standard gain connections using no external resistor. The minimum specified output voltage and current specifications over temperature are set by worst-case simulations at the cold temperature extreme. Only at cold startup will the output current and voltage decrease to the numbers shown in the over-temperature min/max specifications. As the output transistors deliver power, their junction temperatures increase, which decreases their VBE’s (increasing the available output voltage swing) and increases their current gains (increasing the available output current). In steady state operation, the available output voltage and current will always be greater than that shown in the over-temperature characteristics since the output stage junction temperatures will be higher than the minimum specified operating ambient. To maintain maximum output stage linearity, no output shortcircuit protection is provided. This will not normally be a problem, since most applications include a series matching resistor at the output that limits the internal power dissipation if the output side of this resistor is shorted to ground. However, shorting the output pin directly to an adjacent positive power supply pin will, in most cases, destroy the amplifier. If additional protection to a power-supply short is required, consider a small series resistor in the power supply leads. Under heavy output loads, this will reduce the available output voltage swing. A 5Ω series resistor in each supply lead will limit the internal power dissipation to < 1W for an output short while decreasing the available output voltage swing only 0.5V, for up to 100mA desired load currents. Always place the 0.1µF power supply decoupling capacitors after these supply current limiting resistors directly on the device supply pins. DRIVING CAPACITIVE LOADS OUTPUT CURRENT AND VOLTAGE The OPA693 provides output voltage and current capabilities that can easily support multiple video loads and/or 100Ω loads with very low distortion. Under no-load conditions at 25°C, the output voltage typically swings to 1V of either supply rail; the tested swing limit is within 1.2V of either rail. Into a 15Ω load (the minimum tested load), it is tested to deliver more than ±90mA. The specifications described above, though familiar in the industry, consider voltage and current limits separately. In many applications, it is the voltage × current, or V-I product, which is more relevant to circuit operation. Refer to the Output Voltage and Current Limitations plot in the Typical Characteristics. The X and Y axes of this graph show the zero-voltage output current limit and the zero-current output voltage limit, respectively. The four quadrants give a more detailed view of the OPA693’s output drive capabilities, noting that the graph is bounded by a “Safe Operating Area” of 1W maximum internal power dissipation. Superimposing resistor load lines onto the plot shows that the OPA693 can drive ±3.4V into 20Ω or ±3.7V into 50Ω without exceeding 18 either the output capabilities or the 1W dissipation limit. A 100Ω load line (the standard test-circuit load) shows full ±3.8V output swing capability, as shown in the Typical Characteristics. One of the most demanding, and yet very common, load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an ADC, including additional external capacitance, which may be recommended to improve ADC linearity. A high-speed, high open-loop gain, amplifier like the OPA693 can be very susceptible to decreased stability and may give closed-loop response peaking when a capacitive load is placed directly on the output pin. When the amplifier’s open loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. OPA693 www.ti.com SBOS285 DISTORTION PERFORMANCE The OPA693 provides good distortion performance into a 100Ω load on ±5V supplies. Relative to alternative solutions, the OPA693 holds much lower distortion at higher frequencies (> 20Mhz) than alternative solutions. Generally, until the fundamental signal reaches very high frequency or power levels, the 2nd harmonic will dominate the distortion with a negligible 3rd harmonic component. Focusing then on the 2nd harmonic, increasing the load impedance improves distortion directly. Remember that the total load includes the feedback network—in the noninverting configuration (see Figure 1) this is the sum of RF + RG, while in the inverting configuration it is just RF (see Figure 3). Also, providing an additional supply decoupling capacitor (0.01µF) between the supply pins (for bipolar operation) improves the 2nd-order distortion slightly (3dB to 6dB). The OPA693 has an extremely low 3rd-order harmonic distortion. This also produces a high 2-tone, 3rd-order intermodulation intercept. Two graphs for this intercept are given in the in the Typical Characteristics; one for ±5V and one for +5V. The lower curve shown in each graph is defined at the 50Ω load when driven through a 50Ω matching resistor, to allow direct comparisons to RF MMIC devices. The higher curve in each graph shows the intercept if the output is taken directly at the output pin with a 500Ω load, to allow prediction of the 3rd-order spurious level when driving a lighter load, such as an ADC input. The output matching resistor attenuates the voltage swing from the output pin to the load by 6dB. If the OPA693 drives directly into the input of a highimpedance device, such as an ADC, this 6dB attenuation is not taken and the intercept will increase a minimum of 6dB, as shown in the 500Ω load typical characteristic. The intercept is used to predict the intermodulation spurious levels for two closely-spaced frequencies. If the two test frequencies (f1 and f2) are specified in terms of average and delta frequency, fO = (f1 + f2)/2 and ∆f = |f2 – f1|/2, then the two, 3rdorder, close-in spurious tones will appear at fO ±3 × ∆f. The difference between two equal test tone power levels and these GAIN ACCURACY AND LINEARITY The OPA693 provides improved absolute gain accuracy and DC linearity over earlier fixed gain of two line drivers. Operating at a gain of +2V/V by tying the –IN pin to ground, the OPA693 shows a maximum gain error of ±0.9% at 25°C. The DC gain will therefore lie between 1.982V/V and 2.018V/V at room temperature. Over the specified temperature ranges, this gain tolerance expands only slightly due to the matched temperature drift for RF and RG. Achieving this gain accuracy requires a very low impedance ground at –IN. Typical production lots show a much tighter distribution in gain than this ±0.9% specification. Figure 12 shows a typical distribution in measured gain at the gain of +2V/V configuration, in this case showing a slight drop in the mean (0.25%) from the nominal but with a very tight distribution. 600 400 300 200 100 0 Gain(V/V) Figure 12. Typical +2V/V Gain Distribution. OPA693 SBOS285 Mean = 1.995 σ = 0.005 500 1.980 1.982 1.984 1.986 1.988 1.990 1.992 1.994 1.996 1.998 2.000 2.002 2.004 2.006 2.008 2.010 2.012 2.014 2.016 2.018 2.020 The criterion for setting this RS resistor is a maximum bandwidth, flat frequency response at the load (< 0.1dB peaking). For the OPA693 operating in a gain of +2, the frequency response at the output pin is very flat to begin with, allowing relatively small values of RS to be used for low capacitive loads. intermodulation spurious power levels is given by ∆dBc = 2 × (IM3 – PO), where IM3 is the intercept taken from the Typical Characteristics and PO is the power level in dBm at the 50Ω load for one of the two closely-spaced test frequencies. For instance, at 50MHz, the OPA693 at a gain of +2 has an intercept of 44dBm at a matched 50Ω load. If the full envelope of the two frequencies needs to be 2VPP at this load, this requires each tone to be 4dBm (1VPP). The 3rd-order intermodulation spurious tones will then be 2 × (44 – 4) = 80dBc below the test tone power level (–76dBm). If this same 2VPP 2-tone envelope were delivered directly into a lighter 500Ω load, the intercept would increase to the 52dBm shown in the Typical Characteristics. With the same output signal and gain conditions, but now driving directly into a light load with no matching loss, the 3rd-order spurious tones will then be at least 2 × (52 – 4) = 96dBc below the 4dBm test tone power levels centered on 50MHz (–92dBm). We are still using a 4dBm for the 1VPP output swing into this 500Ω load. While not strictly correct from a power standpoint, this does give the correct prediction for spurious level. The class AB output stage for the OPA693 is much more voltage swing dependent on output distortion than strictly power dependent. To use the 500Ω intercept curve, use the single-tone voltage swing as if it were driving a 50Ω load to compute the PO used in the intercept equation. Number of Units The Typical Characteristics show a Recommended RS vs Capacitive Load curve to help the designer pick a value to give < 0.1dB peaking to the load. The resulting frequency response curves show a 0.1dB peaked response for several selected capacitive loads and recommended RS combinations. Parasitic capacitive loads greater than 2pF can begin to degrade the performance of the OPA693. Long PC board traces, unmatched cables, and connections to other amplifier inputs can easily exceed this value. Always consider this effect carefully, and add the recommended series resistor as close as possible to the OPA693 output pin (see the Board Layout Guidelines section). www.ti.com 19 The exceptionally linear output stage (as illustrated by the high 3rd-order intermodulation intercept) and low thermal gradient induced errors for the OPA693 give an extremely linear output over large voltage swings and heavy loads. Figure 13 shows the tested deviation (in % of peak to peak) from linearity for a range of symmetrical output swings and loads. Below 4VPP, for either a 100Ω or a 500Ω load, the OPA693 delivers > 14-bit linear output response. The total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage contributors. Equation 1 shows the general form for the output noise voltage using the terms shown in Figure 14. (1) 2 2 EO = ENI2 + (IBNR S ) + 4kTRS NG2 + (IBIRF ) + 4kTRFNG Dividing this expression through by noise gain (NG = 1 + RF/RG) will give the equivalent input-referred spot noise voltage at the non-inverting input, as shown in Equation 2. 0.0200 Figure 1 Test Circuit 0.0175 (2) % Deviation 0.0150 2 4kTRF 2 I R EN = ENI2 + (IBNR S ) + 4kTRS + BI F + NG NG 0.0125 RL = 100Ω 0.0100 0.0075 Evaluating the output noise and input noise expressions for the two noninverting gain configurations, and with two different values for the noninverting source impedance, gives output and input referred spot noise voltages of Table II. 0.0050 RL = 500Ω 0.0025 0 2 3 4 5 6 7 8 RS (Ω) OUTPUT SPOT NOISE EO (nV/ √Hz ) TOTAL INPUT SPOT NOISE EN (nV/ √Hz ) 4.15 VO (peak to peak) Figure 13. DC Linearity vs Output Swing and Loads. CONFIGURATION NOISE PERFORMANCE G = +2 (Figure 1) 25 8.3 G = +2 (Figure 1) 300 14 7 The OPA693 offers an excellent balance between voltage and current noise terms to achieve a low output noise under a variety of operating conditions. The inverting node noise current (internal) will appear at the output multiplied by the relatively low 300Ω feedback resistor. The input noise voltage (1.8nV/√Hz) is extremely low for a unity gain stable amplifier. This low input voltage noise was achieved at the price of higher noninverting input current noise (17.8pA/√Hz). As long as the AC source impedance looking out of the noninverting input is less than 100Ω, this current noise will not contribute significantly to the total output noise. The op amp input voltage noise and the two input current noise terms combine to give low output noise for the each of the three gain settings available using the OPA693. Figure 14 shows the op amp noise analysis model with all of the noise terms included. In this model, all noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz. G = +1 (Figure 2) 25 7.3 7.3 G = +1 (Figure 2) 300 9.2 9.2 ENI EO OPA693 RS IBN ERS RF √4kTRS 4kT RG RG Figure 14. Op Amp Noise Model. 20 IBI √4kTRF 4kT = 1.6E –20J at 290°K TABLE II. Total Output and Input Referred Noise. The output noise is being dominated by the inverting current noise times the internal feedback resistor. This gives a total input referred noise voltage that exceeds the 1.8nV voltage term for the amplifier itself. DC ACCURACY AND OFFSET CONTROL A current-feedback op amp like the OPA693 provides exceptional bandwidth and slew rate giving fast pulse settling but only moderate DC accuracy. The Electrical Characteristics show an input offset voltage comparable to high-speed voltage-feedback amplifiers. However, the two input bias currents are somewhat higher and are unmatched. Whereas bias current cancellation techniques are very effective with most voltage-feedback op amps, they do not generally reduce the output DC offset for wideband current-feedback op amps. Since the two input bias currents are unrelated in both magnitude and polarity, matching the source impedance looking out of each input to reduce their error contribution to the output is ineffective. Evaluating the configuration of Figure 1, using worst case +25°C input offset voltage and the two input bias currents, gives a worst-case output offset range equal to: ±(NG × VOS) + (IBN × RS/2 × NG) ± (IBI × RF) = ±(2 × 2.0mV) ± (35µA × 25Ω × 2) ± (50µA × 300Ω) = ±4mV ± 1.75mV ± 15mV = ±30.75mV where NG = noninverting signal gain. OPA693 www.ti.com SBOS285 Minimizing the resistance seen by the noninverting input will minimize the output DC error. For improved DC precision in a wideband low-gain amplifier, consider the OPA842 where a bipolar input is acceptable (low source resistance) or the OPA656 where a JFET input is required. DISABLE OPERATION The OPA693 provides an optional disable feature that can be used to reduce system power. If the V DIS control pin is left unconnected, the OPA693 will operate normally. This shutdown is intended only as a power-savings feature. Forward path isolation when disabled is very good for small signals for gains of +1 or +2. Large-signal isolation is not ensured. Using this feature to multiplex two or more outputs together is not recommended. Large signals applied to the disabled output stages can turn on parasitic devices degrading signal linearity for the desired channel. Turn-on time is very quick from the shutdown condition, typically < 60ns. Turn-off time is strongly dependent on the selected gain configuration and load, but is typically 3µs for the circuit of Figure 1. To shutdown, the control pin must be asserted low. This logic control is referenced to the positive supply, as shown in the simplified circuit of Figure 15. +VS 15kΩ Q1 The OPA693 does not require heatsinking or airflow in most applications. Maximum desired junction temperature sets the maximum allowed internal power dissipation as described here. In no case should the maximum junction temperature be allowed to exceed 150°C. Operating junction temperature (TJ) is given by TA + PD × θJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL will depend on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 either supply voltage (for equal bipolar supplies). Under this worst-case condition, PDL = VS2/(4 × RL) where RL includes feedback network loading. This is the absolute highest power that can be dissipated for a given RL. All actual applications will dissipate less power in the output stage. As a worst-case example, compute the maximum TJ using an OPA693IDBV (SOT23-6 package) in the circuit of Figure 1 operating at the maximum specified ambient temperature of +85°C and driving a grounded 100Ω load. Maximum internal power is: 25kΩ IS Control THERMAL ANALYSIS Note that it is the power in the output stage and not into the load that determines internal power dissipation. 110kΩ VDIS The shutdown feature for the OPA693 is a positive supply referenced, current-controlled, interface. Open collector (or drain) interfaces are most effective, as long as the controlling logic can sustain the resulting voltage (in the open mode) that will appear at the V DIS pin. That voltage will be one diode below the positive supply voltage applied to the OPA693. For voltage output logic interfaces, the on/off voltage levels described in the Electrical Characteristics apply only for a +5V positive supply on the OPA693. An open-drain interface is recommended for shutdown operation using a higher positive supply for the OPA693 and/or logic families with inadequate high-level voltage swings. –VS PD = 10V × 14.1mA + 52 /(4 × (100Ω+|| 600Ω)) = 214mW Figure 15. Simplified Disable Control Circuit. Maximum TJ = +85°C + (0.21W × 150°C/W) = 117°C. In normal operation, base current to Q1 is provided through the 110kΩ resistor while the emitter current through the 15kΩ resistor sets up a voltage drop that is inadequate to turn on the two diodes in Q1’s emitter. As V DIS is pulled LOW, additional current is pulled through the 15kΩ, eventually turning on these two diodes (≈80µA). At this point, any further current pulled out of VDIS goes through those diodes holding the emitter-base voltage of Q1 at approximately 0V. This shuts off the collector current out of Q1, turning the amplifier off. The supply current in the shutdown mode is only that required to operate the circuit of Figure 15. All actual applications will operate at a lower junction temperature than the 117°C computed above. Compute your actual output stage power to get an accurate estimate of maximum junction temperature, or use the results shown here as an absolute maximum. OPA693 SBOS285 www.ti.com 21 BOARD LAYOUT GUIDELINES Achieving optimum performance with a high-frequency amplifier like the OPA693 requires careful attention to PC board layout parasitics and external component types. Recommendations that will optimize performance include: a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output can cause instability; on the noninverting input, it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, create a window around the signal I/O pins in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. b) Minimize the distance (< 0.25”) from the power supply pins to high frequency 0.1µF decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power supply connections should always be decoupled with these capacitors. Larger (2.2µF to 6.8µF) decoupling capacitors, effective at lower frequency, should also be used on the supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. c) Careful selection and placement of external components will preserve the high frequency performance of the OPA693. Use resistors that have low reactance at high frequencies. Surface-mount resistors work best and allow a tighter overall layout. Metal film and carbon composition axially-leaded resistors can also provide good high-frequency performance. Again, keep their leads and PC board trace length as short as possible. Never use wirewound type resistors in a high-frequency application. Since the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the series output resistor, if any, as close as possible to the output pin. Since the inverting input node is internal for the OPA693, it is more robust to layout issues than amplifiers with similar speed but external feedback and gain resistors. Other network components, such as noninverting input termination resistors, should also be placed close to the package. Good axial metal film or surface mount resistors have approximately 0.2pF in shunt with the resistor. For resistor values > 2.0kΩ, this parasitic capacitance can add a pole and/or zero below 400MHz that can effect circuit operation. Keep resistor values as low as possible consistent with load driving considerations. d) Connections to other wideband devices on the PC board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50 to 100mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the plot of Recommended RS vs Capacitive Load. Low parasitic capacitive loads (< 4pF) may not need an RS since the OPA693 is nominally compensated to operate with a 2pF parasitic load. If a long trace is required, and the 6dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a 22 matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is normally not necessary on board, and in fact, a higher impedance environment will improve distortion, as shown in the distortion versus load plots. With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the OPA693 is used, as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device; this total effective impedance should be set to match the trace impedance. If the 6dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of Recommended RS vs Capacitive Load. This will not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. e) Socketing a high-speed part like the OPA693 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network, which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA693 directly onto the board. INPUT AND ESD PROTECTION The OPA693 is built using a very high-speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins are protected with internal ESD protection diodes to the power supplies, as shown in Figure 16. +V CC External Pin Internal Circuitry –V CC Figure 16. Internal ESD Protection. These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher currents are possible (for example, in systems with ±15V supply parts driving into the OPA693), current limiting series resistors may be added on the noninverting input. Keep this resistor value as low as possible since high values degrade both noise performance and frequency response. The inverting input already has a 300Ω resistor from the external pin to the internal summing junction for the op amp. This provides considerable protection for that node. OPA693 www.ti.com SBOS285 MECHANICAL DATA MSOI002B – JANUARY 1995 – REVISED SEPTEMBER 2001 D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 8 PINS SHOWN 0.020 (0,51) 0.014 (0,35) 0.050 (1,27) 8 0.010 (0,25) 5 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 1 4 0.010 (0,25) 0°– 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.010 (0,25) 0.004 (0,10) 0.069 (1,75) MAX PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047/E 09/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). 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