OPA683 OPA 683 OPA68 3 SBOS221B – NOVEMBER 2001 — REVISED – JUNE 2002 Very Low-Power, Current Feedback OPERATIONAL AMPLIFIER With Disable FEATURES APPLICATIONS ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● REDUCED BANDWIDTH CHANGE VERSUS GAIN 150MHz BANDWIDTH G = +2 > 90MHz BANDWIDTH TO GAIN > +10 LOW DISTORTION: < –69dBc at 5MHz HIGH OUTPUT CURRENT: 110mA SINGLE +5V TO +12V SUPPLY OPERATION DUAL ±2.5V TO ±6V SUPPLY OPERATION LOW SUPPLY CURRENT: 0.94mA LOW SHUTDOWN CURRENT: 100µA DESCRIPTION The OPA683 provides a new level of performance in very lowpower, wideband, current feedback amplifiers. This CFBplus amplifier is among the first to use an internally closed-loop input buffer stage that enhances performance significantly over earlier lowpower CFB amplifiers. While retaining the benefits of very low power operation, this new architecture provides many of the advantages of a more ideal CFB amplifier. The closed-loop input stage buffer gives a very low and linearized impedance path at the inverting input to sense the feedback error current. This improved inverting input impedance gives exceptional bandwidth retention to much higher gains and improved harmonic distortion over earlier solutions limited by inverting input linearity. Beyond simple high gain applications, the OPA683 CFBplus amplifier can allow the gain setting element to be set with considerable freedom from amplifier bandwidth interaction. This allows frequency response peaking elements to be added, multiple input inverting summing circuits to LOW POWER BROADCAST VIDEO DRIVERS EQUALIZING FILTERS SAW FILTER HIGH GAIN POST AMPLIFIERS SHORT LOOP ADSL CO DRIVERS MULTICHANNEL SUMMING AMPLIFIERS PROFESSIONAL CAMERAS ADC INPUT DRIVERS have greater bandwidth, and low-power line drivers to meet the demanding requirements of studio cameras and broadcast video. The output capability for the OPA683 also sets a new mark in performance for very low-power current feedback amplifiers. Delivering a full ±4Vp-p swing on ±5V supplies, the OPA683 also has the output current to support this swing into a 100Ω load. This minimal output headroom requirement is complemented by a similar 1.2V input stage headroom giving exceptional capability for single +5V operation. The OPA683’s low 0.94mA supply current is precisely trimmed at 25°C. This trim, along with low shift over temperature and supply voltage, gives a very robust design over a wide range of operating conditions. System power may be further reduced by using the optional disable control pin. Leaving this disable pin open, or holding it HIGH, gives normal operation. If pulled LOW, the OPA683 supply current drops to less than 100µA while the I/O pins go to a high impedance state. V+ OPA683 BANDWIDTH vs GAIN 9 G=2 G=5 + Normalized Gain (dB) 6 VO Z(S) IERR V– IERR RF 3 0 –3 –6 –9 G = 10 –12 G = 20 G = 50 –15 –18 RF = 1.2kΩ –21 RG 1 Low-Power Amplifier G = 100 10 Frequency (MHz) 100 200 Patent Pending Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) Power Supply ............................................................................... ±6.5VDC Internal Power Dissipation ................................. See Thermal Information Differential Input Voltage .................................................................. ±1.2V Input Voltage Range ............................................................................ ±VS Storage Temperature Range: ID, IDBV ......................... –40°C to +125°C Lead Temperature (soldering, 10s) .............................................. +300°C Junction Temperature (TJ ) ........................................................... +175°C This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. OPA683 RELATED PRODUCTS SINGLES DUALS TRIPLES QUADS OPA684 OPA691 OPA685 OPA2683 OPA2691 — OPA3684 OPA3691 — OPA4684 — — FEATURES Low-Power CFBplus High Slew Rate CFB > 500MHz CFB PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR(1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY SO-8 D –40°C to +85°C OPA683D " " " " OPA683ID OPA683IDR Rails,100 Tape and Reel, 2500 SOT23-6 DBV –40°C to +85°C A83 OPA683IDBVT Tape and Reel, 250 " " " " OPA683IDBVR Tape and Reel, 3000 OPA683 " OPA683 " NOTES: (1) For the most current specifications, and package information, refer to our web site at www.ti.com. PIN CONFIGURATION Top View SO-8 NC 1 8 DIS Inverting Input 2 7 +VS Noninverting Input 3 6 Output –VS 4 5 NC Top View SOT23-6 Output 1 6 +VS –VS 2 5 DIS Noninverting Input 3 4 Inverting Input 6 5 4 A83 NC = No Connection 1 2 3 Pin Orientation/Package Marking OPA683 2 www.ti.com SBOS221B ELECTRICAL CHARACTERISTICS: VS = ±5V RF = 1.2kΩ, RL = 1kΩ, and G = +2, (see Figure 1 for AC performance only), unless otherwise noted. OPA683ID, IDBV TYP PARAMETER AC PERFORMANCE (See Figure 1) Small-Signal Bandwidth (VO = 0.5Vp-p) Bandwidth for 0.1dB Gain Flatness Peaking at a Gain of +1 Large-Signal Bandwidth Slew Rate Rise-and-Fall Time Harmonic Distortion 2nd-Harmonic 3rd-Harmonic Input Voltage Noise Noninverting Input Current Noise Inverting Input Current Noise Differential Gain Differential Phase DC PERFORMANCE(4) Open-Loop Transimpedance Gain (ZOL) Input Offset Voltage Average Offset Voltage Drift Noninverting Input Bias Current Average Noninverting Input Bias Current Drift Inverting Input Bias Current Average Inverting Input Bias Current Drift INPUT Common-Mode Input Range(5) (CMIR) Common-Mode Rejection Ratio (CMRR) Noninverting Input Impedance Inverting Input Resistance (RI) OUTPUT Voltage Output Swing Current Output, Sourcing Current Output, Sinking Closed-Loop Output Impedance DISABLE (Disabled LOW) Power-Down Supply Current (+VS) Disable Time Enable Time Off Isolation Output Capacitance in Disable Turn On Glitch Turn Off Glitch Enable Voltage Disable Voltage Control Pin Input Bias Current (DIS) POWER SUPPLY Specified Operating Voltage Maximum Operating Voltage Range Max Quiescent Current Min Quiescent Current Power-Supply Rejection Ratio (–PSRR) TEMPERATURE RANGE Specification: D, DBV Thermal Resistance, θJA D SO-8 DBV SOT-23-6 MIN/MAX OVER TEMPERATURE +25°C(1) 0°C to 70°C(2) –40°C to +85°C(2) 124 121 117 15 6.5 14 7.7 14 8.0 450 345 450 338 430 336 –63 –65 –67 –74 4.4 5.1 11.6 0.06 0.03 –54 –55 –62 –67 5.0 5.8 11.9 –54 –55 –62 –66 5.5 6.4 12.3 700 ±1.5 360 ±3.5 ±2.0 ±4.0 ±3.0 ±10 Open-Loop, DC ±3.75 60 50 2 4.5 1kΩ Load VO = 0 VO = 0 G = +2, f = 100kHz VDIS = 0 VIN = +1, See Figure 1 VIN = +1, See Figure 1 G = +2, 5MHz CONDITIONS +25°C G = +1, RF = 1.2kΩ G = +2, RF = 1.2kΩ G = +5, RF = 1.2kΩ G = +10, RF = 1.2kΩ G = +20, RF = 1.2kΩ G = +2, VO = 0.5Vp-p, RF = 1.2kΩ RF = 1.2kΩ, VO = 0.5Vp-p G = +2, VO = 4Vp-p G = –1, VO = 4V Step (see Figure 2) G = +2,VO = 4V Step G = +2, VO = 0.5V Step G = +2, VO = 4VStep G = +2, f = 5MHz, VO = 2Vp-p RL = 100Ω RL ≥ 1kΩ RL = 100Ω RL ≥ 1kΩ f > 1MHz f > 1MHz f > 1MHz G = +2, NTSC, VO = 1.4Vp, RL = 150Ω G = +2, NTSC, VO = 1.4Vp, RL = 150Ω 200 150 121 94 72 37 1.8 63 540 400 4.6 7.8 VO = 0V, RL = 1kΩ VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V G = +2, RL = 150Ω, VIN = 0 G = +2, RL = 150Ω, VIN = 0 VDIS = 0V MIN/ TEST MAX LEVEL(3) MHz MHz MHz MHz MHz MHz dB MHz V/µs V/µs ns ns typ min typ typ typ min max typ min min typ typ C B C B C B B C B B C C –54 –55 –62 –66 5.8 6.7 12.4 dBc dBc dBc dBc nV/√Hz pA/√Hz pA/√Hz % deg max max max max max max max typ typ B B B B B B B C C 270 ±4.1 ±12 ±4.6 ±15 ±11 ±20 250 ±4.3 ±12 ±4.8 ±15 ±11.5 ±20 kΩ mV µV/°C µA nA/°C µA nA°/C min max max max max max max A A B A B A B ±3.65 53 ±3.65 52 ±3.60 52 V dB kΩ || pF Ω min min typ typ A A C C ±4.1 150 –110 0.007 ±4.0 130 –100 ±4.0 125 –95 ±3.9 120 –90 V mA mA Ω min min min typ A A A C –100 60 40 70 1.7 ±70 ±20 3.4 1.8 80 –150 –170 –180 3.5 1.7 120 3.6 1.6 130 3.7 1.5 135 µA ms ns dB pF mV mV V V µA typ typ typ typ typ typ typ min max max C C C C C C C A A A ±6 1.03 0.85 55 ±6 1.04 0.80 54 ±6 1.05 0.77 54 V V mA mA dB typ max max min typ C A A A A –40 to +85 °C typ C 125 150 °C/W °C/W typ typ C C ±5 VS = ±5V VS = ±5V Input Referred UNITS 0.94 0.94 62 Junction-to-Ambient NOTES: (1) Junction temperature = ambient for 25°C tested specifications. (2) Junction temperature = ambient at low temperature limit: junction temperature = ambient +2°C at high temperature limit for over temperature tested specifications. (3) Test levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. VCM is the input common-mode voltage. (5) Tested < 3dB below minimum specified CMR at ± CMIR limits. OPA683 SBOS221B 3 www.ti.com ELECTRICAL CHARACTERISTICS: VS = +5V RF = 1.4kΩ, RL = 1kΩ, and G = +2, (see Figure 3 for AC performance only), unless otherwise noted. OPA683ID, IDBV TYP PARAMETER AC PERFORMANCE (See Figure 3) Small-Signal Bandwidth (VO = 0.2Vp-p) Bandwidth for 0.1dB Gain Flatness Peaking at a Gain of +1 Large-Signal Bandwidth Slew Rate Rise-and-Fall Time Harmonic Distortion 2nd-Harmonic 3rd-Harmonic Input Voltage Noise Noninverting Input Current Noise Inverting Input Current Noise Differential Gain Differential Phase DC PERFORMANCE(4) Open-Loop Transimpedance Gain (ZOL) Input Offset Voltage Average Offset Voltage Drift Noninverting Input Bias Current Average Noninverting Input Bias Current Drift Inverting Input Bias Current Average Inverting Input Bias Current Drift INPUT Least Positive Input Voltage(5) Most Positive Input Voltage(5) Common-Mode Refection Ratio (CMRR) Noninverting Input Impedance Inverting Input Resistance (RI ) OUTPUT Most Positive Output Voltage Least Positive Output Voltage Current Output, Sourcing Current Output, Sinking Closed-Loop Output Impedance DISABLE (Disabled LOW) Power-Down Supply Current (+VS) Off Isolation Output Capacitance in Disable Turn On Glitch Turn Off Glitch Enable Voltage Disable Voltage Control Pin Input Bias Current (DIS) POWER SUPPLY Specified Single-Supply Operating Voltage Max Single-Supply Operating Voltage Max Quiescent Current Min Quiescent Current Power-Supply Rejection Ratio (+PSRR) TEMPERATURE RANGE Specification: D, DBV Thermal Resistance, θJA D SO-8 DBV SOT-23-6 MIN/MAX OVER TEMPERATURE +25°C(1) 0°C to 70°C(2) –40°C to +85°C(2) 96 92 90 9 6 8 8 8 8 180 175 170 –60 –66 –59 –63 4.4 5.1 11.6 0.24 0.19 –54 –55 –58 –57 5.0 5.8 11.9 –53 –55 –58 –56 5.5 6.4 12.3 700 ±1.0 300 ±3.0 ±2 ±4 ±3 ±8 Open-Loop 1.1 3.9 58 50 2 4.8 RL = 1kΩ to VS/2 RL = 1kΩ to VS/2 VO = VS/2 VO = VS/2 G = +2, f = 100kHz 4.2 0.8 80 70 0.009 VDIS = 0 G = +2, 5MHz 100 70 1.7 ±70 ±20 3.4 1.8 80 CONDITIONS +25°C G = +1, RF = 1.4kΩ G = +2, RF = 1.4kΩ G = +5, RF = 1.4kΩ G = +10, RF = 1.4kΩ G = +20, RF = 1.4kΩ G = +2, VO < 0.5Vp-p, RF = 1.2kΩ RF = 1.4kΩ, VO < 0.5Vp-p G = +2, VO = 2Vp-p G = +2, VO = 2V Step G = +2, VO = 0.5V Step G = +2, VO = 2VStep G = 2, f = 5MHz, VO = 2Vp-p RL = 100Ω to VS/2 RL ≥ 1kΩ to VS/2 RL = 100Ω to VS/2 RL ≥ 1kΩ to VS/2 f > 1MHz f > 1MHz f > 1MHz G = +2, NTSC, VO = 1.4Vp, RL = 150Ω G = +2, NTSC, VO = 1.4Vp, RL = 150Ω 145 119 95 87 60 14 1 70 210 5.9 7.8 VO = VS/2, RL = 1kΩ to VS/2 VCM = VS/2 VCM = VS/2 VCM = VS/2 VCM = VS/2 VCM = VS/2 VCM = VS/2 VCM = VS/2 G = +2, RL = 150Ω, VIN = VS/2 G = +2, RL = 150Ω, VIN = VS/2 VDIS = 0V MIN/ TEST MAX LEVEL(3) MHz MHz MHz MHz MHz MHz dB MHz V/µs ns ns typ min typ typ typ min max typ min typ typ B C C C B B C B C C –53 –55 –58 –56 5.8 6.7 12.4 dBc dBc dBc dBc nV/√Hz pA/√Hz pA/√Hz % deg max max max max max max max typ typ B B B B B B B C C 270 ±3.6 ±12 ±4.6 ±12 ±8.7 ±15 250 ±3.8 ±12 ±4.8 ±12 ±8.9 ±15 kΩ mV µV/°C µA nA/°C µA nA°/C min max max max max max max A A B A B A B 1.25 3.75 51 1.29 3.73 50 1.34 3.67 50 V V dB kΩ || pF Ω max min min typ typ A A A C C 4.1 0.9 65 52 4.1 0.9 63 50 4.0 1.00 58 45 V mA mA Ω min min min min typ A A A A C µA dB pF mV mV V V µA typ typ typ typ typ min max max C C C C C A A A V V mA mA dB typ max max min typ C A A A C –40 to +85 °C typ C 125 150 °C/W °C/W typ typ C C 3.5 1.7 120 3.6 1.6 130 3.7 1.5 135 12 0.91 0.71 12 0.91 0.69 12 0.91 0.67 5 VS = +5V VS = +5V Input Referred UNITS 0.82 0.82 65 Junction-to-Ambient NOTES: (1) Junction temperature = ambient for 25°C tested specifications. (2) Junction temperature = ambient at low temperature limit: junction temperature = ambient +2°C at high temperature limit for over temperature tested specifications. (3) Test levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (4) Current is considered positive out-of-node. VCM is the input common-mode voltage. (5) Tested < 3dB below minimum specified CMR at ± CMIR limits. OPA683 4 www.ti.com SBOS221B TYPICAL CHARACTERISTICS: VS = ±5V TA = 25°C, RF = 1.2kΩ, RL = 1kΩ, and G = +2, (see Figure 1 for AC performance only), unless otherwise noted. NONINVERTING SMALL-SIGNAL FREQUENCY RESPONSE VO = 0.5Vp-p RF = 1.2kΩ Normalized Gain (3dB/div) 3 INVERTING SMALL-SIGNAL FREQUENCY RESPONSE 3 G = 100 G=1 0 G=2 –3 –6 G = 10 –9 G=5 0 –6 G = –2 –9 See Figure 2 –12 1 10 100 200 1 10 NONINVERTING LARGE-SIGNAL FREQUENCY RESPONSE VO = 0.5Vp-p 0 VO = 1Vp-p VO = 1Vp-p Gain (dB) Gain (dB) G = –1 RL = 1kΩ VO = 0.5Vp-p 6 200 INVERTING LARGE-SIGNAL FREQUENCY RESPONSE 3 G = +2 RL = 1kΩ 100 Frequency (MHz) Frequency (MHz) 9 G = –1 G = –5 –3 See Figure 1 –12 G = –10 G = –24 VO = 0.5Vp-p RF = 1.2kΩ G = 50 Normalized Gain (3dB/div) 6 3 –3 VO = 5Vp-p –6 VO = 2Vp-p VO = 5Vp-p 0 –9 VO = 2Vp-p See Figure 1 1 See Figure 2 –12 10 100 200 1 10 Frequency (MHz) NONINVERTING PULSE RESPONSE 0.8 0.8 3.2 0.6 2.4 Large-Signal Right Scale 0.2 1.6 0.8 Small-Signal Left Scale 0 0 –0.2 –0.8 –0.4 –1.6 –0.6 Output Voltage (200mV/div) G = –1 Output Voltage (800mV/div) Output Voltage (200mV/div) G = +2 –2.4 0.6 2.4 0.4 1.6 0.2 0.8 0 0 Small-Signal Left Scale –0.2 –0.8 Large-Signal Right Scale –0.4 –0.6 See Figure 1 –1.6 –2.4 See Figure 2 –0.8 –3.2 Time (10ns/div) –0.8 –3.2 Time (10ns/div) OPA683 SBOS221B 200 INVERTING PULSE RESPONSE 3.2 0.4 100 Frequency (MHz) 5 www.ti.com Output Voltage (800mV/div) –3 TYPICAL CHARACTERISTICS: VS = ±5V (Cont.) TA = 25°C, RF = 1.2kΩ, RL = 1kΩ, and G = +2, (see Figure 1 for AC performance only), unless otherwise noted. HARMONIC DISTORTION vs LOAD RESISTANCE HARMONIC DISTORTION vs FREQUENCY –50 –50 VO = 2Vp-p f = 5MHz G = +2 –60 2nd-Harmonic Harmonic Distortion (dBc) Harmonic Distortion (dBc) –55 VO = 2Vp-p RL = 1kΩ –65 –70 –75 –80 –85 –60 2nd-Harmonic –70 3rd-Harmonic –80 3rd-Harmonic See Figure 1 –90 See Figure 1 –90 100 0.1 1k 1 Load Resistance (Ω) HARMONIC DISTORTION vs OUTPUT VOLTAGE f = 5MHz RL = 1kΩ –60 Harmonic Distortion (dBc) Harmonic Distortion (dBc) –50 2nd-Harmonic –70 –80 3rd-Harmonic See Figure 1 0.5 1 VO = 2Vp-p RL = 1kΩ 5 2nd-Harmonic –60 –70 –80 3rd-Harmonic See Figure 1 –90 ±2.5 ±3 ±3.5 –90 Output Voltage (Vp-p) ±4 ±4.5 ±5 Supply Voltage (±V) ±5.5 ±6 HARMONIC DISTORTION vs INVERTING GAIN HARMONIC DISTORTION vs NONINVERTING GAIN –50 –50 –60 2nd-Harmonic –65 –70 –75 3rd-Harmonic –80 VO = 2Vp-p f = 5MHz RL = 1kΩ –55 Harmonic Distortion (dBc) VO = 2Vp-p f = 5MHz RL = 1kΩ –55 Harmonic Distortion (dBc) 20 5MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE –50 –60 2nd-Harmonic –65 –70 –75 3rd-Harmonic –80 –85 –85 –90 10 Frequency (MHz) See Figure 2 See Figure 1 –90 1 10 1 20 10 20 Inverting Gain (–V/V) Gain (V/V) OPA683 6 www.ti.com SBOS221B TYPICAL CHARACTERISTICS: VS = ±5V (Cont.) TA = 25°C, RF = 1.2kΩ, RL = 1kΩ, and G = +2, (see Figure 1 for AC performance only), unless otherwise noted. 2-TONE, 3RD-ORDER INTERMODULATION DISTORTION INPUT VOLTAGE AND CURRENT NOISE DENSITY –45 Inverting Current Noise 11.6pA/√Hz Noninverting Current Noise 5.2pA/√Hz 10 Voltage Noise 4.4nV/√Hz 3rd-Order Spurious Level (dBc) Voltage Noise (nV/√Hz) Current Noise (pA/√Hz) 100 20MHz –55 10MHz +5V –65 PI 1kΩ –5V 1.2kΩ –75 1.2kΩ 1 1MHz –85 102 103 104 105 106 107 0.1 0.4 1 Vp-p at 1kΩ Load (each tone) Frequency (Hz) DISABLE TIME –40 VDIS G = +2 VDIS = 0V –50 VIN = 1VDC See Figure 1 4 –60 Feedthru (dB) VOUT and VDIS (V) 5 2 DISABLED FEEDTHRU 6 3 2 5MHz PO 50Ω OPA684 VOUT –70 –80 1 –90 See Figure 1 0 –100 0 10 20 30 40 50 60 70 80 90 100 0.1 1 Time (ms) 10 100 Frequency (MHz) SMALL-SIGNAL BANDWIDTH vs CLOAD RS vs CLOAD 160 9 0.5dB Peaking 10pF 140 6 Normalized Gain (dB) 120 RS (Ω) 100 80 60 40 3 +5V RS VI 0 VO 100pF 50Ω OPA683 CL 1kΩ 47pF –5V 1.2kΩ –3 20 1.2kΩ 22pF 0 –6 1 10 100 1 CLOAD (pF) OPA683 SBOS221B 10 100 200 Frequency (MHz) 7 www.ti.com TYPICAL CHARACTERISTICS: VS = ±5V (Cont.) TA = 25°C, RF = 1.2kΩ, RL = 1kΩ, and G = +2, (see Figure 1 for AC performance only), unless otherwise noted. OPEN-LOOP TRANSIMPEDANCE GAIN AND PHASE CMRR and PSRR vs FREQUENCY CMRR 60 50 +PSRR 40 –PSRR 20 10 0 104 105 106 Frequency (Hz) 107 –30 80 –60 60 –90 ∠ ZOL 40 –120 20 –150 0 –180 104 108 105 108 109 OUTPUT CURRENT AND VOLTAGE LIMITATIONS COMPOSITE VIDEO DIFFERENTIAL GAIN/PHASE Gain = +2 NTSC, Positive Video 4 1W Power Limit RL = 500Ω 5 0.2 3 0.15 2 dG VO (V) 0.1 = RL 50 Ω 1 0 –1 –2 0.05 –3 dP –4 1 2 3 4 Number of 150Ω Video Loads –150 0 IO (mA) TYPICAL DC DRIFT OVER TEMPERATURE SUPPLY AND OUTPUT CURRENT vs TEMPERATURE –50 50 100 150 1 Sourcing Output Current 3 2 Output Current (mA) Input Bias Currents (µA) and Offset Voltage (mV) –100 200 4 1 1W Power Limit –5 0 Noninverting Input Bias Current 0 Input Offset Voltage –1 –2 175 0.95 Supply Current Right Scale 150 0.9 Sinking Output Current 125 0.85 –3 Inverting Input Bias Current 100 –4 –50 –25 0 25 50 75 100 125 0.8 –25 Ambient Temperature (°C) 0 25 50 75 Ambient Temperature (°C) 100 125 OPA683 8 www.ti.com SBOS221B Supply Current (mA) Differential Gain (%) Differential Phase (°) 106 107 Frequency (Hz) =1 00Ω 103 100 L 102 0 20log (ZOL) R 30 120 Open-Loop Phase (°) Open-Loop Transimpedance Gain (dBΩ) Common-Mode Rejection Ratio (dB) Power-Supply Rejection Ratio (dB) 70 TYPICAL CHARACTERISTICS: VS = ±5V (Cont.) TA = 25°C, RF = 1.2kΩ, RL = 1kΩ, and G = +2, (see Figure 1 for AC performance only), unless otherwise noted. SETTLING TIME DISABLED SUPPLY CURRENT vs TEMPERATURE 0.05 110 0.03 0.02 0.01 0 –0.01 –0.02 –0.03 100 90 80 70 –0.04 +VS Current –0.05 60 0 10 20 30 Time (ns) 40 50 60 –50 0 25 50 75 Ambient Temperature (°C) 125 8.0 3.2 6.4 6.4 6.4 2.4 4.8 4.8 4.8 1.6 3.2 0.8 1.6 0 0 Output Voltage Right Scale –0.8 –1.6 See Figure 1 –1.6 –2.4 –3.2 –4.8 Input Voltage Left Scale –4.0 Input Voltage (1.6V/div) 8.0 Output Voltage (1.6V/div) 8.0 –3.2 3.2 3.2 Output Voltage Right Scale 1.6 1.6 0 0 –1.6 –1.6 –3.2 –3.2 –4.8 –6.4 –6.4 –8.0 –8.0 –4.8 Input Voltage Left Scale See Figure 2 –6.4 –8.0 Time (100ns/div) Time (100ns/div) CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY INPUT AND OUTPUT RANGE vs SUPPLY VOLTAGE 100 6 5 4 3 2 1 0 –1 –2 –3 –4 –5 –6 Input Voltage Range Output Impedance (Ω) Input and Output Voltage Range 100 INVERTING OVERDRIVE RECOVERY NONINVERTING OVERDRIVE RECOVERY 4.0 Input Voltage (0.8V/div) –25 Output Voltage Range OPA683 10 ZO 1.2kΩ 1.2kΩ 1 0.01 0.001 ±2 ±3 ±4 ±5 ±6 100 ± Supply Voltage 10k 100k 1M 10M 100M Frequency (Hz) OPA683 SBOS221B 1k 9 www.ti.com Input Voltage (1.6V/div) % Error to Final Value Disabled Supply Current (µA) 2V Step See Figure 1 0.04 TYPICAL CHARACTERISTICS: VS = +5V TA = 25°C, RF = 1.4kΩ, RL = 1kΩ, and G = +2, (see Figure 3 for AC performance only), unless otherwise noted. NONINVERTING SMALL-SIGNAL FREQUENCY RESPONSE 3 Normalized Gain (dB) 0 INVERTING SMALL-SIGNAL FREQUENCY RESPONSE 3 G = 50 RF = 1.4kΩ VO = 0.2Vp-p RL = 1kΩ G=1 Normalized Gain (3dB/div) 6 G=2 –3 –6 G=5 –9 G = 10 –12 –15 0 –3 RF = 1.4kΩ VO = 0.2Vp-p RL = 1kΩ –6 G = 20 See Figure 3 –18 See Figure 4 –12 1 10 100 200 1 10 Frequency (MHz) 0.5Vp-p G = –1 RL = 1kΩ VO = 0.2Vp-p 0 6 VO = 0.5Vp-p 0.2Vp-p Gain (dB) Gain (dB) 200 INVERTING LARGE-SIGNAL FREQUENCY RESPONSE 3 G = +2 RL = 1kΩ 100 Frequency (MHz) NONINVERTING LARGE-SIGNAL FREQUENCY RESPONSE 9 G = –1 G = –2 G = –5 G = –10 G = –28 –9 3 –3 VO = 1Vp-p –6 1Vp-p VO = 2Vp-p 0 –9 2Vp-p See Figure 3 –3 See Figure 4 –12 10 100 200 1 10 Frequency (MHz) NONINVERTING PULSE RESPONSE 0.3 INVERTING PULSE RESPONSE 0.4 1.6 1.2 0.3 1.2 0.2 0.8 0.1 0.4 0.2 0.8 0.1 0.4 Small-Signal Left Scale 0 0 –0.1 –0.4 –0.2 –0.8 –0.3 Output Voltage (100mV/div) Large-Signal Right Scale 200 1.6 Output Voltage (400mV/div) Output Voltage (100mV/div) 0.4 100 Frequency (MHz) –1.2 0 0 Small-Signal Left Scale –0.1 –0.4 Large-Signal Right Scale –0.2 –0.3 See Figure 3 –0.8 –1.2 See Figure 4 –0.4 –1.6 Time (10ns/div) –0.4 –1.6 Time (10ns/div) OPA683 10 www.ti.com SBOS221B Output Voltage (400mV/div) 1 TYPICAL CHARACTERISTICS: VS = +5V (Cont.) TA = 25°C, RF = 1.4kΩ, RL = 1kΩ, and G = +2, (see Figure 3 for AC performance only), unless otherwise noted. HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs LOAD RESISTANCE –50 –50 3rd-Harmonic Harmonic Distortion (dBc) Harmonic Distortion (dBc) VO = 2Vp-p RL = 1kΩ VO = 2Vp-p f = 5MHz –55 –60 –65 –70 2nd-Harmonic –75 –80 3rd-Harmonic –60 2nd-Harmonic –70 –80 –85 See Figure 3 See Figure 3 –90 –90 100 0.1 1k 1 –45 G = +2 RL = 1kΩ f = 5MHz 3rd-Order Spurious Level (dBc) Harmonic Distortion (dBc) –50 –60 2nd-Harmonic –70 3rd-Harmonic –80 See Figure 3 0.5 20MHz –55 10MHz –65 –75 See Figure 3 2 3 0.1 1 Vp-p at 1Ω Load (each tone) SUPPLY AND OUTPUT CURRENT vs TEMPERATURE COMPOSITE VIDEO DIFFERENTIAL GAIN/PHASE 0.3 90 0.9 0.25 Sourcing Output Current Left Scale Supply Current Right Scale 0.85 0.8 70 Left Scale Sinking Output Current 0.75 60 0.7 50 –50 –25 0 25 50 75 Ambient Temperature (°C) 100 G = +2 NTSC, Positive Video 0.2 dP 0.15 0.1 dG 0.05 0 1 125 2 3 4 Number of 150Ω Video Loads OPA683 SBOS221B Differential Gain (%) Differential Phase (°) 0.95 Supply Current (mA) 100 80 5MHz –85 1 Output Voltage (Vp-p) Output Current (mA) 20 2-TONE, 3RD-ORDER INTERMODULATION DISTORTION HARMONIC DISTORTION vs OUTPUT VOLTAGE –90 10 Frequency (MHz) Load Resistance (Ω) 11 www.ti.com APPLICATIONS INFORMATION VERY LOW POWER CURRENT-FEEDBACK OPERATION The OPA683 gives a new level of performance in very low power current-feedback op amps. Using a new input stage buffer architecture, the OPA683 CFBplus amplifier gives improved bandwidth to higher gains than previous < 1mA supply current amplifiers. This closed-loop internal buffer gives a very low and linearized impedance at the inverting node—isolating the amplifier’s AC performance from gain element variations. This allows both the bandwidth and distortion to remain nearly constant over gain—moving closer to the ideal current-feedback performance of Gain Bandwidth independence. This low power amplifier also delivers exceptional output power—it’s ±4V swing on ±5V supplies with > 100mA output drive gives excellent performance into standard video loads or doubly-terminated 50Ω cables. Single +5V supply operation is also supported with similar bandwidths, but reduced output power capability. For improved harmonic distortion driving heavier loads, in a low power CFBplus amplifier, consider the OPA684 while, for even higher output power, consider the OPA691. Figure 2 shows the DC-coupled, gain of –1V/V, dual powersupply circuit used as the basis of the Inverting Typical Characteristics. Inverting operation offers several performance benefits. Since there is no common-mode signal across the input stage, the slew rate for inverting operation is higher and the distortion performance is slightly improved. An additional input resistor, RM, is included in Figure 2 to set the input impedance equal to the 50Ω. The parallel combination of RM and RG set the input impedance. As the desired gain increases for the inverting configuration, RG is adjusted to achieved the desired gain and RM is also adjusted to hold a 50Ω input match. A point will be reached where RG will equal 50Ω, RM is then removed and the input match is set by RG only. With RG fixed to achieve an input match to 50Ω, to increase gain, RF is simply increased. This will, however, quickly reduce the achievable bandwidth as the feedback resistor increases from its recommended value of 1.2kΩ. If the source does not require an input match to 50Ω, either adjust RM to the get the desired load or remove it and let the RG resistor alone provide the input load. +5V Figure 1 shows the DC-coupled, gain of +2, dual powersupply circuit used as the basis of the ±5V Electrical Characteristics and Typical Characteristics. For test purposes, the input impedance is set to 50Ω with a resistor to ground while the output load is a 1kΩ resistor. Voltage swings reported in the specifications are taken directly at the input and output pins while load powers (dBm) are interpreted as the voltage swing at the output converted to dBm as if the load were 50Ω. For the circuit of Figure 1, the total effective load will be 1kΩ || 2.4kΩ = 706Ω. Gain changes are most easily accomplished by simply resetting the RG value—holding RF constant at its recommended value of 1.2kΩ. The disable control line (DIS) is typically left open to ensure normal amplifier operation. It may, however, be asserted LOW to reduce the amplifier quiescent to 100µA typically. 0.1µF + 6.8µF OPA683 RS = 50Ω VO 1kΩ DIS RF 1.2kΩ RG 1.2kΩ VI RT 52.3Ω 0.1µF + 6.8µF –5V FIGURE 2. DC-Coupled, G = –1V/V, Bipolar Supply, Specification and Test Circuit. +5V 0.1µF + These circuits are showing ±5V operation. The same circuit can be applied with bipolar supplies ranging from ±2.5V to ±6V. Internal supply independent biasing gives nearly the same performance for the OPA683 over this wide range of supplies. Generally, the optimum feedback resistor value (for nominally flat frequency response at G = +2) will increase in value as the total supply voltage across the OPA683 is reduced. 6.8µF VI RG = 50Ω 50Ω OPA683 VO 1kΩ DIS RF 1.2kΩ RG 1.2kΩ 0.1µF + 6.8µF –5V FIGURE 1. DC-Coupled, G = +2V/V, Bipolar Supply, Specification and Test Circuit. See Figure 3 for the AC-coupled, single +5V supply, gain of +2V/V circuit configuration used as a basis for the +5V only Electrical Characteristics and Typical Characteristics. The key requirement of broadband single-supply operation is to maintain input and output signal swings within the usable voltage ranges at both the input and the output. The circuit of Figure 3 establishes an input midpoint bias using a simple resistive divider from the +5V supply (two 12.5kΩ resistors) to the noninverting input. The input signal is then AC-coupled OPA683 12 www.ti.com SBOS221B +5V 0.1µF 50Ω Source + +5V 6.8µF 12.5kΩ 0.1µF 0.1µF 2.5V VI 0.1µF 50Ω 12.5kΩ OPA683 DIS RF 1.4kΩ + 6.8µF 12.5kΩ 2.5V VO 0.1µF 0.1µF 1kΩ 50Ω Source 0.1µF 12.5kΩ OPA683 DIS RF 1.4kΩ RG 1.4kΩ VO 1kΩ VI RG 1.4kΩ 52.3Ω 0.1µF FIGURE 3. AC-Coupled, G = +2V/V, Single-Supply, Specification and Test Circuit. into this midpoint voltage bias. The input voltage can swing to within 1.25V of either supply pin, giving a 2.5Vp-p input signal range centered between the supply pins. The input impedance of Figure 3 is set to give a 50Ω input match. If the source does not require a 50Ω match, remove this and drive directly into the blocking capacitor. The source will then see the 6.25kΩ load of the biasing network. The gain resistor (RG) is AC-coupled, giving the circuit a DC gain of +1—which puts the noninverting input DC bias voltage (2.5V) on the output as well. The feedback resistor value has been adjusted from the bipolar supply condition to re-optimize for a flat frequency response in +5V only, gain of +2 operation. On a single +5V supply, the output voltage can swing to within 1.0V of either supply pin while delivering more than 50mA output current giving 3Vp-p output swing into an AC-coupled 100Ω load if required (8dBm maximum at the matched load). The circuit of Figure 3 shows a blocking capacitor driving into a 1kΩ load resistor. Alternatively, the blocking capacitor could be removed if the load is tied to a supply midpoint or to ground if the DC current required by the load is acceptable. Figure 4 shows the AC-coupled, single +5V supply, gain of –1V/V circuit configuration used as a basis for the +5V only Typical Characteristics. In this case, the midpoint DC bias on the noninverting input is also decoupled with an additional 0.1µF decoupling capacitor. This reduces the source impedance at higher frequencies for the noninverting input bias current noise. This 2.5V bias on the noninverting input pin appears on the inverting input pin and, since RG is DC blocked by the input capacitor, will also appear at the output pin. One advantage to inverting operation is that since there is no signal swing across the input stage, higher slew rates and operation to even lower supply voltages is possible. To retain a 1Vp-p output capability, operation down to a 3V supply is allowed. At a +3V supply, the input stage is saturated, but for the inverting configuration of a currentfeedback amplifier, wideband operation is retained even under this condition. FIGURE 4. AC-Coupled, G = –1V/V, Single-Supply, Specification and Test Circuit. The circuits of Figure 3 and 4 show single-supply operation at +5V. These same circuits may be used up to single supplies of +12V with minimal changes in the performance of the OPA683. LOW POWER, VIDEO LINE DRIVER APPLICATIONS For low power, video line driving, the OPA683 provides the output current and linearity to support multiple load composite video signals. Figure 5 shows a typical ±5V supply video line driver application. The improved 2nd-harmonic distortion of the CFBplus architecture, along with the OPA683’s high output current and voltage, gives exceptional differential gain and phase performance in a very low power solution. As the Typical Characteristics show, a single video load shows a dG/dP of 0.06%/0.03°. Multiple loads may also be driven with < 0.15%/0.1° dG/dP for up to 4 parallel video loads where the amplifier is driving an equivalent load of 37.5Ω. +5V VIDEOIN Supply Decoupling not shown. 75Ω 75Ω Coax 75Ω Load OPA683 1.2kΩ 1.2kΩ –5V FIGURE 5. Gain of +2 Video Cable Driver. OPA683 SBOS221B DIS 13 www.ti.com VERY LOW POWER ACTIVE FILTER HIGH GAIN HF AMPLIFIER The OPA683 provides an exceptionally capable gain block for implementing Sallen-Key type filters. Typically, the bandwidth interaction with gain setting for low power amplifiers, constrain these filters to using unity-gain amplifiers. Since the OPA683 CFBplus design holds very high bandwidth to high gains, implementations that provide signal gain, as well as the desired filter shape, are easily implemented. Figure 6 shows an example of a 5MHz 2nd-order low-pass filter where the amplifier is providing a voltage gain of 4. This singlesupply implementation (applicable to single +12V operation as well) consumes only 5.1mW quiescent power. The two 12.5kΩ resistors bias the input and output at the supply midpoint while the three 0.1µF capacitors block off the DC current paths to ground for this mid-scale operating point. The filter resistors and capacitors have been adjusted to provide a Butterworth (Q = 0.707) response with a Wo = 2π • 5MHz. This gives a flat passband response with a –3dB cutoff at 5MHz. Figure 7 shows the small-signal frequency response for the circuit of Figure 6. Where high gains at moderate frequencies are required in an HF receiver channel, the OPA683 can provide a very low power solution with moderate input noise figure. Figure 8 shows a technique that can improve the noise figure with no added power. An input transformer provides a noiseless voltage gain at the cost of higher source impedance for the amplifier’s noninverting input current noise. The circuit of Figure 8, using a 1:4 turns ratio (1:16 impedance ratio) transformer, reduces the input noise figure from about 20dB for just the amplifier to 10.6dB in combination. The bandwidth for this circuit will be principally set by the transformer since the OPA683 will give > 80MHz for the gain of 20V/V shown in Figure 8. The overall circuit gives a gain to a matched 50Ω load of 32dB (40V/V) from the transformer input. This example circuit provides this gain using only 10mW of quiescent power with application from 500kHz to 30MHz. +5V PI +5V Supply De-coupling Not Shown 50Ω 1:4 50Ω OPA683 800Ω PO 50Ω 100pF 12.5kΩ 0.1µF 157Ω 1.2kΩ 446Ω VI 0.1µF 150pF OPA683 12.5kΩ VO 10.6dB Noise Figure –5V 63Ω 1kΩ PO = 32dB PI 0.01µF 1.4kΩ FIGURE 8. Low Power, High Gain HF Amplifier. 467Ω 0.1µF LOW POWER, ADC DRIVER FIGURE 6. 5MHz, 2nd-Order Low Pass Filter. LOW POWER 5MHz LP ACTIVE FILTER 15 12 Gain (dB) 9 6 3 0 –3 –6 –9 103 104 105 106 107 20E6 Frequency (Hz) FIGURE 7. Low Power Active Filter Frequency Response. Where a low power, single-supply interface to a single-ended input +5V ADC is required, the circuit of Figure 9 can provide a very flexible, high performance solution. Running in an ACcoupled inverting mode allows the noninverting input to be used for the common-mode voltage from the ADS820 converter. This midpoint reference biases both the noninverting converter input and the amplifier noninverting input. With an AC-coupled gain path, this +2.5V DC bias has a gain of +1 to the output putting the output at the DC midpoint for the converter. The output then drives through an isolating resistor (60Ω) to the inverting input of the converter which is further decoupled by a 22pF external capacitance to add to its 5pF input capacitance. This coupling network provides a high cutoff low-pass while also giving a low source impedance at high frequencies for the converter. The gain for this circuit is set by adjusting RG to the desired value. For a 2Vp-p maximum output driving the light load of Figure 9, the OPA683 will provide < –80dBc THD through 1MHz as shown in the Typical Characteristics. One of the important advantages for this CFBplus amplifier is that this distortion does not degrade significantly at higher gains. OPA683 14 www.ti.com SBOS221B RI 1.4kΩ +5V DIS RG 2.5VDC VI 60Ω VO OPA683 IN ADS830 10-Bit 20MSPS 22pF VO = – 1.4kΩ RG VI 2Vp-p Max 50Ω IN +2.5V CM 0.1µF FIGURE 9. Low Power, Single-Supply, ADC Driver. DESIGN-IN TOOLS DEMONSTRATION BOARDS VI Two PC boards are available to assist in the initial evaluation of circuit performance using the OPA683 in its two package styles. Both of these are available free as an unpopulated PC board delivered with descriptive documentation. The summary information for these boards is shown in Table I. PRODUCT OPA683ID OPA683IDBQ PACKAGE BOARD PART NUMBER LITERATURE REQUEST NUMBER SO-8 SOT23-6 DEM-OPA68xU DEM-OPA6xxN SBOU009 SBOU010 α VO RI iERR Z(S) iERR RF RG TABLE I. EVM Boards by Package. FIGURE 10. Current Feedback Transfer Function Analysis Circuit. OPERATING SUGGESTIONS SETTING RESISTOR VALUES TO OPTIMIZE BANDWIDTH Any current-feedback op amp like the OPA683 can hold high bandwidth over signal gain settings with the proper adjustment of the external resistor values. A low-power part like the OPA683 typically shows a larger change in bandwidth due to the significant contribution of the inverting input impedance to loop-gain changes as the signal gain is changed. Figure 10 shows a simplified analysis circuit for any current feedback amplifier. The key elements of this current feedback op amp model are: α ⇒ Buffer gain from the noninverting input to the inverting input RI ⇒ Buffer output impedance iERR ⇒ Feedback error current signal Z(s) ⇒ Frequency dependent open loop transimpedance gain from iERR to VO The buffer gain is typically very close to 1.00 and is normally neglected from signal gain considerations. It will, however set the CMRR for a single op amp differential amplifier configuration. For the buffer gain α < 1.0, the CMRR = –20 • log(1 – α). The closed loop input stage buffer used in the OPA683 gives a buffer gain more closely approaching 1.00 and this shows up in a slightly higher CMRR than any previous current feedback op amp. The 60dB typical CMRR shown in the Electrical Characteristics implies a buffer gain of 0.9990. RI, the buffer output impedance, is a critical portion of the bandwidth control equation. The OPA683 reduces this element to approximately 4.5Ω using the loop-gain of the input buffer stage. This significant reduction in buffer output impedance, on very low power, contributes significantly to extending the bandwidth at higher gains. OPA683 SBOS221B 15 www.ti.com R α 1 + F R VO α NG G = = VI RF 1 + RF + RI NG RF + RI 1 + Z (S ) RG 1+ Z (S ) R NG = 1 + F R G This is written in a loop-gain analysis format where the errors arising from a non-infinite open-loop gain are shown in the denominator. If Z(s) was infinite over all frequencies, the denominator of Equation 1 would reduce to 1 and the ideal desired signal gain shown in the numerator would be achieved. The fraction in the denominator of Equation 1 determines the frequency response. Equation 2 shows this as the loop-gain equation. (2) Z (S ) RF + RI NG = Loop Gain 3900 325 VO = 0.5Vp-p 3400 275 –3dB Bandwidth 2900 225 2400 175 1900 125 RF 1400 75 900 25 2 The OPA683 is internally compensated to give a maximally flat frequency response for RF = 1.2kΩ at NG = 2 on ±5V supplies. That optimum value goes to 1.4kΩ on a single +5V supply. Normally, with a current feedback amplifier, it is possible to adjust the feedback resistor to hold this bandwidth up as the gain is increased. The CFBplus architecture has reduced the contribution of the inverting input impedance to provide exceptional bandwidth to higher gains without adjusting the feedback resistor value. The Typical Characteristics show the small-signal bandwidth over gain with a fixed feedback resistor. 5 10 20 50 100 Voltage Gain (V/V) FIGURE 11. Bandwidth and RF Optimized vs Gain. 3 G=5 G=2 0 Normalized Gain (dB) If 20 • log(RF + NG • RI) were drawn on top of the open-loop transimpedance plot, the difference between the two would be the loop gain at a given frequency. Eventually, Z(s) rolls off to equal the denominator of Equation 2 at which point the loop gain has reduced to 1 (and the curves have intersected). This point of equality is where the amplifier’s closed-loop frequency response given by Equation 1 will start to roll off, and is exactly analogous to the frequency at which the noise gain equals the open-loop voltage gain for a voltage feedback op amp. The difference here is that the total impedance in the denominator of Equation 2 may be controlled somewhat separately from the desired signal gain (or NG). Bandwidth (MHz) (1) At very high gains, 2nd-order effects in the buffer output impedance cause the overall response to peak up. If desired, it is possible to retain a flatter frequency response at higher gains by adjusting the feedback resistor to higher values as the gain is increased. Figure 11 shows the empirically determined feedback resistor and resulting –3dB bandwidth from gains of +2 to +100 to hold a < 0.5dB peaked response. Here, since a slight peaking was allowed, a lower nominal RF is suggested at a gain of +2 giving > 250MHz bandwidth. This exceeds that shown in the Electrical Characteristics due to the slightly lower feedback resistor allowing a modest peaking in the response. Figure 12 shows the measured frequency response curves with the adjusted feedback resistor value. While the bandwidth for this low-power part does reduce at higher gains, going over a 50:1 gain range gives only a factor of 10 bandwidth reduction. The 25MHz bandwidth at a gain of 100V/V is equivalent to a 2.5GHz gain bandwidth product voltage feedback amplifier capability. Even better bandwidth retention to higher gains can be delivered by the slightly higher quiescent power OPA684. Feedback Resistor (Ω) A current-feedback op amp senses an error current in the inverting node (as opposed to a differential input error voltage for a voltage feedback op amp) and passes this on to the output through an internal frequency dependent transimpedance gain. The Typical Characteristics show this open-loop transimpedance response. This is analogous to the openloop voltage gain curve for a voltage feedback op amp. Developing the transfer function for the circuit of Figure 10 gives Equation 1: –3 G = 100 –6 G = 10 G = 50 –9 G = 20 –12 1 10 100 200 Frequency (MHz) FIGURE 12. Small-Signal Frequency Response with Optimized RF. OPA683 16 www.ti.com SBOS221B OUTPUT CURRENT AND VOLTAGE The OPA683 provides output voltage and current capabilities that can support the needs of driving doubly-terminated 50Ω lines. Changing the 1kΩ load in Figure 1 to a 100Ω will give a total load that is the parallel combination of the 100Ω load and the 2.4kΩ total feedback network impedance. This 96Ω load will require no more than 36mA output current to support a ±3.5V output voltage swing. This is within the specified minimum output current of +58mA/–45mA over the full temperature range. The specifications described above, though familiar in the industry, consider voltage and current limits separately. In many applications, it is the voltage • current, or V-I product, which is more relevant to circuit operation. Refer to the “Output Voltage and Current Limitations” plot in the Typical Characteristics. The X and Y axes of this graph show the zero-voltage output current limit and the zero-current output voltage limit, respectively. The four quadrants give a more detailed view of the OPA683’s output drive capabilities. Superimposing resistor load lines onto the plot shows the available output voltage and current for specific loads. The minimum specified output voltage and current over temperature are set by worst-case simulations at the cold temperature extreme. Only at cold startup will the output current and voltage decrease to the numbers shown in the Electrical Specifications. As the output transistors deliver power, their junction temperatures will increase, decreasing their VBE’s (increasing the available output voltage swing) and increasing their current gains (increasing the available output current). In steady state operation, the available output voltage and current will always be greater than that shown in the over-temperature specifications since the output stage junction temperatures will be higher than the minimum specified operating ambient. To maintain maximum output stage linearity, no output short circuit protection is provided. This will not normally be a problem since most applications include a series matching resistor at the output that will limit the internal power dissipation if the output side of this resistor is shorted to ground. However, shorting the output pin directly to the adjacent positive power-supply pin (8-pin packages) will, in most cases, destroy the amplifier. If additional short-circuit protection is required, consider a small series resistor in the powersupply leads. This will, under heavy output loads, reduce the available output voltage swing. A 5Ω series resistor in each power-supply lead will limit the internal power dissipation to less than 1W for an output short circuit while decreasing the available output voltage swing only 0.25V for up to 50mA desired load currents. Always place the 0.1µF power-supply decoupling capacitors after these supply current limiting resistors directly on the supply pins. DRIVING CAPACITIVE LOADS One of the most demanding and yet very common load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an ADC—including additional external capacitance which may be recommended to im- prove ADC linearity. A high-speed, high open-loop gain amplifier like the OPA683 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. When the amplifier’s open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. The Typical Characteristics show the recommended “RS vs Capacitive Load” and the resulting frequency response at the load. The 1kΩ resistor shown in parallel with the load capacitor is a measurement path and may be omitted. Parasitic capacitive loads greater than 3pF can begin to degrade the performance of the OPA683. Long PC board traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. Always consider this effect carefully, and add the recommended series resistor as close as possible to the OPA683 output pin (see Board Layout Guidelines). DISTORTION PERFORMANCE The OPA683 provides low distortion in a very low power amplifier. The CFBplus architecture also gives two significant areas of distortion improvement. First, in operating regions where the 2nd-harmonic distortion due to output stage nonlinearities is very low (frequencies < 1MHz, low output swings into light loads) the linearization at the inverting node provided by the CFBplus design gives 2nd-harmonic distortions that extend into the –90dBc region. Previous current feedback amplifiers have been limited to approximately –85dBc due to the nonlinearities at the inverting input. The second area of distortion improvement comes in a distortion performance that is more gain independent than prior solutions. To the extent that the distortion at a particular output power is output stage dependent, 2nd-harmonic particularly, and to a lesser extend 3rd-harmonic distortion, is constant as the gain is increased. This is due to the constant loop gain versus signal gain provided by the CFBplus design. As shown in the Typical Characteristics, while the 2nd-harmonic is constant with gain, the 3rd-harmonic degrades at higher gains. Relative to alternative amplifiers with < 1mA supply current, the OPA683 holds much lower distortion at higher frequencies (> 5MHz) and to higher gains. Generally, until the fundamental signal reaches very high frequency or power levels, the 2nd-harmonic will dominate the distortion with a lower 3rd-harmonic component. Focusing then on the 2ndharmonic, increasing the load impedance improves distortion slightly for the OPA683. Remember that the total load in- OPA683 SBOS221B 17 www.ti.com cludes the feedback network—in the noninverting configuration (see Figure 1) this is the sum of RF + RG, while in the inverting configuration it is just RF. Also, providing an additional supply decoupling capacitor (0.1µF) between the supply pins (for bipolar operation) improves the 2nd-order distortion slightly (3dB to 6dB). In most op amps, increasing the output voltage swing increases harmonic distortion directly. A low-power part like the OPA683 includes quiescent boost circuits to provide the fullpower bandwidth shown. These act to increase the bias in a very linear fashion only when high slew rate or output power are required. The Typical Characteristics show the 2nd-harmonic increasing slightly from 500mVp-p to 5Vp-p outputs while the 3rd-harmonics also increase with output power. The OPA683 has an extremely low 3rd-order harmonic distortion—particularly for light loads and at lower frequencies. This also gives low 2-tone, 3rd-order intermodulation distortion as shown in the Typical Characteristics. Since the OPA683 includes internal power boost circuits to retain good full-power performance at high frequencies and outputs, it does not show a classical 2-tone, 3rd-order intermodulation intercept characteristic. Instead, it holds relatively low and constant 3rd-order intermodulation spurious levels over power. The Typical Characteristics show this spurious level as a dBc below the carrier at fixed center frequencies swept over single-tone voltage swing at a 1kΩ load. Very light loads such as ADC inputs for will see < –85dBc 3rd-order spurious to 1MHz for full-scale inputs. For much lower 3rd-order intermodulation distortion through 200MHz, consider the OPA685. NOISE PERFORMANCE Wideband current-feedback op amps generally have a higher output noise than comparable voltage feedback op amps. The OPA683 offers an excellent balance between voltage and current noise terms to achieve low output noise in a low- power amplifier. The inverting current noise (11.6pA/√Hz) is lower than most other current feedback op amps while the input voltage noise (4.4nV/√Hz) is lower than any unity-gain stable, comparable slew rate, voltage feedback op amp. This low input voltage noise was achieved at the price of higher noninverting input current noise (5.1pA/√Hz). As long as the AC source impedance looking out of the noninverting node is less than 300Ω, this current noise will not contribute significantly to the total output noise. The op amp input voltage noise and the two input current noise terms combine to give low output noise under a wide variety of operating conditions. Figure 13 shows the op amp noise analysis model with all the noise terms included. In this model, all noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz. The total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage contributors. Equation 3 shows the general form for the output noise voltage using the terms shown in Figure 13. (3) 2 2 EO = ENI2 + (IBNR S ) + 4kTRS GN2 + (IBIRF ) + 4kTRF GN ENI EO OPA683 RS IBN ERS RF √ 4kTRS 4kT RG RG IBI √ 4kTRF 4kT = 1.6E –20J at 290°K FIGURE 13. Op Amp Noise Analysis Model. Dividing this expression by the noise gain (NG = (1 + RF/RG)) will give the equivalent input referred spot noise voltage at the noninverting input, as shown in Equation 4. (4) 2 I R 4kTRF 2 EN = ENI2 + (IBNR S ) + 4kTRS + BI F + GN GN Evaluating these two equations for the OPA683 circuit and component values (see Figure 1) will give a total output spot noise voltage of 17.6nV/√Hz and a total equivalent input spot noise voltage of 8.8nV/√Hz. This total input referred spot noise voltage is higher than the 4.4nV/√Hz specification for the op amp voltage noise alone. This reflects the noise added to the output by the inverting current noise times the feedback resistor. As the gain is increased, this fixed output noise power term contributes less to the total output noise and the total input referred voltage noise given by Equation 3 will approach just the 4.4nV/√Hz of the op amp itself. For example, going to a gain of +20 in the circuit of Figure 1, adjusting only the gain resistor to 63.2Ω, will give a total input referred noise of 4.6nV/√Hz. A more complete description of op amp noise analysis can be found in the TI application note AB-103 (SBOA066). Refer to Texas Instruments’ web site www.ti.com. DC ACCURACY AND OFFSET CONTROL A current-feedback op amp like the OPA683 provides exceptional bandwidth in high gains, giving fast pulse settling but only moderate DC accuracy. The Electrical Characteristics show an input offset voltage comparable to high slew rate voltage-feedback amplifiers. However, the two input bias currents are somewhat higher and are unmatched. Whereas bias current cancellation techniques are very effective with most voltage feedback op amps, they do not generally reduce the output DC offset for wideband current-feedback op amps. Since the two input bias currents are unrelated in both magnitude and polarity, matching the source impedance looking out of each input to reduce their error contribution to the output is ineffective. Evaluating the configuration of Figure 1, using worst case +25°C input offset voltage and OPA683 18 www.ti.com SBOS221B the two input bias currents, gives a worst case output offset range equal to: ±(NG • VOS(MAX)) ± (IBN • RS/2 • NG) ± (IBI • RF) where NG = noninverting signal gain = ±(2 • 3.5mV) ± (4µA • 25Ω • 2) ± (1.2kΩ • 10µA) = ±7mV ± 0.1mV ± 12mV = ±19.1mV While the last term, the inverting bias current error, is dominant in this low-gain circuit, the input offset voltage will become the dominant DC error term as the gain exceeds 4V/V. Where improved DC precision is required in a high-speed amplifier, consider the OPA642 single and OPA2822 dual voltagefeedback amplifiers. DISABLE OPERATION The OPA683 provides an optional disable feature that may be used to reduce system power when channel operation is not required. If the V DIS control pin is left unconnected, the OPA683 will operate normally. To disable, the control pin must be asserted LOW. Figure 14 shows a simplified internal circuit for the disable control feature. The OPA683 provides very high power gain on low quiescent current levels. When disabled, internal high impedance nodes discharge slowly which, with the exceptional power gain provided, give a self powering characteristic that leads to a slow turn off characteristic. Typical full turn off times to rated 100µA disabled supply current are 60ms. Turn on times are very fast—less than 40ns. THERMAL ANALYSIS Operating junction temperature (TJ) is given by TA + PD • θJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL will depend on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 either supply voltage (for equal bipolar supplies). Under this condition PDL = VS2/(4 • RL) where RL includes feedback network loading. 40kΩ Q1 25kΩ 250kΩ IS Control When disabled, the output and input nodes go to a high impedance state. If the OPA683 is operating in a gain of +1 (with a 1.2kΩ feedback resistor still required for stability), this will show a very high impedance (1.7pF || 1MΩ) at the output and exceptional signal isolation. If operating at a gain greater than +1, the total feedback network resistance (RF + RG) will appear as the impedance looking back into the output, but the circuit will still show very high forward and reverse isolation. If configured as an inverting amplifier, the input and output will be connected through the feedback network resistance (RF + RG) giving relatively poor input to output isolation. The OPA683 will not require external heat-sinking for most applications. Maximum desired junction temperature will set the maximum allowed internal power dissipation as described below. In no case should the maximum junction temperature be allowed to exceed 175°C. +VS VDIS This shuts off the collector current out of Q1, turning the amplifier off. The supply current in the disable mode are only those required to operate the circuit of Figure 14. –VS Note that it is the power in the output stage and not into the load that determines internal power dissipation. FIGURE 14. Simplified Disable Control Circuit. In normal operation, base current to Q1 is provided through the 250kΩ resistor while the emitter current through the 40kΩ resistor sets up a voltage drop that is inadequate to turn on the two diodes in Q1’s emitter. As V DIS is pulled LOW, additional current is pulled through the 40kΩ resistor eventually turning on these two diodes (≈ 33µA). At this point, any further current pulled out of V DIS goes through those diodes holding the emitter-base voltage of Q1 at approximately 0V. As an absolute worst case example, compute the maximum TJ using an OPA683IDBV (SOT23-6 package) in the circuit of Figure 1 operating at the maximum specified ambient temperature of +85°C and driving a grounded 100Ω load. PD = 10V • 1.05mA + 52 /(4 • (100Ω || 2.4kΩ)) = 76mW Maximum TJ = +85°C + (0.076W • 150°C/W) = 96°C. This maximum operating junction temperature is well below most system level targets. Most applications will be lower than this since an absolute worst case output stage power was assumed in this calculation. OPA683 SBOS221B 19 www.ti.com BOARD LAYOUT GUIDELINES is a good starting point for design. Note that a 1.2kΩ feedback resistor, rather than a direct short, is required for the unity-gain follower application. A current-feedback op amp requires a feedback resistor even in the unity-gain follower configuration to control stability. Achieving optimum performance with a high frequency amplifier like the OPA683 requires careful attention to board layout parasitics and external component types. Recommendations that will optimize performance include: a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability: on the noninverting input, it can react with the source impedance to cause unintentional band-limiting.. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. b) Minimize the distance (< 0.25") from the power-supply pins to high frequency 0.1µF decoupling capacitors. At the device pins, the ground and power-plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections should always be decoupled with these capacitors. An optional supply decoupling capacitor across the two power supplies (for bipolar operation) will improve 2nd-harmonic distortion performance. Larger (2.2µF to 6.8µF) decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. c) Careful selection and placement of external components will preserve the high frequency performance of the OPA683. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal film and carbon composition axially-leaded resistors can also provide good high frequency performance. Again, keep their leads and PC board trace length as short as possible. Never use wirewound type resistors in a high-frequency application. Since the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as noninverting input termination resistors, should also be placed close to the package. Where double side component mounting is allowed, place the feedback resistor directly under the package on the other side of the board between the output and inverting input pins. The frequency response is primarily determined by the feedback resistor value as described previously. Increasing its value will reduce the peaking at higher gains, while decreasing it will give a more peaked frequency response at lower gains. The 1.2kΩ feedback resistor used in the Electrical Characteristics at a gain of +2 on ±5V supplies d) Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the plot of recommended RS versus capacitive load. Low parasitic capacitive loads (< 5pF) may not need an RS since the OPA683 is nominally compensated to operate with a 2pF parasitic load. If a long trace is required, and the 6dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is normally not necessary on board, and in fact a higher impedance environment will improve distortion as shown in the distortion versus load plots. With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the OPA683 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device: this total effective impedance should be set to match the trace impedance. The high output voltage and current capability of the OPA683 allows multiple destination devices to be handled as separate transmission lines, each with their own series and shunt terminations. If the 6dB attenuation of a doublyterminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of “RS vs Capacitive Load”. This will not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is LOW, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. e) Socketing a high-speed part like the OPA683 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA683 onto the board. OPA683 20 www.ti.com SBOS221B INPUT AND ESD PROTECTION The OPA683 is built using a very high speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table where an absolute maximum 13V across the supply pins is reported. All device pins have limited ESD protection using internal diodes to the power supplies as shown in Figure 15. These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher currents are possible (e.g. in systems with ±15V supply parts driving into the OPA683), current limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible since high values degrade both noise performance and frequency response. +V CC External Pin –V CC FIGURE 15. Internal ESD Protection. OPA683 SBOS221B Internal Circuitry 21 www.ti.com PACKAGE DRAWINGS MSOI002B – JANUARY 1995 – REVISED SEPTEMBER 2001 D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 8 PINS SHOWN 0.020 (0,51) 0.014 (0,35) 0.050 (1,27) 8 0.010 (0,25) 5 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 1 4 0.010 (0,25) 0°– 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.010 (0,25) 0.004 (0,10) 0.069 (1,75) MAX PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047/E 09/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 OPA683 22 www.ti.com SBOS221B PACKAGE DRAWINGS (Cont.) MPDS018E – FEBRUARY 1996 – REVISED FEBRUARY 2002 DBV (R-PDSO-G5) PLASTIC SMALL-OUTLINE 0,50 0,30 0,95 5 0,20 M 4 1,70 1,50 1 0,15 NOM 3,00 2,60 3 Gage Plane 3,00 2,80 0,25 0° – 8° 0,55 0,35 Seating Plane 1,45 0,95 0,05 MIN 0,10 4073253-4/G 01/02 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-178 OPA683 SBOS221B 23 www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. 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