® OPA2681 OPA 268 OPA 1 268 1 Dual Wideband, Current Feedback OPERATIONAL AMPLIFIER With Disable TM FEATURES APPLICATIONS ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● WIDEBAND +5V OPERATION: 225MHz (G = +2) UNITY GAIN STABLE: 280MHz (G = 1) HIGH OUTPUT CURRENT: 150mA OUTPUT VOLTAGE SWING: ±4.0V HIGH SLEW RATE: 2100V/µs LOW SUPPLY CURRENT: 6mA/ch LOW DISABLED CURRENT: 200µA/ch ENABLE/DISABLE TIME: 25ns/100ns xDSL LINE DRIVER MATCHED I/Q CHANNEL AMPLIFIER BROADBAND VIDEO BUFFERS HIGH SPEED IMAGING CHANNELS PORTABLE INSTRUMENTS DIFFERENTIAL ADC DRIVERS ACTIVE FILTERS WIDEBAND INVERTING SUMMING DESCRIPTION The OPA2681 sets a new level of performance for broadband dual current feedback op amps. Operating on a very low 6mA/ch supply current, the OPA2681 offers a slew rate and output power normally associated with a much higher supply current. A new output stage architecture delivers a high output current with minimal voltage headroom and crossover distortion. This gives exceptional single supply operation. Using a single +5V supply, the OPA2681 can deliver a 1V to 4V output swing with over 100mA drive current and 150MHz bandwidth. This combination of features makes the OPA2681 an ideal RGB line driver or single supply ADC input driver. The OPA2681’s low 6mA/ch supply current is precisely trimmed at 25°C. This trim, along with low drift over temperature, guarantees lower guaranteed maximum supply current than competing products. System power may be further reduced by using the optional disable control pin (SO-14 only). Leaving this disable pin open, or holding it high, gives normal operation. If pulled low, the OPA2681 supply current drops to less than 400µA while the output goes into a high impedance state. This feature may be used for either power savings or for video MUX applications. OPA2681 RELATED PRODUCTS +12V Voltage Feedback Current Feedback Fixed Gain 1/2 OPA2681 324Ω 2kΩ +6.5V 12.4Ω DUALS TRIPLES OPA680 OPA681 OPA682 OPA2680 OPA2681 OPA2682 OPA3680 OPA3681 OPA3682 1:2 1µF 100Ω 2Vp-p 2kΩ SINGLES 15Vp-p 100Ω 324Ω 12.4Ω 1/2 OPA2681 Single Supply ADSL Upstream Driver International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1997 Burr-Brown Corporation PDS-1440B Printed in U.S.A. October, 1998 SPECIFICATIONS: VS = ±5V RF = 402Ω, RL = 100Ω, and G = +2, (Figure 1 for AC performance only), unless otherwise noted. OPA2681U, N TYP CONDITIONS +25°C G = +1, RF = 453Ω G = +2, RF = 402Ω G = +5, RF = 261Ω G = +10, RF = 180Ω G = +2, VO = 0.5Vp-p RF = 453, VO = 0.5Vp-p G = +2, VO = 5Vp-p G = +2, 4V Step G = +2, VO = 0.5V Step G = +2, 5V Step G = +2, VO = 2V Step G = +2, VO = 2V Step G = +2, f = 5MHz, VO = 2Vp-p RL = 100Ω RL ≥ 500Ω RL = 100Ω RL ≥ 500Ω f > 1MHz f > 1MHz f > 1MHz G = +2, NTSC, VO = 1.4Vp, RL = 150Ω RL = 37.5Ω G = +2, NTSC, VO = 1.4Vp, RL = 150Ω RL = 37.5Ω f = 5MHz 280 220 185 125 90 0.4 150 2100 1.7 2.0 12 8 PARAMETER AC PERFORMANCE (Figure 1) Small-Signal Bandwidth (VO = 0.5Vp-p) Bandwidth for 0.1dB Gain Flatness Peaking at a Gain of +1 Large-Signal Bandwidth Slew Rate Rise/Fall Time Settling Time to 0.02% 0.1% Harmonic Distortion 2nd Harmonic 3rd Harmonic Input Voltage Noise Non-Inverting Input Current Noise Inverting Input Current Noise Differential Gain Differential Phase Channel-to-Channel Crosstalk DC PERFORMANCE(4) Open-Loop Transimpedance Gain (ZOL) Input Offset Voltage Average Offset Voltage Drift Non-Inverting Input Bias Current Average Non-Inverting Input Bias Current Drift Inverting Input Bias Current Average Inverting Input Bias Current Drift INPUT Common-Mode Input Range (CMIR)(5) Common-Mode Rejection (CMR) Non-Inverting Input Impedance Minimum Inverting Input Resistance (RI) Maximum Inverting Input Resistance (RI) OUTPUT Voltage Output Swing Current Output, Sourcing Current Output, Sinking Closed-Loop Output Impedance DISABLE (Disabled Low) (SO-14 only) Power Down Supply Current (+VS) Disable Time Enable Time Off Isolation Output Capacitance in Disable Turn On Glitch Turn Off Glitch Enable Voltage Disable Voltage Control Pin Input Bias Current (DIS) POWER SUPPLY Specified Operating Voltage Maximum Operating Voltage Range Max Quiescent Current Min Quiescent Current Power Supply Rejection Ratio (–PSRR) TEMPERATURE RANGE Specification: U, N Thermal Resistance, θJA U SO-8 N SO-14 VO = 0V, RL = 100Ω VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V VCM = 0V –79 –85 –74 –77 2.5 12 15 0.001 0.008 0.01 0.05 –70 GUARANTEED +25°C(2) 0°C to 70°C(3) –40°C to +85°C(3) 220 210 190 50 2 45 4 45 1600 1600 1200 –73 –77 –71 –75 3.0 14 18 –70 –70 –71 –74 3.4 15 18 56 typ min typ typ min max typ min typ typ typ typ C B C C B B C B C C C C –68 –69 –68 –72 3.6 15 19 dBc dBc dBc dBc nV/√Hz pA/√Hz pA/√Hz % % deg deg dBc max max max max max max max typ typ typ typ typ B B B B B B B C C C C C 56 ±6.5 +35 ±65 –400 ±50 –125 56 ±7.5 +40 ±85 –450 ±55 –150 kΩ mV µV/°C µA nA/°C µA nA°/C min max max max max max max A A B A B A B 47 ±3.3 46 ±3.2 45 V dB kΩ || pF Ω Ω min min typ min max A A C A A V V mA mA Ω min min min min typ A A A A C typ typ typ typ typ typ typ min max max C C C C C C C A A A ±5 +30 +55 ±10 ±40 ±3.4 Open-Loop Open-Loop ±3.5 52 100 || 2 45 45 27 60 25 62 24 68 No Load 100Ω Load VO = 0 VO = 0 G = +2, f = 100kHz ±4.0 ±3.9 +190 –150 0.03 ±3.8 ±3.7 ±3.7 ±3.6 +140 –130 ±3.6 ±3.3 +80 –80 VDIS = 0, Both Channels -600 100 25 70 4 ±50 ±20 3.3 1.8 100 G = +2, 5MHz G = +2, RL = 150Ω, VIN = 0 G = +2, RL = 150Ω, VIN = 0 VDIS = 0, Each Channel +160 –135 3.5 1.7 160 3.6 1.6 160 3.7 1.5 160 µA ns ns dB pF mV mV V V µA ±6 ±6 13 11 50 ±6 13.2 10 49 V V mA mA dB typ max max min min C A A A A –40 to +85 °C typ C 125 100 °C/W °C/W typ typ C C ±5 VS = ±5V VS = ±5V Input Referred MIN/ TEST MAX LEVEL(1) MHz MHz MHz MHz MHz dB MHz V/µs ns ns ns ns 100 ±1.3 VCM = 0V UNITS 12 12 58 Junction-to-Ambient 12.4 11.4 52 NOTES: (1) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (2) Junction temperature = ambient for 25°C guaranteed specifications. (3) Junction temperature = ambient at low temperature limit: junction temperature = ambient +23°C at high temperature limit for over temperature guaranteed specifications. (4) Current is considered positive out of node. VCM is the input common-mode voltage. (5) Tested < 3dB below minimum specified CMR at ± CMIR limits. ® OPA2681 2 SPECIFICATIONS: VS = +5V RF = 499Ω, RL = 100Ω to VS /2, G = +2, (Figure 2 for AC performance only), unless otherwise noted. OPA2681U, N TYP PARAMETER AC PERFORMANCE (Figure 2) Small Signal Bandwidth (VO = 0.5Vp-p) Bandwidth for 0.1dB Gain Flatness Peaking at a Gain of +1 Large Signal Bandwidth Slew Rate Rise/Fall Time Settling Time to 0.02% 0.1% Harmonic Distortion 2nd Harmonic 3rd Harmonic Input Voltage Noise Non-Inverting Input Current Noise Inverting Input Current Noise DC PERFORMANCE(4) Open-Loop Transimpedance Gain (ZOL) Input Offset Voltage Average Offset Voltage Drift Non-Inverting Input Bias Current Average Non-Inverting Input Bias Current Drift Inverting Input Bias Current Average Inverting Input Bias Current Drift INPUT Least Positive Input Voltage(5) Most Positive Input Voltage(5) Common-Mode Rejection (CMR) Non-Inverting Input Impedance Minimum Inverting Input Resistance (RI ) Maximum Inverting Input Resistance (RI ) OUTPUT Most Positive Output Voltage Least Positive Output Voltage Current Output, Sourcing Current Output, Sinking Closed-Loop Output Impedance DISABLE (Disable Low) (SO-14 only) Power Down Supply Current (+VS) Disable Time Enable Time Off Isolation Output Capacitance in Disable Turn On Glitch Turn Off Glitch Enable Voltage Disable Voltage Control Pin Input Bias Current (DIS) POWER SUPPLY Specified Single Supply Operating Voltage Maximum Single Supply Operating Voltage Max Quiescent Current Min Quiescent Current Power Supply Rejection Ratio (–PSRR) TEMPERATURE RANGE Specification: U, N Thermal Resistance, θJA U SO-8 N SO-14 GUARANTEED +25°C(2) 0°C to 70°C(3) –40°C to +85°C(3) 180 140 110 50 2 45 4 45 700 680 570 CONDITIONS +25°C G = +1, RF = 649Ω G = +2, RF = 499Ω G = +5, RF = 360Ω G = +10, RF = 200Ω G = +2, VO < 0.5Vp-p RF = 649Ω, VO < 0.5Vp-p G = +2, VO = 2Vp-p G = +2, 2V Step G = +2, VO = 0.5V Step G = +2, VO = 2V Step G = +2, VO = 2V Step G = +2, VO = 2V Step G = +2, f = 5MHz, VO = 2Vp-p RL = 100Ω to VS /2 RL ≥ 500Ω to VS /2 RL = 100Ω to VS /2 RL ≥ 500Ω to VS /2 f > 1MHz f > 1MHz f > 1MHz 250 225 180 165 100 0.4 200 830 1.5 2.0 14 9 –70 –72 –72 –73 2.2 12 15 –68 –70 –65 –68 3 14 18 –67 –70 –65 –67 3.4 14 18 VO = VS /2, RL = 100Ω to VS /2 VCM = 2.5V VCM = 2.5V VCM = 2.5V VCM = 2.5V VCM = 2.5V VCM = 2.5V 100 ±1 ±5 60 +40 +65 ±5 ±20 Open-Loop Open-Loop 1.5 3.5 51 100 || 2 45 45 No Load RL = 100Ω, 2.5V No Load RL = 100Ω, 2.5V VO = VS /2 VO = VS /2 G = +2, f = 100kHz 4 3.9 1 1.1 150 –110 0.03 VDIS = 0, Both Channels -500 100 25 65 4 ±50 ±20 3.3 1.8 100 VCM = 2.5V G = +2, 5MHz G = +2, RL = 150Ω, VIN = VS /2 G = +2, RL = 150Ω, VIN = VS /2 VDIS = 0, Each Channel MIN/ TEST MAX LEVEL(1) MHz MHz MHz MHz MHz dB MHz V/µs ns ns ns ns typ min typ typ min max min min typ typ typ typ C B C C B B B B C C C C –63 –68 –62 –67 3.6 15 19 dBc dBc dBc dBc nV/√Hz pA/√Hz pA/√Hz max max max max max max max B B B B B B B 53 ±6.0 +15 +75 –300 ±25 –125 51 ±7 +20 +95 –350 ±35 –175 kΩ mV µV/°C µA nA/°C µA nA /°C min max max max max max max A A B A B A B 1.6 3.4 45 1.7 3.3 44 1.8 3.2 44 32 65 30 67 29 74 V V dB kΩ || pF Ω Ω max min min typ min max A A A C A A 3.8 3.7 1.2 1.3 110 –75 3.7 3.6 1.3 1.4 110 –70 3.5 3.4 1.5 1.6 60 –50 V V V V mA mA Ω min min max max min min typ A A A A A A C µA ns ns dB pF mV mV V V µA typ typ typ typ typ typ typ min max typ C C C C C C C A A C V V mA mA dB typ max max min typ C A A A C –40 to +85 °C typ C 125 100 °C/W °C/W typ typ C C 3.5 1.7 3.6 1.6 3.7 1.5 12 10.6 8.2 12 10.8 8.0 12 10.8 8.0 5 VS = +5V VS = +5V Input Referred UNITS 9.6 9.6 48 NOTES: (1) Test Levels: (A) 100% tested at 25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (2) Junction temperature = ambient for 25°C guaranteed specifications. (3) Junction temperature = ambient at low temperature limit: junction temperature = ambient +23°C at high temperature limit for over temperature guaranteed specifications. (4) Current is considered positive out of node. VCM is the input common-mode voltage. (5) Tested < 3dB below minimum specified CMR at ±CMIR limits. ® 3 OPA2681 PIN CONFIGURATIONS ABSOLUTE MAXIMUM RATINGS Power Supply .............................................................................. ±6.5VDC Internal Power Dissipation(1) ............................ See Thermal Information Differential Input Voltage .................................................................. ±1.2V Input Voltage Range ............................................................................ ±VS Storage Temperature Range: U, N ................................ –40°C to +125°C Lead Temperature (soldering, 10s) .............................................. +300°C Junction Temperature (TJ ) ........................................................... +175°C Top View NOTE:: (1) Packages must be derated based on specified θJA. Maximum TJ must be observed. SO-8 Out A 1 8 +VS –In A 2 7 Out B +In A 3 6 –In B –VS 4 5 +In B SO-14 ELECTROSTATIC DISCHARGE SENSITIVITY Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr-Brown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. –In A 1 14 Out A +In A 2 13 NC DIS A 3 12 NC –VS 4 11 +VS DIS B 5 10 NC +In B 6 9 NC –In B 7 8 Out B PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER(1) OPA2681U SO-8 Surface Mount 182 " OPA2681N " SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER(2) TRANSPORT MEDIA –40°C to +85°C OPA2681U OPA2681U Rails Tape and Reel " " " " OPA2681U/2K5 SO-14 Surface Mount 235 –40°C to –85°C OPA2681N OPA2681N Rails " " " " OPA2681N/2K5 Tape and Reel NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are available only as Tape and Reel in the quantity indicated after the slash (e.g. /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of the OPA2681U/2K5 will get a single 2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of the Burr-Brown IC Data Book. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® OPA2681 4 TYPICAL PERFORMANCE CURVES: VS = ±5V G = +2, RF = 402Ω, RL = 100Ω, unless otherwise noted (see Figure 1). SMALL-SIGNAL FREQUENCY RESPONSE LARGE-SIGNAL FREQUENCY RESPONSE 2 8 G = +1, RF = 453Ω 0 6 –1 5 –2 –3 –4 G = +5, RF = 261Ω –5 –6 G = +2, RL = 100Ω 7 G = +2, RF = 402Ω Gain (1dB/div) Normalized Gain (1dB/div) 1 2Vp-p 4 3 2 4Vp-p 7Vp-p 0 G = +10, RF = 180Ω –7 –1 –8 –2 0 125MHz 250MHz 0 Frequency (25MHz/div) +4 G = +2 VO = 5Vp-p Output Voltage (1V/div) +3 100 0 –100 –200 +2 +1 0 –1 –2 –3 –300 –4 –400 Time (5ns/div) Time (5ns/div) LARGE-SIGNAL DISABLE/ENABLE RESPONSE CHANNEL-TO-CHANNEL CROSSTALK 4.0 4.0 VDIS 2.0 2.0 0 0 Output Voltage 2.0 1.6 1.2 (SO-14 only) 0.8 G = +2 VIN = +1V 0 –10 –20 Crosstalk (10dB/div) 6.0 VDIS (2V/div) 5.0 Output Voltage (400mV/div) Output Voltage (100mV/div) G = +2 VO = 0.5Vp-p 200 0 250MHz LARGE-SIGNAL PULSE RESPONSE SMALL-SIGNAL PULSE RESPONSE 300 125MHz Frequency (25MHz/div) 400 0.4 1Vp-p 1 –30 –40 –50 –60 –70 –80 –90 –100 Time (50ns/div) 1 10 100 Frequency (MHz) ® 5 OPA2681 TYPICAL PERFORMANCE CURVES: VS = ±5V (CONT) G = +2, RF = 402Ω, RL = 100Ω, unless otherwise noted (see Figure 1). 5MHz 2ND HARMONIC DISTORTION vs OUTPUT VOLTAGE 5MHz 3RD HARMONIC DISTORTION vs OUTPUT VOLTAGE –60 –65 3rd Harmonic Distortion (dBc) 2nd Harmonic Distortion (dBc) –60 RL = 100Ω –70 RL = 200Ω –75 –80 RL = 500Ω –85 –90 1 RL = 100Ω –75 RL = 200Ω –80 –85 10 RL = 500Ω 0.1 1 10 Output Voltage Swing (Vp-p) Output Voltage Swing (Vp-p) 10MHz 2ND HARMONIC DISTORTION vs OUTPUT VOLTAGE 10MHz 3RD HARMONIC DISTORTION vs OUTPUT VOLTAGE –60 –60 RL = 100Ω –65 3rd Harmonic Distortion (dBc) 2nd Harmonic Distortion (dBc) –70 –90 0.1 RL = 200Ω –70 –75 RL = 500Ω –80 –85 –90 –65 RL = 100Ω –70 RL = 200Ω –75 –80 RL = 500Ω –85 –90 0.1 1 10 0.1 1 10 Output Voltage Swing (Vp-p) Output Voltage Swing (Vp-p) 20MHz 2ND HARMONIC DISTORTION vs OUTPUT VOLTAGE 20MHz 3RD HARMONIC DISTORTION vs OUTPUT VOLTAGE –50 –50 RL = 100Ω –55 3rd Harmonic Distortion (dBc) 2nd Harmonic Distortion (dBc) –65 RL = 200Ω –60 –65 RL = 500Ω –70 –75 –55 RL = 100Ω –60 –65 RL = 200Ω –70 –75 RL = 500Ω –80 –80 0.1 1 10 0.1 Output Voltage Swing (Vp-p) ® OPA2681 1 Output Voltage Swing (Vp-p) 6 10 TYPICAL PERFORMANCE CURVES: VS = ±5V (CONT) G = +2, RF = 402Ω, RL = 100Ω, unless otherwise noted (see Figure 1). 2ND HARMONIC DISTORTION vs FREQUENCY 3RD HARMONIC DISTORTION vs FREQUENCY –40 VO = 2Vp-p RL = 100Ω –50 G = +10, RF = 180Ω 3rd Harmonic Distortion (dBc) 2nd Harmonic Distortion (dBc) –40 G = +5, RF = 261Ω –60 –70 G = +2, RF = 402Ω –80 –90 –50 G = +10, RF = 180Ω –60 G = +5, RF = 261Ω –70 –80 G = +2, RF = 402Ω –90 0.1 1 10 20 0.1 1 Frequency (MHz) INPUT VOLTAGE AND CURRENT NOISE DENSITY TWO-TONE, 3RD-ORDER INTERMODULATION SPURIOUS 20 3rd-Order Spurious Level (dBc) –40 Inverting Input Current Noise 15.1pA/√Hz 10 Non-Inverting Input Current Noise 12.2pA/√Hz 2.2nV/√Hz Voltage Noise dBc = dB below carriers –45 –50 50MHz –55 –60 –65 –70 20MHz –75 –80 10MHz –85 Load Power at Matched 50Ω Load –90 1 100 1k 10k 100k 1M 10M –8 –6 –4 Frequency (Hz) –2 0 2 4 6 8 10 Single-Tone Load Power (dBm) RECOMMENDED RS vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD 60 Gain to Capacitive Load (3dB/div) 15 50 40 RS (Ω) 10 Frequency (MHz) 100 Current Noise (pA/√Hz) Voltage Noise (nV/√Hz) VO = 2Vp-p RL = 100Ω 30 20 10 12 CL = 10pF 9 CL = 22pF 6 3 CL = 47pF 0 –3 VIN RS VO –6 402Ω –9 CL 1kΩ 402Ω –12 1kΩ is optional. 0 –15 1 10 100 0 Capacitive Load (pF) CL = 100pF 150MHz 300MHz Frequency (30MHz/div) ® 7 OPA2681 TYPICAL PERFORMANCE CURVES: VS = ±5V (CONT) G = +2, RF = 402Ω, RL = 100Ω, unless otherwise noted (see Figure 1). OPEN-LOOP TRANSIMPEDANCE GAIN/PHASE 120 –PSR 55 CMR 50 45 40 35 30 25 100 –40 | ZOL| 80 –80 60 –120 40 –160 20 –200 0 20 102 103 104 105 106 107 104 108 105 106 TYPICAL DC DRIFT OVER TEMPERATURE COMPOSITE VIDEO dG/dP 5 0.05 Positive Video Negative Sync Input Offset Voltage (mV) dP dG/dP (%/°) 50 4 0.04 0.03 0.02 0.01 dG 1 30 2 20 Inverting 1 0 2 3 0 –1 –10 –2 –20 –3 –30 –4 –40 –50 –40 4 –20 0 Supply Current (2.5mA/div) VO (Volts) 1-Channel Only 25Ω Load Line 50Ω Load Line –1 100Ω Load Line –3 –4 1W Internal Power Limit Output Current Limit 60 80 100 120 140 SUPPLY AND OUTPUT CURRENT vs TEMPERATURE 1W Internal Power Limit –2 40 10 Output Current Limited 0 20 Ambient Temperature (°C) OUTPUT VOLTAGE AND CURRENT LIMITATIONS 5 1 10 VIO Number of 150Ω Loads 2 40 Non-Inverting Input Bias Current 3 –5 0 3 –240 109 108 Frequency (Hz) Frequency (Hz) 4 107 –5 200 Sourcing Output Current Sinking Output Current 7.5 150 5 100 Quiescent Supply Current 2.5 50 0 –300 –200 –100 0 100 200 300 0 –40 IO (mA) –20 0 20 40 60 80 Ambient Temperature (°C) ® OPA2681 Input Bias Currents (µA) 60 0 ∠ ZOL 8 100 120 140 Output Current (mA) +PSR Transimpedance Gain (20dBΩ/div) Rejection Ratio (dB) 65 Transimpedance Phase (40°/div) CMR AND PSR vs FREQUENCY 70 TYPICAL PERFORMANCE CURVES: VS = +5V G = +2, RF = 499Ω, RL = 100Ω to +2.5V, unless otherwise noted (see Figure 2). LARGE-SIGNAL FREQUENCY RESPONSE SMALL-SIGNAL FREQUENCY RESPONSE 8 2 G = +2, RF = 499Ω 0 –1 G = +5, RF = 360Ω –4 –5 VO = 1Vp-p 5 4 VO = 2Vp-p 3 2 1 G = +10, RF = 200Ω –6 0 –1 –7 –2 –8 0 125 0 250 125 LARGE-SIGNAL PULSE RESPONSE SMALL-SIGNAL PULSE RESPONSE 4.5 2.10 G = +2 VO = 0.5Vp-p 2.8 G = +2 VO = 2Vp-p 4.1 Output Voltage (400mV/div) Output Voltage (100mV/div) 2.9 250 Frequency (25MHz/div) Frequency (25MHz/div) 2.7 2.6 2.5 2.4 2.3 2.2 3.7 3.3 2.9 2.5 2.1 1.7 1.3 0.9 2.1 0.5 2.0 Time (5ns/div) Time (5ns/div) RECOMMENDED RS vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD 70 Gain to Capacitive Load (3dB/div) 15 60 50 RS (Ω) VO = 0.5Vp-p 6 G = +1, RF = 649Ω –2 –3 G = +2 RL = 100Ω to 2.5V 7 Gain (1dB/div) Normalized Gain (1dB/div) 1 40 30 20 10 0 CL = 10pF CL = 47pF 12 9 CL = 22pF 6 +5V 3 0 0.1µF 806Ω VI –3 0.1µF 57.6Ω VO 806Ω RS C L –6 1kΩ 499Ω –9 499Ω –12 CL = 100pF 0.1µF –15 1 10 100 0 Capacitive Load (pF) 100MHz 200MHz Frequency (20MHz/div) ® 9 OPA2681 TYPICAL PERFORMANCE CURVES: VS = +5V (CONT) G = +2, RF = 499Ω, RL = 100Ω to +2.5V, unless otherwise noted (see Figure 2). 2ND HARMONIC DISTORTION vs FREQUENCY 3RD HARMONIC DISTORTION vs FREQUENCY –40 VO = 2Vp-p RL = 100Ω to 2.5V 3rd Harmonic Distortion (dBc) 2nd Harmonic Distortion (dBc) –40 G = +10, RF = 200Ω –50 G = +5, RF = 360Ω –60 G = +2, RF = 499Ω –70 VO = 2Vp-p RL = 100Ω to 2.5V –50 G = +10, RF = 200Ω G = +5, RF = 360Ω –60 –70 G = +2, RF = 499Ω –80 –80 0.1 1 10 20 0.1 1 Frequency (MHz) –50 VO = 2Vp-p G = +2 3rd Harmonic Distortion (dBc) 2nd Harmonic Distortion (dBc) 20 3RD HARMONIC DISTORTION vs FREQUENCY 2ND HARMONIC DISTORTION vs FREQUENCY –50 RL = 100Ω –60 RL = 200Ω –70 RL = 500Ω –80 VO = 2Vp-p G = +2 –60 RL = 100Ω –70 RL = 200Ω –80 RL = 500Ω Loads to 2.5V Loads to 2.5V –90 –90 0.1 1 10 0.1 20 1 TWO-TONE, 3RD ORDER SPURIOUS LEVEL 20 CLOSED-LOOP OUTPUT IMPEDANCE –45 10 dBc = dB Below Carrier –50 10 Frequency (MHz) Frequency (MHz) +5 50MHz –55 Output Impedance (Ω) 3rd Order Spurious (dBc) 10 Frequency (MHz) –60 –65 20MHz –70 10MHz –75 50Ω 1 1/2 OPA2681 ZO 402Ω 402Ω 0.1 –5 –80 Load Power at Matched 50Ω Load –85 0.01 –14 –12 –10 –8 –6 –4 –2 0 2 10k Single-Tone Load Power (dBm) 1M Frequency (Hz) ® OPA2681 100k 10 10M 100M APPLICATIONS INFORMATION pins. In practical PC board layouts, this optional added capacitor will typically improve the 2nd harmonic distortion performance by 3dB to 6dB. WIDEBAND CURRENT FEEDBACK OPERATION The OPA2681 gives the exceptional AC performance of a wideband current feedback op amp with a highly linear, high power output stage. Requiring only 6mA/ch. quiescent current, the OPA2681 will swing to within 1V of either supply rail and deliver in excess of 135mA guaranteed at room temperature. This low output headroom requirement, along with supply voltage independent biasing, gives remarkable single (+5V) supply operation. The OPA2681 will deliver greater than 200MHz bandwidth driving a 2Vp-p output into 100Ω on a single +5V supply. Previous boosted output stage amplifiers have typically suffered from very poor crossover distortion as the output current goes through zero. The OPA2681 achieves a comparable power gain with much better linearity. The primary advantage of a current feedback op amp over a voltage feedback op amp is that AC performance (bandwidth and distortion) is relatively independent of signal gain. For similar AC performance with improved DC accuracy, consider the high slew rate, unity gain stable, voltage feedback OPA2680. Figure 2 shows the AC coupled, gain of +2, single supply circuit configuration used as the basis of the +5V Specifications and Typical Performance Curves. Though not a “railto-rail” design, the OPA2681 requires minimal input and output voltage headroom compared to other very wideband current feedback op amps. It will deliver a 3Vp-p output swing on a single +5V supply with greater than 150MHz bandwidth. The key requirement of broadband single supply operation is to maintain input and output signal swings within the usable voltage ranges at both the input and the output. The circuit of Figure 2 establishes an input midpoint bias using a simple resistive divider from the +5V supply (two 806Ω resistors). The input signal is then AC coupled into this midpoint voltage bias. The input voltage can swing to within 1.5V of either supply pin, giving a 2Vp-p input signal range centered between the supply pins. The input impedance matching resistor (57.6Ω) used for testing is adjusted to give a 50Ω input match when the parallel combination of the biasing divider network is included. The gain resistor (RG) is AC coupled, giving the circuit a DC gain of +1—which puts the input DC bias voltage (2.5V) on the output as well. The feedback resistor value has been adjusted from the bipolar supply condition to re-optimize for a flat frequency response in +5V, gain of +2, operation (see Setting Resistor Values to Optimize Bandwidth). Again, on a single +5V supply, the output voltage can swing to within 1V of either supply pin while delivering more than 75mA output current. A demanding 100Ω load to a midpoint bias is used in this characterization circuit. The new output stage used in the OPA2681 can deliver large bipolar output currents into this midpoint load with minimal crossover distortion, as shown by the +5V supply, 3rd harmonic distortion plots. Figure 1 shows the DC coupled, gain of +2, dual power supply circuit configuration used as the basis of the ±5V Specifications and Typical Performance Curves. For test purposes, the input impedance is set to 50Ω with a resistor to ground and the output impedance is set to 50Ω with a series output resistor. Voltage swings reported in the specifications are taken directly at the input and output pins while load powers (dBm) are defined at a matched 50Ω load. For the circuit of Figure 1, the total effective load will be 100Ω || 804Ω = 89Ω. The disable control line (DIS) is typically left open (SO-14 only) to guarantee normal amplifier operation. One optional component is included in Figure 1. In addition to the usual power supply de-coupling capacitors to ground, a 0.1µF capacitor is included between the two power supply 0.1µF +5V +VS +5V +VS 6.8µF + + 0.1µF 50Ω Source DIS VI 50Ω VO 1/2 OPA2681 0.1µF 6.8µF 806Ω 50Ω 50Ω Load 0.1µF VI 57.6Ω DIS 806Ω 1/2 OPA2681 VO 100Ω VS/2 RF 499Ω RF 402Ω RG 402Ω RG 499Ω + 6.8µF 0.1µF 0.1µF –VS –5V FIGURE 2. AC-Coupled, G = +2, Single Supply Specification and Test Circuit. FIGURE 1. DC-Coupled, G = +2, Bipolar Supply, Specification and Test Circuit. ® 11 OPA2681 WIDEBAND VIDEO MULTIPLEXING One common application for video speed amplifiers which include a disable pin is to wire multiple amplifier outputs together, then select which one of several possible video inputs to source onto a single line. This simple “Wired-OR Video Multiplexer” can be easily implemented using the OPA2681N as shown in Figure 4. SINGLE SUPPLY DIFFERENTIAL A/D CONVERTER DRIVER Figure 3 shows a gain of +10 Diff. In/Diff. Out single supply ADC driver. Using a dual amplifier like the OPA2681 helps reducing the necessary board space, as it also reduces the amount of required supply bypassing components. From a signal point of view, dual amplifiers provide excellent performance matching, e.g., gain and phase matching. The differential ADC driver circuit shown in Figure 3 takes advantage of this fact. A transformer converts the singleended input signal into a low level differential signal which is applied to the high impedance non-inverting inputs of each of the two amplifiers in the OPA2681. Resistor RG between the inverting inputs controls the ac-gain of this circuit according to equation G = 1 + 2RF/RG. With the resistor values shown the AC-gain is set to 10. Adding a capacitor (0.1µF) in series with RG blocks the dc-path giving a DC gain of +1 for the common-mode voltage. This allows, in a very simple way, to apply the required DC bias voltage of +2.5V to the inputs of the amplifiers, which will also appear at their outputs. Like the OPA2681 the A/D converter ADS823 operates on a single +5V supply. Its internal common-mode voltage is typically +2.5V which equals the required bias voltage for the OPA2681. Connecting two resistors between the top-reference (REFT = +3.5V) and bottom reference (REFB = +1.5V) develop a +2.5V voltage level at their midpoint. Applying that to the center tap of the transformer biases amplifiers appropriately. Sufficient bypassing at the center tap must be provided to keep this point at a solid AC ground. Resistors RS isolate the op amp output from the capacitive input of the converter, as well as forming a first order low-pass filter with capacitor CI to attenuate some of the wideband noise. This interface will provide > 150MHz full scale input bandwidth to the ADS823. Typically, channel switching is performed either on sync or retrace time in the video signal. The two inputs are approximately equal at this time. The “make-before-break” disable characteristic of the OPA2681 ensures that there is always one amplifier controlling the line when using a wired-OR circuit like that shown in Figure 4. Since both inputs may be on for a short period during the transition between channels, the outputs are combined through the output impedance matching resistors (82.5Ω in this case). When one channel is disabled, its feedback network forms part of the output impedance and slightly attenuates the signal in getting out onto the cable. The gain and output matching resistor have been slightly increased to get a signal gain of +1 at the matched load and provide a 75Ω output impedance to the cable. The video multiplexer connection (Figure 4) also insures that the maximum differential voltage across the inputs of the unselected channel do not exceed the rated ±1.2V maximum for standard video signal levels. The section on Disable Operation shows the turn-on and turn-off switching glitches using a grounded input for a single channel is typically less than ±50mV. Where two outputs are switched (as shown in Figure 4), the output line is always under the control of one amplifier or the other due to the “make-before-break” disable timing. In this case, the switching glitches for two 0V inputs drop to < 20mV. +5V +5V 1/2 OPA2681 1:1 +VS RS 24.9Ω IN C1 10pF VI RF 200Ω 50Ω 0.1µF + 4.7µF ADS823 10-Bit 60MSPS RG 44Ω 0.1µF RF 200Ω RS 24.9Ω C1 10pF 1/2 OPA2681 IN REFT (+3.5V) REFB (+1.5V) 2kΩ 2 RF G=1+ = 10 RG VBIAS = +2.5V 2kΩ 0.1µF FIGURE 3. Wideband, Single Supply, Differential ADC Driver. ® OPA2681 12 0.1µF GND +5V 2kΩ VDIS +5V Power supply de-coupling not shown Video 1 DIS 1/2 OPA2681N 75Ω 340Ω 82.5Ω –5V 402Ω 75Ω Cable 340Ω RG-59 402Ω +5V 82.5Ω 1/2 OPA2681N Video 2 DIS 75Ω –5V 2kΩ FIGURE 4. Two-Channel Video Multiplexer. +5V Power supply de-coupling not shown 0.1µF 5kΩ 100pF VI 51Ω 5kΩ 1/2 OPA2681 32.3Ω 105Ω 150pF 1/2 OPA2681 4VI 375Ω 600Ω 125Ω 20MHz, 2nd Order Butterworth Low Pass 0.1µF FIGURE 5. Buffered, Single Supply Active Filter. HIGH SPEED ACTIVE FILTERS Wideband current feedback op amps make ideal elements for implementing high speed active filters where the amplifier is used as fixed gain block inside a passive RC circuit network. Their relatively constant bandwidth vs gain, provides low interaction between the actual filter poles and the required gain for the amplifier. Figure 5 shows an example single-supply buffered filter application. In this case, one of the OPA2681 channels is used to set-up the DC operating point and provide impedance isolation from the signal source into the 2nd stage filter. That stage is set up to implement a 20MHz maximally flat Butterworth frequency response and provide an AC gain of +4. The 51Ω input matching resistor is optional in this case. The input signal is AC coupled to the 2.5V DC reference voltage developed through the resistor divider from the +5V power supply. This first stage acts as a gain of +1 voltage buffer for the signal where the 600Ω feedback resistor is required for ® 13 OPA2681 ential to single-ended conversion is performed by voltage feedback amplifier OPA680 configured as a standard difference amplifier. To maintain good distortion performance for the OPA2681, the loading at each amplifier output has been matched by setting R3 + R4 = R1, rather than using the same resistor values within the difference amplifier. stability. This first stage easily drives the low input resistors required at the input of this high frequency filter. The 2nd stage is set for a DC gain of +1—carrying the 2.5V operating point through to the output pin, and an AC gain of +4. The feedback resistor has been adjusted to optimize bandwidth for the amplifier itself. As the single-supply frequency response plots show, the OPA2681 in this configuration will give > 200MHz small signal bandwidth. The capacitor values were chosen as low as possible but adequate to swamp out the parasitic input capacitance of the amplifier. The resistor values were slightly adjusted to give the desired filter frequency response while accounting for the approximate 1ns propogation delay through each channel of the OPA2681. +5V VIN R1 499Ω R2 499Ω +5V RF 261Ω RG 130Ω HIGH POWER TWISTED PAIR DRIVER A very demanding application for a high-speed amplifier is to drive a low load impedance while maintaining a high output voltage swing to high frequencies. Using the dual current feedback op amp OPA2681, a 15Vp-p output signal swing into a twisted-pair line with a typical impedance of 100Ω can be realized. Configured as shown in the front page the two amplifiers of the OPA2681 drive the output transformer in a push-pull configuration thus doubling the peak-to-peak signal swing at each op amp’s output to 15Vp-p. The transformer has a turns ratio of 2. In order to provide a matched source, this requires a 25Ω source impedance (RS), for the primary side, given the transformer equation n2 = RL/RS. Dividing this impedance equally between the outputs requires a series termination matching resistor at each output of 12.4Ω. Taking the total resistive load of 25Ω (for the differential output signal) and drawing a load line on the Output Voltage and Current Limitations plot it can be seen a 1.5V headroom is required at the positive peak current of 150mA, while a 2.5V headroom is required at the negative peak current of 150mA. The full 7.5Vp-p out of each amplifier is achieved on a single +12V supply by shifting the DC operating point positive 0.5V to 6.5V—as shown on the front page ADSL upstream driver. VO OPA680 RF 261Ω –5V 1/2 OPA2681 R3 249Ω VO (VIN – VIN) VIN =5 R4 249Ω –5V FIGURE 6. Wideband, 3-Op Amp Instrumentation Diff. Amp. DESIGN-IN TOOLS DEMONSTRATION BOARDS Several PC boards are available to assist in the initial evaluation of circuit performance using the OPA2681 in its 2 package styles. Both of these are available free as an unpopulated PC board delivered with descriptive documentation. The summary information for these boards is shown in the table below. Line driver applications usually have a high demand for transmitting the signal with low distortion. Current-feedback amplifiers like the OPA2681 are ideal for delivering low distortion performance to higher gains. The example shown is set for a differential gain of 7.5. This circuit can deliver the maximum 15Vp-p signal with over 60 MHz bandwidth. PRODUCT PACKAGE DEMO BOARD NUMBER ORDERING NUMBER OPA2681U OPA2681N 8-Pin SO-8 14-Pin SO-14 DEM-OPA268xU DEM-OPA268xN MKT-352 MKT-353 Contact the Burr-Brown applications support line to request any of these boards. MACROMODELS AND APPLICATIONS SUPPORT Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for Video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model for the OPA2681 is available through either the Burr-Brown Internet web page (http://www.burrbrown.com) or as one model on a disk from the Burr-Brown Applications department (1-800-548-6132). The Application department is also available for design assistance at this number. These models do a good job of predicting small signal AC and transient performance under a wide variety of WIDEBAND (160MHZ) INSTRUMENTATION AMPLIFIER As discussed previously, the current feedback topology of the OPA2681 provides a nearly constant bandwidth as signal gain is increased. The three op amp wideband instrumentation amplifier depicted in Figure 6 takes advantage of this, achieving a differential bandwidth of 160MHz. The signal is applied to the high-impedance non-inverting inputs of the OPA2681. The differential gain is set by (1 + 2RF / RG) — which equal to 5 using the values shown in Figure 6. The feedback resistors, RF, are optimized at this particular gain. Gain adjustments can be made by adjusting RG. The differ- ® OPA2681 1/2 OPA2681 14 A current feedback op amp senses an error current in the inverting node (as opposed to a differential input error voltage for a voltage feedback op amp) and passes this on to the output through an internal frequency dependent transimpedance gain. The Typical Performance Curves show this open loop transimpedance response. This is analogous to the open loop voltage gain curve for a voltage feedback op amp. Developing the transfer function for the circuit of Figure 7 gives Equation 1: operating conditions. They do not do as well in predicting the harmonic distortion or dG/dP characteristics. These models do not attempt to distinguish between the package types in their small signal AC performance, nor do they attempt to simulate channel-to-channel coupling. OPERATING SUGGESTIONS SETTING RESISTOR VALUES TO OPTIMIZE BANDWIDTH A current feedback op amp like the OPA2681 can hold an almost constant bandwidth over signal gain settings with the proper adjustment of the external resistor values. This is shown in the Typical Performance Curves; the small signal bandwidth decreases only slightly with increasing gain. Those curves also show that the feedback resistor has been changed for each gain setting. The resistor “values” on the inverting side of the circuit for a current feedback op amp can be treated as frequency response compensation elements while their “ratios” set the signal gain. Figure 7 shows the small signal frequency response analysis circuit for the OPA2681. VO = VI 1+ Eq. 1 R α 1 + F RG α NG = R F + R I NG R R F + R I 1 + F 1 + Z (S) RG Z (S) This is written in a loop gain analysis format where the errors arising from a non-infinite open loop gain are shown in the denominator. If Z(s) were infinite over all frequencies, the denominator of Equation 1 would reduce to 1 and the ideal desired signal gain shown in the numerator would be achieved. The fraction in the denominator of Equation 1 determines the frequency response. Equation 2 shows this as the loop gain equation: The key elements of this current feedback op amp model are: VI Z (S) α R F + R I NG VO RI IERR RF NG ≡ 1 + R G = Loop Gain Eq. 2 If 20 x log (RF + NG x RI) were drawn on top of the open loop transimpedance plot, the difference between the two would be the loop gain at a given frequency. Eventually, Z(s) rolls off to equal the denominator of Equation 2 at which point the loop gain has reduced to 1 (and the curves have intersected). This point of equality is where the amplifier’s closed loop frequency response given by Equation 1 will start to roll off, and is exactly analogous to the frequency at which the noise gain equals the open loop voltage gain for a voltage feedback op amp. The difference here is that the total impedance in the denominator of Equation 2 may be controlled somewhat separately from the desired signal gain (or NG). Z(S) IERR RF RG FIGURE 7. Current Feedback Transfer Function Analysis Circuit. α → Buffer gain from the non-inverting input to the inverting input RI → Buffer output impedance The OPA2681 is internally compensated to give a maximally flat frequency response for RF = 402Ω at NG = 2 on ±5V supplies. Evaluating the denominator of Equation 2 (which is the feedback transimpedance) gives an optimal target of 492Ω. As the signal gain changes, the contribution of the NG x RI term in the feedback transimpedance will change, but the total can be held constant by adjusting RF. Equation 3 gives an approximate equation for optimum RF over signal gain: iERR → Feedback error current signal Z(s) → Frequency dependent open loop transimpedance gain from iERR to VO The buffer gain is typically very close to 1.00 and is normally neglected from signal gain considerations. It will, however set the CMRR for a single op amp differential amplifier configuration. For a buffer gain α < 1.0, the CMRR = -20 x log (1– α) dB. RI, the buffer output impedance, is a critical portion of the bandwidth control equation. The OPA2681 is typically about 45Ω. R F = 492Ω – NG R I Eq. 3 As the desired signal gain increases, this equation will eventually predict a negative RF. A somewhat subjective limit to this adjustment can also be set by holding RG to a ® 15 OPA2681 minimum value of 20Ω. Lower values will load both the buffer stage at the input and the output stage if RF gets too low—actually decreasing the bandwidth. Figure 8 shows the recommended RF vs NG for both ±5V and a single +5V operation. The values for RF vs Gain shown here are approximately equal to the values used to generate the Typical Performance Curves. They differ in that the optimized values used in the Typical Performance Curves are also correcting for board parasitics not considered in the simplified analysis leading to Equation 3. The values shown in Figure 8 give a good starting point for design where bandwidth optimization is desired. the OPA2681. Figure 9 shows a typical inverting configuration where the I/O impedances and signal gain from Figure 1 are retained in an inverting circuit configuration. +5V Power supply de-coupling not shown 50Ω Load 1/2 OPA2681 50Ω Source VO 50Ω RF 365Ω RG 182Ω VI FEEDBACK RESISTOR vs NOISE GAIN RM 68.1Ω 600 Feedback Resistor (Ω) 500 –5V +5V 400 FIGURE 9. Inverting Gain of –2 with Impedance Matching. 300 In the inverting configuration, two key design considerations must be noted. The first is that the gain resistor (RG) becomes part of the signal channel input impedance. If input impedance matching is desired (which is beneficial whenever the signal is coupled through a cable, twisted pair, long PC board trace or other transmission line conductor), it is normally necessary to add an additional matching resistor to ground. RG by itself is normally not set to the required input impedance since its value, along with the desired gain, will determine an RF which may be non-optimal from a frequency response standpoint. The total input impedance for the source becomes the parallel combination of RG and RM. ±5V 200 100 0 0 5 10 15 20 Noise Gain FIGURE 8. Recommended Feedback Resistor vs Noise Gain. The total impedance going into the inverting input may be used to adjust the closed loop signal bandwidth. Inserting a series resistor between the inverting input and the summing junction will increase the feedback impedance (denominator of Equation 2), decreasing the bandwidth. The internal buffer output impedance for the OPA2681 is slightly influenced by the source impedance looking out of the noninverting input terminal. High source resistors will have the effect of increasing RI, decreasing the bandwidth. For those single supply applications which develop a midpoint bias at the non-inverting input through high valued resistors, the decoupling capacitor is essential for power supply ripple rejection, non-inverting input noise current shunting, and to minimize the high frequency value for RI in Figure 7. The second major consideration, touched on in the previous paragraph, is that the signal source impedance becomes part of the noise gain equation and will have slight effect on the bandwidth through Equation 1. The values shown in Figure 9 have accounted for this by slightly decreasing RF (from Figure 1) to re-optimize the bandwidth for the noise gain of Figure 9 (NG = 2.74) In the example of Figure 9, the RM value combines in parallel with the external 50Ω source impedance, yielding an effective driving impedance of 50Ω || 68Ω = 28.8Ω. This impedance is added in series with RG for calculating the noise gain—which gives NG = 2.74. This value, along with the RF of Figure 8 and the inverting input impedance of 45Ω, are inserted into Equation 3 to get a feedback transimpedance nearly equal to the 492Ω optimum value. INVERTING AMPLIFIER OPERATION Since the OPA2681 is a general purpose, wideband current feedback op amp, most of the familiar op amp application circuits are available to the designer. Those dual op amp applications that require considerable flexibility in the feedback element (e.g. integrators, transimpedance, some filters) should consider the unity gain stable voltage feedback OPA2680, since the feedback resistor is the compensation element for a current feedback op amp. Wideband inverting operation (and especially summing) is particularly suited to Note that the non-inverting input in this bipolar supply inverting application is connected directly to ground. It is often suggested that an additional resistor be connected to ground on the non-inverting input to achieve bias current error cancellation at the output. The input bias currents for a current feedback op amp are not generally matched in either magnitude or polarity. Connecting a resistor to ground on the non-inverting input of the OPA2681 in the circuit of ® OPA2681 16 the 0.1uF power supply decoupling capacitors after these supply current limiting resistors directly on the supply pins. Figure 9 will actually provide additional gain for that input’s bias and noise currents, but will not decrease the output DC error since the input bias currents are not matched. DRIVING CAPACITIVE LOADS One of the most demanding and yet very common load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an A/D converter—including additional external capacitance which may be recommended to improve A/D linearity. A high speed, high open-loop gain amplifier like the OPA2681 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. When the amplifier’s open loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. OUTPUT CURRENT AND VOLTAGE The OPA2681 provides output voltage and current capabilities that are unsurpassed in a low cost dual monolithic op amp. Under no-load conditions at 25°C, the output voltage typically swings closer than 1V to either supply rail; the guaranteed swing limit is within 1.2V of either rail. Into a 15Ω load (the minimum tested load), it is guaranteed to deliver more than ±135mA. The specifications described above, though familiar in the industry, consider voltage and current limits separately. In many applications, it is the voltage x current, or V-I product, which is more relevant to circuit operation. Refer to the “Output Voltage and Current Limitations” plot in the Typical Performance Curves. The X and Y axes of this graph show the zero-voltage output current limit and the zerocurrent output voltage limit, respectively. The four quadrants give a more detailed view of the OPA2681’s output drive capabilities, noting that the graph is bounded by a “Safe Operating Area” of 1W maximum internal power dissipation (in this case for 1 channel only). Superimposing resistor load lines onto the plot shows that the OPA2681 can drive ±2.5V into 25Ω or ±3.5V into 50Ω without exceeding the output capabilities or the 1W dissipation limit. A 100Ω load line (the standard test circuit load) shows the full ±3.9V output swing capability, as shown in the Typical Specifications. The Typical Performance Curves show the recommended RS vs Capacitive Load and the resulting frequency response at the load. Parasitic capacitive loads greater than 2pF can begin to degrade the performance of the OPA2681. Long PC board traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. Always consider this effect carefully, and add the recommended series resistor as close as possible to the OPA2681 output pin (see Board Layout Guidelines). The minimum specified output voltage and current over temperature are set by worst-case simulations at the cold temperature extreme. Only at cold startup will the output current and voltage decrease to the numbers shown in the guaranteed tables. As the output transistors deliver power, their junction temperatures will increase, decreasing their VBE’s (increasing the available output voltage swing) and increasing their current gains (increasing the available output current). In steady state operation, the available output voltage and current will always be greater than that shown in the over-temperature specifications since the output stage junction temperatures will be higher than the minimum specified operating ambient. DISTORTION PERFORMANCE The OPA2681 provides good distortion performance into a 100Ω load on ±5V supplies. Relative to alternative solutions, it provides exceptional performance into lighter loads and/or operating on a single +5V supply. Generally, until the fundamental signal reaches very high frequency or power levels, the 2nd harmonic will dominate the distortion with a negligible 3rd harmonic component. Focusing then on the 2nd harmonic, increasing the load impedance improves distortion directly. Remember that the total load includes the feedback network— in the non-inverting configuration (Figure 1) this is the sum of RF + RG, while in the inverting configuration it is just RF. Also, providing an additional supply de-coupling capacitor (0.1µF) between the supply pins (for bipolar operation) improves the 2nd order distortion slightly (3 to 6dB). To maintain maximum output stage linearity, no output short circuit protection is provided. This will not normally be a problem since most applications include a series matching resistor at the output that will limit the internal power dissipation if the output side of this resistor is shorted to ground. However, shorting the output pin directly to the adjacent positive power supply pin (8 pin package) will, in most cases, destroy the amplifier. If additional short circuit protection is required, consider a small series resistor in the power supply leads. This will, under heavy output loads, reduce the available output voltage swing. A 5Ω series resistor in each power supply lead will limit the internal power dissipation to less than 1W for an output short circuit while decreasing the available output voltage swing only 0.5V for up to 100mA desired load currents. Always place In most op amps, increasing the output voltage swing increases harmonic distortion directly. The Typical Performance Curves show the 2nd harmonic increasing at a little less than the expected 2X rate while the 3rd harmonic increases at a little less than the expected 3X rate. Where the test power doubles, the difference between it and the 2nd ® 17 OPA2681 harmonic decreases less than the expected 6dB while the difference between it and the 3rd decreases by less than the expected 12dB. This also shows up in the 2-tone 3rd order intermodulation spurious (IM3) response curves. The 3rd order spurious levels are extremely low at low output power levels. The output stage continues to hold them low even as the fundamental power reaches very high levels. As the Typical Performance Curves show, the spurious intermodulation powers do not increase as predicted by a traditional intercept model. As the fundamental power level increases, the dynamic range does not decrease significantly. For 2 tones centered at 20MHz, with 10dBm/tone into a matched 50Ω load (i.e. 2Vp-p for each tone at the load, which requires 8Vp-p for the overall 2-tone envelope at the output pin), the Typical Performance Curves show 62dBc difference between the test tone power and the 3rd order intermodulation spurious levels. This exceptional performance improves further when operating at lower frequencies. Evaluating these two equations for the OPA2681 circuit and component values shown in Figure 1 will give a total output spot noise voltage of 8.4nV/√Hz and a total equivalent input spot noise voltage of 4.2nV/√Hz. This total input referred spot noise voltage is higher than the 2.2nV/√Hz specification for the op amp voltage noise alone. This reflects the noise added to the output by the inverting current noise times the feedback resistor. If the feedback resistor is reduced in high gain configurations (as suggested previously), the total input referred voltage noise given by Equation 5 will approach just the 2.2nV/√Hz of the op amp itself. For example, going to a gain of +10 using RF = 180Ω will give a total input referred noise of 2.4nV/√Hz . ENI NOISE PERFORMANCE Wideband current feedback op amps generally have a higher output noise than comparable voltage feedback op amps. The OPA2681 offers an excellent balance between voltage and current noise terms to achieve low output noise. The inverting current noise (15pA/√Hz) is significantly lower than earlier solutions while the input voltage noise (2.2nV/√Hz) is lower than most unity gain stable, wideband, voltage feedback op amps. This low input voltage noise was achieved at the price of higher non-inverting input current noise (12pA/√Hz). As long as the AC source impedance looking out of the non-inverting node is less than 100Ω, this current noise will not contribute significantly to the total output noise. The op amp input voltage noise and the two input current noise terms combine to give low output noise under a wide variety of operating conditions. Figure 10 shows the op amp noise analysis model with all the noise terms included. In this model, all noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz. (E 2 NI ) RF ÷ 4kTRS 4kT RG RG IBI ÷ 4kTRF 4kT = 1.6E –20J at 290°K FIGURE 10. Op Amp Noise Analysis Model. DC ACCURACY AND OFFSET CONTROL A current feedback op amp like the OPA2681 provides exceptional bandwidth in high gains, giving fast pulse settling but only moderate DC accuracy. The Typical Specifications show an input offset voltage comparable to high speed voltage feedback amplifiers. However, the two input bias currents are somewhat higher and are unmatched. Whereas bias current cancellation techniques are very effective with most voltage feedback op amps, they do not generally reduce the output DC offset for wideband current feedback op amps. Since the two input bias currents are unrelated in both magnitude and polarity, matching the source impedance looking out of each input to reduce their error contribution to the output is ineffective. Evaluating the configuration of Figure 1, using worst case +25°C input offset voltage and the two input bias currents, gives a worst case output offset range equal to: + ( I BN R S ) + 4kTR S NG 2 + ( I BI R F ) + 4kTR F NG 2 EO IBN ERS The total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage contributors. Equation 4 shows the general form for the output noise voltage using the terms shown in Figure 10. EO = 1/2 OPA2681 RS 2 Dividing this expression by the noise gain (NG = (1+RF/RG)) will give the equivalent input referred spot noise voltage at the non-inverting input as shown in Equation 5. ± (NG x VOS(MAX)) + (IBN x RS /2 x NG) ± (IBI x RF) where NG = non-inverting signal gain = ± (2 x 5.0mV) + (55uA x 25Ω x 2) ± (402Ω x 40µA) E N = E NI + ( I BN R S ) 2 2 = ±10mV + 2.75mV ± 16mV I R 2 4kTR F + 4kTR S + BI F + NG NG = –23.25mV → +28.25mV ® OPA2681 18 DISABLE OPERATION (SO-14 ONLY) The OPA2681N provides an optional disable feature that may be used either to reduce system power or to implement a simple channel multiplexing operation. If the DIS control pin is left unconnected, the OPA2681N will operate normally. To disable, the control pin must be asserted low. Figure 11 shows a simplified internal circuit for the disable control feature. The transition edge rate (dv/dt) of the DIS control line will influence this glitch. For the plot of Figure 12, the edge rate was reduced until no further reduction in glitch amplitude was observed. This approximately 1V/ns maximum slew rate may be achieved by adding a simple RC filter into the VDIS pin from a higher speed logic line. If extremely fast transition logic is used, a 2kΩ series resistor between the logic gate and the VDIS input pin will provide adequate bandlimiting using just the parasitic input capacitance on the VDIS pin while still ensuring adequate logic level swing. +VS Output Voltage (20mV/div) 40 15kΩ Q1 25kΩ VDIS 110kΩ IS Control 20 Output Voltage (0V Input) 0 –20 –40 4.8V VDIS 0.2V Time (20ns/div) –VS FIGURE 12. Disable/Enable Glitch. FIGURE 11. Simplified Disable Control Circuit, Each Channel. THERMAL ANALYSIS Due to the high output power capability of the OPA2681, heatsinking or forced airflow may be required under extreme operating conditions. Maximum desired junction temperature will set the maximum allowed internal power dissipation as described below. In no case should the maximum junction temperature be allowed to exceed 175°C. Operating junction temperature (TJ) is given by TA + PD • θJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipation in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL will depend on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 of either supply voltage (for equal bipolar supplies). Under this condition, PDL = VS2/(4 • RL) where RL includes feedback network loading. In normal operation, base current to Q1 is provided through the 110kΩ resistor while the emitter current through the 15kΩ resistor sets up a voltage drop that is inadequate to turn on the two diodes in Q1’s emitter. As VDIS is pulled low, additional current is pulled through the 15kΩ resistor eventually turning on these two diodes (≈ 100uA). At this point, any further current pulled out of VDIS goes through those diodes holding the emitter-base voltage of Q1 at approximately zero volts. This shuts off the collector current out of Q1, turning the amplifier off. The supply current in the disable mode are only those required to operate the circuit of Figure 11. Additional circuitry ensures that turn-on time occurs faster than turn-off time (make-before-break). When disabled, the output and input nodes go to a high impedance state. If the OPA2681 is operating in a gain of +1, this will show a very high impedance (4pF || 1MΩ) at the output and exceptional signal isolation. If operating at a gain greater than +1, the total feedback network resistance (RF + RG) will appear as the impedance looking back into the output, but the circuit will still show very high forward and reverse isolation. If configured as an inverting amplifier, the input and output will be connected through the feedback network resistance (RF + RG) giving relatively poor input to output isolation. Note that it is the power in the output stage and not into the load that determines internal power dissipation. As a worst-case example, compute the maximum TJ using an OPA2681 SO-8 in the circuit of Figure 1 operating at the maximum specified ambient temperature of +85°C with both outputs driving a grounded 20Ω load to +2.5V. PD = 10V • 14.4mA + 2 • [52/(4 • (20Ω || 804Ω))] = 785mW One key parameter in disable operation is the output glitch when switching in and out of the disabled mode. Figure 12 shows these glitches for the circuit of Figure 1 with the input signal set to zero volts. The glitch waveform at the output pin is plotted along with the DIS pin voltage. Maximum TJ = +85°C + (0.79 • 125°C/W) = 184°C This absolute worst case condition exceeds specified maximum junction temperature. Normally this extreme case will not be encountered. Careful attention to internal power dissipation is required. ® 19 OPA2681 BOARD LAYOUT GUIDELINES Achieving optimum performance with a high frequency amplifier like the OPA2681 requires careful attention to board layout parasitics and external component types. Recommendations that will optimize performance include: d) Connections to other wideband devices on the board may be made with short direct traces or through on-board transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50 to 100mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the plot of recommended RS vs Capacitive Load. Low parasitic capacitive loads (< 5pF) may not need an RS since the OPA2681 is nominally compensated to operate with a 2pF parasitic load. If a long trace is required, and the 6dB signal loss intrinsic to a doubly terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is normally not necessary on board, and in fact a higher impedance environment will improve distortion as shown in the Distortion vs Load plots. With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the OPA2681 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device: this total effective impedance should be set to match the trace impedance. The high output voltage and current capability of the OPA2681 allows multiple destination devices to be handled as separate transmission lines, each with their own series and shunt terminations. If the 6dB attenuation of a doubly terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of RS vs Capacitive Load. This will not preserve signal integrity as well as a doubly terminated line. If the input impedance of the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability: on the noninverting input, it can react with the source impedance to cause unintentional bandlimiting.. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. b) Minimize the distance (< 0.25") from the power supply pins to high frequency 0.1uF decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power supply connections (on pins 4 and 7) should always be decoupled with these capacitors. An optional supply de-coupling capacitor across the two power supplies (for bipolar operation) will improve 2nd harmonic distortion performance. Larger (2.2uF to 6.8uF) decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. c) Careful selection and placement of external components will preserve the high frequency performance of the OPA2681. Resistors should be a very low reactance type. Surface mount resistors work best and allow a tighter overall layout. Metal film and carbon composition axially leaded resistors can also provide good high frequency performance. Again, keep their leads and PC board trace length as short as possible. Never use wirewound type resistors in a high frequency application. Since the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as non-inverting input termination resistors, should also be placed close to the package. Where double side component mounting is allowed, place the feedback resistor directly under the package on the other side of the board between the output and inverting input pins. The frequency response is primarily determined by the feedback resistor value as described previously. Increasing its value will reduce the bandwidth, while decreasing it will give a more peaked frequency response. The 402Ω feedback resistor used in the typical performance specifications at a gain of +2 on ±5V supplies is a good starting point for design. Note that a 453Ω feedback resistor, rather than a direct short, is recommended for the unity gain follower application. A current feedback op amp requires a feedback resistor even in the unity gain follower configuration to control stability. e) Socketing a high speed part like the OPA2681 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA2681 onto the board. If socketing for the DIP package is desired, high frequency flush mount pins (e.g., McKenzie Technology #710C) can give good results. INPUT AND ESD PROTECTION The OPA2681 is built using a very high speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins have limited ESD protection using internal diodes to the power supplies as shown in Figure 13. ® OPA2681 20 These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher currents are possible (e.g. in systems with ±15V supply parts driving into the OPA681), current limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible since high values degrade both noise performance and frequency response. +V CC External Pin Internal Circuitry –V CC FIGURE 13. Internal ESD Protection. ® 21 OPA2681