® PCM1700U PCM1700P Dual 18-Bit Monolithic Audio DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION ● DUAL 18-BIT LOW-POWER MONOLITHIC AUDIO D/A CONVERTER The PCM1700 is a low cost, high-performance, dual 18-bit digital-to-analog converter. The PCM1700 features low glitch, co-phase current and voltage outputs and only requires ±5V supplies. The PCM1700 comes complete with an internal reference and optional MSB adjustability for even greater THD performance. Total power dissipation is less than 400mW max. Low maximum Total Harmonic Distortion + Noise (–92dB max; PCM1700P-K) is 100% tested. The very fast PCM1700 is also capable of 16X oversampling rates on both channels simultaneously, providing freedom in output filter selection. ● VERY LOW MAX THD+N: –92dB Without External Adjust ● CO-PHASE, LOW-GLITCH ±3V OR ±670µA AUDIO OUTPUTS ● CAPABLE OF 16X PER CHANNEL OVERSAMPLING RATE ● COMPLETE WITH INTERNAL REFERENCE ● SERIAL INPUT FORMAT 100% COMPATIBLE WITH INDUSTRY STD PCM56P ● RUNS ON ±5V SUPPLIES AND DISSIPATES 300mW MAX ● COMPACT 28-PIN PLASTIC DIP OR SOIC The PCM1700 comes in space-saving 28-pin plastic DIP and SOIC packages. PCM1700 accepts a serial data input format that is compatible with other BurrBrown PCM products such as the industry standard PCM56P. MSB Adj Left Data Left Clock Latch Enable 18-Bit Serial-to-Parallel Shift Register SJ 18-Bit I OUT DAC Control Logic Data Right I OUT Left VOUT Left Reference 18-Bit Serial-to-Parallel Shift Register VOUT Right 18-Bit I OUT DAC MSB Adj Right I OUT Right SJ International Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1990 Burr-Brown Corporation PDS-1035D Printed in U.S.A. August, 1993 SPECIFICATIONS ELECTRICAL At 25°C, and ±VCC= ±5.00V unless otherwise noted. Where relevant, specifications apply to both left and right input/output channels. PCM1700U/U-J/U-K, PCM1700P/P-J/P-K PARAMETER CONDITIONS RESOLUTION MIN TYP MAX 18 DYNAMIC RANGE UNITS Bits +108 dB INPUT DIGITAL INPUT Logic Family Logic Level: VIH VIL IIH IIL Data Format Input Clock Frequency TTL Compatible +2 0 +VDD +0.8 +1 –50 VIH = +2.7V VIL = +0.4V 11.288 Serial BTC(1) 20 V V µA µA MHz DYNAMIC CHARACTERISTICS TOTAL HARMONIC DISTORTION + N(6) PCM1700_: f = 991kHz (0dB) f = 991kHz (–20dB) fIN = 991kHz (–60dB) PCM1700_-J: f = 991kHz (0dB) f = 991kHz (–20dB) f = 991kHz (–60dB) PCM1700_-K: f = 991kHz (0dB) f = 991kHz (–20dB) f = 991kHz (–60dB) fS = 352.8kHz(4) fS = 352.8kHz fS = 352.8kHz –88 –74 –34 –82 –68 –28 dB dB dB fS = 352.8kHz fS = 352.8kHz fS = 352.8kHz –94 –76 –36 –88 –74 –34 dB dB dB fS = 352.8kHz fS = 352.8kHz fS = 352.8kHz –98 –80 –40 –92 –74 –34 dB dB dB CHANNEL SEPARATION SIGNAL-TO-NOISE RATIO(5) +96 20Hz to 20kHz at BPZ(6) +108 dB +108 dB TRANSFER CHARACTERISTICS ACCURACY Gain Error Gain Mismatch Bipolar Zero Error BPZ Error Mismatch BPZ Differential Linearity Error(7) Gain Drift Bipolar Zero Drift Warm-up Time Channel to Channel POWER SUPPLY REJECTION ±VCC to VOUT ANALOG OUTPUT Voltage: Output Range Output Impedance Current Output Capacitive Load Drive Short Circuit Duration Settling Time Glitch Energ Current: Output Range Output Impedance ±1 ±1 10 5 ±1 100 20 Channel to Channel ±3 ±3 1 +86 RLOAD = 1.5kΩ (±2%) (±2%) % % mV mV LSB ppm/°C ppm of FSR/°C minute dB ±3 V 0.1 Ω ±2 mA TBD pF Indefinite Sufficient to Meet THD+N Specs Meets All THD+N Specs Without External Output Deglitching ±670 µA 1.67 kΩ POWER SUPPLY REQUIREMENTS ±VCC Supply Voltage Supply Current: +ICC –ICC Power Dissipation +4.75 +VCC = +5.0V –VCC = –5.0V ±VCC = ±5.0V +5.00 +18 –42 280 +5.25 +30 –65 475 V mA mA mW +70 +70 +100 °C °C °C TEMPERATURE RANGE Specification Operating Storage 0 –30 –60 NOTES: (1) Binary Two’s Complement coding. (6) Ratio of (DistortionRMS + NoiseRMS) / SignalRMS. (3) D/A converter input frequency/signal level on both left and right channels. (4) D/A converter sample frequency (8 X 44.1kHz; 8X oversampling per channel). (5) Ratio of NoiseRMS / SignalRMS. Measured using an A-weighted filter. (6) Bipolar zero. (7) Differential non-linearity at bipolar major carry input code. Measured in 16-bit LSBs. Adjustable to zero error. ® PCM1700 2 PIN ASSIGNMENTS (Plastic PKG) PIN ASSIGNMENTS (SOIC PKG) PIN DESCRIPTION MNEMONIC PIN DESCRIPTION MNEMONIC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 –5V Analog Supply Left Channel Servo-Amp Decoupling Point Left Channel MSB Adjustment No Connect Left Channel Bipolar Offset Decoupling Point Left Channel Current Output Left Channel Analog Common Left Channel Summing Junction Left Channel Voltage Output No Connect +5V Digital Supply Left Channel Data Input Clock Input –5V Logic Supply Latch Enable Input Right Channel Data Input Digital Common No Connect Right Channel Voltage Output Right Channel Summing Junction Right Channel Analog Common Right Channel Current Output Right Channel Bipolar Offset Decoupling Point Right Channel MSB Adjustment Right Channel Servo-Amp Decoupling Point MSB Adjustment Potentiometer Voltage Output +5V Analog Supply Digital Common –VCC CAP MSB ADJ (L) NC CAP IOUT (L) ACOM SJ (L) VOUT (L) NC +VDD DATA CLOCK –VDD LE DATA (R) DCOM NC VOUT (R) SJ (R) ACOM IOUT (R) CAP MSB ADJ (R) CAP VPOT +VCC DCOM 9 10 11 19 12 13 14 15 16 17 18 20 21 22 23 24 25 26 27 28 1 2 3 4 5 6 7 8 –5V Analog Supply Left Channel Servo-Amp Decoupling Point Left Channel MSB Adjustment No Connect Left Channel Bipolar Offset Decoupling Point Left Channel Current Output Left Channel Analog Common Left Channel Summing Junction Left Channel Voltage Output No Connect +5V Digital Supply Left Channel Data Input Clock Input –5V Logic Supply Latch Enable Input Right Channel Data Input Digital Common No Connect Right Channel Voltage Output Right Channel Summing Junction Right Channel Analog Common Right Channel Current Output Right Channel Bipolar Offset Decoupling Point Right Channel MSB Adjustment Right Channel Servo-Amp Decoupling Point MSB Adjustment Potentiometer Voltage Output +5V Analog Supply Digital Common –VCC CAP MSB ADJ (L) NC CAP IOUT (L) ACOM SJ (L) VOUT (L) NC +VDD DATA CLOCK –VDD LE DATA (R) DCOM NC VOUT (R) SJ (R) ACOM IOUT (R) CAP MSB ADJ (R) CAP VPOT +VDD DCOM NOTE: In the SOIC (PCM1700U) package, the die is rotated 90°. Therefore, the pin assignments are different from the DIP. See pin assignments on page 4 for details. ORDERING INFORMATION PCM1700 ( ) ( ) Basic Model Number P: Plastic U: SOIC Performance Grade Code PACKAGE INFORMATION MODEL ABSOLUTE MAXIMUM RATINGS PCM1700U PCM1700U-J PCM1700U-K PCM1700P PCM1700P-J PCM1700P-K DC Supply Voltages ..................................................................... ±7.5VDC Input Logic Voltage ................................................................. –1V to +VCC Power Dissipation .......................................................................... 500mW Operating Temperature ..................................................... –25°C to +70°C Storage Temperature ...................................................... –60°C to +100°C Lead Temperature (soldering, 10s) ................................................ +300°C PACKAGE PACKAGE DRAWING NUMBER(1) 28-Pin SOIC 28-Pin SOIC 28-Pin SOIC 28-Pin Plastic DIP 28-Pin Plastic DIP 28-Pin Plastic DIP 217 217 217 126 126 126 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. ® 3 PCM1700 DIGITAL INPUT > 25ns Data Input LSB MSB > 15ns > 15ns > 5ns Clock In > 25ns > 25ns > 60ns ANALOG OUTPUT Binary Two’s Complement (BTC) DAC Output Voltage (V) VOUT Mode Current (mA) IOUT Mode 1FFFF Hex 00000 Hex 3FFFF Hex 20000 Hex + FS BPZ BPZ – 1LSB – FS +2.99997711 0.00000000 –0.00002289 –3.00000000 –0.66999489 0.00000000 +0.00000511 +0.67000000 TABLE I. PCM1700 Input/Output Relationships. > 15ns Latch Enable > One Clock Cycle > One Clock Cycle FIGURE 1. PCM1700P Setup and Hold Timing Diagram. P13 (Clock) P12 Data (L) P16 Data (R) 1 2 3 4 10 11 12 13 14 15 16 17 18 19 MSB 1 LSB 2 3 4 10 11 12 13 14 15 16 17 18 19 MSB LSB P15 (Latch Enable) FIGURE 2. Timing Diagram. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® PCM1700 4 100kΩ +5V 10µF + 0.01µF –5V 1 –VCC DCOM 28 2 CAP +VCC 27 3 MSB Adj (Left) VPOT 26 4 NC CAP 25 5 CAP MSB Adj (Right) 24 0.47µF 10µF 0.47µF 0.1µF 0.1µF 0.47µF 100kΩ 100kΩ 6 IOUT (Left) CAP 23 7 ACOM (Left) 8 SJ (Left) 9 VOUT (Left) 10 NC 11 +VDD 12 DATA (Left) 13 Clock 14 –VDD LE 15 IOUT (Right) 22 ACOM (Right) 21 SJ (Right) 20 VOUT (Right) 19 NC 18 DCOM 17 DATA (Right) 16 0.1µF 100kΩ Optional Bit Adjust Circuit .01µF 0.1µF 0.47µF FIGURE 3. Voltage Output Connection Diagram (DIP Package Diagram.) 100kΩ +5V 10µF + 0.01µF –5V 1 –VCC DCOM 28 2 CAP +VCC 27 3 MSB Adj (Left) VPOT 26 4 NC CAP 25 5 CAP MSB Adj (Right) 24 6 IOUT (Left) CAP 23 7 ACOM (Left) IOUT (Right) 22 8 SJ (Left) ACOM (Right) 21 9 VOUT (Left) SJ (Right) 20 10 NC VOUT (Right) 19 11 +VDD NC 18 12 DATA (Left) DCOM 17 13 Clock DATA (Right) 16 14 –VDD LE 15 0.47µF 10µF + 0.47µF 0.1µF 4.5kΩ (1) 0.1µF VOUT (R) 1.22kΩ (1) BB OPA602BP 0 .47µF 100kΩ 100kΩ 0.1µF 100kΩ 0.01µF 0.1µF Optional Bit Adjust Circuit 4.55kΩ (1) VOUT (L) BB OPA602BP 1.22kΩ (1) NOTES: (1) Low TCR resistors such as Vishay. 0.47µF FIGURE 4. Current Output Connection Diagram (DIP Package Diagram.) ® 5 PCM1700