PCM58P ® Precision, 18-Bit Monolithic Audio DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION ● 18-BIT MONOLITHIC AUDIO D/A CONVERTER ● VERY LOW MAX THD+N: –96dB Without External Adjustment; PCM58P-K ● SERIAL INPUT FORMAT 100% COMPATIBLE WITH INDUSTRY STD 16-BIT PCM56P ● VERY FAST SETTLING, GLITCH-FREE CURRENT OUTPUT (200ns) ● LOW-NOISE SCHMITT TRIGGER LOGIC INPUT CIRCUITRY The PCM58P is a complete, precision 18-bit digitalto-analog converter with ultra-low distortion over a very wide frequency range. The latched serial input data format of the PCM58P is totally based on the widely successful 16-bit PCM56P format (with the addition of two more data bits). The PCM58P features a very low noise and fast settling current output. The PCM58P comes in a 28-pin plastic DIP package. A provision is made for external adjustment of the four MSBs to further improve the PCM58P’s specifications, if desired. Applications include very low distortion frequency synthesis and high-end consumer and professional digital audio applications. ● COMPLETE WITH REFERENCE ● RELIABLE PLASTIC 28-PIN DIP PACKAGE Reference VREF MSB Adj Clock Control Logic 18-Bit IOUT DAC RF Latch Enable Data IOUT Serial-to-Parallel Shift Register RF International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © PCM58P 1988 Burr-Brown Corporation PDS-868A Printed in U.S.A. October, 1993 SPECIFICATIONS ELECTRICAL All Specifications at 25°C, and ±VCC = +5.0V and –12.0V unless otherwise noted. PCM58P /P,J/P,K PARAMETER CONDITIONS MIN TYP RESOLUTION DYNAMIC RANGE MAX UNITS 18 BITS 108 DIGITAL INPUT Logic Family Logic Level: VIH VIL IIH IIL Data Format Input Clock Frequency DYNAMIC CHARACTERISTICS TOTAL HARMONIC DISTORTION + N(2) VIH = +2.7V VIL = +0.4V dB TTL/CMOS Compatible +2.0 +VCC 0.0 0.8 +1.0 –50 Serial BTC(1) 16.9 20 MHz V V µA µA Without MSB Adjustments PCM58P: f = 991Hz (0dB)(3) f = 991Hz (–20dB) f = 991Hz (–60dB) fS = 176.4kHz(4) fS = 176.4kHz fS = 176.4kHz –94 –74 –40 –92 –72 –34 dB dB dB f = 991Hz (0dB) f = 991Hz (–20dB) f = 991Hz (–60dB) fS = 176.4kHz fS = 176.4kHz fS = 176.4kHz –96 –80 –40 –94 –74 –34 dB dB dB f = 991Hz (0dB) f = 991Hz (–20dB) f = 991Hz (–60dB) fS = 176.4kHz fS = 176.4kHz fS = 176.4kHz –100 –82 –42 –96 –80 –40 dB dB dB ±2 0°C to 70°C 0°C to 70°C ±1 ±10 25 4 % mV ppm/°C ppm of FSR/°C Minute PCM58P-J: PCM58P-K TRANSFER CHARACTERISTICS ACCURACY Gain Error Bipolar Zero Error(5) Gain Drift Bipolar Zero Drift Warm-up Time IDLE CHANNEL SNR(6) 1 20Hz to 20kHz at BPZ(7) POWER SUPPLY REJECTION ANALOG OUTPUT Output Range Output Impedance Internal Feedback Settling Time Glitch Energy +126 dB +72 dB ±0.98 ±1.0 ±1.02 mA 1.2 kΩ 3 kΩ 200 ns Meets all THD+N Specs Without External Deglitching 1mA Step POWER SUPPLY REQUIREMENTS +VCC Supply Voltage –VCC Supply Voltage Supply Current +ICC –ICC Power Dissipation +4.75 –10.8 +VCC = +5.0V –VCC = –12.0V +5.00 –12.0 +10 –30 410 +5.50 –13.2 V V mA mA mW +70 +70 +100 °C °C °C TEMPERATURE RANGE Specification Operating Storage 0 –30 –60 NOTES: (1) Binary Two’s Complement coding. (2) Ratio of (DistortionRMS + NoiseRMS) / SignalRMS. (3) D/A converter output frequency/signal level. (4) D/A converter sample frequency (4 x 44.1kHz; 4 times oversampling). (5) Offset error at bipolar zero. (6) Measured using an OPA27 and 10kΩ feedback and an A-weighted filter. (7) Bipolar Zero. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® PCM58P 2 PIN ASSIGNMENTS P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 DESCRIPTION Decoupling Capacitor +Vcc Voltage Supply Decoupling Capacitor Decoupling Capacitor Bipolar Offset Point Current DAC IOUT Feedback Resistor Analog Common –VCC Voltage Supply Feedback Resistor Digital Common No Connection +VCC Voltage Supply No Connection Decoupling Capacitor Clock DAC Latch Enable No Connection Data Input –VCC Voltage Supply No Connection No Connection No Connection Bit 4 Adjust Bit 3 Adjust Bit 2 Adjust Bit 1 (MSB) Adjust Bit Adjust VPOT Use 400Hz High-Pass Filter and 30kHz Low-Pass Filter Meter Settings PCM58P MNEMONIC CAP +VCC CAP CAP BPO IOUT RF1 ACOM –VCC RF2 DCOM NC +VCC NC CAP CLK LE NC DATA –VCC NC NC NC B4 ADJ B3 ADJ B2 ADJ B1 ADJ VPOT ABSOLUTE MAXIMUM RATINGS ±VCC Supply Voltages ................................................................ +6V; –16V Input Logic Voltage ................................................................. –1V to +VCC Storage Temperature ...................................................... –60°C to +100°C Lead Temperature (soldering, 10s) ................................................ +300°C PACKAGE INFORMATION(1) PACKAGE PACKAGE DRAWING NUMBER 28-Pin Plastic DIP 28-Pin Plastic DIP 28-Pin Plastic DIP 215 215 215 MODEL PCM58P PCM58P, J PCM58P, K NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. LOW-PASS FILTER CHARACTERISTIC Low-Pass Filter (Toko APQ-25 or Equivalent) Programmable Gain Amp 0dB to 60dB Distortion Analyzer -X Basic Model Number P: Plastic Performance Grade Code 0 –20 Gain (dB) PIN ORDERING INFORMATION (Shiba Soku Model 725 or Equivalent) –40 –60 –80 –100 Binary Counter Digital Code (EPROM) Parallel-to-Serial Conversion DUT (PCM58P) –120 1 101 102 103 104 105 Frequency (Hz) Clock Latch Enable Timing Logic Sampling Rate = 44.1kHz X 4 (176.4kHz) Output Frequency = 991Hz FIGURE 1. PCM58P Production THD+N Test Setup. DISCUSSION OF SPECIFICATIONS TOTAL HARMONIC DISTORTION + NOISE The key specification for the PCM58P is total harmonic distortion plus noise. Digital data words are read into the PCM58P at four times the standard audio sampling frequency of 44.1kHz or 176.4kHz such that a sinewave output of 991Hz is realized. For production testing, the output of the DAC goes to a programmable gain amplifier to provide gain at lower signal output test levels and then through a 20kHz low pass filter before being fed into an analog type distortion analyzer. Figure 1 shows a block diagram of the production THD+N test setup. ® 3 PCM58P In terms of signal measurement, THD+N is the ratio of DistortionRMS + NoiseRMS / SignalRMS expressed in dB. For the PCM58P, THD+N is 100% tested at three different output levels using the test setup shown in Figure 1. It is significant to note that this test setup does not include any output deglitching circuitry. This means the PCM58P even meets its –60dB THD+N specification without use of external deglitchers. TIMING CONSIDERATIONS The PCM58P accepts TTL-compatible logic input levels. Noise immunity is enhanced by the use of Schmitt trigger input architectures on all input signal lines. The data format of the PCM58P is binary two’s complement (BTC) with the most significant bit (MSB) being first in the serial input bit stream. Table I describes the exact input data to voltage output coding relationship. Any number of bits can precede the 18 bits to be loaded as only the last 18 will be transferred to the parallel DAC register after LE (P17; latch enable) has gone low. ABSOLUTE LINEARITY Even though absolute integral and differential linearity specs are not given for the PCM58P, the extremely low THD+N performance is typically indicative of 15-bit to 16-bit integral linearity in the DAC depending on the grade specified. The relationship between THD+N and linearity, however, is not such that an absolute linearity specification for every individual output code can be guaranteed. The individual DAC serial input data bit shifts transfer are triggered on positive CLK edges. The serial to parallel data transfer to the DAC occurs on the falling edge of LE (P17). Refer to Figure 2 for graphical relationships of these signals. MAXIMUM CLOCK RATE The maximum clock rate of 16.9mHz for the PCM58P is derived by multiplying the standard audio sample rate of 44.1kHz times sixteen (16X oversampling) times the standard audio word bit length of 24 (44.1kHz x 16 x 24 = 16.9mHz). Note that this clock rate accommodates a 24-bit word length, even though only 18 bits are actually being used. IDLE CHANNEL SNR Another appropriate spec for a digital audio converter is idle channel signal-to-noise ratio (idle channel SNR). This is the ratio of the noise on the DAC output at bipolar zero in relation to the full scale range of the DAC. The output of the DAC is band-limited from 20Hz to 20kHz and an A-weighted filter is applied to make this measurement. The idle channel SNR for the PCM58P is typically greater than +126dB, making it ideal for low-noise applications. DIGITAL INPUT OFFSET, GAIN, AND TEMPERATURE DRIFT Although the PCM58P is primarily meant for use in dynamic applications, specifications are also given for more traditional DC parameters such as gain error, bipolar zero offset error, and temperature gain drift and offset drift. ANALOG OUTPUT Binary Two’s Complement (BTC) DAC Output Voltage (V) VOUT Mode Current (mA) IOUT Mode 3FFFF Hex 20000 Hex 1FFFF Hex 00000 Hex +FS BPZ BPZ – 1LSB –FS +2.9999943 0.0000000 –0.0000057 –3.0000000 –0.9999981 0.0000000 +0.0000019 +1.0000000 TABLE I. PCM60P Input/Output Relationships. P16 (Clock) P18 (Data) 1 MSB 2 3 4 10 11 12 13 14 15 16 17 18 LSB 1 P17 (Latch Enable) NOTES: (1) If clock is stopped between input of 18-bit data words, latch enable (LE) must remain low until after the first clock of the next 18-bit data word stream. (2) Data format is binary two’s complement (BTC). Individual data bits are clocked in on the corresponding positive clock edge. (3) Latch enable (LE) must remain low at least one clock cycle after going negative. (4) Latch enable (LE) must be high for at least one clock cycle before going negative. FIGURE 2. PCM58P Timing Diagram. ® PCM58P 4 “STOPPED-CLOCK” OPERATION The PCM58P is normally operated with a continuous clock input signal. If the clock is to be stopped in between input data words, the last 18-bits shifted in are not actually shifted from the serial register to the latched parallel DAC register until LE (latch enable) goes low. If the clock input (P16, CLK) is stopped between data words, LE (P17) must remain low until after the first clock cycle of the next data word to insure proper DAC operation. In either case, the setup and hold times for DATA and LE must still be observed as shown in Figure 3. >40ns Data Input MSB LSB >15ns >15ns Clock Input >40ns >40ns >5ns >100ns >15ns Latch Enable >One Clock Cycle INSTALLATION >One Clock Cycle FIGURE 3. PCM58P Setup and Hold Timing Diagram. Refer to Figure 4 for proper connection of the PCM58P in the voltage-out mode using the internal feedback resistor. The feedback resistor connections (P7 and P10) should be connected to ACOM (P8) if not used. The PCM58P requires only a +5V and –12V supply. It is very important that these supplies be as “clean” as possible to reduce coupling of supply noise to the output. Power supply decoupling capacitors shown in Figure 4 should be used, regardless of how good the supplies are to maximize power supply rejection. All grounds should be connected to the analog ground plane as close to the PCM58P as possible. 0.1µF + FILTER CAPACITOR REQUIREMENTS As shown in Figure 4, other various decoupling capacitors are required around the supply and reference points with no special tolerances being required. Placement of all capacitors should be as close to the appropriate pins of the PCM58P as possible to reduce noise pickup from surrounding circuitry. 1kΩ 100kΩ 1kΩ 1 CAP VPOT 28 2 +VCC Bit Adj (MSB) 27 3 CAP Bit Adj (B2) 26 4 CAP Bit Adj (B3) 25 5 BPO Bit Adj (B4) 24 6 IOUT NC 23 7 RF1 NC 22 8 ACOM NC 21 9 –VCC –VCC 20 10 RF2 DATA 19 11 DCOM NC 18 12 NC LE 17 13 +VCC CLK 16 14 NC CAP 15 330kΩ +5V 0.1µF + + 330kΩ 330kΩ 0.1µF Optional External Op-Amp Burr-Brown OPA602BP 3.3µF + NOTE: Connect P7 and P10 to P8 (ACOM) if internal feedback resistor is not used 3.3µF + 330kΩ RF 3kΩ Optional Bit Adjust Circuit –12V 3.3µF + + 0.1µF FIGURE 4. PCM58P Connection Diagram. ® 5 PCM58P MSB ADJUSTMENT CIRCUITRY With the optional bit adjustment circuitry shown in Figure 4, even greater performance can be realized by reducing the first four major bit carry output errors to zero. The most important adjustment for low level outputs would be the step between BPZ (bipolar zero; MSB on, all other bits off) and the code, which is one LSB less than BPZ (MSB off, all other bits on), since every crossing of zero would go through this bipolar major carry point. This MSB bit adjustment would be made by outputing a very low level signal sine wave and calibrating the 100kΩ potentiometer circuit connected to P28 and P27 while monitoring the THD+N of the PCM58P until peak performance is observed. Bits 2 through 4 can also be adjusted if desired to obtain optimum full-scale output THD+N performance. An additional 100kΩ potentiometer adjustment circuit is required for every additional bit to be adjusted. If bit adjustment is not performed, the respective pins on the PCM58P should be left open. Once bit adjustment is performed, the reference voltage at VPOT (P28) will track the internal reference, insuring that the THD+N performance of the PCM58P will remain unaffected by external temperature changes. ® PCM58P 6