VCA8617 SBOS308B − AUGUST 2004 − REVISED NOVEMBER 2004 8-Channel VARIABLE GAIN AMPLIFIER D D D D D FEATURES D 3V OPERATION D LOW INPUT NOISE: 1.0nV//Hz at fIN = 5MHz D EXTREMELY LOW POWER OPERATION: 100mW/CHANNEL D INTEGRATED LOW-PASS, 2-POLE FILTER INTEGRATED INPUT CLAMP DIODES DIFFERENTIAL OUTPUT INTEGRATED INPUT LNA READABLE CONTROL REGISTERS INTEGRATED CONTINUOUS WAVE (CW) PROCESSOR 15MHz BANDWIDTH DESCRIPTION The VCA8617 is an 8-channel variable gain amplifier ideally suited to portable ultrasound applications. Excellent dynamic performance enables use in low-power, high-performance portable applications. Each channel consists of a 20dB gain Low-Noise pre-Amplifier (LNA) and a Variable Gain Amplifier (VGA). The differential outputs of the LNA can be switched through the 8x10 cross-point switch, which is programmable through the serial interface input port. The output of the LNA is fed directly into the VGA stage. The VGA consists of two parts, a Voltage-Controlled Attenuator (VCA) and a Programmable Gain Amplifier (PGA). The gain and gain range of the PGA can be digitally configured separately. The gain of the PGA can vary between four discrete settings of 25dB, 30dB, 35dB, and 40dB. The VCA has four programmable maximum attenuation settings: 29dB, 33dB, 36.5dB, and 40dB. Also, the VCA can be continuously varied by a control voltage from 0dB to a maximum of 29dB, 33dB, 36.5dB, and 40dB. The output of the PGA feeds directly into an integrated two-pole, low-pass filter. 10x8 FIFO CW(0−9) CW Processor ••• D(0−3) DATA CLK ••• Serial Interface Analog Control CS + − ••• Attenuator PGA ••• 2−Pole Filter OutP(1) OutN(1) ••• LNA ••• LNAIN1 1 VLNA + LNAIN8 LNA 8 − Attenuator PGA 2−Pole Filter OutP(8) OutN(8) Analog Control VLNA Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright 2004, Texas Instruments Incorporated ! ! www.ti.com " #$%& www.ti.com SBOS308B − AUGUST 2004 − REVISED NOVEMBER 2004 ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC DISCHARGE SENSITIVITY +AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.6V Analog Input . . . . . . . . . . . . . . . . . . . . . . . . −0.3V to +AVDD + 0.3V Logic Input . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3V to +AVDD + 0.3V Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +100°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Thermal Resistance, Junction-to-Ambient (qJA) . . . . . . . . . 66.6°C/W Thermal Resistance, Junction-to-Case(qJC) . . . . . . . . . . . . . 4.3°C/W (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION(1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING VCA8617 TQFP-64 PAG −40°C to +85°C VCA8617PAG ORDERING NUMBER TRANSPORT MEDIA, QUANTITY VCA8617PAGT Tape and Reel, 250 VCA8617PAGR Tape and Reel, 1500 (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet. 2 " #$%& www.ti.com SBOS308B − AUGUST 2004 − REVISED NOVEMBER 2004 ELECTRICAL CHARACTERISTICS: AVDD = 3V At TA = +25°C, load resistance = 1kΩ on each output to ground, unless otherwise noted. The input to the preamp (LNA) is single-ended; pre-amp gain is fixed at +20dB, fIN= 2MHz, PG = 01, ATN = 00, and the output from the VCA is differential, unless otherwise noted. VCA8617 PARAMETER CONDITIONS MIN TYP MAX UNITS PREAMPLIFIER Input Resistance 4.5 Input Capacitance 52 pF Input Bias Current 1 nA 200 1.05 mVPP nV/√Hz 1.15 nV/√Hz Maximum Input Voltage(1) Input Voltage Noise (TGC) fIN = 5MHz fIN = 5MHz Input Voltage Noise (CW) Output Swing (Differential) kΩ 2 V Bandwidth 100 MHz Gain 20 dB 18 dB/V ACCURACY Gain Slope 0.2V − 1.7V, VCACNTRL Gain Error 0.2V − 1.7V, VCACNTRL Output Offset Voltage 1.7 Differential 0.65 dB mV GAIN CONTROL INTERFACE Input Voltage (VCACNTRL) Range Input Resistance Response Time 40dB Gain Change, PG = 11 0 to 20 V 1 MΩ 0.2 µs POWER SUPPLY Specified Operating Range 2.85 Power-Down Delay 3.15 µs 100 Operating All Channels 825 V µs 5 Power-Up Delay Power Dissipation (TGC Mode) 3.0 950 mW PROGRAMMABLE VGA AND LOW-PASS FILTER −3dB Cutoff (low-pass) 14.5 −3dB Cutoff (high-pass) 400 kHz Slew Rate 300 V/µs Output Impedance 10 Ω Crosstalk 49 dB Output Common-Mode 1.5 Output Swing (Differential)(2) MHz V 2 3rd-Harmonic Distortion −65 −50 VPP dB 2nd-Harmonic Distortion −60 −50 dB Group Delay Variation ±3 ns CONTINUOUS WAVE PROCESSOR V/I Converter Transconductance 17 20 23 mA/V Common-Mode 1.4 V Max Output Swing 3.4 mAPP LOGIC INPUTS VIN LOW (input low voltage) VIN HIGH (input high voltage) 0 0.6 V 2.1 VDD ±1 V µA 25M Hz Input Current Input Pin Capacitance Clock Input Frequency 5 10k pF (1) Under conditions when input signal is within linear range of LNA. (2) Under conditions when signal is within linear range of output amplifier. 3 " #$%& www.ti.com AGND IN7 AGND IN8 AVDD CW0 CW2 CW4 CW6 CW8 AGND AVDD VCNTRL VLNA AGND VREF SBOS308B − AUGUST 2004 − REVISED NOVEMBER 2004 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 IN6 1 48 OUT8 AGND 2 47 OUT8 IN5 3 46 OUT7 AGND 4 45 OUT7 DVDD 5 44 OUT6 DGND 6 43 OUT6 DOUT 7 42 OUT5 CLK 8 DIN 9 40 OUT4 CS 10 39 OUT4 DGND 11 38 OUT3 DVDD 12 37 OUT3 AGND 13 36 OUT2 IN4 14 35 OUT2 AGND 15 34 OUT1 IN3 16 33 OUT1 41 OUT5 24 25 26 27 28 29 30 31 32 CW9 AGND AVDD VFIL VCM GNDR VDDR 23 CW7 22 CW5 AGND 21 CW3 IN2 20 CW1 19 AVDD 18 IN1 17 AGND VCA8617 PIN DESCRIPTIONS PIN DESIGNATOR DESCRIPTION 5, 12 Digital supplies 1, 3, 14, 16, 18, 20, 61, 63 DVDD AGND IN(1−8) 22−26, 55−59 CW(0−9) 51 VLNA VFIL 2, 4, 13, 15, 17, 19, 27, 50, 54, 62, 64 29 30 Single-ended LNA inputs Continuous wave outputs Reference voltage for LNA−internally generated; requires external bypass cap Reference voltage for Output Filter−internally generated; requires external bypass cap VCM OUT(1−8) OUT(1−8) Common-mode voltage−internally generated; requires external bypass cap Attenuator control input 9 VCNTRL DIN 10 CS Serial data chip select 8 CLK Serial data input clock 7 Serial data output pin 21, 28, 53, 60 DOUT AVDD 6, 11 DGND Digital ground 49 Reference voltage for attenuator−internally generated; requires external bypass cap 32 VREF VDDR 31 GNDR Reference ground 24, 36, 38, 40, 42, 44, 46, 48 33, 35, 37, 39, 41, 43, 45, 47 52 4 Analog ground Positive polarity PGA outputs Negative polarity PGA outputs Serial data input pin Analog supplies Reference power supply " #$%& www.ti.com SBOS308B − AUGUST 2004 − REVISED NOVEMBER 2004 INPUT REGISTER BIT MAPS Byte 1—Control Byte Register Map BIT # LSB 1 2 3 4 5 6 MSB NAME 1 W/R PWR A0 A1 Mode PG0 PG1 DESCRIPTION Start bit; always a ‘1’—40-bit count down starts upon first ‘1’ after chip select. 1 = Write, 0 = Read—Read prevents latching of DATA only—Control register still latched. Entire chip. Power Control—1 = Off. Otherwise, chip is on. Attenuator control bit. Attenuator control bit. 1 = TGC Control mode (CW powered down), 0 = Doppler mode (TGC powered down) LSB of PGA Gain Control MSB of PGA Gain Control Byte 2—First Data Byte BIT # LSB 1 2 3 4 5 6 MSB NAME Data 1:0 Data 1:1 Data 1:2 Data 1:3 Data 2:0 Data 2:1 Data 2:2 Data 2:3 DESCRIPTION Channel 1, LSB of Matrix Control Channel 1, Matrix Control Channel 1, Matrix Control Channel 1, MSB of Matrix Control Channel 2, LSB of Matrix Control Channel 2, Matrix Control Channel 2, Matrix Control Channel 2, MSB of Matrix Control Byte 3—Second Data Byte BIT # LSB 1 2 3 4 5 6 MSB NAME Data 3:0 Data 3:1 Data 3:2 Data 3:3 Data 4:0 Data 4:1 Data 4:2 Data 4:3 DESCRIPTION Channel 3, LSB of Matrix Control Channel 3, Matrix Control Channel 3, Matrix Control Channel 3, MSB of Matrix Control Channel 4, LSB of Matrix Control Channel 4, Matrix Control Channel 4, Matrix Control Channel 4, MSB of Matrix Control Byte 4—Third Data Byte BIT # LSB 1 2 3 4 5 6 MSB NAME Data 5:0 Data 5:1 Data 5:2 Data 5:3 Data 6:0 Data 6:1 Data 6:2 Data 6:3 DESCRIPTION Channel 5, LSB of Matrix Control Channel 5, Matrix Control Channel 5, Matrix Control Channel 5, MSB of Matrix Control Channel 6, LSB of Matrix Control Channel 6, Matrix Control Channel 6, Matrix Control Channel 6, MSB of Matrix Control Byte 5—Fourth Data Byte BIT # LSB 1 2 3 4 5 6 MSB NAME Data 7:0 Data 7:1 Data 7:2 Data 7:3 Data 8:0 Data 8:1 Data 8:2 Data 8:3 DESCRIPTION Channel 7, LSB of Matrix Control Channel 7, Matrix Control Channel 7, Matrix Control Channel 7, MSB of Matrix Control Channel 8, LSB of Matrix Control Channel 8, Matrix Control Channel 8, Matrix Control Channel 8, MSB of Matrix Control 5 " #$%& www.ti.com SBOS308B − AUGUST 2004 − REVISED NOVEMBER 2004 WRITE/READ TIMING Generally follows SP1 Timing Specification: D D D D D All writes and reads will be 8 bytes at a time; Separate write and read data lines; Reads will follow the same bit stream pattern seen in the write cycle; Reads will extract data from the FIFO, not the latched register; DOUT data is continuously available and need not be enabled with a read cycle. Selecting a read cycle in the control register only prevents latching of data. The control register is still latched. WRITE CYCLE TIMING t0 t1 CLK 1 2 39 40 t3 t2 t4 t5 CS t7 LSB DATA 1 6 MSB t6 t0 = t1 = 12.5ns minimum t2 = t3 = t4 = t5 = t7 = 2ns minimum t6 = 1ns minimum NOTE: It is highly recommended that the clock be turned off after the required data has been programmed into the VCA8617. SERIAL PORT TIMING TABLE Chip Select (CS) must be held low (active LOW) during transfer. CS can be held permanently low. PARAMETER t1 t2 t3 t4 t5 t6 t7 6 DESCRIPTION Serial CLK Period Serial CLK HIGH Time Serial CLK LOW Time CS Falling Edge to Serial CLK Falling Edge Data Setup Time Data Hold Time Serial CLK Falling Edge to CS Rising Edge MIN 40 13 13 10 5 5 10 TYP MAX UNITS ns ns ns ns ns ns ns " #$%& www.ti.com SBOS308B − AUGUST 2004 − REVISED NOVEMBER 2004 DATA SHIFT SEQUENCE Shift Direction DIN MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB Table 1. Maximum Attenuation. DOUT Table 2. PGA Gain Settings. A1, A0 MAXIMUM ATTENUATION PG1, PG0 PGA GAIN 0, 0 29dB 00 25dB 0, 1 33dB 01 30dB 1, 0 36.5dB 10 35dB 1, 1 40dB 11 40dB Table 3. CW Coding for Each Channel. CHANNEL CW CODING (MSB, LSB) 0 0000 Output 0 1 0001 Output 1 2 0010 Output 2 3 0011 Output 3 4 0100 Output 4 5 0101 Output 5 6 0110 Output 6 7 0111 Output 7 8 1000 Output 8 9 1001 Output 9 10 1010 Channel tied to +V (internal) 11 1011 Channel tied to +V (internal) 12 1100 Channel tied to +V (internal) 13 1101 Channel tied to +V (internal) 14 1110 Channel tied to +V (internal) 15 1111 Channel tied to +V (internal) CHANNEL DIRECTED TO: Applies to bytes 2 through 5. 7 " #$%& www.ti.com SBOS308B − AUGUST 2004 − REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS: AVDD = 3V At TA = +25°C, load resistance = 1kΩ on each output to ground, unless otherwise noted. The input to the preamp (LNA) is single-ended; pre-amp gain is fixed at +20dB, fIN = 2MHz, PG = 01, ATN = 00, and the output from the VCA is differential, unless otherwise noted. GAIN vs VCACNTRL (PG = 01) 60 55 55 50 50 45 45 40 40 ATN = 00 35 30 Gain (dB) Gain (dB) GAIN vs VCACNTRL (PG = 00) ATN = 01 25 35 ATN = 01 30 25 ATN = 11 20 20 15 15 10 ATN = 10 10 ATN = 11 5 5 ATN = 10 0 0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 VCACNTRL (V) VCACNTRL (V) GAIN vs VCACNTRL (PG = 10) GAIN vs VCACNTRL (PG = 11) 60 55 ATN = 00 50 40 ATN = 01 35 30 ATN = 11 25 Gain (dB) 45 Gain (dB) ATN = 00 20 15 ATN = 10 10 5 0 65 60 55 50 45 40 35 30 25 20 15 10 5 0 ATN = 00 ATN = 01 ATN = 11 ATN = 10 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 VCACNTRL (V) VCACNTRL (V) GAIN ERROR vs VCNTRL (PG = 01) 2.0 2.0 1.5 1.5 1.0 1.0 0.5 ATN = 01 ATN = 00 0 ATN = 10 − 0.5 − 1.0 Gain Error (dB) Gain Error (dB) GAIN ERROR vs VCNTRL (PG = 00) 0.5 ATN = 01 ATN = 00 0 ATN = 11 − 0.5 ATN = 10 − 1.0 − 1.5 − 1.5 ATN = 11 − 2.0 8 − 2.0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 VCNTRL (V) VCNTRL (V) " #$%& www.ti.com SBOS308B − AUGUST 2004 − REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS: AVDD = 3V (continued) At TA = +25°C, load resistance = 1kΩ on each output to ground, unless otherwise noted. The input to the preamp (LNA) is single-ended; pre-amp gain is fixed at +20dB, fIN= 2MHz, PG = 01, ATN = 00, and the output from the VCA is differential, unless otherwise noted. GAIN ERROR vs VCNTRL (PG = 11) GAIN ERROR vs VCNTRL (PG = 10) 2.0 2.0 1.5 1.5 0.5 ATN = 01 1.0 ATN = 01 Gain Error (dB) Gain Error (dB) 1.0 ATN = 00 0 − 0.5 ATN = 11 ATN = 00 0.5 0 − 0.5 ATN = 10 − 1.0 − 1.0 − 1.5 − 1.5 ATN = 10 ATN = 11 − 2.0 − 2.0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 VCNTRL (V) VCNTRL (V) GAIN ERROR vs VCACNTRL GAIN ERROR vs VCNTRL 2.0 10MHz 1.5 5MHz 0.5 Gain (dB) Gain Error (dB) 1.0 2MHz 0 − 0.5 − 1.0 − 1.5 +85°C +25°C −40°C 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 VCNTRL (V) VCACNTRL (V) TIME GAIN CONTROL (TGC) CURRENT vs TEMPERATURE CONTINUOUS WAVE (CW) CURRENT vs TEMPERATURE 220 285 284 283 282 281 280 279 278 277 276 275 274 273 272 271 270 269 268 218 216 CW Current (mA) TGC Current (mA) − 2.0 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 − 0.2 − 0.4 − 0.6 − 0.8 − 1.0 − 1.2 − 1.4 − 1.6 − 1.8 − 2.0 214 212 210 208 206 204 202 200 198 196 − 40 − 20 0 20 40 Temperature (°C) 60 80 − 40 − 20 0 20 40 60 80 Temperature (°C) 9 " #$%& www.ti.com SBOS308B − AUGUST 2004 − REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS: AVDD = 3V (continued) At TA = +25°C, load resistance = 1kΩ on each output to ground, unless otherwise noted. The input to the preamp (LNA) is single-ended; pre-amp gain is fixed at +20dB, fIN= 2MHz, PG = 01, ATN = 00, and the output from the VCA is differential, unless otherwise noted. GAIN MATCH (VCNTRL = 1.7V) 140 120 120 100 100 80 80 Units 140 60 40 40 20 20 0 0 0.02 0.11 0.21 0.30 0.39 0.49 0.58 0.67 0.77 0.86 0.95 1.05 1.14 1.23 − 0.81 −0.75 −0.68 −0.62 −0.55 − 0.48 −0.42 −0.35 −0.28 −0.22 − 0.15 −0.08 0.05 0.12 0.18 0.25 0.32 0.38 0.45 0.52 0.58 0.65 0.71 0.78 0.85 0.91 0.98 60 − 1.28 − 1.19 − 1.10 − 1.00 − 0.91 − 0.82 − 0.72 − 0.63 − 0.54 − 0.44 − 0.35 − 0.26 − 0.16 − 0.07 Units GAIN MATCH (VCNTRL = 0.2V) Delta Gain (dB) Delta Gain (dB) GAIN vs FREQUENCY (ATN = 00, VCNTRL = 0.2V) CW ACCURACY 900 800 700 Gain (dB) Units 600 500 400 300 200 100 0 50 45 40 35 30 25 20 15 10 5 0 −5 − 10 − 15 PG = 11 PG = 10 PG = 00 PG = 01 18.1 18.2 18.3 18.4 18.5 18.7 18.8 18.9 19.0 19.1 19.3 19.4 19.5 19.6 19.7 19.9 20.0 20.1 20.2 20.3 20.5 20.6 20.7 20.8 20.9 21.1 21.2 21.3 0.1 1 10 100 Frequency (MHz) Transconductance (mA/V) OUTPUT−REFERRED NOISE vs VCACNTRL (ATN = 00, fIN = 2MHz) GAIN vs FREQUENCY (ATN = 00, VCNTRL = 1.7V) 65 PG = 11 60 PG = 10 Noise (nV/√Hz) 55 Gain (dB) 50 45 40 35 PG = 01 PG = 00 30 25 20 0.1 1 10 Frequency (MHz) 10 100 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 PG = 11 PG = 10 PG = 01 PG = 00 0.2 0.4 0.6 0.8 1.0 1.2 VCACNTRL (V) 1.4 1.6 1.8 2.0 " #$%& www.ti.com SBOS308B − AUGUST 2004 − REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS: AVDD = 3V (continued) At TA = +25°C, load resistance = 1kΩ on each output to ground, unless otherwise noted. The input to the preamp (LNA) is single-ended; pre-amp gain is fixed at +20dB, fIN= 2MHz, PG = 01, ATN = 00, and the output from the VCA is differential, unless otherwise noted. OUTPUT−REFERRED NOISE vs VCACNTRL (ATN = 00, fIN = 5MHz) INPUT−REFERRED NOISE vs VCACNTRL (ATN = 00, fIN = 2MHz) 1200 20 1100 1000 PG = 11 16 800 Noise (nV/√Hz) 900 Noise (nV/√Hz) PG = 00 18 PG = 11 PG = 10 700 600 500 PG = 01 400 300 14 12 10 PG = 01 8 6 PG = 10 4 200 2 100 PG = 00 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 2.0 0.2 0.4 0.6 0.8 42 PG = 00 1.6 1.8 2.0 1.6 1.8 2.0 PG = 01 39 Noise Figure (dB) Noise (nV/√Hz) 1.4 45 PG = 11 PG = 01 PG = 11 36 PG = 10 33 PG = 00 30 27 24 21 PG = 10 18 15 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.2 0.4 0.6 0.8 VCACNTRL (V) 1.0 1.2 1.4 VCACNTRL (V) NOISE FIGURE vs VCACNTRL (ATN = 00, f IN = 5MHz) OUTPUT−REFERRED NOISE vs VCACNTRL (ATN = 11, fIN = 2MHz) 45 1200 PG = 00 42 1100 PG = 11 39 1000 900 PG = 01 36 Noise (nV/√Hz) Noise Figure (dB) 1.2 NOISE FIGURE vs VCACNTRL (ATN = 00, f IN = 2MHz) INPUT−REFERRED NOISE vs VCACNTRL (ATN = 00, fIN = 5MHz) 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1.0 VCACNTRL (V) VCACNTRL (V) 33 30 27 PG = 10 24 21 800 700 600 PG = 11 500 PG = 10 400 300 PG = 01 200 100 18 PG = 00 0 15 0.2 0.4 0.6 0.8 1.0 1.2 VCACNTRL (V) 1.4 1.6 1.8 2.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VCACNTRL (V) 11 " #$%& www.ti.com SBOS308B − AUGUST 2004 − REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS: AVDD = 3V (continued) At TA = +25°C, load resistance = 1kΩ on each output to ground, unless otherwise noted. The input to the preamp (LNA) is single-ended; pre-amp gain is fixed at +20dB, fIN= 2MHz, PG = 01, ATN = 00, and the output from the VCA is differential, unless otherwise noted. INPUT−REFERRED NOISE vs VCACNTRL (ATN = 11, fIN = 2MHz) OUTPUT−REFERRED NOISE vs VCACNTRL (ATN = 11, fIN = 5MHz) 1100 80 1000 70 PG = 00 900 700 PG = 11 600 500 400 PG = 01 PG = 10 Noise (nV/√Hz) Noise (nV/√Hz) PG = 01 60 800 300 50 40 30 PG = 11 20 PG = 10 200 10 100 PG = 00 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 0.2 2.0 0.4 0.6 0.8 VCACNTRL (V) INPUT−REFERRED NOISE vs VCACNTRL (ATN = 11, fIN = 5MHz) PG = 01 50 Noise Figure (dB) Noise (nV/√Hz) 1.6 1.8 2.0 1.6 1.8 2.0 PG = 00 55 60 PG = 10 40 30 PG = 11 PG = 01 50 45 PG = 11 40 PG = 10 35 30 10 25 0 20 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.2 0.4 0.6 VCACNTRL (V) 0.8 1.0 1.2 1.4 VCACNTRL (V) NOISE FIGURE vs VCACNTRL (ATN = 11, f IN = 5MHz) INPUT−REFERRED NOISE (2MHZ, 2V VCNTRL) 55 1.25 AT00 PG = 00 PG = 01 51 AT11 1.20 Noise (nV/√Hz) 47 Noise Figure (dB) 1.4 60 PG = 00 43 1.2 NOISE FIGURE vs VCACNTRL (ATN = 11, f IN = 2MHz) 70 20 1.0 VCACNTRL (V) PG = 11 39 PG = 10 35 31 27 1.15 1.10 1.05 23 17 1.00 0.2 0.4 0.6 0.8 1.0 1.2 VCACNTRL (V) 12 1.4 1.6 1.8 2.0 PG 00 PG 01 PG 10 Gain Setting PG 11 " #$%& www.ti.com SBOS308B − AUGUST 2004 − REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS: AVDD = 3V (continued) At TA = +25°C, load resistance = 1kΩ on each output to ground, unless otherwise noted. The input to the preamp (LNA) is single-ended; pre-amp gain is fixed at +20dB, fIN= 2MHz, PG = 01, ATN = 00, and the output from the VCA is differential, unless otherwise noted. INPUT−REFERRED NOISE (5MHZ, 2V VCNTRL) INPUT−REFERRED NOISE (CW Output) 1.10 2.00 AT00 AT11 1.90 Noise (nV/√Hz) Noise (nV/√Hz) 1.80 1.05 1.70 1.60 1.50 1.40 1.30 1.20 1.10 1.00 1.00 PG 00 PG 01 PG 10 PG 11 1 − 30 − 30 − 35 − 35 − 40 − 40 − 45 − 45 − 50 2nd−Harmonic − 60 − 65 − 70 4 5 − 50 2nd−Harmonic − 55 − 60 − 65 − 70 3rd−Harmonic − 75 3rd−Harmonic − 75 − 80 − 80 1 10 1 Frequency (MHz) DISTORTION vs FREQUENCY (ATN = 00, PG = 10, VCNTL = 2.0V) DISTORTION vs FREQUENCY (ATN = 00, PG = 11, VCNTL = 2.0V) − 30 − 30 − 35 − 35 − 40 − 40 − 45 − 45 − 50 − 55 − 60 10 Frequency (MHz) Distortion (dB) Distortion (dB) 3 DISTORTION vs FREQUENCY (ATN = 00, PG = 01, VCNTL = 2.0V) Distortion (dBc) Distortion (dB) DISTORTION vs FREQUENCY (ATN = 00, PG = 00, VCNTL = 2.0V) − 55 2 Frequency (MHz) Gain Setting 2nd−Harmonic − 65 − 50 2nd−Harmonic − 55 − 60 − 65 3rd−Harmonic − 70 − 70 − 75 − 75 − 80 3rd−Harmonic − 80 1 10 Frequency (MHz) 1 10 Frequency (MHz) 13 " #$%& www.ti.com SBOS308B − AUGUST 2004 − REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS: AVDD = 3V (continued) At TA = +25°C, load resistance = 1kΩ on each output to ground, unless otherwise noted. The input to the preamp (LNA) is single-ended; pre-amp gain is fixed at +20dB, fIN= 2MHz, PG = 01, ATN = 00, and the output from the VCA is differential, unless otherwise noted. DISTORTION vs VCACNTRL (ATN = 01, PG = 10, fIN = 2MHz, 750mVPP) − 30 − 30 − 35 − 35 − 40 − 40 − 45 − 45 Distortion (dB) − 50 − 55 − 60 2nd−Harmonic − 65 − 50 − 55 − 60 2nd−Harmonic − 65 − 70 − 70 3rd−Harmonic − 75 3rd−Harmonic − 75 − 80 − 80 0.2 0.5 0.8 1.1 1.4 1.7 2.0 0.2 0.5 0.8 VCACNTRL (V) − 40 Distortion (dB) − 40 − 45 − 50 − 55 − 60 2nd−Harmonic − 65 − 45 − 50 − 55 − 60 − 70 − 70 2nd−Harmonic − 65 3rd−Harmonic 3rd−Harmonic − 75 − 75 0.8 1.1 1.4 1.7 2.0 VCACNTRL (V) VCACNTRL (V) DISTORTION vs VCACNTRL (ATN = 00, PG = 00, 500mVPP) 2nd−Harmonic DISTORTION vs VCACNTRL (ATN = 00, PG = 01, 500mVPP) 2nd−Harmonic − 30 − 35 − 35 − 40 − 40 − 45 10MHz − 50 − 55 − 60 5MHz − 65 − 70 Distortion (dB) − 30 − 45 1.7 1.8 1.9 2.0 0.5 0.2 0.3 0.4 0.5 0.6 0.7 0.2 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 − 80 − 80 10MHz − 50 − 55 5MHz − 60 2MHz − 65 − 70 1MHz 2MHz − 75 1MHz VCACNTRL (V) VCACNTRL (V) 1.7 1.8 1.9 2.0 1.7 1.8 1.9 2.0 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 − 80 0.2 0.3 0.4 0.5 0.6 0.7 − 80 0.2 0.3 0.4 0.5 0.6 0.7 Distortion (dB) 2.0 Under this test condition, at lower VCA control voltage, the LNA is overloaded. − 35 − 35 Distortion (dB) 1.7 − 30 − 30 14 1.4 DISTORTION vs VCACNTRL (ATN = 11, PG = 10, fIN = 2MHz, 750mVPP) DISTORTION vs VCACNTRL (ATN = 10, PG = 10, fIN = 2MHz, 750mVPP) − 75 1.1 VCACNTRL (V) 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 Distortion (dB) DISTORTION vs VCACNTRL (ATN = 00, PG = 10, fIN = 2MHz, 750mVPP) " #$%& www.ti.com SBOS308B − AUGUST 2004 − REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS: AVDD = 3V (continued) At TA = +25°C, load resistance = 1kΩ on each output to ground, unless otherwise noted. The input to the preamp (LNA) is single-ended; pre-amp gain is fixed at +20dB, fIN= 2MHz, PG = 01, ATN = 00, and the output from the VCA is differential, unless otherwise noted. DISTORTION vs VCACNTRL (ATN = 00, PG = 10, 500mVPP) 2nd−Harmonic DISTORTION vs VCACNTRL (ATN = 00, PG = 11, 500mVPP) 2nd−Harmonic − 30 − 30 − 35 − 35 − 40 10MHz − 45 − 50 − 55 − 60 5MHz 2MHz − 65 Distortion (dB) − 60 1MHz VCACNTRL (V) VCACNTRL (V) DISTORTION vs VCACNTRL (ATN = 00, PG = 00, 500mVPP) 3rd−Harmonic DISTORTION vs VCACNTRL (ATN = 00, PG = 01, 500mVPP) 3rd−Harmonic − 30 − 35 − 35 − 40 1.7 1.8 1.9 2.0 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 0.2 0.3 0.4 0.5 0.6 0.7 1.7 1.8 1.9 2.0 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 0.2 0.3 0.4 0.5 0.6 0.7 − 80 − 30 − 40 Distortion (dB) 2MHz − 50 10MHz − 55 − 60 5MHz − 45 − 50 10MHz − 55 − 60 5MHz − 65 − 70 2MHz 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1MHz 0.2 0.3 0.4 0.5 0.6 0.7 − 80 1.7 1.8 1.9 2.0 − 80 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 − 75 0.2 0.3 0.4 0.5 0.6 0.7 − 75 VCNTRL (V) VCNTRL (V) DISTORTION vs VCACNTRL (ATN = 00, PG = 10, 500mVPP) 3rd−Harmonic DISTORTION vs VCACNTRL (ATN = 00, PG = 11, 500mVPP) 3rd−Harmonic − 30 − 35 − 35 − 40 − 40 − 45 − 45 − 50 Distortion (dB) − 30 10MHz − 55 − 60 5MHz − 65 − 50 − 60 − 70 2MHz 5MHz 2MHz − 75 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 VCACNTRL (V) 1.7 1.8 1.9 2.0 1MHz − 80 1MHz − 80 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 − 75 10MHz − 55 − 65 − 70 1.7 1.8 1.9 2.0 1MHz 1.7 1.8 1.9 2.0 − 65 − 70 5MHz 2MHz − 75 1MHz − 80 Distortion (dB) − 55 − 70 − 75 Distortion (dB) − 50 − 65 − 70 − 45 10MHz − 45 0.2 0.3 0.4 0.5 0.6 0.7 Distortion (dB) − 40 VCACNTRL (V) 15 " #$%& www.ti.com SBOS308B − AUGUST 2004 − REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS: AVDD = 3V (continued) At TA = +25°C, load resistance = 1kΩ on each output to ground, unless otherwise noted. The input to the preamp (LNA) is single-ended; pre-amp gain is fixed at +20dB, fIN= 2MHz, PG = 01, ATN = 00, and the output from the VCA is differential, unless otherwise noted. CROSSTALK vs VCNTRL (ATN = 00, fIN = 5MHz) CH4 to CH5 − 30 − 35 − 35 − 40 − 40 PG10 − 50 − 55 − 60 PG = 01 − 50 − 65 − 70 − 70 0.2 0.3 0.4 0.5 0.6 0.7 1.7 1.8 1.9 2.0 − 65 0.2 0.3 0.4 0.5 0.6 0.7 PG = 00 PG = 01 − 55 − 60 PG = 00 VCNTRL (V) VCNTRL (V) CROSSTALK vs VCNTRL (ATN = 00, fIN = 10MHz) CH4 to CH5 CROSSTALK vs VCNTRL (ATN = 11, PG11) CH4 to CH5 − 30 − 35 PG10 PG11 5MHz − 40 − 45 Crosstalk (dB) − 40 PG = 00 PG = 01 − 50 − 55 − 45 − 50 − 55 − 65 − 70 − 70 2MHz 0.2 0.3 0.4 0.5 0.6 0.7 − 65 1.7 1.8 1.9 2.0 − 60 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 − 60 0.2 0.3 0.4 0.5 0.6 0.7 10MHz VCNTRL (V) VCNTRL (V) INPUT IMPEDANCE 5000 0 4500 −10 4000 −20 3500 −30 Phase (_) Magnitude INPUT IMPEDANCE 3000 2500 2000 −40 −50 −60 1500 1000 −70 500 −80 −90 0 0.1 1 10 Frequency (MHz) 16 1.7 1.8 1.9 2.0 − 35 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 − 30 Crosstalk (dB) − 45 1.7 1.8 1.9 2.0 PG11 PG10 PG11 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 − 45 Crosstalk (dB) − 30 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 Crosstalk (dB) CROSSTALK vs VCNTRL (ATN = 00, fIN = 2MHz) CH4 to CH5 100 0.1 1 10 Frequency (MHz) 100 " #$%& www.ti.com SBOS308B − AUGUST 2004 − REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS: AVDD = 3V (continued) At TA = +25°C, load resistance = 1kΩ on each output to ground, unless otherwise noted. The input to the preamp (LNA) is single-ended; pre-amp gain is fixed at +20dB, fIN= 2MHz, PG = 01, ATN = 00, and the output from the VCA is differential, unless otherwise noted. OVERLOAD RECOVERY vs TIME (ATN = 00, PG = 00, VCNTRL = 1V) Channel 1 (Output) (2V/div) OVERLOAD RECOVERY vs TIME (ATN = 00, PG = 01, VCNTRL = 2V) Channel 1 (Output) (2V/div) The signal is 40mVPP input, so the LNA is in the linear region and the output amplifier is overloaded. Overload recovery time is 456ns. External time constant is 560ns. The signal is greater than 2VPP input, so the LNA is severely overloaded. Overload recovery time is 480ns. External time constant is 560ns. Channel 2 (Input) (20mV/div) Channel 2 (Input) (1V/div) Time (400ns/div) Time (400ns/div) 17 " #$%& www.ti.com SBOS308B − AUGUST 2004 − REVISED NOVEMBER 2004 APPLICATIONS INFORMATION NOTE: For current users of the VCA8613 who are switching to the VCA8617, pin 32 of the VCA8617 is a VDD reference pin and requires a minimum 0.1µF bypass capacitor to ground. conversion accomplished within the LNA itself. The output of the LNA is limited to a little over 2V differential swing. This implies a maximum input voltage swing of approximately 200mV to be operating in the linear range at 5MHz. Larger input signals can be accepted by the LNA, but distortion performance will degrade with high-level input signals. INPUT CIRCUIT The input of the VCA8617 integrates several commonly-used elements. Prior to reaching the input of the VCA, the receive signal should be coupled with a capacitor of at least 1nF (preferably more). When this AC-coupling element is inserted, the LNA input bias point is held to a common-mode value of 2.4V by an integrated 4.5kΩ resistor. This common-mode value will change with temperature and may also vary from chip to chip, but for each chip, it will be held constant. In parallel with this resistor are two back-to-back clipping diodes. These diodes prevent excessive input voltages from passing through to the LNA input, preventing deep saturation effects in the LNA itself. LOW-NOISE PRE-AMPLIFIER (LNA) The VCA8617 integrates a low-noise pre-amplifier. Because of the high level of integration in the system, noise performance was traded for power consumption, resulting in an extremely low-power pre-amplifier, with 0.8nV/√Hz noise performance at 5MHz. The LNA is configured as a fixed-gain 20dB amplifier. Of this total gain, 6dB results from the single-ended to differential CW DOPPLER PROCESSOR The VCA8617 integrates many of the elements necessary to allow for the implementation of a simple CW Doppler processing circuit. One circuit that was integrated was a V/I converter following the LNA (see Figure 1). The V/I converter converts the differential LNA voltage output to a current, which is then passed through an 8x10 switch matrix (see Figure 2). Within this switch matrix, any of the eight LNA outputs can be connected to any of ten CW output pins. This is a simple current−summing circuit, such that each CW output can represent the sum of any or all the channel currents. The transconductance of the V/I converter is approximately 20mA/V relative to the LNA input. For proper operation of the CW Doppler Processor, it is mandatory to have a bias on the output/outputs that are selected (see Figure 3). The CW output common-mode is 1.4V. The CW outputs are typically routed to a passive delay line, allowing coherent summing of the signals. After summing, IQ separation and down conversion to base band precedes a pair of high-resolution, low sample rate ADCs. VCM = 1.5V Buffer Input 1 Cross Point Switch LNA 20dB Buffer VCM = 1.5V Figure 1. Basic CW Processing Block Diagram. 18 Control Logic CW Output " #$%& www.ti.com SBOS308B − AUGUST 2004 − REVISED NOVEMBER 2004 V/I Converter Channel 1 Input CW0 CW1 SDI CW2 CW3 Decode Logic CLK CW4 CW5 CW6 SDO CW7 CW8 CW9 +V V/I Converter Channel 8 Input SDI Decode Logic SDO Figure 2. Basic CW Cross-point Switch Matrix for All Eight Channels. R To CW Circuitry CW Output OPA 1.2V to 1.6V Figure 3. Operational Amplifier. 19 " #$%& www.ti.com SBOS308B − AUGUST 2004 − REVISED NOVEMBER 2004 VOLTAGE-CONTROLLED ATTENUATOR (VCA)—DETAIL The VCA is designed to have a dB-linear attenuation characteristic; that is, the gain loss in dB is constant for each equal increment of the VCACNTRL control voltage. Figure 4 shows a block diagram of the VCA. The attenuator is essentially a variable voltage divider consisting of one series input resistor, RS, and ten identical shunt FETs, placed in parallel and controlled by sequentially-activated clipping amplifiers. Each clipping amplifier can be thought of as a specialized voltage comparator with a soft transfer characteristic and well-controlled output limit voltages. The reference voltages V1 through V10 are equally spaced over the 0V to 1.8V control voltage range. As the control voltage rises through the input range of each clipping amplifier, the amplifier output will rise from 0V (FET completely ON) to VCM _ VT (FET nearly OFF), where VCM is the common source voltage and VT is the threshold voltage of the FET. As each FET approaches its OFF state and the control voltage continues to rise, the next clipping amplifier/FET combination takes over for the next portion of the piecewise-linear attenuation characteristic. Thus, low control voltages have most of the FETs turned ON, while high control voltages have most turned OFF. Each FET acts to decrease the shunt resistance of the voltage divider formed by RS and the parallel FET network. The attenuator is comprised of two sections, with five parallel clipping amplifier/FET combinations in each. Special reference circuitry is provided so that the (VCM − VT) limit voltage will track temperature and IC process variations, minimizing the effects on the attenuator control characteristic. In addition to the analog VCACNTRL gain setting input, the attenuator architecture provides digitally- programmable adjustment in eight steps, via the two attenuation bits. These adjust the maximum achievable gain (corresponding to minimum attenuation in the VCA, with VCACNTRL = 1.8V) in 5dB increments. This function is accomplished by providing multiple FET sub−elements for each of the Q1 to Q10 FET shunt elements (see Figure 5). In the simplified diagram of Figure 4, each shunt FET is shown as two sub-elements, QNA and QNB. Selector switches, driven by the MGS bits, activate either or both of the sub-element FETs to adjust the maximum RON and thus achieve the stepped attenuation options. The VCA can be used to process either differential or single-ended signals. Fully differential operation will reduce 2nd-harmonic distortion by about 10dB for full-scale signals. Input impedance of the VCA will vary with gain setting, because of the changing resistances of the programmable voltage divider structure. At large attenuation factors (that is, low gain settings), the impedance will approach the series resistor value of approximately 120Ω. As with the LNA stage, the VCA output is AC-coupled into the PGA. This means that the attenuation- dependent DC common-mode voltage will not propagate into the PGA, and so the PGA DC output level will remain constant. Finally, note that the VCACNTRL input consists of FET gate inputs. This provides very high impedance and ensures that multiple VCA8617 devices may be connected in parallel with no significant loading effects. The nominal voltage range for the VCACNTRL input spans from 0V to 1.8V. Overdriving this input ( > 3V) does not affect the performance. PGA POST-AMPLIFIER Figure 6 shows a simplified circuit diagram of the PGA. PGA gain is programmed through the serial port, and can be configured to 24 different gain settings of 24dB, 29dB, 34dB, and 39dB, as shown in Table 4. A patented circuit has been implemented in the PGA that allows for exceptional overload signal recovery. Table 4. PGA Gain Settings. PGA GAIN 00 25 01 30 10 35 11 40 RS OUTPUT INPUT Q1A Q1B Q2A Q2B Q3A Q3B Q4 A VCM A0 A1 Figure 4. Programmable Attenuator Section. 20 Q4B Q5 A Q5B " #$%& www.ti.com SBOS308B − AUGUST 2004 − REVISED NOVEMBER 2004 Attenuator Input RS A1−A10 Attenuator Stages Attenuator Output QS Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q 10 V CM A1 A2 C1 A3 C2 V1 A4 C3 V2 A5 C4 V3 A6 A7 C5 V4 V5 C ontrol Input A8 C6 V6 A9 C7 A10 C8 V7 C9 V8 V9 C 10 V10 C 1−C 10 Clipping Amplifiers 0dB − 4dB Attenuation C haracteristic of Individual FETs V CM−V T 0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 Characteristic of Attenuator Control Stage Output Overall Control Characteristics of Attenuator 0dB − 40dB 0.2V Control Signal 1.8V Figure 5. Piecewise Approximation to Logarithmic Control Characteristics. 21 " #$%& www.ti.com SBOS308B − AUGUST 2004 − REVISED NOVEMBER 2004 OUTPUT FILTER SERIAL INTERFACE The VCA8617 integrates a two-pole, 15MHz low-pass Butterworth filter in the output stage. The cutoff frequency is implemented with passive semiconductor elements and as such, the cutoff frequency will not be precise. The output pins of the VCA8617, as shown in Figure 6, nominally sit at approximately 1.5VDC. However, this DC voltage varies slightly over PG gain settings as well as from chip to chip as a result of process variations. For users who cannot tolerate this slight variation, an AC coupling capacitor is recommended between the VCA outputs and the ADC inputs. The smaller the value of this capacitor, the better, because it reduces the pulse signal settling time. For the typical performance charts in this datasheet, a 560pF capacitor was used. The serial interface of the VCA8617 allows flexibility in the use of the part. The following parameters are set from the serial control registers: D Mode − TGC Mode − CW Mode D Attenuation Range D PGA Gain D Power-Down (this is the default state in which the VCA8617 initializes) D CW Output Selection For Each Input Channel The serial interface uses an SPI style of interface format. The Input Register Bit Maps (see page 5) show the functionality of each control register. 2MΩ V CM OUT+ 80pF V CM Attenuator 80pF OUT− V CM 2MΩ Figure 6. Simplified PGA and Output Filter Circuit. 22 " #$%& www.ti.com SBOS308B − AUGUST 2004 − REVISED NOVEMBER 2004 maintained. The analog ground should be a solid plane. Power-supply decoupling and decoupling of the control voltage (VCACNTRL) pin are essential in order to ensure that the noise performance be maintained. For further help in determining basic values, please refer to Figure 7. LAYOUT CONSIDERATIONS The VCA8617 is a multi-channel amplifier capable of high gains that has integrated digital controls. Layout of the VCA8617 is fairly straightforward. By connecting all of the grounds (including the digital grounds) to the analog ground, noise performance will help to be J 27 V CNTRL 1 C 39 0.1µ F NOTE : (1) 0.1µF cap acitor (2) 2.2µF capacitor (1) (2) (2) (1) (1) (1) (1) (1) (1) (1) C 54 2.2µ F +3V C 83 0.1µ F 5 12 10 6 30 60 AV DD V CM 53 32 28 AV DD CW 6 V CA8617 63 1 3 14 16 18 20 62 64 IN8 CW 7 IN7 CW 5 IN6 CW 3 IN5 CW 1 IN4 OUT 8 IN3 OUT 8 IN2 OUT 7 IN1 OUT 7 A GND OUT 6 A GND 2 4 13 15 17 A GND OUT 5 A GND OUT 5 A GND OUT 4 A GND OUT 4 A GND 19 57 56 55 26 25 24 23 22 48 47 46 45 44 43 OUT 6 42 41 40 39 38 OUT 3 C 84 0.1µ F 51 58 CW 9 C 55 2.2µ F 29 59 CW 8 C W0 C 56 2.2µF C 85 0.1µF C W2 C W4 C W6 C W8 C W9 C W7 C W5 C W3 C W1 O UT8 O UT8 O UT7 O UT7 O UT6 O UT6 O UT5 O UT5 O UT4 O UT4 O UT3 O UT 3 37 OUT2 O UT 2 36 35 O UT 1 A GND 34 Input 1 CS OUT1 Input 2 CW 4 33 Input 3 DIN A GND Input 4 CW 2 A GND Input 5 CLK A GND Input 6 CW 0 DGND 61 27 Input 7 DOUT DGND 11 Input 8 V LNA 54 CS 9 DV DD GND R DIN 8 V FIL 50 CLK U 15 DV DD 31 DOUT 7 V DDR 21 AV DD 49 V REF AV DD +3V Figure 7. Basic Connection Diagram. 23 PACKAGE OPTION ADDENDUM www.ti.com 9-Dec-2004 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty VCA8617PAGR ACTIVE TQFP PAG 64 1500 None CU SNPB Level-3-240C-168 HR VCA8617PAGT ACTIVE TQFP PAG 64 250 None CU SNPB Level-3-240C-168 HR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. 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Addendum-Page 1 MECHANICAL DATA MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 48 0,08 M 33 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 1,05 0,95 0°– 7° 0,75 0,45 Seating Plane 0,08 1,20 MAX 4040282 / C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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