VCA8500
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SBOS390A – JANUARY 2008 – REVISED MARCH 2008
8-Channel, Ultralow-Power, Variable Gain Amplifier
with Low-Noise Pre-Amp
FEATURES
APPLICATIONS
• Ultralow Power: 65mW/Channel
• Low Noise: 0.8nV/√Hz
• Low-Noise Pre-Amp (LNP):
– 20dB Fixed Gain
– 250mVPP Linear Input Range
• Variable Gain Amplifier:
– Gain Control Range: 46dB
– Selectable PGA Gain:
20dB, 25dB, 27dB, 30dB
– Fast Overload Recovery
– Output Clamping Control
• Integrated Low-Pass Filter:
– Second-Order, Linear Phase
– Bandwidth: 10MHz, 15MHz
• High Accuracy:
– Low Gain Error: ±0.5dB
– Excellent Channel Matching: ±0.25dB
• Distortion, HD2: –50dBc at 5MHz
• Integrated CW Switch Matrix:
– Easy Current Summing
• Serial Control Interface
• Small Package: QFN-64, 9×9mm
•
1
2345
SDI
LNA
IN
Logic
LNA
20dB
Medical Imaging, Ultrasound Systems
– Portable Systems
– Low- and Mid-Range Systems
DESCRIPTION
The VCA8500 is an 8-channel variable gain amplifier
consisting of a low-noise pre-amplifier (LNP) and a
variable-gain amplifier (VGA). This combination,
along with the device features, makes it ideal for a
variety of ultrasound systems.
The LNP gain is fixed at 20dB, and has excellent
noise and signal handling characteristics. The gain of
the voltage-controlled attenuator can vary over a
46dB range with a 0V to 1.2V control voltage
common to all channels of the VCA8500.
The post-gain amplifier (PGA) can be programmed
for four gain settings: 20dB, 25dB, 27dB, or 30dB
gain. As a means to improve system overload
recovery time, the VCA8500 provides an internal
clamping function. The PGA settings as well the
clamp levels are controlled through the serial
interface.
The VCA8500 is built on TI’s BiCOM process and is
available in a small QFN-64 PowerPAD™ package.
CW Switch Matrix
(8 in ´ 10 out)
Attenuation
(46dB)
CW
OUT
(1)
PGA
Clamping
Circuit
LPF
(Twopole)
OUT
OUT
VCA8500
(1 of 8 Channels)
Gain
Control
NOTE (1): 20dB, 25dB, 27dB, or 30dB gain setting.
1
2
3
4
5
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
Infineon is a registered trademark of Infineon Technologies.
SPI is a trademark of Motorola.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
VCA8500
www.ti.com
SBOS390A – JANUARY 2008 – REVISED MARCH 2008
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION (1)
PRODUCT
PACKAGELEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
VCA8500
QFN-64
RGC
–40°C to +85°C
VCA8500
(1)
(2)
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
ECO
STATUS (2)
VCA8500IRGCT
Tape and Reel, 250
VCA8500IRGCR
Tape and Reel, 2000
Pb-Free,
Green
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Eco-Status information: Additional details including specific material content can be accessed at www.ti.com/leadfree
GREEN: Ti defines Green to mean Lead (Pb)-Free and in addition, uses less package materials that do not contain halogens, including
bromine (Br), or antimony (Sb) above 0.1% of total product weight.
N/A: Not yet available Lead (Pb)-Free; for estimated conversion dates, go to www.ti.com/leadfree.
Pb-FREE: Ti defines Lead (Pb)-Free to mean RoHS compatible, including a lead concentration that does not exceed 0.1% of total
product weight, and, if designed to be soldered, suitable for use in specified lead-free soldering processes.
NOTE
These packages conform to Lead-Free and Green Manufacturing Specifications.
ABSOLUTE MAXIMUM RATINGS (1) (2)
Over operating free-air temperature range, unless otherwise noted.
VCA8500
UNIT
Supply voltage range, AVDD1
PARAMETER
–0.3 to +3.9
V
Supply voltage range, AVDD2
–0.3 to +6
V
Supply voltage range, DVDD
–0.3 to +3.9
V
Voltage at analog inputs
–0.3 to (AVDD1 +0.3)
V
Voltage at digital inputs
–0.3 to (DVDD to +0.3)
V
Soldering temperature (lead, 5s) (3)
+260
°C
Maximum junction temperature (TJ), any condition (2)
+150
°C
Maximum junction temperature (TJ), continuous operation, long-term
reliability (2)
+125
°C
Storage temperature range, Tstg
–55 to +150
°C
Operating temperature range, TA
ESD rating
(1)
(2)
(3)
2
–40 to +85
°C
Human body model (HBM)
2000
V
Charged device model (CDM)
1000
V
Machine model (MM)
200
V
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the ground terminal, which is the exposed thermal pad of the package.
Both the part being reworked and the board must be baked out before rework to reduce the risk of delamination. Refer to Application
Note SLUA271 (available for download at www.ti.com) for recommended rework techniques.
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SBOS390A – JANUARY 2008 – REVISED MARCH 2008
ELECTRICAL CHARACTERISTICS
All specifications at TA = +25°C, AVDD2 = 5.0V, AVDD1 = DVDD = 3.3V; single-ended, ac-coupled (1µF) input configuration to the preamp
(LNA), fIN = 5MHz, VCNTL = 1.0V, PG = 30dB, clamp disabled (CL = 1), LPF = 15MHz, and RLOAD = 1kΩ on each output to ground, unless
otherwise noted.
VCA8500
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TEST
LEVEL (1)
dB
C
PREAMPLIFIER (LNA)
LNA gain
Single-ended input to differential output
20
Input voltage
Linear operation (THD ≤ –40dBc)
250
mVPP
C
Input voltage noise
At f = 2MHz
0.70
nV/√Hz
B
Input current noise
At f = 2MHz
3.0
pA/√Hz
B
Input bias voltage (VBL)
Internally generated
+2.4
V
B
Bandwidth
Small-signal, –3dB
55
MHz
C
Input resistance (2)
At f = 4MHz
8
kΩ
C
Input capacitance (2)
Including internal ESD and clamping diodes
30
pF
C
PGA = 30dB, RS = 0Ω, f = 2MHz
0.81
nV/√Hz
B
PGA = 20dB, RS = 0Ω, f = 2MHz
0.95
nV/√Hz
B
Noise figure
RS = 200Ω, f = 1MHz to 10MHz
1.1
dB
C
Group delay variation
1MHz to 10MHz
±3
ns
B
Overload recovery time
To within 1% of 2VPP output
(VCNTL = 0.54V), PGA = 20dB
80
ns
B
Output voltage (VOUT)
Differential, non-clipped
TGC SIGNAL PATH (LNA, VCA, PGA)
Input voltage noise
Output common-mode voltage (VCM)
2
VPP
B
+1.65
V
B
1
Ω
C
Output impedance
DC to 10MHz, single-ended,
either output
Output current
RL = 5Ω into VCM
±20
mA
B
Second-harmonic distortion
fIN = 5MHz, PGA = 20dB, VOUT = 1VPP
–50
–60
dBc
A
fIN = 5MHz, PGA = 30dB, VOUT = 2VPP
–42
–55
dBc
A
fIN = 5MHz, PGA = 20dB, VOUT = 1VPP
–48
–68
dBc
A
fIN = 5MHz, PGA = 30dB, VOUT = 2VPP
–40
Third-harmonic distortion
Two-tone intermodulation
Crosstalk, channel-to-channel
–50
dBc
A
f1 = 4.99MHz, f2 = 5.01MHz,
VCNTL = 1V; VOUT = 1VPP
–52
dBc
B
Worst case; PGA = 20dB, VCNTRL = 0.6V,
VOUT = 1VPP
–67
dBc
B
PGA = 30dB, VOUT = 1VPP
–66
dBc
B
10, 15
MHz
B
±15
%
B
150
kHz
C
FILTER
Low-pass filter (second-order)
–3dB point
Tolerance
High-pass filter (first-order, due to
internal ac coupling)
(1)
(2)
–3dB point, VCNTL = 1.2V
Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization
and simulation, not production tested. (C) Typical value only for information.
See Figure 29 of the Typical Characteristics.
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SBOS390A – JANUARY 2008 – REVISED MARCH 2008
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = +25°C, AVDD2 = 5.0V, AVDD1 = DVDD = 3.3V; single-ended, ac-coupled (1µF) input configuration to the preamp
(LNA), fIN = 5MHz, VCNTL = 1.0V, PG = 30dB, clamp disabled (CL = 1), LPF = 15MHz, and RLOAD = 1kΩ on each output to ground, unless
otherwise noted.
VCA8500
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TEST
LEVEL (1)
dB
A
ACCURACY
20, 25,
27, 30
Gain (PGA)
Selectable through SPI™
Total gain, maximum
LNA + PGA gain, VCNTL = 1.2V
dB
A
Gain range
VCNTL = 0V to 1.2V
46
dB
A
Gain range
VCNTL = 0.1V to 1.0V
40
dB
A
Gain slope
VCNTL = 0.1V to 1.0V
44.4
dB/V
A
Gain error, absolute
0V < VCNTL < 0.1V
±0.5
dB
A
dB
A
dB
A
0.1V < VCNTL < 1.0V
48
–1.5
49.5
±0.5
51
+1.5
1.0V < VCNTL < 1.2V
±0.5
Gain matching
Channel-to-channel
±0.25
±0.5
dB
A
Output offset voltage
Differential
–25
±1
+25
mV
A
Single-ended (3)
–50
±25
+50
mV
A
Clamp level (VOUT)
CL = 0
1.7
VPP
A
CL = 1 (clamp disabled)
2.8
VPP
B
GAIN CONTROL INTERFACE
Input voltage range (VCNTL)
Gain range = 46dB
Input resistance
Response time
VCNTL= 0V to 1.2V step;
to 90% signal level, VOUT = 1VPP
Gain control bandwidth
0 to 1.2
V
A
25
kΩ
C
0.5
µs
B
1.5
MHz
C
CW SIGNAL PATH
Output transconductance (V/I)
At VIN = 100mVPP
14
mA/V
A
14.5
mA/V
B
Dynamic CW output current, max
2.9
mAPP
B
Static CW output current (sink)
0.9
mA
B
B
At VIN = 200mVPP
16.4
18
Output common-mode voltage (VCM0)
Supplied externally
+2.5
V
Output compliance range
Symmetric around VCMO
±0.5
V
B
10
pF
C
Output capacitance
Output impedance
50
kΩ
C
1.15
nV/√Hz
B
At 2kHz offset from 2MHz CW carrier
+2
dB
B
At 2kHz offset from 5MHz CW carrier
+2
dB
B
Summing of eight channels (all modes)
[compared to ideal 0dB]
0.6
dB
B
Input voltage noise, CW mode
At f = 2MHz
Signal-dependent noise (RTO)
Output noise correlation factor
(3)
4
Deviation from ideal common-mode voltage (VCM = 1.65V).
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SBOS390A – JANUARY 2008 – REVISED MARCH 2008
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = +25°C, AVDD2 = 5.0V, AVDD1 = DVDD = 3.3V; single-ended, ac-coupled (1µF) input configuration to the preamp
(LNA), fIN = 5MHz, VCNTL = 1.0V, PG = 30dB, clamp disabled (CL = 1), LPF = 15MHz, and RLOAD = 1kΩ on each output to ground, unless
otherwise noted.
VCA8500
PARAMETER
DIGITAL INPUTS (SDI)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TEST
LEVEL (1)
VD
V
B
V
B
µA
A
(PD, DIN, DOUT, CLK, RST)
VIH, high-level input voltage
2.0
VIL, low-level input voltage
0
Input current
0.8
±10
Clock frequency (fCLK)
10k
20M
Hz
B
Input resistance
1
MΩ
C
Input capacitance
5
pF
C
POWER SUPPLY
Supply Voltages
AVDD1, DVDD
Operating
3.15
3.3
3.6
V
B
AVDD2
Operating
4.75
5
5.25
V
B
TGC mode (D5 = 1)
145
156
mA
A
CW mode (D5 = 0)
78
84
mA
A
IDVDD
TGC, CW mode
1.5
3
mA
A
IAVDD2
TGC mode
8
10
mA
A
CW mode
54
59
mA
A
All channels, TGC mode, no signal
522
570
mW
A
All channels, CW mode, no signal
533
575
mW
A
Supply Currents (4)
IAVDD1
Power dissipation, total
POWER-DOWN MODES
Standby Mode
PD (pin 49) = high
IAVDD1
18
mA
A
IDVDD
1.5
mA
A
IAVDD2
8
mA
A
Power dissipation
104
Power-down response time
mW
A
0.2
µs
C
50
µs
C
IAVDD1
1.5
mA
A
IDVDD
1.5
mA
A
IAVDD2
2
mA
A
Power dissipation
19
mW
A
Power-up response time (5)
PD to valid output (90% level)
Shut-Down Mode
D2 (PWR) = high
130
35
THERMAL CHARACTERISTICS
Temperature range
Thermal resistance, θJA
Thermal resistance, θJC
(4)
(5)
Ambient, operating
–40
Soldered pad; four-layer PCB
with thermal vias
+85
°C
22.5
°C/W
17.0
°C/W
Clamp enabled (D4 = 0).
See Figure 59 of the Typical Characteristics.
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SBOS390A – JANUARY 2008 – REVISED MARCH 2008
DEVICE INFORMATION
CW0
PD
CW2
CW1
CW4
CW3
D_IN
D_OUT
CLK
RST
CW5
DVDD
CW7
CW6
CW9
CW8
RGC PACKAGE
QFN-64
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VBL1
1
48
VBL5
IN1
2
47
IN5
AVDD1
3
46
AVDD1
IN2
4
45
IN6
VBL2
5
44
VBL6
VBL3
6
43
VBL7
IN3
7
42
IN7
VBL4
8
41
VBL8
VCA8500
TM
PowerPAD
(GND)
IN4
9
VCNTL
10
40
IN8
39
AVDD2
AVDD2
11
38
VB2
VB3
12
37
VB6
VB1
13
36
VB4
VB5
14
35
VREFH
VCM
15
34
VREFL
AVDD1
16
33
AVDD1
OUT8
OUT8
OUT7
OUT7
OUT6
OUT6
OUT5
OUT1
OUT5
OUT1
OUT2
OUT2
OUT3
OUT3
OUT4
OUT4
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Table 1. TERMINAL FUNCTIONS
TERMINAL
6
PIN NO.
NAME
1
VBL1
I/O
DESCRIPTION
2
IN1
3
AVDD1
4
IN2
5
VBL2
6
VBL3
7
IN3
8
VBL4
9
IN4
10
VCNTL
11
AVDD2
12
VB3
Internal bias voltage (+4.2V); bypass with 0.1µF capacitor (min)
13
VB1
Internal bias voltage (+2.4V); bypass with 2.2µF capacitor (1.0µF min)
14
VB5
Internal bias voltage (+2.4V); bypass with 0.1µF capacitor (min)
15
VCM
Internal common-mode voltage (+1.65V); bypass with 0.1µF capacitor (min)
16
AVDD1
17
OUT4
O
PGA output channel 4 (inverted)
18
OUT4
O
PGA output channel 4
LNA bias voltage (+2.4V); bypass with 0.1µF capacitor (min)
I
LNA input channel 1
+3.3V analog supply
I
LNA input channel 2
LNA bias voltage (+2.4V); bypass with 0.1µF capacitor (min)
LNA bias voltage (+2.4V); bypass with 0.1µF capacitor (min)
I
LNA input channel 3
LNA bias voltage (+2.4V); bypass with 0.1µF capacitor (min)
LNA input channel 4
I
Attenuator control voltage input (all channels)
+5V analog supply (VCA, CW)
+3.3V analog supply
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Table 1. TERMINAL FUNCTIONS (continued)
TERMINAL
PIN NO.
NAME
I/O
DESCRIPTION
19
OUT3
O
PGA output channel 3 (inverted)
20
OUT3
O
PGA output channel 3
21
OUT2
O
PGA output channel 2 (inverted)
22
OUT2
O
PGA output channel 2
23
OUT1
O
PGA output channel 1 (inverted)
24
OUT1
O
PGA output channel 1
25
OUT5
O
PGA output channel 5 (inverted)
26
OUT5
O
PGA output channel 5
27
OUT6
O
PGA output channel 6 (inverted)
28
OUT6
O
PGA output channel 6
29
OUT7
O
PGA output channel 7 (inverted)
30
OUT7
O
PGA output channel 7
31
OUT8
O
PGA output channel 8 (inverted)
32
OUT8
O
PGA output channel 8
33
AVDD1
34
VREFL
Clamp reference level low, 2.0V; bypass with 0.1µF capacitor (min)
35
VREFH
Clamp reference level high, 2.7V; bypass with 0.1µF capacitor (min)
36
VB4
Internal bias voltage (+2.4V); bypass with 0.1µF capacitor (min)
37
VB6
Internal bias voltage (+2.9V); bypass with 0.1µF capacitor (min)
38
VB2
Internal bias voltage (+2.7V); bypass with 0.1µF capacitor (min)
39
AVDD2
40
IN8
41
VBL8
42
IN7
43
VBL7
44
VBL6
45
IN6
46
AVDD1
47
IN5
48
VBL5
49
PD
I
Power-down pin for standby mode; 0 = normal operation, 1 = power down
50
CW0
O
CW channel 0 current output
51
CW1
O
CW channel 1 current output
52
CW2
O
CW channel 2 current output
53
CW3
O
CW channel 3 current output
54
CW4
O
CW channel 4 current output
55
D_IN
I
Serial data input
56
CLK
I
Clock input for serial interface
57
D_OUT
O
Serial data output
58
RST
I
Reset input; rising edge resets register to default values.
59
DVDD
60
CW5
CW channel 5 current output
61
CW6
CW channel 6 current output
62
CW7
CW channel 7 current output
63
CW8
CW channel 8 current output
64
CW9
CW channel 9 current output
—
GND
PowerPAD must be connected to the analog ground of the printed circuit board; use this ground for
bypass capacitor return ground.
+3.3V analog supply
+5V analog supply (VCA, CW)
I
LNA input channel 8
LNA bias voltage (+2.4V); bypass with 0.1µF capacitor (min)
I
LNA input channel 7
LNA bias voltage (+2.4V); bypass with 0.1µF capacitor (min)
I
LNA bias voltage (+2.4V); bypass with 0.1µF capacitor (min)
LNA input channel 6
+3.3V analog supply
I
LNA input channel 5
LNA bias voltage (+2.4V); bypass with 0.1µF capacitor (min)
+3.3V digital supply; connect to a low-noise analog supply plane (AVDD1)
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SBOS390A – JANUARY 2008 – REVISED MARCH 2008
FUNCTIONAL BLOCK DIAGRAM
DVDD
AVDD1
AVDD2
GND
D_IN
CW0
D_OUT
CW1
Serial Digital Interface (SDI)
and Logic
RST
CLK
CW2
CW3
PD
CW4
CW Switch Matrix
(8 in x 10 out)
CW5
CW6
CW7
8
V/I
CW8
CW9
IN1
VCA
LNA
PGA
Clamp
LPF
VBL1
OUT1
OUT1
IN2
VCA
LNA
PGA
Clamp
LPF
VBL2
OUT2
OUT2
IN3
VCA
LNA
PGA
Clamp
LPF
VBL3
OUT3
OUT3
IN4
VCA
LNA
PGA
Clamp
LPF
VBL4
OUT4
OUT4
IN5
VCA
LNA
PGA
Clamp
LPF
VBL5
OUT5
OUT5
IN6
VCA
LNA
PGA
Clamp
LPF
VBL6
OUT6
OUT6
IN7
VCA
LNA
PGA
Clamp
LPF
VBL7
OUT7
OUT7
IN8
VCA
LNA
PGA
Clamp
LPF
VBL8
OUT8
OUT8
Reference
VB1 VB2 VB3 VB4 VB5 VB6
8
VCNTL
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VREFH VREFL
VCM
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INPUT REGISTER BIT MAPS
Register Map
BYTE #1
BYTE #2
BYTE #3
BYTE #4
BYTE #5
D0:D7
D8:D11
D12:D15
D16:D19
D20:D23
D24:D27
D28:D31
D32:D35
D36:D39
Control
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
Table 2. Default Register Configuration
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
0
0
1
1
Table 3. Byte 1—Control Byte Register Map
BIT #
NAME
DESCRIPTION
D0 (LSB)
1
D1
R/W
Start bit; must be a ‘1’ (high); 40-bit countdown starts with first falling clock edge.
1 = Write, 0 = Read; read prevents latching of new data/bits. Control register remains
latched with previously loaded data.
D2
PWR
1 = Power-down mode enabled (shutdown).
D3
BW
Low-pass filter bandwidth setting (see Table 8)
D4
CL
Clamp level setting (see Table 8)
D5
Mode
1 = TGC mode, 0 = CW doppler mode (TGC powered down)
D6
PG0
LSB of PGA gain control (see Table 9)
D7 (MSB)
PG1
MSB of PGA gain control
BIT #
NAME
DESCRIPTION
D8 (LSB)
DB1:1
Channel 1, LSB of matrix control
D9
DB1:2
Channel 1, matrix control
D10
DB1:3
Channel 1, matrix control
D11
DB1:4
Channel 1, MSB of matrix control
D12
DB2:1
Channel 2, LSB of matrix control
D13
DB2:2
Channel 2, matrix control
D14
DB2:3
Channel 2, matrix control
D15 (MSB)
DB2:4
Channel 2; MSB of matrix control
Table 4. Byte 2—First Data Byte
Table 5. Byte 3—Second Data Byte
BIT #
NAME
DESCRIPTION
D16 (LSB)
DB3:1
Channel 3, LSB of matrix control
D17
DB3:2
Channel 3, matrix control
D18
DB3:3
Channel 3, matrix control
D19
DB3:4
Channel 3, MSB of matrix control
D20
DB4:1
Channel 4, LSB of matrix control
D21
DB4:2
Channel 4, matrix control
D22
DB4:3
Channel 4, matrix control
D23 (MSB)
DB4:4
Channel 4, MSB of matrix control
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Table 6. Byte 4—Third Data Byte
BIT #
NAME
DESCRIPTION
D24 (LSB)
DB5:1
Channel 5, LSB of matrix control
D25
DB5:2
Channel 5, matrix control
D26
DB5:3
Channel 5, matrix control
D27
DB5:4
Channel 5, MSB of matrix control
D28
DB6:1
Channel 6; LSB of matrix control
D29
DB6:2
Channel 6, matrix control
D30
DB6:3
Channel 6, matrix control
D31 (MSB)
DB6:4
Channel 6, MSB of matrix control
Table 7. Byte 5—Fourth Data Byte
BIT #
NAME
DESCRIPTION
D32 (LSB)
DB7:1
Channel 7, LSB of matrix control
D33
DB7:2
Channel 7, matrix control
D34
DB7:3
Channel 7, matrix control
D35
DB7:4
Channel 7, MSB of matrix control
D36
DB8:1
Channel 8; LSB of matrix control
D37
DB8:2
Channel 8, matrix control
D38
DB8:3
Channel 8, matrix control
D39 (MSB)
DB8:4
Channel 8, MSB of matrix control
Table 8. Clamp Level and LPF Bandwidth Setting
NAME
BW
CL
SETTING
FUNCTION
D3 = 0
Bandwidth set to 15MHz (default)
D3 = 1
Bandwidth set to 10MHz
D4 = 0
Clamps the output signal at 1.7VPP on each PGA output channel (default)
D4 = 1
Clamp transparent (disabled)
Table 9. PGA Gain Setting
10
PG1
PG0
0
0
FUNCTION
Set PGA gain to 20dB (default)
0
1
Set PGA gain to 25dB
1
0
Set PGA gain to 27dB
1
1
Set PGA gain to 30dB
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Table 10. CW Switch Matrix Control for Each Channel
DBn:4
(MSB)
DBn:3
DBn:2
DBn:1
(LSB)
0
0
0
0
Output CW0
0
0
0
1
Output CW1
0
0
1
0
Output CW2
0
0
1
1
Output CW3
0
1
0
0
Output CW4
0
1
0
1
Output CW5
0
1
1
0
Output CW6
0
1
1
1
Output CW7
1
0
0
0
Output CW8
1
0
0
1
Output CW9
1
0
1
0
Connected to AVDD2; channel disabled
1
0
1
1
Connected to AVDD2; channel disabled
1
1
0
0
Connected to AVDD2; channel disabled
1
1
0
1
Connected to AVDD2; channel disabled
1
1
1
0
Connected to AVDD2; channel disabled
1
1
1
1
Connected to AVDD2; channel disabled
LNA Input Channel Directed To:
V/I
Converter
Channel 1
Input
CW0
CW1
DIN
CLK
CW2
CW3
Decode
Logic
CW4
CW5
CW6
DOUT
CW7
CW8
CW9
AVDD2
(To Other Channels)
Figure 1. Basic CW Cross-Point Switch Matrix Configuration
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SERIAL DIGITAL INTERFACE (SDI)
•
•
•
•
•
•
All writes and reads are five bytes at a time. Each byte consists of 8 bits, for a total instruction set of 40 bits.
Data are latched on the falling edge of CLK.
Separate write (DIN) and read data (DOUT) lines.
Reads follow the same bitstream pattern seen in the write cycle.
Reads extract data from the FIFO buffer, not the latched register.
DOUT data are continuously available and do not need to be enabled with a read cycle. Selecting a read
cycle in the control register only prevents latching of data. The control register remains latched.
The Reset pin (RST) must be low in order to allow the register to update with new data. RST can be held low
permanently. To initiate a reset cycle, pull the RST pin high for at least 100ns.
•
TIMING INFORMATION
RST (Low)
t2
CLK
t3
DIN
D0 (LSB)
t1
t4
t5
D1
D2
D3
D5
D4
D6
D7 (MSB)
NOTE: This figure shows timing example for one data byte. A full register update cycle requires all five bytes (that is, 40 bits).
SERIAL PORT TIMING TABLE
12
PARAMETER
DESCRIPTION
MIN
t1
Serial CLK period
100
TYP
MAX
UNIT
ns
t2
Serial CLK HIGH time
40
ns
t3
Serial CLK LOW time
40
ns
t4
Data hold time
5
ns
t5
Data setup time
5
ns
RST
Reset pulse (L - H - L)
100
ns
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TYPICAL CHARACTERISTICS
All specifications at TA = +25°C, AVDD2 = 5.0V, AVDD1 = DVDD = 3.3V; single-ended, ac-coupled (1µF) input configuration
to the preamp (LNA), fIN = 5MHz, VCNTL = 1.0V, clamp disabled (CL = 1), LPF = 15MHz, and RLOAD = 1kΩ on each output to
ground, unless otherwise noted.
GAIN ERROR vs VCNTRL
0.50
27dB
0.25
30dB
Gain (dB)
Gain (dB)
GAIN vs VCNTRL (at PGA = X)
55
50
45
40
35
30
25
20
15
10
5
0
-5
-10
25dB
PGA = 30dB
0
PGA = 25dB
PGA = 27dB
-0.25
20dB
PGA = 20dB
-0.50
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
VCNTRL (V)
VCNTRL (V)
Figure 2.
Figure 3.
GAIN ERROR DRIFT vs VCNTRL
1.50
1.25
1.00
20dB at +85°C
0.75
30dB at -40°C
30dB at +25°C
30dB at +85°C
20dB at -40°C
20dB at +25°C
20dB at +85°C
Gain Error (dB)
Gain (dB)
GAIN vs VCNTRL OVER TEMPERATURE
55
50
45
40
35
30
25
20
15
10
5
0
-5
-10
0.50
0.25
30dB at +85°C
0
-0.25
-0.50
30dB at -40°C
-0.75
-1.00
20dB at -40°C
-1.25
-1.50
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
0
Figure 4.
Figure 5.
GAIN MATCHING vs VCNTRL
0.50
PGA = 20dB and 30dB
0.45
0.40
30dB at 2MHz
30dB at 5MHz
30dB at 10MHz
20dB at 2MHz
20dB at 5MHz
20dB at 10MHz
Gain Matching (dB)
Gain (dB)
GAIN vs VCNTRL OVER FREQUENCY
55
50
45
40
35
30
25
20
15
10
5
0
-5
-10
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
VCNTRL (V)
VCNTRL (V)
0.35
0.30
PGA = 30dB
0.25
0.20
0.15
PGA = 20dB
0.10
0.05
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
VCNTRL (V)
VCNTRL (V)
Figure 6.
Figure 7.
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SBOS390A – JANUARY 2008 – REVISED MARCH 2008
TYPICAL CHARACTERISTICS (continued)
All specifications at TA = +25°C, AVDD2 = 5.0V, AVDD1 = DVDD = 3.3V; single-ended, ac-coupled (1µF) input configuration
to the preamp (LNA), fIN = 5MHz, VCNTL = 1.0V, clamp disabled (CL = 1), LPF = 15MHz, and RLOAD = 1kΩ on each output to
ground, unless otherwise noted.
GAIN MATCH AT VCNTRL = 0.1V
GAIN MATCH AT VCNTRL = 0.6V
3000
3000
Channel-to-Channel
2000
2000
Units
2500
1500
1500
1000
500
500
0
0
-1.00
-0.91
-0.82
-0.72
-0.63
-0.54
-0.44
-0.35
-0.26
-0.16
-0.07
0.02
0.11
0.21
0.30
0.39
0.49
0.58
0.67
0.77
0.86
0.95
1.05
1000
-1.00
-0.91
-0.82
-0.72
-0.63
-0.54
-0.44
-0.35
-0.26
-0.16
-0.07
0.02
0.11
0.21
0.30
0.39
0.49
0.58
0.67
0.77
0.86
0.95
1.05
Units
Channel-to-Channel
2500
D Gain (dB)
D Gain (dB)
Figure 8.
Figure 9.
GAIN MATCH AT VCNTRL = 1.2V
2000
1800
CW ACCURACY
2500
Channel-to-Channel
1600
2000
CW Outputs
Units
1400
1200
1000
800
1500
1000
600
400
500
200
D Gain (dB)
TRANSCONDUCTANCE vs TEMPERATURE
Output Offset (mV)
Transconductance (mA/V)
16.25
16.00
15.75
15.50
35
60
85
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1.0
-1.1
-1.2
-1.3
-1.4
17.8
18.0
17.6
17.2
17.4
16.8
17.0
16.6
16.2
Differential
-40
Temperature (°C)
-15
10
35
60
85
Temperature (°C)
Figure 12.
14
16.4
OUTPUT OFFSET vs TEMPERATURE
16.50
10
15.8
Figure 11.
16.75
-15
16.0
Transconductance (mA/V)
Figure 10.
-40
15.6
15.2
15.0
15.4
0
-0.81
-0.75
-0.68
-0.62
-0.55
-0.48
-0.42
-0.35
-0.28
-0.22
-0.15
-0.08
-0.02
0.05
0.12
0.18
0.25
0.32
0.38
0.45
0.52
0.58
0.65
0.71
0.78
0.85
0.91
0.98
0
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
All specifications at TA = +25°C, AVDD2 = 5.0V, AVDD1 = DVDD = 3.3V; single-ended, ac-coupled (1µF) input configuration
to the preamp (LNA), fIN = 5MHz, VCNTL = 1.0V, clamp disabled (CL = 1), LPF = 15MHz, and RLOAD = 1kΩ on each output to
ground, unless otherwise noted.
CW CURRENT vs TEMPERATURE
+3.3VA
CW Current (mA)
TGC Current (mA)
TGC CURRENT vs TEMPERATURE
170
160
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
+3.3VD
+5V
-40
10
-15
35
60
85
+5V
+3.3VD
60
85
Figure 14.
Figure 15.
TOTAL POWER vs TEMPERATURE
FREQUENCY RESPONSE vs VCNTRL AT PGA = 20dB
(LPF = 15MHz and 10MHz)
Gain (dB)
CW Mode
530
520
TGC Mode
510
500
490
10
-15
35
60
85
50
45
40
35
30
25
20
15
10
5
0
-5
-10
-15
-20
-25
-30
15MHz
10MHz
1.0VCNTRL
0.7VCNTRL
0.4VCNTRL
0.1VCNTRL
1
0.1
100
10
Temperature (°C)
Frequency (MHz)
Figure 16.
Figure 17.
FREQUENCY RESPONSE vs VCNTRL AT PGA = 30dB
(LPF = 15MHz and 10MHz)
OUTPUT-REFERRED NOISE vs VCNTRL
250
Frequency = 2MHz
1.0VCNTRL
200
Noise (nV/ÖHz)
Gain (dB)
35
Temperature (°C)
540
50
45
40
35
30
25
20
15
10
5
0
-5
-10
-15
-20
10
-15
-40
550
Total Power (V)
+3.3VA
Temperature (°C)
560
-40
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
0.7VCNTRL
0.4VCNTRL
150
PGA = 30dB
100
PGA = 20dB
0.1VCNTRL
50
15MHz
10MHz
0
0.1
1
10
100
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
VCNTRL (V)
Frequency (MHz)
Figure 18.
Figure 19.
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TYPICAL CHARACTERISTICS (continued)
All specifications at TA = +25°C, AVDD2 = 5.0V, AVDD1 = DVDD = 3.3V; single-ended, ac-coupled (1µF) input configuration
to the preamp (LNA), fIN = 5MHz, VCNTL = 1.0V, clamp disabled (CL = 1), LPF = 15MHz, and RLOAD = 1kΩ on each output to
ground, unless otherwise noted.
OUTPUT-REFERRED NOISE vs VCNTRL
INPUT-REFERRED NOISE vs VCNTRL
250
120
Frequency = 5MHz
100
200
90
Noise (nV/ÖHz)
Noise (nV/ÖHz)
Frequency = 2MHz
110
150
PGA = 30dB
100
PGA = 20dB
80
PGA = 20dB
70
60
50
40
30
50
20
PGA = 30dB
10
0
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
VCNTRL (V)
Figure 20.
Figure 21.
INPUT-REFERRED NOISE vs VCNTRL
CURRENT NOISE vs FREQUENCY OVER RSOURCE
120
4.0
Frequency = 5MHz
110
Current Noise (pA/ÖHz)
90
Noise (nV/ÖHz)
VCNTRL = 1.2V
3.8
100
80
70
60
50
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
0
VCNTRL (V)
PGA = 20dB
40
30
RS = 1kW
3.6
3.4
RS = 200W
3.2
3.0
RS = 400W
2.8
2.6
2.4
20
10
2.2
PGA = 30dB
0
2.0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
Figure 23.
RS = 1kW
VCNTRL = 1.2V
RS = 400W
RS = 200W
RS = 50W
10
1
INPUT-REFERRED NOISE vs FREQUENCY OVER RS
Noise (nV/ÖHz)
Noise (nV/ÖHz)
OUTPUT-REFERRED NOISE vs FREQUENCY OVER RS
20
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
RS = 1kW
VCNTRL = 1.2V
RS = 400W
RS = 200W
RS = 50W
10
1
20
Frequency (MHz)
Frequency (MHz)
Figure 24.
16
20
Frequency (MHz)
Figure 22.
1500
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
10
1
VCNTRL (V)
Figure 25.
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TYPICAL CHARACTERISTICS (continued)
All specifications at TA = +25°C, AVDD2 = 5.0V, AVDD1 = DVDD = 3.3V; single-ended, ac-coupled (1µF) input configuration
to the preamp (LNA), fIN = 5MHz, VCNTL = 1.0V, clamp disabled (CL = 1), LPF = 15MHz, and RLOAD = 1kΩ on each output to
ground, unless otherwise noted.
NOISE FIGURE vs FREQUENCY OVER RS
INPUT-REFERRED NOISE
3.5
1.00
3.0
0.95
2MHz
2.5
Noise (nV/ÖHz)
2.0
RS = 1kW
1.5
1.0
RS = 200W
0.5
0.90
5MHz
0.85
0.80
0.75
PGA = 30dB
VCNTRL = 1.2V
0.70
0
20
10
1
Gain Setting (PGA)
Figure 26.
Figure 27.
MAGNITUDE AND PHASE vs FREQUENCY
100
12k
CW Output
80
10k
Magnitude (W)
Noise (nV/ÖHz)
INPUT-REFERRED NOISE vs FREQUENCY
1.30
1.28
1.26
1.24
1.22
1.20
1.18
1.16
1.14
1.12
1.10
1.08
1.06
1.04
1.02
1.00
60
40
8k
20
0
6k
-20
4k
Magnitude (ZIN)
-40
Phase
-60
2k
-80
10
1.0
0.1
0
100k
20
1M
Figure 28.
3RD HARMONIC vs FREQUENCY
-45
VOUT = 1VPP
VCNTRL = 1.2V
-50
-100
100M
Figure 29.
2ND HARMONIC vs FREQUENCY
-45
10M
Frequency (Hz)
Frequency (MHz)
VOUT = 1VPP
VCNTRL = 1.2V
-50
30dB
Distortion (dBc)
Distortion (dBc)
30dB
27dB
25dB
20dB
Frequency (MHz)
Phase (°)
Noise Figure (dB)
RS = 50W
RS = 400W
RS = 0W
VCNTRL = 1.2V
-55
27dB
-60
-65
25dB
20dB
-55
30dB
-60
27dB
-65
25dB
-70
-70
-75
-75
20dB
10
1
10
1
Frequency (MHz)
Frequency (MHz)
Figure 30.
Figure 31.
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TYPICAL CHARACTERISTICS (continued)
All specifications at TA = +25°C, AVDD2 = 5.0V, AVDD1 = DVDD = 3.3V; single-ended, ac-coupled (1µF) input configuration
to the preamp (LNA), fIN = 5MHz, VCNTL = 1.0V, clamp disabled (CL = 1), LPF = 15MHz, and RLOAD = 1kΩ on each output to
ground, unless otherwise noted.
2ND HARMONIC vs VCNTRL OVER PGA GAIN
-45
25dB
-55
30dB
27dB
-60
Frequency = 5MHz
VOUT = 1VPP
-50
Distortion (dBc)
-50
Distortion (dB)
3RD HARMONIC vs VCNTRL OVER PGA GAIN
-45
Frequency = 5MHz
VOUT = 1VPP
20dB
-65
-55
-60
30dB
27dB
-65
-70
-70
-75
-75
20dB
0.6
0.7
0.8
1.0
0.9
1.1
1.2
0.6
Figure 33.
10MHz
1.1
1.2
2ND HARMONIC vs VCNTRL OVER FREQUENCY
PGA = 20dB
VOUT = 1VPP
-55
2MHz
1.0
-45
5MHz
-65
PGA = 25dB
VOUT = 1VPP
10MHz
-50
Distortion (dB)
Distortion (dBc)
-50
-70
-55
5MHz
-60
2MHz
-65
-70
-75
-75
0.6
0.7
0.8
0.9
1.0
1.1
1.2
0.6
0.7
0.8
0.9
VCNTRL (V)
VCNTRL (V)
Figure 34.
Figure 35.
2ND HARMONIC vs VCNTRL OVER FREQUENCY
-45
1.1
1.2
2ND HARMONIC vs VCNTRL OVER FREQUENCY
-60
2MHz
5MHz
PGA = 30dB
VOUT = 1VPP
10MHz
-50
Distortion (dB)
-55
-65
1.0
-45
PGA = 27dB
VOUT = 1VPP
10MHz
-50
Distortion (dB)
0.9
Figure 32.
2ND HARMONIC vs VCNTRL OVER FREQUENCY
-55
-60
5MHz
-65
2MHz
-70
-70
-75
-75
0.6
18
0.8
VCNTRL (V)
-45
-60
0.7
VCNTRL (V)
25dB
0.7
0.8
0.9
1.0
1.1
1.2
0.6
0.7
0.8
0.9
VCNTRL (V)
VCNTRL (V)
Figure 36.
Figure 37.
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1.0
1.1
1.2
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TYPICAL CHARACTERISTICS (continued)
All specifications at TA = +25°C, AVDD2 = 5.0V, AVDD1 = DVDD = 3.3V; single-ended, ac-coupled (1µF) input configuration
to the preamp (LNA), fIN = 5MHz, VCNTL = 1.0V, clamp disabled (CL = 1), LPF = 15MHz, and RLOAD = 1kΩ on each output to
ground, unless otherwise noted.
3RD HARMONIC vs VCNTRL OVER FREQUENCY
-45
PGA = 20dB
VOUT = 1VPP
-55
10MHz
2MHz
-60
-65
PGA = 25dB
VOUT = 1VPP
-50
Distortion (dB)
-50
Distortion (dB)
3RD HARMONIC vs VCNTRL OVER FREQUENCY
-45
-70
-55
2MHz
-60
10MHz
-65
-70
5MHz
5MHz
-75
-75
0.6
0.7
0.8
1.0
0.9
1.1
1.2
0.6
0.7
0.8
1.0
0.9
VCNTRL (V)
VCNTRL (V)
Figure 38.
Figure 39.
3RD HARMONIC vs VCNTRL OVER FREQUENCY
-45
1.2
3RD HARMONIC vs VCNTRL OVER FREQUENCY
-45
PGA = 27dB
VOUT = 1VPP
-50
1.1
PGA = 30dB
VOUT = 1VPP
-50
Distortion (dB)
Distortion (dB)
10MHz
-55
10MHz
2MHz
-60
-65
-70
0.7
0.8
5MHz
1.0
0.9
1.1
1.2
0.6
0.8
1.0
0.9
VCNTRL (V)
Figure 40.
Figure 41.
DISTORTION vs RLOAD
(Clamp Disabled)
DISTORTION vs RLOAD
(Clamp Enabled)
1.1
1.2
-45
VOUT = 1VPP
VCNTRL = 1V
PGA = 20dB and 30dB
3rd Harmonic, 30dB
-50
2nd Harmonic, 20dB
-55
0.7
VCNTRL (V)
2nd Harmonic, 30dB
-60
3rd Harmonic, 30dB
-65
-70
Distortion (dB)
Distortion (dB)
-65
-75
0.6
-50
2MHz
-60
-70
5MHz
-75
-45
-55
-55
2nd Harmonic, 20dB
-60
3rd Harmonic, 20dB
-65
2nd Harmonic, 30dB
-70
3rd Harmonic, 20dB
-75
VOUT = 1VPP
VCNTRL = 1V
PGA = 20dB and 30dB
-75
750
1000
1250
1500
750
1000
1250
Output Resistor Load (W)
Output Resistor Load (W)
Figure 42.
Figure 43.
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TYPICAL CHARACTERISTICS (continued)
All specifications at TA = +25°C, AVDD2 = 5.0V, AVDD1 = DVDD = 3.3V; single-ended, ac-coupled (1µF) input configuration
to the preamp (LNA), fIN = 5MHz, VCNTL = 1.0V, clamp disabled (CL = 1), LPF = 15MHz, and RLOAD = 1kΩ on each output to
ground, unless otherwise noted.
DISTORTION vs FREQUENCY
DISTORTION vs PGA GAIN
-45
-45
3rd Harmonic, 30dB
3rd Harmonic, 20dB
-55
-60
2nd Harmonic, 20dB
-65
2nd Harmonic, 30dB
PGA = 20dB and 30dB
VOUT = 2VPP
VCNTRL = 1V
-70
-75
2nd Harmonic, 1.2VCNTRL
-60
-65
-70
Frequency = 5MHz
VOUT = 2VPP
-75
25
20
30
27
Frequency (MHz)
PGA Gain (dB)
Figure 44.
Figure 45.
DISTORTION vs VOUT, PEAK-TO-PEAK
INTERMODULATION DISTORTION
(4.99MHz and 5.01MHz)
10
PGA = 30dB
VCNTRL = 1.2V
Frequency = 5MHz
0
-10
Magnitude (dBm)
Distortion (dB)
-50
2nd Harmonic, 1.0VCNTRL
-55
10
1
-45
3rd Harmonic, 1.2VCNTRL
-50
Distortion (dB)
Distortion (dB)
-50
3rd Harmonic, 1.0VCNTRL
-55
2nd Harmonic
-60
-65
3rd Harmonic
VOUT = 1VPP
PGA = 30dB
VCNTRL = 1V
4.5
-20
-21.3
-30
-40
-50
-60
-70
-70
-73.5
-80
-75
1.0
1.2
1.4
1.6
-90
4.90 4.92 4.94 4.96 4.98 5.00 5.02 5.04 5.06 5.08 5.10
2.0
1.8
VOUT (VPP)
Frequency (MHz)
Figure 46.
Figure 47.
CROSSTALK vs VCNTRL
Crosstalk (dBc)
-55
CROSSTALK vs VCNTRL
-50
Adjacent Channels
PGA = 20dB
VOUT = 1VPP
-60
-55
Crosstalk (dBc)
-50
10MHz
-65
5MHz
-70
Adjacent Channels
PGA = 25dB
VOUT = 1VPP
-60
10MHz
-65
5MHz
-70
2MHz
2MHz
-75
-75
-80
-80
0.5
20
0.6
0.7
0.8
0.9
1.0
1.1
1.2
0.4
0.5
0.6
0.7
0.8
VCNTRL (V)
VCNTRL (V)
Figure 48.
Figure 49.
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0.9
1.0
1.1
1.2
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TYPICAL CHARACTERISTICS (continued)
All specifications at TA = +25°C, AVDD2 = 5.0V, AVDD1 = DVDD = 3.3V; single-ended, ac-coupled (1µF) input configuration
to the preamp (LNA), fIN = 5MHz, VCNTL = 1.0V, clamp disabled (CL = 1), LPF = 15MHz, and RLOAD = 1kΩ on each output to
ground, unless otherwise noted.
CROSSTALK vs VCNTRL
-50
Adjacent Channels
PGA = 30dB
VOUT = 1VPP
-55
-60
Crosstalk (dBc)
-55
Crosstalk (dBc)
CROSSTALK vs VCNTRL
-50
Adjacent Channels
PGA = 27dB
VOUT = 1VPP
10MHz
-65
5MHz
-70
-60
10MHz
-65
5MHz
-70
2MHz
2MHz
-75
-75
-80
-80
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
VCNTRL (V)
VCNTRL (V)
Figure 50.
Figure 51.
LNA OVERLOAD
(VIN = 300mVPP)
LNA OVERLOAD
(VIN = 400mVPP)
1.0
1.1
1.2
Input
CH 1
(200mV/div)
Input
CH 1
(100mV/div)
PGA = 20dB
VOUT = 2VPP
VCNTRL = 0.54V
PGA = 20dB
VOUT = 2VPP
VCNTRL = 0.54V
Output
CH 2
(1V/div)
Output
CH 2
(500mV/div)
Time (200ns/div)
Time (200ns/div)
Figure 52.
Figure 53.
PGA OVERLOAD
(VIN = 34mVPP)
PGA OVERLOAD
(VIN = 50mVPP)
Input
CH 1
(20mV/div)
PGA = 20dB
VOUT = 2.5VPP
VCNTRL = 1V
Output
CH 2
(0.5V/div)
Input
CH 1
(50mV/div)
PGA = 20dB
VOUT = 2.8VPP
VCNTRL = 1V
Output
CH 2
(0.5V/div)
Time (200ns/div)
Time (200ns/div)
Figure 54.
Figure 55.
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TYPICAL CHARACTERISTICS (continued)
All specifications at TA = +25°C, AVDD2 = 5.0V, AVDD1 = DVDD = 3.3V; single-ended, ac-coupled (1µF) input configuration
to the preamp (LNA), fIN = 5MHz, VCNTL = 1.0V, clamp disabled (CL = 1), LPF = 15MHz, and RLOAD = 1kΩ on each output to
ground, unless otherwise noted.
PGA OVERLOAD
(VIN = 50mVPP, Clamp Enabled)
Input
CH 1
(50mV/div)
PGA = 20dB
VOUT = 1.7VPP
VCNTRL = 1V
Output
CH 2
(0.5V/div)
PGA OVERLOAD
(VIN = 20mVPP)
Input
CH 1
(22.4mV/div)
Output
CH 2
(2.8V/div)
Time (200ns/div)
Time (200ns/div)
Figure 56.
Figure 57.
VCNTRL RESPONSE TIME
POWER-DOWN RESPONSE TIME
VCNTRL
CH 1
(0.5V/div)
PD Pin
CH 1
(1V/div)
Output
CH 2
(0.5V/div)
Output
CH 2
(0.2V/div)
PGA = 20dB
VOUT = 1VPP
VCNTRL = 0.6V
PGA = 30dB
VOUT = 1VPP
Time (1ms/div)
Time (1ms/div)
Figure 58.
22
PGA = 30dB
VOUT = 2.8VPP
VCNTRL = 1V
Figure 59.
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THEORY OF OPERATION
Built on TI’s bipolar-complementary (BiCOM)
process, the VCA8500 is a third-generation, octal
variable gain amplifier that implements a number of
proprietary circuit design techniques to specifically
address the performance demands of medical
ultrasound systems.
The VCA8500 is an 8-channel VGA that is ideally
suited for portable ultrasound applications. It offers
unparalleled low-noise and low-power performance at
a high level of integration. For the TGC signal path,
each channel consists of a 20dB fixed-gain low-noise
amplifier (LNA), a linear-in-dB voltage-controlled
attenuator (VCA), and a programmable gain amplifier
(PGA), as well as a clamping and low-pass filter
stage. Digitally controlled through the logic interface,
the PGA gain can be set to four different settings:
20dB, 25dB, 27dB, and 30dB. At its highest setting,
the total available gain of the VCA8500 is therefore
50dB, sufficient for 10-bit systems. To facilitate the
logarithmic time-gain compensation required for
ultrasound systems, the VCA is designed to provide a
46dB attenuation range. Here, all channels are
simultaneously controlled by an externally-applied
control voltage (VCNTL) in the range of 0V to 1.2V.
While the LNA is designed to be driven from a
single-ended source, the internal TGC signal path is
designed to be fully differential to maximize dynamic
range while also optimizing for low, even-order
harmonic distortion.
CW doppler signal processing is facilitated by routing
the differential LNA outputs to V/I amplifier stages.
The resulting signal currents of each channel then
connect to an 8×10 switch matrix that is controlled
through the serial interface and a corresponding
register. The CW outputs are typically routed to a
passive delay line that allows coherent summing
(beam forming) of the active channels and additional
off-chip signal processing, as shown in Figure 60.
Applications that do not utilize the CW path can
simply operate the VCA8500 in TGC mode. In this
mode, the CW blocks (V/I amplifiers and switch
matrix) remain powered down, and the CW outputs
can be unconnected.
VCA8500
V/I
T/R
Switch
CW/IOUT
CW Switch Matrix
CIN
LNA
Attenuator
(VCA)
LPF
PGA
OUT
Clamp
OUT
VCNTL
Figure 60. Functional Block Diagram
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LOW-NOISE AMPLIFIER (LNA)
As with many high-gain systems, the front-end
amplifier is critical to achieve a certain overall
performance level. Using a proprietary new
architecture, the LNA of the VCA8500 delivers
exceptional low-noise performance, while operating
on a very low quiescent current of only 8.3mA per
channel. This current consumption is significantly
lower compared to CMOS-based architectures with
similar noise performances.
The LNA performs a single-ended input to differential
output voltage conversion and is configured for a
fixed gain of 20dB (10V/V). The ultralow
input-referred noise of only 0.7nV/√Hz, along with the
linear input range of 250mVPP, results in a wide
dynamic range that supports the high demands of
PW and CW ultrasound imaging modes. Larger input
signals can be accepted by the LNA, but distortion
performance degrades as input signals levels
increase. The LNA input is internally biased to
approximately 2.4V; the signal source should be
ac-coupled to the LNA input by an adequately-sized
capacitor. Internally, the LNA directly drives the VCA,
avoiding the typical drawbacks of ac-coupled
architectures, such as slow overload recovery.
The attenuator is essentially a variable voltage divider
that consists of the series input resistor (RS) and
eight identical shunt FETs placed in parallel and
controlled by sequentially activated clipping amplifiers
(A1 through A8). Each clipping amplifier can be
understood as a specialized voltage comparator with
a soft transfer characteristic and well-controlled
output limit voltage. Reference voltages V1 through
V8 are equally spaced over the 0V to 1.2V control
voltage range. As the control voltage rises through
the input range of each clipping amplifier, the
amplifier output rises from 0V (FET completely ON) to
VCM – VT (FET nearly OFF), where VCM is the
common source voltage and VT is the threshold
voltage of the FET. As each FET approaches its off
state and the control voltage continues to rise, the
next clipping amplifier/FET combination takes over for
the next portion of the piecewise-linear attenuation
characteristic.
Thus, low control voltages have most of the FETs
turned on, producing maximum signal attenuation.
Similarly, high control voltages turn the FETs off,
leading to minimal signal attenuation. Therefore, each
FET acts to decrease the shunt resistance of the
voltage divider formed by RS and the parallel FET
network.
VOLTAGE-CONTROLLED ATTENUATOR
(VCA)
The amplified differential signal swing that comes
from the LNA is reduced by the subsequent VCA
stage. The VCA is designed to have a linear-in-dB
attenuation characteristic; that is, the average gain
loss in dB is constant for each equal increment of the
control voltage (VCNTL). Figure 61 shows the
simplified schematic of this VCA stage.
A1-A8 Attenuator Stages
Attenuator
Input
RS
QS
Q1
VB
A1
A2
C1
V1
VCNTRL
Q2
Q3
A3
C2
V2
Control
Input
Q4
A4
C3
V3
Attenuator
Output
Q5
A5
C4
V4
Q6
A6
C5
V5
Q7
A7
C6
A8
C7
V6
Q8
V7
C8
V8
C1-C8 Clipping Amplifiers
Figure 61. Voltage-Controlled Attenuator Simplified Schematic
24
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PROGRAMMABLE POST-GAIN AMPLIFIER
(PGA)
Following the VCA is a programmable post-gain
amplifier (PGA). Figure 62 shows a simplified
schematic of the PGA, including the clamping stage.
The gain of this PGA can be configured to four
different gain settings: 20dB, 25dB, 27dB, and 30dB,
programmable through the serial port; see Table 8.
The PGA structure consists of a differential,
programmable-gain
voltage-to-current
converter
stage followed by transimpedance amplifiers to create
and buffer each side of the differential output. Low
input noise is also a requirement for the PGA design
as a result of the large amount of signal attenuation
that can be applied in the preceding VCA stage. At
minimum VCA attenuation (used for small input
signals), the LNA noise dominates; at maximum VCA
attenuation (large input signals), the attenuator and
PGA noise dominates.
A1
From
Attenuator
Gain
Control
Bits
Clamp
Control
Bit
RG
To
Low-Pass
Filter
Clamp
A2
PROGRAMMABLE CLAMPING
To further optimize the overload recovery behavior of
a complete TGC channel, the VCA8500 integrates a
programmable clamping stage, as shown in
Figure 63. This clamping stage precedes the
low-pass filter in order to prevent the filter circuit from
being driven into overload, the result of which would
be an extended recovery time. Programmable
through the serial interface, the clamping level can be
either set to clamp the output to approximately 1.7VPP
differential, or be disabled. Disabling the clamp
function increases the current consumption on the
3.3V analog supply (AVDD1) by about 3mA for the
full device. Note that with the clamp function enabled,
the third-harmonic distortion increases.
LOW-PASS FILTER
As part of a typical data acquisition system, the signal
bandwidth generally must be limited by the use of an
anti-aliasing filter before the analog-to-digital
converter (ADC). The VCA8500 integrates such an
anti-aliasing filter in the form of a programmable
low-pass filter (LPF) for each channel. The LPF is
designed as a differential, active, second-order filter
that approximates a Butterworth characteristic, with
typically 12dB per octave roll-off. Figure 63 shows the
simplified schematic of half the differential active
low-pass filter. Programmable through the serial
interface, the –3dB frequency corner can be set to
either 10MHz or 15MHz. The filter is set for all
channels simultaneously.
Figure 62. Post-Gain Amplifier
(Simplified Schematic)
PGA
OUT
(OUT)
VCM
(+1.65V)
Figure 63. Clamping Stage and Low-Pass Filter (Simplified Schematic)
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APPLICATION INFORMATION
This architecture minimizes any loading of the signal
source
that
may
otherwise
lead
to
a
frequency-dependent voltage divider. Moreover, the
closed-loop design yields very low offsets and offset
drift; this consideration is important because the LNA
directly drives the subsequent voltage-controlled
attenuator.
ANALOG INPUT AND LNA
While the LNA is designed as a fully differential
amplifier, it is optimized to perform a single-ended
input to differential output conversion. A simplified
schematic of an LNA channel is shown in Figure 64.
A bias voltage (VB) of +2.4V is internally applied to
the LNA inputs through 8kΩ resistors. In addition, the
dedicated signal input (IN pin) includes a pair of
back-to-back diodes that provide a coarse input
clamping function in case the input signal rises to
very large levels, exceeding 0.7VPP. This
configuration prevents the LNA from being driven into
a severe overload state, which may otherwise cause
an extended overload recovery time. The integrated
diodes are designed to handle a dc current of up to
approximately 5mA. Depending on the application
requirements, the system overload characteristics
may be improved by adding external Schottky diodes
at the LNA input, as shown in Figure 64.
The LNA of the VCA8500 uses the benefits of a
bipolar process technology to achieve an
exceptionally low-noise voltage of 0.7nV/√Hz, and a
low current noise of only 3pA/√Hz. With these
input-referred noise specifications, the VCA8500
achieves very low noise figure numbers over a wide
range of source resistances and frequencies (see
Figure 26 in the Typical Characteristics). The optimal
noise power matching is achieved for source
impedances of around 200Ω.
Further details of the VCA8500 input and output
noise performance are shown in the Typical
Characteristic graphs; the input-referred noise voltage
is derived by dividing the output-referred noise by the
measured gain at each point along the gain control
range.
As Figure 64 also shows, the complementary LNA
input (VBL pin) is internally decoupled by a small
capacitor. Furthermore, for each input channel, a
separate VBL pin is brought out for external
bypassing. This bypassing should be done with a
small, 0.1µF (typical) ceramic capacitor placed in
close proximity to each VBL pin. Attention should be
given to provide a low-noise analog ground for this
bypass capacitor. A noisy ground potential may
cause noise to be picked up and injected into the
signal path, leading to higher noise levels.
Noise Figure versus Source Resistance (RS)
RS (Ω)
NOISE FIGURE (dB)
50
2.21
200
1.10
400
1.14
1000
2.06
The LNA closed-loop architecture is internally
compensated for maximum stability without the need
of external compensation components (inductors or
capacitors). At the same time, the total input
capacitance is kept to a minimum with only 30pF.
IN
T/R
A1
CIN
³ 0.1mF
8kW
VB
(+2.4V)
To
Attenuator
8kW
A2
VBL
0.1mF
7pF
VCA8500
Figure 64. LNA Channel (Simplified Schematic)
26
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OVERLOAD RECOVERY
are largely determined by the biasing current of the
diodes, which can be set by adjusting the 3kΩ
resistor values; for example, setting a higher current
level may lead to an improved switching characteristic
and reduced noise contribution. A typical front-end
protection circuitry may add in the order of 2nV/√Hz
of noise to the signal path. This slight increase also
depends on the value of the termination resistor (RT).
The VCA8500 is designed in particular for ultrasound
applications where the front-end device is required to
recover very quickly from an overload condition. Such
an overload can either be the result of a transmit
pulse feed-through or a strong echo, which can cause
overload of the LNA, the PGA, or both. As discussed
earlier, the LNA inputs are internally protected by a
pair of back-to-back diodes to prevent severe
overload of the LNA. Figure 65 illustrates an
ultrasound receive channel front-end that includes
typical external overload protection elements. Here,
four high-voltage switching diodes are configured in a
bridge configuration and form the transmit/receive
(T/R) switch. During the transmit period, high voltage
pulses from the pulser are applied to the transducer
elements and the T/R switch isolates the sensitive
LNA input from being damaged by the high voltage
signal. However, it is common that fast transients up
to several volts leak through the T/R switch and
potentially overload the receiver. Therefore, an
additional pair of clamping diodes is placed between
the T/R switch and the LNA input. In order to clamp
the over-voltage to small levels, Schottky diodes
(such as the BAS40 series by Infineon®) are
commonly used. For example, clamping to levels of
±0.3V can significantly reduce the overall overload
recovery performance. The T/R switch characteristics
As Figure 65 shows, the front-end circuitry should be
capacitively coupled to the LNA signal input (IN). This
coupling ensures that the LNA input bias voltage of
+2.4V is maintained and decoupled from any other
biasing voltage before the LNA.
Within the VCA8500, overload can occur in either the
LNA or the PGA. LNA overload can occur as the
result of T/R switch feed-through; and the PGA can
be driven into an overload condition by a strong echo
in the near-field while the signal gain is high. In any
case, the VCA8500 is optimized for very short
recovery times, as shown in Figure 65.
+5V
3kW
C1
Cable
C2
³ 0.1mF
LNA
BAS40
RT
3kW
Probe
Transducer
From
Pulser
0.1mF
VCA8500
-5V
Figure 65. Typical Input Overload Protection Circuit of an Ultrasound System
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VCA—GAIN CONTROL
The attenuator (VCA) for each of the eight channels
of the VCA8500 is controlled by a single-ended
control signal input, the VCNTRL pin. The control
voltage range spans from 0V to 1.2V, referenced to
ground. This control voltage varies the attenuation of
the VCA based on its linear-in-dB characteristic with
its maximum attenuation (minimum gain) at VCNTRL =
0V, and minimum attenuation (maximum gain) at
VCNTRL = 1.2V. Table 12 shows the nominal gains for
each of the four PGA gain settings. The total gain
range is typically 46dB and remains constant
independent of the PGA selected; the Max Gain
column reflects the absolute gain of the full signal
path comprised of the fixed LNA gain of 20dB and the
programmable PGA gain.
When the VCA8500 operates in CW mode, the
attenuator stage remains connected to the LNA
outputs. Therefore, it is recommended to set the
VCNTRL voltage to +1.2V in order to minimize the
internal loading of the LNA outputs. Small
improvements in reduced power dissipation and
improved distortion performance may also be
realized.
VCA8500
Attenuator
RS
To
PGA
LNA
Table 12. Nominal Gain Control Ranges for Each
of the Four PGA Gain Settings
PGA GAIN
MIN GAIN AT
VCNTRL = 0V
MAX GAIN AT
VCNTRL = 1.2V
20dB
–4.5dB
41.5dB
VCNTRL
25dB
–0.5dB
45.5dB
RF
27dB
1.5dB
47.5dB
30dB
3.5dB
49.5dB
As previously discussed, the VCA architecture uses
eight attenuator segments that are equally spaced in
order to approximate the linear-in-dB gain-control
slope. This approximation results in a monotonic
slope; gain ripple is typically less than ±0.5dB.
The VCA8500 gain-control input has a –3dB
bandwidth of approximately 1.5MHz. This wide
bandwidth, although useful in many applications, can
allow high-frequency noise to modulate the gain
control input. In practice, this modulation can easily
be avoided by additional external filtering (RF and CF)
of the control input, as Figure 66 shows. Stepping the
control voltage from 0V to 1.2V, the gain control
response time is typically less than 500ns to settle
within 10% of the final signal level of a 1VPP output.
The control voltage input (VCNTRL pin) represents a
high-impedance input. Multiple VCA8500 devices can
be connected in parallel with no significant loading
effects using the VCNTRL pin of each device. Note that
when the VCNTRL pin is left unconnected, it floats up
to a potential of about +3.7V. For any voltage level
above 1.2V and up to 5.0V, the VCA continues to
operate at its minimum attenuation level; however, it
is recommended to limit the voltage to approximately
1.5V or less.
28
RS
CF
Figure 66. External Filtering of the VCNTL Input
OUTPUT
The output stage of the VCA8500 delivers a
differential output signal that swings symmetrically
around a fixed common-mode output voltage of
+1.65V. The design of the output stage includes a
common-mode control loop to hold the output
common-mode voltage stable over a wide range of
operating conditions. At the same time the output
offset and drift are kept to a minimum, allowing the
VCA8500 to be dc-coupled directly to other devices
(such as an ADC). In cases where the output of the
VCA8500 drives devices with a non-matching input
common-mode level, small ac-coupling capacitors
(for instance, 0.1µF) should be used.
It should be noted, however, that unlike many other
high-speed operational amplifiers, the VCA8500 is
designed to drive a typical output load of 1kΩ
single-ended (from each output to ground) or 2kΩ
differentially. For most applications, this consideration
should not represent a limitation; many high-speed
ADCs have input impedances in the kΩ range. For
the VCA8500 to maintain the ability to provide the full
2VPP output swing, however, it is recommended to
keep the output loading to 800Ω, single-ended (1.6kΩ
differential), or higher. In addition, care should be
taken to keep the capacitive loading of the outputs to
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INTERFACING TO ADCs
The VCA8500 is ideally suited to drive the ADS5281,
a low-power, octal, 12-bit ADC that can be operated
at sampling rates of up to 50MSPS. The VCA outputs
can be directly connected the ADC inputs without the
need for any external components, as shown in
Figure 67. Observing proper layout considerations,
the two devices can be placed in close proximity to
each other and allow for a very compact printed
circuit board (PCB) layout.
The
ADS5281
features
many
performance
characteristics that make it an excellent choice for
ultrasound systems: low channel power of only
55mW/ch (at 40MSPS); high signal-to-noise ratio of
70dB; and fast overload recovery time of only one
clock cycle. The VCA8500 can be configured to
complement this level of performance by choosing
the most suitable amplification setting of the post-gain
amplifier. For example, the ADS5281 has a full-scale
input of 2VPP and an input-referred noise of
approximately 50nV/√Hz. In order to achieve the
highest combined dynamic range performance, the
PGA gain can be set to 20dB. With this gain setting,
the output-referred noise is dominated by the noise
contribution of the attenuator and PGA and remains
constant over most of the gain control range
(approximately 65nV/√Hz). Only at the high end of
the gain control range does the LNA and
source-related noise contribution become the
prevailing factor. Higher gain PGA settings may be
chosen to interface to lower resolution ADCs that
have a higher noise floor.
OUT
Optional
LPF
INP
VCA8500
OUT
INN
ADS5281
12-Bit
40MSPS
Figure 67. The VCA8500 Can Be Interfaced to the
ADS5281 Without the Need for External
Components
uses sampling rates of up to 40MSPS. Here, the ratio
of the bandwidth (BW) to the Nyquist frequency (fS/2)
is approximately 0.75, which provides a good
compromise between the passband area and the stop
band attenuation. Choosing the lower 10MHz
bandwidth setting may be considered if the sampling
rate is reduced further, or if the input signal
bandwidth is lower. In this case, the reduced noise
bandwidth can potentially improve the noise floor.
3
0
Normalized Amplitude (dB)
a minimum (CLOAD ≤ 18pF, differential). The user
should examine all factors that contribute to the total
load (RLTOTAL = RL + XL). Depending on the overall
system requirements, trade-offs can be made
between the output loading and the desired distortion
levels and output swing.
15MHz
-3
-6
-9
10MHz
-12
-15
-18
-21
1
10
100
Frequency (MHz)
Figure 68. Normalized Frequency Response of the
10MHz and 15MHz Low-Pass Filter
CW DOPPLER PROCESSING
The VCA8500 integrates many of the elements
necessary to allow for the implementation of a CW
doppler processing circuit, such as a V/I converter for
each channel and a cross-point switch matrix with an
8-input into 10-output (8×10) configuration.
In order to switch the VCA8500 from the default TGC
mode operation into CW mode, bit D5 of the control
register must be updated to low ('0'). This setting also
enables access to all other registers that determine
the switch matrix configuration (see the Input Register
Bit Map tables). In order to process CW signals, the
LNA internally feeds into a differential V/I amplifier
stage. The transconductance of the V/I amplifier is
typically 16.4mA/V with a 100mVPP input signal. For
proper operation, the CW outputs must be connected
to an external bias voltage of +2.5V. Each CW output
is designed to sink a small dc current of 0.9mA, and
can deliver a signal current up to 2.9mAPP.
Figure 68 shows the normalized frequency response
of the low-pass filter. The 15MHz bandwidth is
intended to be the upper bandwidth for a system that
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SBOS390A – JANUARY 2008 – REVISED MARCH 2008
The resulting signal current then passes through the
8×10 switch matrix. Depending on the programmed
configuration of the switch matrix, any V/I amplifier
current output can be connected to any of 10 CW
outputs. This design is a simple current-summing
circuit such that each CW output can represent the
sum of any or all of the channel currents. The CW
outputs are typically routed to a passive LC delay
line, allowing coherent summing of the signals.
L 220mH
After summing, the CW signal path further consists of
a high dynamic range mixer for down-conversion to
I/Q base-band signals. The I/Q signals are then
band-limited (that is, low-frequency contents are
removed) in a filter stage that precedes a pair of
high-resolution, low sample rate ADCs.
VCM0
(+2.5V)
ADC
Amplifier
0
90
CW0
I and Q
Channel
ADC
CW1
CW2
CW3
VCA8500
CW4
CW Out
8 In By 10 Out CW5
Passive
Delay
Line
Clock
CW6
CW7
CW8
CW9
CW0
CW1
CW2
CW3
VCA8500
CW4
CW Out
8 In By 10 Out CW5
CW6
CW7
CW8
CW9
Figure 69. Conceptual CW Doppler Signal Path Using Current Summing and a Passive Delay Line for
Beamforming
30
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SBOS390A – JANUARY 2008 – REVISED MARCH 2008
POWER SUPPLIES
The VCA8500 operates on two supply rails, a +3.3V
and a +5V supply. At initial power-up, the part
operates in the TGC mode, with the registers in the
default configurations (see Table 2).
In TGC mode, only the VCA (attenuator) draws a
small current (typically 1.5mA) from the +5V supply.
Switching into the CW mode, the internal V/I
amplifiers are then powered from the +5V rails as
well, raising the operating current on the +5V rail. At
the same time, the post-gain amplifiers (PGA) are
powered down, reducing the current consumption on
the +3.3V rail (refer to the Electrical Characteristics
table for details).
All supply rails for the VCA8500 should be clean,
low-noise, analog supplies. This consideration
includes the +3.3V digital supply DVDD (pin 59) that
connects to the internal logic blocks of the VCA8500.
It is recommended to tie the DVDD pin to the same
+3.3V analog supply as the AVDD1 pins, rather than
a different +3.3V rail that may also power other logic
devices in the system. Transients and noise
generated by those devices can couple into the
VCA8500 and degrade performance.
While the VCA8500 uses a thermally-enhanced QFN
package that includes a PowerPAD on its backside,
the primary function of the PowerPAD is to provide a
solid ground reference point. Care should be taken to
use this package pad during the PCB layout phase as
the main ground return point.
respective charges, minimizing the wake-up response
time. As an example, Figure 59 illustrates the standby
power-up/down response when the PD pin is toggled
with a period of approximately 7.7ms (130Hz) with a
50% duty cycle. Here, the wake-up response time is
approximately 40µs, while the power-down time is
instantaneous (≤ 0.2µs). Factors such as the control
voltage setting, input signal level, PD pin toggle time,
and duty cycle primarily affect the wake-up response
time. Therefore, the user should evaluate the
VCA8500 performance under the desired system
conditions.
When in standby mode, the part typically dissipates
only 104mW, representing an 80% power reduction
compared to the normal operating mode. This
function is controlled through the PD pin (pin 49),
which is designed to interface to +3.3V low-voltage
logic. For normal operation, the PD pin should be tied
to a logic low ('0'); pulling this pin high ('1') places the
VCA into standby mode.
To achieve the lowest power dissipation of only
19mW, the VCA8500 can be placed in shutdown
mode. This mode is controlled through the serial
interface by setting bit D2 (PWR) of the control
register to '1'. When in shutdown mode, all circuits
(including references) within the VCA8500 are
powered-down, causing the bypass capacitors to be
discharged. Consequently, the wake-up time depends
largely on the time needed to charge the bypass
capacitors back up. Another factor is the elapsed time
the VCA8500 spends in shutdown mode.
POWER-DOWN MODES
The VCA8500 features two power-down modes—a
standby mode and a shutdown mode. The standby
mode function allows the VCA8500 to be rapidly
placed in a low-power state. When in this mode, most
amplifiers in the signal path are powered-down, while
the internal references remain active. This state
ensures that the external bypass capacitors retain the
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31
VCA8500
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SBOS390A – JANUARY 2008 – REVISED MARCH 2008
+5V
C16
1m F
OUT8P
C25
0.1mF
C14
0.1mF
C15
1m F
C35
0.1mF
IN7
C24
0.1mF
C3
0.1mF
C13
1m F
33
34
VREFL
AVDD1
VREFH
35
36
VB4
VB6
37
38
VB2
39
40
IN8
AVDD2
41
42
IN7
VBL8
44
43
VBL7
VBL6
46
45
IN6
OUT4
16
15
14
13
11
12
1
C9
1m F
OUT6P
R12
0W
C42
OUT6N
R11
0W
32
OUT5P
31
R10
0W
30
29
C41
OUT5N
28
27
26
25
24
23
22
R2
0W
21
20
OUT1P
19
R3
0W
18
C37
OUT1N
17
AVDD1
OUT4
CW9
VCM
CW8
VB5
OUT3
VB3
CW7
VB1
OUT3
AVDD2
CW6
Flag
PAD
C10
0.1mF
IN5
OUT2
VBL1
CW5
IN4
64
CW9
OUT2
VCNTRL
63
CW8
OUT1
DVDD
9
62
CW7
OUT1
RST
10
61
CW6
OUT5
VCA8500
OUT_QFN_RGC-64
D_OUT
IN3
60
CW5
CLK
VBL4
C1
0.1mF
OUT5
7
59
OUT6
D_IN
8
RST
+3.3V
CW4
VBL2
58
OUT6
VBL3
57
OUT7
CW3
5
CLK
DOUT
OUT7
CW2
6
56
CW1
IN2
55
DIN
OUT8
4
54
CW4
CW0
AVDD1
53
CW3
+3.3V
OUT8
IN1
52
PD
3
51
AVDD1
48
VBL5
50
2
49
R13
0W
C7
0.1mF
47
C22
0.1mF
CW2
C43
OUT7N
C31
0.1mF
IN5
CW1
OUT7P
R14
0W
C32
0.1mF
IN6
+3.3V
CW0
C44
R15
0W
C33
0.1mF
C14
1m F
R16
0W
OUT8N
C34
0.1mF
C23
0.1mF
PD
R17
0W
C36
2.2mF
IN8
R4
0W
+3.3V
OUT2P
C6
0.1mF
C30
2.2mF
R5
0W
C38
OUT2N
IN1
+3.3V
C17
2.2mF
C29
0.1mF
C10
1m F
C2
0.1mF
IN2
R6
0W
OUT3P
C28
0.1mF
C19
0.1mF
R7
0W
C27
2.2mF
C20
0.1mF
C11
1m F
OUT3N
C26
0.1mF
IN3
R8
0W
C5
0.1mF
C21
0.1mF
C12
1m F
+5V
IN4
R1
100W
C39
OUT4P
R9
0W
C40
OUT4N
C4
0.01mF
VCONTROL
(1) VCONTROL: Values for R1 and C4 should be selected for a desired time constant.
(2) Optional components: Values for R2 to R17 and C37 to C44 should be selected based on the analog-to-digital converter selected.
(3) The +3.3V supply connections for DVDD and AVDD1 should be joined to a low-noise +3.3V system supply. Consider filtering any supply
noise with an LC filter.
Figure 70. Typical Connection Diagram
32
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VCA8500
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SBOS390A – JANUARY 2008 – REVISED MARCH 2008
GROUNDING AND BYPASSING
The VCA8500 uses a thermally-enhanced QFN
package, with an exposed PowerPAD on the back
side of the package. This backside pad is the only
ground reference point of the VCA8500, and it should
be connected to a low-noise system ground plane. All
bypassing and power supplies for the VCA8500
should be referenced to this ground point.
All supply pins should be bypassed with 0.1µF
ceramic chip capacitors (size 0603 or smaller). In
order to minimize lead and trace inductance, the
capacitors should be located as close to the supply
pins as possible. Where double-sided component
mounting is allowed, these capacitors are best placed
directly under the package. In addition, larger bipolar
decoupling capacitors (2.2µF to 10µF), effective at
lower frequencies, may also be used on the main
supply pins. They can be placed on the PCB in
proximity to (less than 0.5in, or 12.7mm from) the
VCA8500.
The VCA8500 internally generates a number of
reference voltages, such as the bias voltages (VB1
through VB6). Note that in order to achieve the best
low-noise performance, VB1 (pin 13) must be
bypassed with a capacitor value of at least 1µF; the
recommended value is 2.2µF. All other designated
reference pins can be bypassed with smaller
capacitor values, typically 0.1µF. For best results
choose low-inductance ceramic chip capacitors (size
402) and place them as close to the device pins as
possible.
BOARD LAYOUT
Proper grounding and bypassing, short lead length,
and the use of ground planes are particularly
important for high-frequency designs. Achieving
optimum performance with a high gain amplifier such
as the VCA8500 requires careful attention to the PCB
layout to minimize the effect of board parasitics and
optimize component placement. A multilayer PCB
usually ensures best results and allows convenient
component placement.
More details on the PowerPAD PCB layout and
assembly process can be found in the Texas
Instruments
Application
Reports,
Power-Pad
Thermally-Enhanced Package (SLMA002), and
QFN/SON PCB Attachment (SLUA271A). These
documents can be downloaded from the TI web site
(www.ti.com).
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33
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jul-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
VCA8500IRGCR
ACTIVE
VQFN
RGC
64
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
VCA8500IRGCRG4
ACTIVE
VQFN
RGC
64
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
VCA8500IRGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
VCA8500IRGCTG4
ACTIVE
VQFN
RGC
64
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
VCA8500IRGCR
VQFN
RGC
64
2000
330.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
VCA8500IRGCT
VQFN
RGC
64
250
330.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
VCA8500IRGCR
VQFN
RGC
64
2000
333.2
345.9
28.6
VCA8500IRGCT
VQFN
RGC
64
250
333.2
345.9
28.6
Pack Materials-Page 2
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