AFE5805
www.ti.com................................................................................................................................................. SBOS421C – MARCH 2008 – REVISED OCTOBER 2008
FULLY-INTEGRATED, 8-CHANNEL ANALOG FRONT-END FOR ULTRASOUND
0.85nV/√Hz, 12-Bit, 50MSPS, 122mW/Channel
FEATURES
1
• 8-Channel Complete Analog Front-End:
– LNA, VCA, PGA, LPF, and ADC
• Ultra-Low, Full-Channel Noise:
– 0.85nV/√Hz (TGC)
– 1.1nV/√Hz (CW)
• Low Power:
– 122mW/Channel (40MSPS)
– 74mW/Channel (CW Mode)
• Low-Noise Pre-Amp (LNA):
– 0.75nV/√Hz
– 20dB Fixed Gain
– 250mVPP Linear Input Range
• Variable-Gain Amplifier:
– Gain Control Range: 46dB
• PGA Gain Settings: 20dB, 25dB, 27dB, 30dB
• Low-Pass Filter:
– Selectable BW: 10MHz, 15MHz
– 2nd-Order
• Gain Error: ±0.5dB
• Channel Matching: ±0.25dB
• Distortion, HD2: –65dBFS at 5MHz
• Clamping Control
• Fast Overload Recovery: Two Clock Cycles
• 12-Bit Analog-to-Digital Converter:
– 10MSPS to 50MSPS
– 69.5dB SNR at 10MHz
– Serial LVDS Interface
• Integrated CW Switch Matrix
• 15mm × 9mm, 135-BGA Package:
– Pb-Free (RoHS-Compliant) and Green
23
APPLICATIONS
•
Medical Imaging, Ultrasound
– Portable Systems
DESCRIPTION
The AFE5805 is a complete analog front-end device
specifically designed for ultrasound systems that
require low power and small size.
The AFE5805 consists of eight channels, including a
low-noise
amplifier
(LNA),
voltage-controlled
attenuator (VCA), programmable gain amplifier
(PGA), low-pass filter (LPF), and a 12-bit
analog-to-digital converter (ADC) with low voltage
differential signaling (LVDS) data outputs.
The LNA gain is set for 20dB gain, and has excellent
noise and signal handling capabilities, including fast
overload recovery. VCA gain can vary over a 46dB
range with a 0V to 1.2V control voltage common to all
channels of the AFE5805.
The PGA can be programmed for gains of 20dB,
25dB, 27dB, and 30dB. The internal low-pass filter
can also be programmed to 10MHz or 15MHz.
The LVDS outputs of the ADC reduce the number of
interface lines to an ASIC or FPGA, thereby enabling
the high system integration densities desired for
portable systems. The ADC can either be operated
with internal or external references. The ADC also
features a signal-to-noise ratio (SNR) enhancement
mode that can be useful at high gains.
The AFE5805 is available in a 15mm × 9mm,
135-ball
BGA
package
that
is
Pb-free
(RoHS-compliant) and green. It is specified for
operation from 0°C to +70°C.
SPI
Logic/Controls
IN1
Clamp
and
LPF
LVDS
OUT
8 Channels
..
..
LNA
VCA/PGA
IN8
12-Bit
ADC
CH1
..
CH8
Reference
CW Switch Matrix (8 ´ 10)
IOUT (10)
AFE5805
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Infineon is a registered trademark of Infineon Technologies.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
AFE5805
SBOS421C – MARCH 2008 – REVISED OCTOBER 2008................................................................................................................................................. www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGING/ORDERING INFORMATION (1) (2)
(1)
(2)
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
AFE5805
µFBGA-135
ZCF
OPERATING
TEMPERATURE
RANGE
0°C to +70°C
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
AFE5805ZCFR
Tape and Reel, 1000
AFE5805ZCFT
Tape and Reel, 250
AFE5805ZCF
Tray, 160
ECO STATUS
Pb-Free, Green
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
These packages conform to Lead (Pb)-free and green manufacturing specifications. Additional details including specific material content
can be accessed at www.ti.com/leadfree.
GREEN: TI defines Green to mean Lead (Pb)-Free and in addition, uses less package materials that do not contain halogens, including
bromine (Br), or antimony (Sb) above 0.1%of total product weight. N/A: Not yet available Lead (Pb)-Free; for estimated conversion
dates, go to www.ti.com/leadfree. Pb-FREE: TI defines Lead (Pb)-Free to mean RoHS compatible, including a lead concentration that
does not exceed 0.1% of total product weight, and, if designed to be soldered, suitable for use in specified lead-free soldering
processes.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
AFE5805
UNIT
Supply voltage range, AVDD1
–0.3 to +3.9
V
Supply voltage range, AVDD2
–0.3 to +3.9
V
–0.3 to +6
V
Supply voltage range, DVDD
–0.3 to +3.9
V
Supply voltage range, LVDD
–0.3 to +2.2
V
Voltage between AVSS1 and LVSS
–0.3 to +0.3
V
–0.3 to minimum [3.6, (AVDD2 + 0.3)]
V
External voltage applied to REFT-pin
–0.3 to +3
V
External voltage applied to REFB-pin
–0.3 to +2
V
–0.3 to minimum [3.9, (AVDD2 + 0.3)]
V
+260
°C
+125
°C
–55 to +150
°C
0 to +70
°C
HBM
2000
V
CDM
1000
V
MM
100
V
Supply voltage range, AVDD_5V
Voltage at analog inputs
Voltage at digital inputs
Peak solder temperature
(2)
Maximum junction temperature, TJ
Storage temperature range
Operating temperature range
ESD ratings
(1)
(2)
2
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
Device complies with JSTD-020D.
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AFE5805
www.ti.com................................................................................................................................................. SBOS421C – MARCH 2008 – REVISED OCTOBER 2008
ELECTRICAL CHARACTERISTICS
AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled (1.0µF),
VCNTL = 1.0V, fIN = 5MHz, Clock = 40MSPS, 50% duty cycle, internal reference mode, ISET = 56kΩ, LVDS buffer
setting = 3.5mA, at ambient temperature TA = +25°C, unless otherwise noted.
AFE5805
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PREAMPLIFIER (LNA)
Gain
A
Input voltage
VIN
SE-input to differential output
20
dB
Linear operation (HD2 ≤ –40dB)
250
mVPP
Maximum input voltage
Limited by internal diodes
600
mVPP
RS = 0Ω, f = 1MHz
0.75
nV/√Hz
3
pA/√Hz
VCMI
Internally generated
2.4
V
BW
Small-signal, –3dB
70
MHz
At f = 4MHz
8
kΩ
Includes internal ESD and clamping diodes
16
pF
RS = 0Ω, f = 2MHz, PGA = 30dB
0.85
nV/√Hz
RS = 0Ω, f = 2MHz, PGA = 20dB
1.08
nV/√Hz
NF
RS = 200Ω, f = 5MHz
1.5
dB
LPF
at –3dB, selectable through SPI
10, 15
MHz
±10
%
HPF
(First-order, due to internal ac-coupling)
200
kHz
blank
Input voltage noise (TGC)
Input current noise
Common-mode voltage, input
Bandwidth
en (RTI)
in (RTI)
Input resistance (1)
Input capacitance (1)
FULL-SIGNAL CHANNEL (LNA+VCA+LPF+ADC)
Input voltage noise (TGC)
Noise figure
Low-pass flter bandwidth
en
Bandwidth tolerance
High-pass filter
Group delay variation
≤ 6dB overload to within 1%
Overload recovery
±3
ns
2
Clock Cycles
ACCURACY
Gain (PGA)
Selectable through SPI
Total gain, max (2)
LNA + PGA gain, VCNTL = 1.2V
Gain range
Gain error, absolute (3)
20, 25, 27, 30
48
dB
VCNTL = 0.1V to 1.0V
40
dB
0V < VCNTL < 0.1V
±0.5
–1.5
±0.5
dB
+1.5
dB
±0.5
Channel-to-channel
–0.5
VCNTL = 1.0V, PGA = 30dB
–39
Offset error drift (tempco)
Clamp level
dB
46
1.0V < VCNTL < 1.2V
Offset error
dB
51
VCNTL = 0V to 1.2V
0.1V < VCNTL < 1.0V
Gain matching
49.5
±0.25
dB
+0.5
dB
+39
LSB
±5
ppm/°C
CL = 0
1.7
VPP
CL = 1 (clamp disabled)
2.8
VPP
GAIN CONTROL (VCA)
Input voltage range
VCNTL
Gain range = 46dB
0 to 1.2
V
VCNTL = 0.1V to 1.0V
44.4
dB/V
25
kΩ
VCNTL = 0V to 1.2V step; to 90% signal
0.5
µs
fIN = 2MHz; –1dBFS, PGA = 30dB
59.8
dBFS
fIN = 5MHz; –1dBFS, PGA = 30dB
59.6
dBFS
fIN = 10MHz; –1dBFS, PGA = 30dB
58.8
dBFS
Gain slope
Input resistance
Response time
DYNAMIC PERFORMANCE
Signal-to-noise ratio
(1)
(2)
(3)
SNR
See Figure 33.
Excludes digital gain within ADC.
Excludes error of internal reference.
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AFE5805
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ELECTRICAL CHARACTERISTICS (continued)
AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled (1.0µF),
VCNTL = 1.0V, fIN = 5MHz, Clock = 40MSPS, 50% duty cycle, internal reference mode, ISET = 56kΩ, LVDS buffer
setting = 3.5mA, at ambient temperature TA = +25°C, unless otherwise noted.
AFE5805
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC PERFORMANCE (continued)
Second-harmonic distortion
Third-harmonic distortion
Intermodulation distortion
HD2
HD3
IMD3
Crosstalk
fIN = 2MHz; –1dBFS, PGA = 30dB
–70
dBFS
fIN = 5MHz; –1dBFS, PGA = 30dB
–54
–65
dBFS
fIN = 5MHz; –6dBFS, PGA = 20dB
–61
–69
dBFS
–58
dBFS
fIN = 2MHz; –1dBFS, PGA = 30dB
fIN = 5MHz; –1dBFS, PGA = 30dB
–51
–59
dBFS
fIN = 5MHz; –6dBFS, PGA = 20dB
–56
–78
dBFS
f1 = 4.99MHz at –6dBFS,
f2 = 5.01MHz at –32dBFS
58.5
dBc
fIN = 5MHz, –1dBFS, PGA = 30dB
–67
dBc
nV/√Hz
CW—SIGNAL CHANNELS
Input voltage noise (CW)
RS = 0Ω, f = 1MHz
1.1
Output noise correlation factor
en
Summing of eight channels
0.6
Output transconductance (V/I)
At VIN = 100mVPP
14
15.6
dB
18
mA/V
Dynamic CW output current,
maximum
IOUTAC
2.9
mAPP
Static CW output current (sink)
IOUTDC
0.9
mA
VCM
2.5
V
Output impedance
50
kΩ
Output capacitance
10
pF
V
Output common-mode
voltage (4)
INTERNAL REFERENCE VOLTAGES (ADC)
Reference top
VREFT
0.5
Reference bottom
VREFB
2.5
VREFT – VREFB
Common-mode voltage
(internal)
VCM
V
1.95
2
2.05
V
1.425
1.5
1.575
V
VCM output current
±2
mA
EXTERNAL REFERENCE VOLTAGES (ADC)
Reference top
VREFT
2.4
2.5
2.6
V
Reference bottom
VREFB
0.4
0.5
0.6
V
VREFT – VREFB
1.9
Switching current (5)
(4)
(5)
4
2.1
2.5
V
mA
CW outputs require an externally applied bias voltage of +2.5V.
Current drawn by the eight ADC channels from the external reference voltages; sourcing for VREFT, sinking for VREFB.
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www.ti.com................................................................................................................................................. SBOS421C – MARCH 2008 – REVISED OCTOBER 2008
ELECTRICAL CHARACTERISTICS (continued)
AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled (1.0µF),
VCNTL = 1.0V, fIN = 5MHz, Clock = 40MSPS, 50% duty cycle, internal reference mode, ISET = 56kΩ, LVDS buffer
setting = 3.5mA, at ambient temperature TA = +25°C, unless otherwise noted.
AFE5805
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AVDD1, AVDD2, DVDD
Operating
3.15
3.3
3.47
V
AVDD_5V
Operating
4.75
5
5.25
V
1.7
1.8
1.9
V
POWER SUPPLY
Supply Voltages
LVDD
Supply Currents
IAVDD1 (ADC)
at 40MSPS
99
110
mA
IAVDD2 (VCA)
TGC mode
146
156
mA
CW mode
79
85
mA
TGC mode
8
10
mA
CW mode
55
61
mA
1.5
3.0
mA
At 40MSPS
70
80
mA
All channels, TGC mode, no signal
980
1080
mW
All channels, CW mode , no signal (6)
580
620
mW
TGC mode, no clock applied, no signal
615
IAVDD_5V (VCA)
IDVDD (VCA)
ILVDD (ADC)
Power dissipation, total
mW
POWER-DOWN MODES
Power-down dissipation, total
Complete power-down mode
64
Power-down response time (7)
85
mW
µs
1.0
Power-up response time (7)
PD to valid output (90% level)
50
µs
Power-down dissipation (7)
Partial power-down mode
233
mW
THERMAL CHARACTERISTICS
Temperature range
Thermal resistance
(6)
(7)
0
+70
°C
TJA
32
°C/W
TJC
4.2
°C/W
The ADC section is powered down during CW mode operation.
With VCA_PD and ADC_PD pins = high. The ADC_PD pin is configured for partial power-down (see the Power-Down Modes section).
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AFE5805
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DIGITAL CHARACTERISTICS
DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level
'0' or '1'. At CLOAD = 5pF (1), IOUT = 3.5mA (2), RLOAD = 100Ω (2), and no internal termination, unless otherwise noted.
AFE5805
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3.3
V
DIGITAL INPUTS
High-level input voltage
1.4
Low-level input voltage
0
0.3
V
High-level input current
10
µA
Low-level input current (3)
–10
µA
3
pF
High-level output voltage
1375
mV
Low-level output voltage
1025
mV
Output differential voltage, |VOD|
350
mV
Common-mode voltage of OUTP and OUTM
1200
mV
Output capacitance inside the device,
from either output to ground
2
pF
Input capacitance
LVDS OUTPUTS
VOS output offset voltage (2)
Output capacitance
FCLKP and FCLKM
10
1x (clock rate)
50
MHz
LCLKP and LCLKM
60
6x (clock rate)
300
MHz
50
MSPS
CLOCK
Clock input rate
10
Clock duty cycle
Clock input amplitude, differential
(VCLKP – VCLKM)
50
%
Sine-wave, ac-coupled
3
VPP
LVPECL, ac-coupled
1.6
VPP
LVDS, ac-coupled
0.7
VPP
Clock input amplitude, single-ended
(VCLKP)
(1)
(2)
(3)
6
High-level input voltage, VIH
CMOS
Low-level input voltage, VIL
CMOS
2.2
V
0.6
V
CLOAD is the effective external single-ended load capacitance between each output pin and ground.
IOUT refers to the LVDS buffer current setting; RLOAD is the differential load resistance between the LVDS output pair.
Except pin J3 (INT/EXT), which has an internal pull-up resistor (52kΩ) to 3.3V.
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AFE5805
LVDD
(1.8V)
AVDD1
(3.3V)
CLKM
CLKP
AVDD2
(3.3V)
AVSS2
FUNCTIONAL BLOCK DIAGRAM
LCLKP
6x ADCLK
Clock
Buffer
LCLKM
12x ADCLK
PLL
FCLKP
1x ADCLK
FCLKM
12-Bit
ADC
VCNTL
10,15MHz
Digital Gain
(0dB to 12dB)
20,25,27
30dB
CW Switch Matrix
(8x10)
Digital
Serializer
Registers
Reference
OUT1M
PowerDown
Channels
2 to 7
OUT8P
OUT8M
Drive Current
LPF
OUT1P
Test Patterns
PGA
Output Format
VCA
Serializer
¼
¼
LNA
Digital
¼
12-Bit
ADC
¼
LPF
¼
PGA
¼
¼
¼
¼
IN8
VCA
¼
LNA
¼
IN1
ADC
Control
PD
SCLK
SDATA
T
CS
ADC_RESET
ISET
REFT
REFB
CM
INT/EXT
AVDD_5V
DVDD(3.3V)
AVSS1
¼
CW[0:9]
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AFE5805
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PIN CONFIGURATION
ZCF PACKAGE
135-BGA
BOTTOM VIEW
OUT4M
OUT3M
OUT2M
OUT1M
LVSS
OUT5M
OUT6M
OUT7M
OUT8M
OUT4P
OUT3P
OUT2P
OUT1P
LVDD
OUT5P
OUT6P
OUT7P
OUT8P
LCLKP
LCLKM
LVSS
LVSS
LVSS
LVDD
LVDD
FCLKM
FCLKP
DNC
DNC
AVSS1
AVSS1
AVSS1
AVSS1
AVSS1
DNC
DNC
CLKP
AVDD1
AVSS1
AVSS1
AVSS1
AVSS1
AVSS1
AVDD1
EN_SM
CLKM
DNC
AVDD1
DNC
AVDD1
AVDD1
AVDD1
CM
ISET
AVSS1
AVDD1
INT/EXT
AVSS2
AVSS2
AVSS2
AVDD1
REFT
REFB
ADS_PD
DNC
DNC
VCA_CS
RST
SCLK
CS
SDATA
ADS_
RESET
CW5
AVDD2
VCM
AVSS2
AVSS2
AVSS2
VREFL
AVDD2
CW4
CW6
VB1
VB5
AVSS2
AVSS2
AVSS2
VREFH
VB6
CW3
CW7
AVDD_5V
VB3
AVSS2
AVSS2
AVSS2
VB4
AVDD_5V
CW2
CW8
VCNTL
AVSS2
AVSS2
DVDD
AVSS2
AVSS2
VB2
CW1
CW9
AVDD2
AVSS2
AVSS2
DVDD
AVSS2
AVSS2
AVDD2
CW0
VBL1
VBL2
VBL3
VBL4
DNC
VBL8
VBL7
VBL6
VBL5
IN1
IN2
IN3
IN4
VCA_PD
IN8
IN7
IN6
IN5
1
2
3
4
5
6
7
8
9
R
P
N
M
L
K
Rows
J
H
G
F
E
D
C
B
A
Columns
8
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ZCF PACKAGE
135-BGA
CONFIGURATION MAP (TOP VIEW)
R
OUT8M
OUT7M
OUT6M
OUT5M
LVSS
OUT1M
OUT2M
OUT3M
OUT4M
P
OUT8P
OUT7P
OUT6P
OUT5P
LVDD
OUT1P
OUT2P
OUT3P
OUT4P
N
FCLKP
FCLKM
LVDD
LVDD
LVSS
LVSS
LVSS
LCLKM
LCLKP
M
DNC
DNC
AVSS1
AVSS1
AVSS1
AVSS1
AVSS1
DNC
DNC
L
EN_SM
AVDD1
AVSS1
AVSS1
AVSS1
AVSS1
AVSS1
AVDD1
CLKP
K
ISET
CM
AVDD1
AVDD1
AVDD1
DNC
AVDD1
DNC
CLKM
J
REFB
REFT
AVDD1
AVSS2
AVSS2
AVSS2
INT/EXT
AVDD1
AVSS1
H
ADS_RESET
SDATA
CS
SCLK
RST
VCA_CS
DNC
DNC
ADS_PD
G
CW4
AVDD2
VREFL
AVSS2
AVSS2
AVSS2
VCM
AVDD2
CW5
F
CW3
VB6
VREFH
AVSS2
AVSS2
AVSS2
VB5
VB1
CW6
E
CW2
AVDD_5V
VB4
AVSS2
AVSS2
AVSS2
VB3
AVDD_5V
CW7
D
CW1
VB2
AVSS2
AVSS2
DVDD
AVSS2
AVSS2
VCNTL
CW8
C
CW0
AVDD2
AVSS2
AVSS2
DVDD
AVSS2
AVSS2
AVDD2
CW9
B
VBL5
VBL6
VBL7
VBL8
DNC
VBL4
VBL3
VBL2
VBL1
A
IN5
IN6
IN7
IN8
VCA_PD
IN4
IN3
IN2
IN1
9
8
7
4
3
2
1
Legend: AVDD1
AVDD2
DVDD
LVDD
AVDD_5V
AVSS1
AVSS2
LVSS
6
5
+3.3V; Analog
+3.3V; Analog
+3.3V; Analog
+1.8V; Digital
+5V; Analog
Analog Ground
Analog Ground
Digital Ground
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Table 1. TERMINAL FUNCTIONS
PIN NO.
PIN NAME
FUNCTION
H7
CS
Input
Chip select for serial interface; active low
DESCRIPTION
H1
ADS_PD
Input
Power-down pin for ADS; active high. See the Power-Down Modes section for more information.
H9
ADS_RESET
Input
RESET input for ADS; active low
H6
SCLK
Input
Serial clock input for serial interface
H8
SDATA
Input
Serial data input for serial interface
J2, L2, K7, J7,
K3, L8, K5, K6
AVDD1
POWER
L3, M3, L4, M4,
L5, M5, L6, M6,
L7, M7, J1
AVSS1
GND
3.3V analog supply for ADS
Analog ground for ADS
P5, N6, N7
LVDD
POWER
N3, N4, N5, R5
LVSS
GND
C5, D5
DVDD
POWER
3.3V digital supply for the VCA; connect to the 3.3V analog supply (AVDD2).
C2, C8, G2, G8
AVDD2
POWER
3.3V analog supply for VCA
E2, E8
AVDD_5V
POWER
5V supply for VCA
C3, D3, C4, D4,
E4, F4, G4, E5,
F5, G5, C6, D6,
E6, F6, G6, C7,
D7, J4, J5, J6
AVSS2
GND
Analog ground for VCA
K1
CLKM
Input
Negative clock input for ADS (connect to Ground in single-ended clock mode)
L1
CLKP
Input
Positive clock input for ADS
K8
CM
Input/Output
C9
CW0
Output
CW output 0
D9
CW1
Output
CW output 1
E9
CW2
Output
CW output 2
F9
CW3
Output
CW output 3
G9
CW4
Output
CW output 4
G1
CW5
Output
CW output 5
F1
CW6
Output
CW output 6
E1
CW7
Output
CW output 7
D1
CW8
Output
CW output 8
C1
CW9
Output
CW output 9
L9
EN_SM
Input
N8
FCLKM
Output
LVDS frame clock (negative output)
N9
FCLKP
Output
LVDS frame clock (positive output)
A1
IN1
Input
LNA input Channel 1
A2
IN2
Input
LNA input Channel 2
A3
IN3
Input
LNA input Channel 3
A4
IN4
Input
LNA input Channel 4
A9
IN5
Input
LNA input Channel 5
A8
IN6
Input
LNA input Channel 6
A7
IN7
Input
LNA input Channel 7
A6
IN8
Input
LNA input Channel 8
J3
INT/EXT
Input
Internal/ external reference mode select for ADS; internal = high (internal pull-up resistor)
K9
ISET
Input
Current bias pin for ADS. Requires 56kΩ to ground.
N2
LCLKM
Output
LVDS bit clock (6x); negative output
N1
LCLKP
Output
LVDS bit clock (6x); positive output
R4
OUT1M
Output
LVDS data output (negative), Channel 1
P4
OUT1P
Output
LVDS data output (positive), Channel 1
R3
OUT2M
Output
LVDS data output (negative), Channel 2
P3
OUT2P
Output
LVDS data output (positive), Channel 2
R2
OUT3M
Output
LVDS data output (negative), Channel 3
10
1.8V digital supply for ADS
Digital ground for ADS
1.5V common-mode I/O for ADS. Becomes input pin in one of the external reference modes.
Enables access to the VCA register. Active high. Connect permanently to 3.3V (AVDD1).
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Table 1. TERMINAL FUNCTIONS (continued)
PIN NO.
PIN NAME
FUNCTION
P2
OUT3P
Output
LVDS data output (positive), Channel 3
DESCRIPTION
R1
OUT4M
Output
LVDS data output (negative), Channel 4
P1
OUT4P
Output
LVDS data output (positive), Channel 4
R6
OUT5M
Output
LVDS data output (negative), Channel 5
P6
OUT5P
Output
LVDS data output (positive), Channel 5
R7
OUT6M
Output
LVDS data output (negative), Channel 6
P7
OUT6P
Output
LVDS data output (positive), Channel 6
R8
OUT7M
Output
LVDS data output (negative), Channel 7
P8
OUT7P
Output
LVDS data output (positive), Channel 7
R9
OUT8M
Output
LVDS data output (negative), Channel 8
P9
OUT8P
Output
LVDS data output (positive), Channel 8
J9
REFB
Input/Output
0.5V Negative reference of ADS. Decoupling to ground. Becomes input in external ref mode.
J8
REFT
Input/Output
2.5V Positive reference of ADS. Decoupling to ground. Becomes input in external ref mode.
H5
RST
Input
H4
VCA_CS
Output
Connect to RST–pin (H5)
F2
VB1
Output
Internal bias voltage. Bypass to ground with 2.2µF.
D8
VB2
Output
Internal bias voltage. Bypass to ground with 0.1µF.
E3
VB3
Output
Internal bias voltage. Bypass to ground with 0.1µF.
E7
VB4
Output
Internal bias voltage. Bypass to ground with 0.1µF
F3
VB5
Output
Internal bias voltage. Bypass to ground with 0.1µF.
F8
VB6
Output
Internal bias voltage. Bypass to ground with 0.1µF.
B1
VBL1
Input
Complementary LNA input Channel 1; bypass to ground with 0.1µF.
B2
VBL2
Input
Complementary LNA input Channel 2; bypass to ground with 0.1µF.
B3
VBL3
Input
Complementary LNA input Channel 3; bypass to ground with 0.1µF.
B4
VBL4
Input
Complementary LNA input Channel 4; bypass to ground with 0.1µF.
B9
VBL5
Input
Complementary LNA input Channel 5; bypass to ground with 0.1µF.
B8
VBL6
Input
Complementary LNA input Channel 6; bypass to ground with 0.1µF.
B7
VBL7
Input
Complementary LNA input Channel 7; bypass to ground with 0.1µF.
B6
VBL8
Input
Complementary LNA input Channel 8; bypass to ground with 0.1µF.
A5
VCA_PD
Input
Power-down pin for VCA; low = normal mode, high = power-down mode.
G3
VCM
Output
D2
VCNTL
Input
F7
VREFH
Output
Clamp reference voltage (2.7V). Bypass to ground with 0.1µF.
G7
VREFL
Output
Clamp reference voltage (2.0V). Bypass to ground with 0.1µF.
B5, H2, H3, K2,
K4, M1, M2,
M8, M9
DNC
RESET input for VCA. Connect to the VCA_CS pin (H4).
VCA reference voltage. Bypass to ground with 0.1µF.
VCA control voltage input
Do not connect
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LVDS TIMING DIAGRAM
Sample n
Sample n + 12
ADC
Input
tD(A)
(1)
Sample n + 13
Clock
Input
tSAMPLE
12 clocks latency
LCLKM
6X FCLK
LCLKP
OUTP
SERIAL DATA
D0
D1
D2
D3
D4 D5 D6
D7
D8
D9 D10 D11
D0
D1 D2
D3
D4 D5
D6
D7 D8
D9 D10 D11 D0
D1 D2 D3
D4
D5 D6 D7
D8 D9 D10 D11
OUTM
FCLKM
1X FCLK
FCLKP
tPROP
(1) Referenced to ADC Input (internal node) for illustration purposes only.
DEFINITION OF SETUP AND HOLD TIMES
LCLKM
LCLKP
OUTM
OUTP
tH1
tSU1
tH2
tSU2
tSU = min(tSU1, tSU2)
tH = min(tH1, tH2)
TIMING CHARACTERISTICS (1)
AFE5805
PARAMETER
tD(A)
TEST CONDITIONS
ADC aperture delay
Aperture delay variation
tJ
Wake-up time
Channel-to-channel within the same device (3σ)
12
MAX
UNIT
4.5
ns
±20
ps
400
fs, rms
Time to valid data after coming out of
COMPLETE POWER-DOWN mode
50
µs
Time to valid data after coming out of PARTIAL
POWER-DOWN mode (with clock continuing to
run during power-down)
2
µs
Time to valid data after stopping and restarting
the input clock
40
µs
12
Clock
cycles
Data latency
(1)
TYP
1.5
Aperture jitter
tWAKE
MIN
Timing parameters are ensured by design and characterization; not production tested.
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LVDS OUTPUT TIMING CHARACTERISTICS (1) (2)
Typical values are at +25°C, minimum and maximum values over specified temperature range of TMIN = 0°C to TMAX = +70°C, sampling
frequency = as specified, CLOAD = 5pF (3), IOUT = 3.5mA, RLOAD = 100Ω (4), and no internal termination, unless otherwise noted.
AFE5805
40MSPS
tSU
tH
TEST CONDITIONS (5)
MIN
Data setup time (6)
Data valid (7) to zero-crossing of LCLKP
0.67
0.47
ns
Zero-crossing of LCLKP to data becoming
invalid (7)
0.85
0.65
ns
Clock propagation delay
Input clock (FCLK) rising edge cross-over to
output clock (FCLKP) rising edge cross-over
10
LVDS bit clock duty cycle
Duty cycle of differential clock,
(LCLKP – LCLKM)
45.5
Data hold time
tPROP
(6)
MAX
MIN
14
16.6
10
50
53
45
TYP
MAX
12.5
14.1
50
53.5
UNIT
ns
250
250
ps, pp
Frame clock cycle-to-cycle jitter
150
150
ps, pp
tRISE, tFALL
Data rise time, data fall time
tCLKRISE,
tCLKFALL
Output clock rise time, output
clock fall time
Rise time is from –100mV to +100mV
Fall time is from +100mV to –100mV
(7)
TYP
Bit clock cycle-to-cycle jitter
Rise time is from –100mV to +100mV
Fall time is from +100mV to –100mV
(1)
(2)
(3)
(4)
(5)
(6)
50MSPS
PARAMETER
0.09
0.2
0.4
0.09
0.2
0.4
ns
0.09
0.2
0.4
0.09
0.2
0.4
ns
All characteristics are at the maximum rated speed for each speed grade.
Timing parameters are ensured by design and characterization; not production tested.
CLOAD is the effective external single-ended load capacitance between each output pin and ground.
IOUT refers to the LVDS buffer current setting; RLOAD is the differential load resistance between the LVDS output pair.
Measurements are done with a transmission line of 100Ω characteristic impedance between the device and the load.
Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume
that data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as
reduced timing margin.
Data valid refers to a logic high of +100mV and a logic low of –100mV.
LVDS OUTPUT TIMING CHARACTERISTICS (1) (2)
Typical values are at +25°C, minimum and maximum values over specified temperature range of TMIN = 0°C to TMAX = +70°C, sampling
frequency = as specified, CLOAD = 5pF (3), IOUT = 3.5mA, RLOAD = 100Ω (4), and no internal termination, unless otherwise noted.
AFE5805
30MSPS
PARAMETER
TEST CONDITIONS (5)
MIN
TYP
20MSPS
MAX
MIN
TYP
10MSPS
MAX
MIN
TYP
MAX
UNIT
tSU
Data setup time (6)
Data valid (7) to zero-crossing of
LCLKP
0.8
1.5
3.7
ns
tH
Data hold time (6)
Zero-crossing of LCLKP to data
becoming invalid (7)
1.2
1.9
3.9
ns
tPROP
Clock propagation delay
Input clock (FCLK) rising edge
cross-over to output clock (FCLKP)
rising edge cross-over
9.5
13.5
17.3
9.5
14.5
17.3
10
14.7
17.1
LVDS bit clock duty cycle
Duty cycle of differential clock,
(LCLKP – LCLKM)
46.5
50
52
48
50
51
49
50
51
ns
Bit clock cycle-to-cycle
jitter
250
250
750
ps, pp
Frame clock cycle-to-cycle
jitter
150
150
500
ps, pp
tRISE,
tFALL
Data rise time, data fall
time
Rise time is from –100mV to +100mV
Fall time is from +100mV to –100mV
0.09
0.2
0.4
0.09
0.2
0.4
0.09
0.2
0.4
ns
tCLKRISE,
tCLKFALL
Output clock rise time,
output clock fall time
Rise time is from –100mV to +100mV
Fall time is from +100mV to –100mV
0.09
0.2
0.4
0.09
0.2
0.4
0.09
0.2
0.4
ns
(1)
(2)
(3)
(4)
(5)
(6)
(7)
All characteristics are at the speeds other than the maximum rated speed for each speed grade.
Timing parameters are ensured by design and characterization; not production tested.
CLOAD is the effective external single-ended load capacitance between each output pin and ground.
IOUT refers to the LVDS buffer current setting; RLOAD is the differential load resistance between the LVDS output pair.
Measurements are done with a transmission line of 100Ω characteristic impedance between the device and the load.
Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume
that data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as
reduced timing margin.
Data valid refers to a logic high of +100mV and a logic low of –100mV.
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TYPICAL CHARACTERISTICS
AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled with 0.1µF,
VCNTL = 1.0V, fIN = 5MHz, clamp disabled, LPF = 15MHz, clock = 40MSPS, 50% duty cycle, internal reference mode,
ISET = 56kΩ, and LVDS buffer setting = 3.5mA, at ambient temperature TA = +25°C, unless otherwise noted.
GAIN vs VCNTL
55
44
50
38
45
27dB
40
32
30dB
26
Gain (dB)
Gain (dB)
GAIN vs VCNTL vs TEMPERATURE
50
20
14
35
30
+85°C
25
20
8
15
20dB
2
+50°C
-40°C
10
25dB
5
-4
+25°C
0
-10
0.2
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
0.6
0.8
VCNTL (V)
VCNTL (V)
Figure 1.
Figure 2.
GAIN MATCH AT VCNTL = 0.1V
1.0
1.2
GAIN MATCH AT VCNTL = 0.6V
3000
3000
Channel-to-Channel
Channel-to-Channel
2500
2000
2000
Channel
2500
1500
1500
1000
500
500
0
0
-0.50
-0.45
-0.40
-0.35
-0.30
-0.25
-0.20
-0.15
-0.10
-0.05
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
1000
-0.50
-0.45
-0.40
-0.35
-0.30
-0.25
-0.20
-0.15
-0.10
-0.05
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
Channel
0.4
Gain (dB)
Gain (dB)
Figure 3.
Figure 4.
GAIN MATCH AT VCNTL = 1.0V
OUTPUT OFFSET
3500
4000
Channel-to-Channel
3500
3000
3000
Channel
Channel
2500
2000
1500
2500
2000
1500
1000
2072
2068
2060
2064
2052
2056
2044
2048
2040
2032
Code
Gain (dB)
Figure 5.
14
2036
0
2028
0
-0.50
-0.45
-0.40
-0.35
-0.30
-0.25
-0.20
-0.15
-0.10
-0.05
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
500
2024
1000
500
Figure 6.
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TYPICAL CHARACTERISTICS (continued)
AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled with 0.1µF,
VCNTL = 1.0V, fIN = 5MHz, clamp disabled, LPF = 15MHz, clock = 40MSPS, 50% duty cycle, internal reference mode,
ISET = 56kΩ, and LVDS buffer setting = 3.5mA, at ambient temperature TA = +25°C, unless otherwise noted.
SNR AND SINAD vs VCNTL
INPUT-REFERRED NOISE vs PGA
67
1.2
PGA = 20dB
61
60
PGA = 30dB
59
0.8
0.6
0.4
2MHz
5MHz
10MHz
62
2MHz
5MHz
10MHz
Input = -45dBm
Frequency = 5MHz
63
1.0
2MHz
5MHz
10MHz
64
R S = 0W
VCNTL = 1.2V
2MHz
5MHz
10MHz
65
Noise (nV/ÖHz)
SNR and SINAD (dBFS)
66
25dB
27dB
30dB
58
57
0.2
SNR
SINAD
56
0
55
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
20dB
VCNTL (V)
Gain Setting (PGA)
Figure 7.
Figure 8.
INPUT-REFERRED NOISE vs VCNTL
Frequency = 2MHz
Noise (nV/ÖHz)
Noise (nV/ÖHz)
INPUT-REFERRED NOISE vs VCNTL
130
120
110
100
90
80
70
60
50
40
30
20
10
0
PGA = 20dB
PGA = 30dB
0
130
120
110
100
90
80
70
60
50
40
30
20
10
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
Frequency = 5MHz
PGA = 20dB
PGA = 30dB
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
0
VCNTL (V)
VCNTL (V)
Figure 9.
Figure 10.
OUTPUT-REFERRED NOISE vs VCNTL
OUTPUT-REFERRED NOISE vs VCNTL
300
300
Frequency = 2MHz
Frequency = 5MHz
250
200
PGA = 30dB
150
100
Noise (nV/ÖHz)
Noise (nV/ÖHz)
250
200
PGA = 30dB
150
100
PGA = 20dB
50
PGA = 20dB
50
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
VCNTL (V)
VCNTL (V)
Figure 11.
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled with 0.1µF,
VCNTL = 1.0V, fIN = 5MHz, clamp disabled, LPF = 15MHz, clock = 40MSPS, 50% duty cycle, internal reference mode,
ISET = 56kΩ, and LVDS buffer setting = 3.5mA, at ambient temperature TA = +25°C, unless otherwise noted.
INPUT-REFERRED NOISE vs FREQUENCY vs RS
RS = 1kW
RS = 400W
Noise (nV/ÖHz)
Noise (nV/ÖHz)
OUTPUT-REFERRED NOISE vs FREQUENCY vs RS
1400
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
RS = 200W
RS = 50W
VCNTL = 1.2V
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
10
1
RS = 1kW
RS = 400W
RS = 200W
VCNTL = 1.2V
10
1
Frequency (MHz)
Frequency (MHz)
Figure 13.
Figure 14.
CURRENT NOISE vs FREQUENCY OVER RSOURCE
4.0
4.5
RS = 1kW
3.6
3.4
RS = 200W
3.2
3.0
RS = 400W
2.8
RS = 1kW
4.0
Noise Figure (dB)
Current Noise (pA/ÖHz)
NOISE FIGURE vs FREQUENCY vs RS
5.0
VCNTL = 1.2V
3.8
2.6
3.5
RS = 50W
3.0
2.5
2.0
RS = 400W
1.5
2.4
1.0
2.2
0.5
20
10
1
PGA = 30dB
VCNTL = 1.2V
RS = 200W
0
2.0
10
1
Frequency (MHz)
Frequency (MHz)
Figure 15.
Figure 16.
CW INPUT-REFERRED NOISE vs FREQUENCY
CW ACCURACY
1.30
4000
1.28
3500
1.26
3000
1.24
1.22
Channel
Noise (nV/ÖHz)
RS = 50W
1.20
1.18
2500
2000
1500
1.16
1000
1.14
500
1.12
17.0
16.6
16.8
16.2
16.4
15.8
16.0
15.6
15.2
15.4
14.8
15.0
14.4
20M
14.6
Frequency (Hz)
10M
14.2
0
1M
14.0
1.10
100k
Transconductance (mA/V)
Figure 17.
16
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled with 0.1µF,
VCNTL = 1.0V, fIN = 5MHz, clamp disabled, LPF = 15MHz, clock = 40MSPS, 50% duty cycle, internal reference mode,
ISET = 56kΩ, and LVDS buffer setting = 3.5mA, at ambient temperature TA = +25°C, unless otherwise noted.
2ND HARMONIC vs VCNTL vs FREQUENCY
3RD HARMONIC vs VCNTL vs FREQUENCY
-55
-50
PGA = 20dB
Output = -6dBFS
-55
-60
5MHz
-60
Distortion (dBFS)
Distortion (dBFS)
PGA = 20dB
Output = -6dBFS
-65
10MHz
-70
-75
2MHz
10MHz
-65
2MHz
-70
-75
-80
-80
-85
-85
5MHz
0.7
0.6
0.8
0.9
1.0
1.1
1.2
0.7
0.6
Figure 20.
Distortion (dBFS)
-60
10MHz
-45
10MHz
-65
2MHz
-70
-50
2MHz
-55
-60
5MHz
-65
-75
PGA = 30dB
Output = -1dBFS
-70
-80
0.9
1.0
1.1
1.2
0.7
0.6
0.8
0.9
VCNTL (V)
VCNTL (V)
Figure 21.
Figure 22.
2ND HARMONIC vs VCNTL vs OUTPUT LEVEL
1.0
1.1
1.2
3RD HARMONIC vs VCNTL vs OUTPUT LEVEL
-30
-30
PGA = 30dB
Frequency = 5MHz
VCNTL = 1V
PGA = 30dB
Frequency = 5MHz
-40
Distortion (dBc)
-40
Distortion (dBc)
1.2
3RD HARMONIC vs VCNTL vs FREQUENCY
Distortion (dBFS)
5MHz
-55
1.1
-40
PGA = 30dB
Output = -1dBFS
0.8
1.0
Figure 19.
2ND HARMONIC vs VCNTL vs FREQUENCY
0.7
0.9
VCNTL (V)
-50
0.6
0.8
VCNTL (V)
VCNTL = 0.4V
-50
-60
-70
-50
VCNTL = 1V
VCNTL = 0.4V
-60
-70
VCNTL = 0.7V
VCNTL = 0.7V
-80
-80
-40
-30
-20
-10
0
-40
-30
-20
Output Level (dBFS)
Output Level (dBFS)
Figure 23.
Figure 24.
-10
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TYPICAL CHARACTERISTICS (continued)
AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled with 0.1µF,
VCNTL = 1.0V, fIN = 5MHz, clamp disabled, LPF = 15MHz, clock = 40MSPS, 50% duty cycle, internal reference mode,
ISET = 56kΩ, and LVDS buffer setting = 3.5mA, at ambient temperature TA = +25°C, unless otherwise noted.
CROSSTALK vs VCNTL
-50
CROSSTALK vs VCNTL
-50
Adjacent Channels
PGA = 20dB
-1dBFS
-55
-60
-65
Crosstalk (dBc)
-60
Crosstalk (dBc)
Adjacent Channels
PGA = 25dB
-1dBFS
-55
10MHz
-70
-75
-80
-65
10MHz
-70
-75
5MHz
-80
2MHz
2MHz
-85
-85
5MHz
-90
-90
0.6
0.7
0.8
0.9
1.0
1.1
1.2
0.6
0.7
Figure 26.
-55
Crosstalk (dBc)
Crosstalk (dBc)
-60
10MHz
-70
-75
5MHz
10MHz
-65
-70
-75
5MHz
-80
2MHz
2MHz
-85
-90
-90
0.6
0.7
0.8
0.9
1.0
1.1
1.2
0.6
0.7
0.8
0.9
1.0
VCNTL (V)
VCNTL (V)
Figure 27.
Figure 28.
10MHz LOW-PASS FILTER RESPONSE
1.1
1.2
15MHz LOW-PASS FILTER RESPONSE
0
0
-2
-2
-4
-4
-6
-6
Magnitude (dB)
Magnitude (dB)
1.2
Adjacent Channels
PGA = 30dB
-1dBFS
-55
-60
-80
1.1
CROSSTALK vs VCNTL
-50
Adjacent Channels
PGA = 27dB
-1dBFS
-85
1.0
Figure 25.
CROSSTALK vs VCNTL
-65
0.9
VCNTL (V)
-50
-8
-10
-12
-8
-10
-12
-14
-14
-16
-16
-18
-18
-20
-20
0
18
0.8
VCNTL (V)
5
10
15
20
25
30
35
0
5
10
15
20
Frequency (MHz)
Frequency (MHz)
Figure 29.
Figure 30.
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30
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TYPICAL CHARACTERISTICS (continued)
AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled with 0.1µF,
VCNTL = 1.0V, fIN = 5MHz, clamp disabled, LPF = 15MHz, clock = 40MSPS, 50% duty cycle, internal reference mode,
ISET = 56kΩ, and LVDS buffer setting = 3.5mA, at ambient temperature TA = +25°C, unless otherwise noted.
INTERMODULATION DISTORTION
(1.99MHz and 2.01MHz)
0
0
PGA = 30dB
VCNTL = 1.0V
IMD3 = 54.2dB
-20
INTERMODULATION DISTORTION
(4.99MHz and 5.01MHz)
-20
Magnitude (dBFS)
-32
Magnitude (dBFS)
PGA = 30dB
VCNTL = 1.0V
IMD3 = 58.5dB
-6
-40
-60
-80
-86.2
-100
-6
-32
-40
-60
-80
-90.5
-100
-120
1.80
1.85
1.90
1.95
2.00
2.05
2.10
2.15
-120
4.80
2.20
4.85
4.90
4.95
5.00
5.05
Frequency (MHz)
Frequency (MHz)
Figure 31.
Figure 32.
INPUT IMPEDANCE vs FREQUENCY
5.15
5.20
LNA OVERLOAD
1.0
100
12k
5.10
80
40
8k
20
0
6k
-20
4k
Magnitude (ZIN)
Phase
-40
Output (±Full-Scale)
60
Phase (°)
Magnitude (W)
10k
-60
2k
0.5
0
-0.5
VIN = 1VPP (+12dBFS)
PGA = 20dB
VCNTL = 0.54V
-80
0
100k
1M
-100
100M
10M
-1.0
0
10
20
30
40
Frequency (Hz)
Figure 33.
0.5
0.5
0
-0.5
VIN = 0.5VPP (+6dBFS)
PGA = 30dB
VCNTL = 1.0V
-1.0
30
40
50
60
80
90 100 110 120
0
-0.5
PGA = 30dB
VCNTL = 1.0V
VIN = 250mVPP, 0.25mVPP
-1.0
20
70
OVERLOAD RECOVERY
1.0
Output (±Full-Scale)
Output (±Full-Scale)
FULL CHANNEL OVERLOAD
10
60
Figure 34.
1.0
0
50
Sample Points
70
80
90 100 110 120
0
5
10
Sample Points
Time (ms)
Figure 35.
Figure 36.
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TYPICAL CHARACTERISTICS (continued)
AVDD_5V = 5.0V, AVDD1 = AVDD2 = DVDD = 3.3V, LVDD = 1.8V, single-ended input into LNA, ac-coupled with 0.1µF,
VCNTL = 1.0V, fIN = 5MHz, clamp disabled, LPF = 15MHz, clock = 40MSPS, 50% duty cycle, internal reference mode,
ISET = 56kΩ, and LVDS buffer setting = 3.5mA, at ambient temperature TA = +25°C, unless otherwise noted.
VCNTL RESPONSE TIME
POWER-UP/POWER-DOWN RESPONSE TIME
1.0
1.0
PD
Output (±Full-Scale)
Output (±Full-Scale)
VCNTL
0.5
0
-0.5
0.5
0
-0.5
PGA = 30dB
VCNTL = 0V to 1.2V
PGA = 30dB
VCNTL = 0.4V
-1.0
-1.0
5
0
15
10
0
5
10
15
20
Time (ms)
Time (ms)
Figure 37.
Figure 38.
AVDD1 AND LVDD POWER-SUPPLY CURRENTS
vs CLOCK FREQUENCY
25
30
POWER DISSIPATION vs TEMPERATURE
170
995
Zero Input on All Channels
TGC Mode
990
150
Total Power (mW)
IAVDD1, ILVDD (mA)
985
130
110
IAVDD1
90
70
ILVDD
975
970
965
960
955
50
950
30
945
5
20
980
15
25
35
45
55
-40
0
25
50
Clock Frequency (MSPS)
Temperature (°C)
Figure 39.
Figure 40.
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SERIAL INTERFACE
The AFE5805 has a set of internal registers that can be accessed through the serial interface formed by pins CS
(chip select, active low), SCLK (serial interface clock), and SDATA (serial interface data). When CS is low, the
following actions occur:
• Serial shift of bits into the device is enabled
• SDATA (serial data) is latched at every rising edge of SCLK
• SDATA is loaded into the register at every 24th SCLK rising edge
If the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples of
24-bit words within a single active CS pulse. The first eight bits form the register address and the remaining 16
bits form the register data. The interface can work with SCLK frequencies from 20MHz down to very low speeds
(a few hertz) and also with a non-50% SCLK duty cycle.
Register Initialization
After power-up, the internal registers must be initialized to the respective default values. Initialization can be
done in one of two ways:
1. Through a hardware reset, by applying a low-going pulse on the ADS_RESET pin; or
2. Through a software reset; using the serial interface, set the S_RST bit high. Setting this bit initializes the
internal registers to the respective default values and then self-resets the bit low. In this case, the
ADS_RESET pin stays high (inactive).
Serial Port Interface (SPI) Information
(connect externally)
ADS_RESET
CS
SCLK
[H5]
[H9]
[H8]
[H76]
[H6]
Tie to:
+3.3V (AVDD1)
[L9]
EN_SM
RST
[H4]
SPI Interface and Register
SDATA
VCA_CS
VCA_SCLK
VCA_SDATA
ADS_CS
ADS_SCLK
ADS_SDATA
ADS_RESET
AFE5805
Figure 41. Typical Connection Diagram for the SPI Control Lines
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SERIAL INTERFACE TIMING
Start Sequence
End Sequence
CS
t6
t1
t7
t2
Data latched on rising edge of SCLK
SCLK
t3
A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDATA
t4
t5
AFE5805
PARAMETER
DESCRIPTION
MIN
t1
SCLK period
50
TYP
MAX
UNIT
ns
t2
SCLK high time
20
ns
t3
SCLK low time
20
ns
t4
Data setup time
5
ns
t5
Data hold time
5
ns
t6
CS fall to SCLK rise
8
ns
t7
Time between last SCLK rising edge to CS rising edge
8
ns
Internally-Generated VCA Control Signals
VCA_SCLK
VCA_SDATA
D0
D39
VCA_SCLK and VCA_SDATA signals are generated if:
• Registers with address 16, 17, or 18 (Hex) are written into, and
• EN_SM pin is HIGH
22
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SERIAL REGISTER MAP
Table 2. SUMMARY OF FUNCTIONS SUPPORTED BY SERIAL INTERFACE (1) (2) (3) (4)
ADDRESS
IN HEX
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
00
D0
NAME
DESCRIPTION
X
S_RST
Self-clearing software RESET.
03
0
0
0
0
0
0
0
0
0
0
RES_
VCA
16
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
VCA_SDATA
<0:15>
See Table 4 information
17
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
VCA_SDATA
<16:31>
See Table 4 information
See Table 4 information
18
X
X
x
0F
X
X
X
X
0
0
0
0
0
X
X
X
X
X
X
X
X
X
PDN_CH<1:4>
Channel-specific ADC
power-down mode.
Inactive
PDN_CH<8:5>
Channel-specific ADC
power-down mode.
Inactive
PDN_PARTIAL
Partial power-down mode (fast
recovery from power-down).
Inactive
PDN_COMPLETE
Register mode for complete
power-down (slower recovery).
X
0
X
X
X
X
X
X
X
X
X
1
X
X
X
Inactive
Configures the PD pin for
partial power-down mode.
Complete
power-down
ILVDS_LCLK<2:0>
LVDS current drive
programmability for LCLKM
and LCLKP pins.
3.5mA drive
ILVDS_FRAME
<2:0>
LVDS current drive
programmability for FCLKM
and FCLKP pins.
3.5mA drive
ILVDS_DAT<2:0>
LVDS current drive
programmability for OUTM and
OUTP pins.
3.5mA drive
EN_LVDS_TERM
Enables internal termination
for LVDS buffers.
Termination
disabled
TERM_LCLK<2:0>
Programmable termination for
LCLKM and LCLKP buffers.
Termination
disabled
TERM_FRAME
<2:0>
Programmable termination for
FCLKM and FCLKP buffers.
Termination
disabled
TERM_DAT<2:0>
Programmable termination for
OUTM and OUTP buffers.
Termination
disabled
PDN_PIN_CFG
X
D5 = 1
(TGC mode)
X
X
11
Inactive
VCA_DATA
<32:39>
X
0
DEFAULT
12
1
X
1
X
X
X
X
X
X
X
X
X
LFNS_CH<1:4>
Channel-specific,
low-frequency noise
suppression mode enable.
Inactive
Channel-specific,
low-frequency noise
suppression mode enable.
Inactive
14
X
x
25
X
X
X
LFNS_CH<8:5>
X
0
0
EN_RAMP
Enables a repeating full-scale
ramp pattern on the outputs.
Inactive
0
X
0
DUALCUSTOM_
PAT
Enables the mode wherein the
output toggles between two
defined codes.
Inactive
0
0
X
SINGLE_CUSTOM
_PAT
Enables the mode wherein the
output is a constant specified
code.
Inactive
BITS_CUSTOM1
<11:10>
2MSBs for a single custom
pattern (and for the first code
of the dual custom pattern).
<11> is the MSB.
Inactive
BITS_CUSTOM2
<11:10>
2MSBs for the second code of
the dual custom pattern.
Inactive
Inactive
Inactive
X
X
(1)
(2)
(3)
(4)
X
X
26
X
X
X
X
X
X
X
X
X
X
BITS_CUSTOM1
<9:0>
10 lower bits for the single
custom pattern (and for the
first code of the dual custom
pattern). <0> is the LSB.
27
X
X
X
X
X
X
X
X
X
X
BITS_CUSTOM2
<9:0>
10 lower bits for the second
code of the dual custom
pattern.
The unused bits in each register (identified as blank table cells) must be programmed as '0'.
X = Register bit referenced by the corresponding name and description (default is 0).
Bits marked as '0' should be forced to 0, and bits marked as '1' should be forced to 1 when the particular register is programmed.
Multiple functions in a register should be programmed in a single write operation.
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Table 2. SUMMARY OF FUNCTIONS SUPPORTED BY SERIAL INTERFACE (continued)
ADDRESS
IN HEX
D15
D14
D13
D12
D11
D10
D9
D8
D7
X
D6
X
D5
D4
X
D3
D2
D1
D0
NAME
X
X
X
X
GAIN_CH4<3:0>
Programmable gain channel 4.
0dB gain
GAIN_CH3<3:0>
Programmable gain channel 3.
0dB gain
GAIN_CH2<3:0>
Programmable gain channel 2.
0dB gain
X
DESCRIPTION
DEFAULT
2A
X
X
X
X
X
X
X
X
GAIN_CH1<3:0>
Programmable gain channel 1.
0dB gain
X
X
X
X
GAIN_CH5<3:0>
Programmable gain channel 5.
0dB gain
GAIN_CH6<3:0>
Programmable gain channel 6.
0dB gain
GAIN_CH7<3:0>
Programmable gain channel 7.
0dB gain
X
GAIN_CH8<3:0>
Programmable gain channel 8.
0dB gain
X
DIFF_CLK
Differential clock mode.
Singleended clock
EN_DCC
Enables the duty-cycle
correction circuit.
Disabled
X
X
X
X
2B
X
X
X
X
X
1
1
1
1
1
1
1
1
X
X
X
EXT_REF_VCM
Drives the external reference
mode through the VCM pin.
External
reference
drives REFT
and REFB
PHASE_DDR<1:0>
Controls the phase of LCLK
output relative to data.
90 degrees
42
X
X
X
0
X
PAT_DESKEW
Enables deskew pattern mode.
Inactive
X
0
PAT_SYNC
Enables sync pattern mode.
Inactive
BTC_MODE
Binary two's complement
format for ADC output.
MSB_FIRST
Serialized ADC output comes
out MSB-first.
45
46
1
1
1
1
1
1
X
EN_SDR
1
1
FALL_SDR
1
1
X
X
Straight
offset binary
LSB-first
output
Enables SDR output mode
(LCLK becomes a 12x input
clock).
DDR output
mode
Controls whether the LCLK
rising or falling edge comes in
the middle of the data window
when operating in SDR output
mode.
Rising edge
of LCLK in
middle of
data window
SUMMARY OF FEATURES
DEFAULT
SELECTION
POWER IMPACT (Relative to Default)
AT fS = 50MSPS
Internal or external reference
(driven on the REFT and REFB pins)
N/A
Pin
Internal reference mode takes approximately 20mW more power on AVDD1
Exernal reference driven on the CM pin
Off
Register 42
Approximately 8mW less power on AVDD1
Duty cycle correction circuit
Off
Register 42
Approximately 7mW more power on AVDD1
Low-frequency noise suppression
Off
Register 14
With zero input to the ADC, low-frequency noise suppression causes digital switching
at fS/2, thereby increasing LVDD power by approximately 5.5mW/channel
Single-ended or differential clock
Single-ended
Register 42
Differential clock mode mode takes approximately 7mW more power on AVDD1
Off
Pin and register 0F
Refer to the Power-Down Modes section in the Electrical Characteristics table
FEATURES
ANALOG FEATURES
Power-down mode
DIGITAL FEATURES
Programmable digital gain (0dB to 12dB)
Straight offset or BTC output
0dB
Registers 2A and 2B
No difference
Straight offset
Register 46
No difference
LVDS OUTPUT PHYSICAL LAYER
LVDS internal termination
LVDS current programmability
Off
Register 12
Approximately 7mW more power on AVDD1
3.5mA
Register 11
As per LVDS clock and data buffer current setting
LSB-first
Register 46
No difference
DDR
Register 46
SDR mode takes approximately 2mW more power on LVDD (at fS = 30MSPS)
Refer to Figure 43
Register 42
No difference
LVDS OUTPUT TIMING
LSB- or MSB-first output
DDR or SDR output
LCLK phase relative to data output
24
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DESCRIPTION OF SERIAL REGISTERS
SOFTWARE RESET
ADDRESS
IN HEX
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NAME
X
S_RST
00
Software reset is applied when the RST bit is set to '1'; setting this bit resets all internal registers and self-clears
to '0'.
Table 3. VCA Register Information
ADDRESS
IN HEX
D15
D14
D13
D12
03
0
0
0
0
16
VCA
D15
VCA
D14
VCA
D13
VCA
D12
17
VCA
D31
VCA
D30
VCA
D29
VCA
D28
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
RES_V
CA
0
0
0
0
0
VCA
D11
VCA
D10
VCA
D9
VCA
D8
VCA
D7
VCA
D6
VCA
D5
VCA
D4
VCA
D3
VCA
D2
1 (1)
D1
1 (1)
D0
VCA
D27
VCA
D26
VCA
D25
VCA
D24
VCA
D23
VCA
D22
VCA
D21
VCA
D20
VCA
D19
VCA
D18
VCA
D17
VCA
D16
VCA
D39
VCA
D38
VCA
D37
VCA
D36
VCA
D35
VCA
D34
VCA
D33
VCA
D32
18
(1)
Bits D0 and D1 of register 16 are forced to '1'.
space
•
•
•
•
•
•
VCA_SCLK and VCA_SDATA become active only when one of the registers 16, 17, or 18 of the AFE5805
are written into.
The contents of all three registers (total 40 bits) are written on VCA_SDATA even if only one of the above
registers is written into. This condition is only valid if the content of the register has changed because of the
most recent write. Writing contents that are the same as existing contents does not trigger activity on
VCA_SDATA.
For example, if register 17 is written into after a RESET is applied, then the contents of register 17 as well as
the default values of the bits in registers 16 and 18 are written into VCA_SDATA.
If register 16 is then written to, then the new contents of register 16, the previously written contents of register
17, and the default contents of register 18 are written into VCA_SDATA. Note that regardless of what is
written into D0 and D1 of register 16, the respective outputs on VCA_SDATA are always ‘1’.
Alternatively, all three registers (16, 17 and 18) can also be written within one write cycle of the serial
interface. In that case, there would be 48 consecutive SCLK edges within the same CS active window.
VCA_SCLK is generated using an oscillator (running at approximately 6MHz) inside the AFE5805, but the
oscillator is gated so that it is active only during the write operation of the 40 VCA bits.
VCA Reset
•
•
•
VCA_CS should be permanently connected to the RST-input.
When VCA_CS goes high (either because of an active low pulse on ADC_RESET for more than 10ns or as a
result or setting bit RES_VCA), the following functions are performed inside the AFE5805:
– Bits D0 and D1 of register 16 are forced to ‘1’
– All other bits in registers 16, 17 and 18 are RESET to the respective default values (‘0’ for all bits except
D5 of register 16 which is set to a default of ‘1’).
– No activity on signals VCA_SCLK and VCA_SDATA.
If bit RES_VCA has been set to ‘1’, then the state machine is in the RESET state until RES_VCA is set to ‘0’.
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INPUT REGISTER BIT MAPS
Table 4. VCA Register Map
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
D0:D7
D8:D11
D12:D15
D16:D19
D20:D23
D24:D27
D28:D31
D32:D35
D36:D39
Control
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
Table 5. Byte 1—Control Byte Register Map
BIT NUMBER
BIT NAME
D0 (LSB)
1
Start bit; this bit is permanently set high = 1
DESCRIPTION
D1
WR
Write bit; this bit is permanently set high = 1
D2
PWR
D3
BW
Low-pass filter bandwidth setting (see Table 10)
D4
CL
Clamp level setting (see Table 10)
D5
Mode
1 = TGC mode (default) , 0 = CW Doppler mode
D6
PG0
LSB of PGA gain control (see Table 11)
D7 (MSB)
PG1
MSB of PGA gain control
1= Power-down mode enabled.
Table 6. Byte 2—First Data Byte
BIT NUMBER
BIT NAME
D8 (LSB)
DB1:1
Channel 1, LSB of matrix control
DESCRIPTION
D9
DB1:2
Channel 1, matrix control
D10
DB1:3
Channel 1, matrix control
D11
DB1:4
Channel 1, MSB of matrix control
D12
DB2:1
Channel 2, LSB of matrix control
D13
DB2:2
Channel 2, matrix control
D14
DB2:3
Channel 2, matrix control
D15 (MSB)
DB2:4
Channel 2, MSB of matrix control
Table 7. Byte 3—Second Data Byte
26
BIT NUMBER
BIT NAME
DESCRIPTION
D16 (LSB)
DB3:1
Channel 3, LSB of matrix control
D17
DB3:2
Channel 3, matrix control
D18
DB3:3
Channel 3, matrix control
D19
DB3:4
Channel 3, MSB of matrix control
D20
DB4:1
Channel 4, LSB of matrix control
D21
DB4:2
Channel 4, matrix control
D22
DB4:3
Channel 4, matrix control
D23 (MSB)
DB4:4
Channel 4, MSB of matrix control
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Table 8. Byte 4—Third Data Byte
BIT NUMBER
BIT NAME
DESCRIPTION
D24 (LSB)
DB5:1
Channel 5, LSB of matrix control
D25
DB5:2
Channel 5, matrix control
D26
DB5:3
Channel 5, matrix control
D27
DB5:4
Channel 5, MSB of matrix control
D28
DB6:1
Channel 6, LSB of matrix control
D29
DB6:2
Channel 6, matrix control
D30
DB6:3
Channel 6, matrix control
D31 (MSB)
DB6:4
Channel 6, MSB of matrix control
Table 9. Byte 5—Fourth Data Byte
BIT NUMBER
BIT NAME
D32 (LSB)
DB7:1
Channel 7, LSB of matrix control
DESCRIPTION
D33
DB7:2
Channel 7, matrix control
D34
DB7:3
Channel 7, matrix control
D35
DB7:4
Channel 7, MSB of matrix control
D36
DB8:1
Channel 8, LSB of matrix control
D37
DB8:2
Channel 8, matrix control
D38
DB8:3
Channel 8, matrix control
D39 (MSB)
DB8:4
Channel 8, MSB of matrix control
Table 10. Clamp Level and LPF Bandwidth Setting
FUNCTION
BW
D3 = 0
Bandwidth set to 15MHz (default)
BW
D3 = 1
Bandwidth set to 10MHz
CL
D4 = 0
Clamps the output signal at approximately –1.4dB below the full-scale of 2VPP.
CL
D4 = 1
Clamp transparent (disabled)
Table 11. PGA Gain Setting
PG1 (D7)
PG0 (D6)
0
0
Sets PGA gain to 20dB (default)
FUNCTION
0
1
Sets PGA gain to 25dB
1
0
Sets PGA gain to 27dB
1
1
Sets PGA gain to 30dB
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Table 12. CW Switch Matrix Control for Each Channel
DBn:4 (MSB)
DBn:3
DBn:2
DBn:1 (LSB)
LNA INPUT CHANNEL n DIRECTED TO
0
0
0
0
Output CW0
0
0
0
1
Output CW1
0
0
1
0
Output CW2
0
0
1
1
Output CW3
0
1
0
0
Output CW4
0
1
0
1
Output CW5
0
1
1
0
Output CW6
0
1
1
1
Output CW7
1
0
0
0
Output CW8
1
0
0
1
Output CW9
1
0
1
0
Connected to AVDD_5V
1
0
1
1
Connected to AVDD_5V
1
1
0
0
Connected to AVDD_5V
1
1
0
1
Connected to AVDD_5V
1
1
1
0
Connected to AVDD_5V
1
1
1
1
Connected to AVDD_5V
V/I
Converter
Channel 1
Input
CW0
CW1
VCA_SDATA
VCA_SCLK
CW2
CW3
Decode
Logic
CW4
CW5
CW6
CW7
CW8
CW9
AVDD_5V
(To Other Channels)
Figure 42. Basic CW Cross-Point Switch Matrix Configuration
28
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POWER-DOWN MODES
ADDRESS
IN HEX
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
X
0F
X
D5
X
D4
D3
D2
D1
D0
NAME
X
X
X
X
PDN_CH<1:4>
X
PDN_CH<8:5>
X
PDN_PARTIAL
0
X
PDN_COMPLETE
X
0
PDN_PIN_CFG
Each of the eight ADC channels within the AFE5805 can be individually powered down. PDN_CH<N> controls
the power-down mode for the ADC channel <N>.
In addition to channel-specific power-down, the AFE5805 also has two global power-down modes: partial
power-down mode and complete power-down mode.
In addition to programming the device for either of these two power-down modes (through either the
PDN_PARTIAL or PDN_COMPLETE bits, respectively), the ADS_PD pin itself can be configured as either a
partial power-down pin or a complete power-down pin control. For example, if PDN_PIN_CFG = 0 (default), when
the ADS_PD pin is high, the device enters complete power-down mode. However, if PDN_PIN_CFG = 1, when
the ADS_PD pin is high, the device enters partial power-down mode.
The partial power-down mode function allows the AFE5805 to be rapidly placed in a low-power state. In this
mode, most amplifiers in the signal path are powered down, while the internal references remain active. This
configuration ensures that the external bypass capacitors retain the respective charges, minimizing the wake-up
response time. The wake-up response is typically less than 50µs, provided that the clock has been running for at
least 50µs before normal operating mode resumes. The power-down time is instantaneous (less than 1.0µs).
In partial power-down mode, the part typically dissipates only 233mW, representing a 76% power reduction
compared to the normal operating mode. This function is controlled through the ADS_PD and VCA_PD pins,
which are designed to interface with 3.3V low-voltage logic. If separate control of the two PD pins is not desired,
then both can be tied together. In this case, the ADS_PD pin should be configured to operate as a partial
power-down mode pin (see below).
For normal operation the PD pins should be tied to a logic low (0); a high (1) places the AFE5805 into partial
power-down mode.
To achieve the lowest power dissipation of only 64mW, the AFE5805 can be placed in complete power-down
mode. This mode is controlled through the serial interface by setting Register 16 (bit D2) and Register 0F (bit
D9:D10). In complete power-down mode, all circuits (including references) within the AFE5805 are
powered-down, and the bypass capacitors then discharge. Consequently, the wake-up time from complete
power-down mode depends largely on the time needed to recharge the bypass capacitors. Another factor that
affects the wake-up time is the elapsed time that the AFE5805 spends in shutdown mode.
LVDS DRIVE PROGRAMMABILITY
ADDRESS
IN HEX
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
11
X
X
X
D5
X
D4
D3
X
D2
D1
D0
NAME
X
X
X
ILVDS_LCLK<2:0>
ILVDS_FRAME<2:0>
X
ILVDS_DAT<2:0>
The LVDS drive strength of the bit clock (LCLKP or LCLKM) and the frame clock (FCLKP or FCLKM) can be
individually programmed. The LVDS drive strengths of all the data outputs OUTP and OUTM can also be
programmed to the same value.
All three drive strengths (bit clock, frame clock, and data) are programmed using sets of three bits. Table 13
details an example of how the drive strength of the bit clock is programmed (the method is similar for the frame
clock and data drive strengths).
Table 13. Bit Clock Drive Strength (1)
(1)
ILVDS_LCLK<2>
ILVDS_LCLK<1>
ILVDS_LCLK<0>
LVDS DRIVE STRENGTH FOR LCLKP AND LCLKM
0
0
0
3.5mA (default)
Current settings lower than 1.5mA are not recommended.
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Table 13. Bit Clock Drive Strength (continued)
ILVDS_LCLK<2>
ILVDS_LCLK<1>
ILVDS_LCLK<0>
LVDS DRIVE STRENGTH FOR LCLKP AND LCLKM
0
0
1
2.5mA
0
1
0
1.5mA
0
1
1
0.5mA
1
0
0
7.5mA
1
0
1
6.5mA
1
1
0
5.5mA
1
1
1
4.5mA
LVDS INTERNAL TERMINATION PROGRAMMING
ADDRESS
IN HEX
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NAME
X
EN_LVDS_TERM
1
X
X
X
TERM_LCLK<2:0>
12
1
X
1
X
X
X
X
TERM_FRAME<2:0>
X
TERM_DAT<2:0>
The LVDS buffers have high-impedance current sources that drive the outputs. When driving traces with
characteristic impedances that are not perfectly matched with the termination impedance on the receiver side,
there may be reflections back to the LVDS output pins of the AFE5805 that cause degraded signal integrity. By
enabling an internal termination (between the positive and negative outputs) for the LVDS buffers, the signal
integrity can be significantly improved in such scenarios. To set the internal termination mode, the
EN_LVDS_TERM bit should be set to '1'. Once this bit is set, the internal termination values for the bit clock,
frame clock, and data buffers can be independently programmed using sets of three bits. Table 14 shows an
example of how the internal termination of the LVDS buffer driving the bit clock is programmed (the method is
similar for the frame clock and data drive strengths). These termination values are only typical values and can
vary by several percent across temperature and from device to device.
Table 14. Bit Clock Internal Termination
TERM_LCLK<2>
TERM_LCLK<1>
TERM_LCLK<0>
INTERNAL TERMINATION BETWEEN
LCLKP AND LCLKM IN Ω
0
0
0
None
0
0
1
260
0
1
0
150
0
1
1
94
1
0
0
125
1
0
1
80
1
1
0
66
1
1
1
55
LOW-FREQUENCY NOISE SUPPRESSION MODE
ADDRESS
IN HEX
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NAME
X
X
X
X
LFNS_CH<1:4>
14
X
X
X
X
LFNS_CH<8:5>
The low-frequency noise suppression mode is especially useful in applications where good noise performance is
desired in the frequency band of 0MHz to 1MHz (around dc). Setting this mode shifts the low-frequency noise of
the AFE5805 to approximately fS/2, thereby moving the noise floor around dc to a much lower value.
LFNS_CH<8:1> enables this mode individually for each channel.
30
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LVDS TEST PATTERNS
ADDRESS
IN HEX
D15
D14
D13
D12
D11
D10
D9
D8
D7
25
D6
D5
D4
X
0
0
D3
D2
D1
0
X
0
DUALCUSTOM_PAT
0
0
X
SINGLE_CUSTOM_PAT
X
X
X
X
X
X
X
X
X
X
X
27
X
X
X
X
X
X
X
X
X
X
NAME
EN_RAMP
X
26
D0
X
X
BITS_CUSTOM1<11:10>
BITS_CUSTOM2<11:10>
BITS_CUSTOM1<9:0>
BITS_CUSTOM2<9:0>
0
X
PAT_DESKEW
X
0
PAT_SYNC
45
The AFE5805 can output a variety of test patterns on the LVDS outputs. These test patterns replace the normal
ADC data output. Setting EN_RAMP to '1' causes all the channels to output a repeating full-scale ramp pattern.
The ramp increments from zero code to full-scale code in steps of 1LSB every clock cycle. After hitting the
full-scale code, it returns back to zero code and ramps again.
The device can also be programmed to output a constant code by setting SINGLE_CUSTOM_PAT to '1', and
programming the desired code in BITS_CUSTOM1<11:0>. In this mode, BITS_CUSTOM<11:0> take the place of
the 12-bit ADC data at the output, and are controlled by LSB-first and MSB-first modes in the same way as
normal ADC data are.
The device may also be made to toggle between two consecutive codes by programming DUAL_CUSTOM_PAT
to '1'. The two codes are represented by the contents of BITS_CUSTOM1<11:0> and BITS_CUSTOM2<11:0>.
In addition to custom patterns, the device may also be made to output two preset patterns:
1. Deskew patten: Set using PAT_DESKEW, this mode replaces the 12-bit ADC output D<11:0> with the
010101010101 word.
2. Sync pattern: Set using PAT_SYNC, the normal ADC word is replaced by a fixed 111111000000 word.
Note that only one of the above patterns can be active at any given instant.
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PROGRAMMABLE GAIN
ADDRESS
IN HEX
D15
D14
D13
D12
D11
D10
D9
D8
D7
X
D6
X
D5
D4
X
D3
D2
D1
D0
NAME
X
X
X
X
GAIN_CH4<3:0>
X
GAIN_CH3<3:0>
2A
X
X
X
X
X
X
X
X
X
X
X
X
GAIN_CH2<3:0>
GAIN_CH1<3:0>
GAIN_CH5<3:0>
X
X
X
X
GAIN_CH6<3:0>
2B
X
X
X
X
GAIN_CH7<3:0>
X
X
X
X
GAIN_CH8<3:0>
The AFE5805, through its registers, allows for a digital gain to be programmed for each channel. This
programmable gain can be set to achieve the full-scale output code even with a lower analog input swing. The
programmable gain not only fills the output code range of the ADC, but also enhances the SNR of the device by
using quantization information from some extra internal bits. The programmable gain for each channel can be
individually set using a set of four bits, indicated as GAIN_CHN<3:0> for Channel N. The gain setting is coded in
binary from 0dB to 12dB, as shown in Table 15.
Table 15. Gain Setting for Channel 1
32
GAIN_CH1<3>
GAIN_CH1<2>
GAIN_CH1<1>
GAIN_CH1<0>
CHANNEL 1 GAIN SETTING
0
0
0
0
0dB
0
0
0
1
1dB
0
0
1
0
2dB
0
0
1
1
3dB
0
1
0
0
4dB
0
1
0
1
5dB
0
1
1
0
6dB
0
1
1
1
7dB
1
0
0
0
8dB
1
0
0
1
9dB
1
0
1
0
10dB
1
0
1
1
11dB
1
1
0
0
12dB
1
1
0
1
Do not use
1
1
1
0
Do not use
1
1
1
1
Do not use
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CLOCK, REFERENCE, AND DATA OUTPUT MODES
ADDRESS
IN HEX
D15
D14
D13
D12
D11
D10
D9
D8
D7
1
1
1
1
1
1
D6
D5
D4
D3
D2
X
D1
D0
NAME
X
DIFF_CLK
EN_DCC
42
1
1
1
1
1
1
X
X
EXT_REF_VCM
X
PHASE_DDR<1:0>
X
X
BTC_MODE
MSB_FIRST
46
1
1
1
1
X
EN_SDR
1
1
FALL_SDR
INPUT CLOCK
The AFE5805 is configured by default to operate with a single-ended input clock; CLKP is driven by a CMOS
clock and CLKM is tied to '0'. However, by programming DIFF_CLK to '1', the device can be made to work with a
differential input clock on CLKP and CLKM. Operating with a low-jitter differential clock generally leads to
improved SNR performance.
In cases where the duty cycle of the input clock falls outside the 45% to 55% range, it is recommended to enable
an internal duty cycle correction circuit. Enable this circuit by setting the EN_DCC bit to '1'.
EXTERNAL REFERENCE
The AFE5805 can be made to operate in external reference mode by pulling the INT/EXT pin to '0'. In this mode,
the REFT and REFB pins should be driven with voltage levels of 2.5V and 0.5V, respectively, and must have
enough drive strength to drive the switched capacitance loading of the reference voltages by each ADC. The
advantage of using the external reference mode is that multiple AFE5805 units can be made to operate with the
same external reference, thereby improving parameters such as gain matching across devices. However, in
applications that do not have an available high drive, differential external reference, the AFE5805 can still be
driven with a single external reference voltage on the CM pin. When EXT_REF_VCM is set as '1' (and the
INT/EXT pin is set to '0'), the CM pin is configured as an input pin, and the voltages on REFT and REFB are
generated as shown in Equation 1 and Equation 2.
V
VREFT = 1.5V + CM
1.5V
(1)
VCM
VREFB = 1.5V 1.5V
(2)
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BIT CLOCK PROGRAMMABILITY
The output interface of the AFE5805 is normally a DDR interface, with the LCLK rising edge and falling edge
transitions in the middle of alternate data windows. Figure 43 shows this default phase.
FCLKP
LCLKP
OUTP
Figure 43. LCLK Default Phase
The phase of LCLK can be programmed relative to the output frame clock and data using bits
PHASE_DDR<1:0>. Figure 44 shows the LCLK phase modes.
PHASE_DDR<1:0> = '00'
PHASE_DDR<1:0> = '10'
FCLKP
FCLKP
LCLKP
LCLKP
OUTP
OUTP
PHASE_DDR<1:0> = '01'
PHASE_DDR<1:0> = '11'
FCLKP
FCLKP
LCLKP
LCLKP
OUTP
OUTP
Figure 44. LCLK Phase Programmability Modes
34
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In addition to programming the phase of LCLK in the DDR mode, the device can also be made to operate in SDR
mode by setting the EN_SDR bit to '1'. In this mode, the bit clock (LCLK) is output at 12 times the input clock, or
twice the rate as in DDR mode. Depending on the state of FALL_SDR, LCLK may be output in either of the two
manners shown in Figure 45. As Figure 45 illustrates, only the LCLK rising (or falling) edge is used to capture the
output data in SDR mode.
EN_SDR = '1', FALL_SDR = '0'
EN_SDR = '1', FALL_SDR = '1'
FCLKP
FCLKP
LCLKP
LCLKP
OUTP
OUTP
Figure 45. SDR Interface Modes
The SDR mode does not work well beyond 40MSPS because the LCLK frequency becomes very high.
DATA OUTPUT FORMAT MODES
The ADC output, by default, is in straight offset binary mode. Programming the BTC_MODE bit to '1' inverts the
MSB, and the output becomes binary two's complement mode.
Also by default, the first bit of the frame (following the rising edge of FCLKP) is the LSB of the ADC output.
Programming the MSB_FIRST mode inverts the bit order in the word, and the MSB is output as the first bit
following the FCLKP rising edge.
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RECOMMENDED POWER-UP SEQUENCING AND RESET TIMING
t1
(3.3V, 5.0V)
AVDD1
AVDD2
DVDD
AVDD-5V
LVDD
t2
(1.8V)
t3
t4
t7
High-Level RESET
(1.4V to 3.6V)
t5
ADS_RESET
t6
Device Ready for
Serial Register Write
High-Level CS
(1.4V to 3.6V)
CS
Start of Clock
Device Ready for
Data Conversion
FCLK
t8
10µs < t1 < 50ms, 10µs < t2 < 50ms, –10ms < t3 < 10ms, t4 > 10ms, t5 > 100ns, t6 > 100ns, t7 > 10ms, and t8 > 100µs.
The AVDDx and LVDD power-on sequence does not matter as long as –10ms < t3 < 10ms. Similar considerations apply while shutting down
the device.
POWER-DOWN TIMING
1m s
VCA_PD, ADC_PD
(1)
tWAKE
(2)
Device Fully
Powers Down
Device Fully
Powers Up
Power-up time shown is based on 1µF bypass capacitors on the reference pins. tWAKE is the time it takes for the device to wake up
completely from power-down mode. The AFE5805 has two power-down modes: complete power-down mode and partial power-down mode.
(1) tWAKE ≤ 50µs for complete power-down mode. tWAKE ≤ 2µs for partial power-down mode (provided the clock is not shut off during
power-down).
(2) The ADS_PD pins can be configured for partial power-down mode through a register setting.
36
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THEORY OF OPERATION
The AFE5805 is an 8-channel, fully integrated analog
front-end device controlling the LNA, attenuator,
PGA, LPF, and ADC, that implements a number of
proprietary circuit design techniques to specifically
address the performance demands of medical
ultrasound systems. It offers unparalleled low-noise
and low-power performance at a high level of
integration. For the TGC signal path, each channel
consists of a 20dB fixed-gain low-noise amplifier
(LNA), a linear-in-dB voltage-controlled attenuator
(VCA), and a programmable gain amplifier (PGA), as
well as a clamping and low-pass filter stage. Digitally
controlled through the logic interface, the PGA gain
can be set to four different settings: 20dB, 25dB,
27dB, and 30dB. At its highest setting, the total
available gain of the AFE5805 is therefore 50dB. To
facilitate the logarithmic time-gain compensation
required for ultrasound systems, the VCA is designed
to provide a 46dB attenuation range. Here, all
channels are simultaneously controlled by an
externally-applied control voltage (VCNTL) in the range
of 0V to 1.2V. While the LNA is designed to be driven
from a single-ended source, the internal TGC signal
path is designed to be fully differential to maximize
dynamic range while also optimizing for low,
even-order harmonic distortion.
CW doppler signal processing is facilitated by routing
the differential LNA outputs to V/I amplifier stages.
The resulting signal currents of each channel then
connect to an 8×10 switch matrix that is controlled
through the serial interface and a corresponding
register. The CW outputs are typically routed to a
passive delay line that allows coherent summing
(beam forming) of the active channels and additional
off-chip signal processing, as shown in Figure 46.
Applications that do not utilize the CW path can
simply operate the AFE5805 in TGC mode. In this
mode, the CW blocks (V/I amplifiers and switch
matrix) remain powered down, and the CW outputs
can be left unconnected.
AFE5805
V/I
T/R
Switch
CW/IOUT
CW Switch Matrix
CIN
LNA
Attenuator
(VCA)
LPF
PGA
Clamp
12-Bit
ADC
LVDS
Serializer
OUT
OUT
VCNTL
Figure 46. Functional Block Diagram
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LOW-NOISE AMPLIFIER (LNA)
As with many high-gain systems, the front-end
amplifier is critical to achieve a certain overall
performance level. Using a new proprietary
architecture, the LNA of the AFE5805 delivers
exceptional low-noise performance, while operating
on a very low quiescent current compared to
CMOS-based architectures with similar noise
performances.
The LNA performs a single-ended input to differential
output voltage conversion and is configured for a
fixed gain of 20dB (10V/V). The ultralow
input-referred noise of only 0.7nV/√Hz, along with the
linear input range of 250mVPP, results in a wide
dynamic range that supports the high demands of
PW and CW ultrasound imaging modes. Larger input
signals can be accepted by the LNA, but distortion
performance degrades as input signal levels
increase. The LNA input is internally biased to
approximately +2.4V; the signal source should be
ac-coupled to the LNA input by an adequately-sized
capacitor. Internally, the LNA directly drives the VCA,
avoiding the typical drawbacks of ac-coupled
architectures, such as slow overload recovery.
VOLTAGE-CONTROLLED ATTENUATOR
(VCA)
The attenuator is essentially a variable voltage divider
that consists of the series input resistor (RS) and
eight identical shunt FETs placed in parallel and
controlled by sequentially activated clipping amplifiers
(A1 through A8). Each clipping amplifier can be
understood as a specialized voltage comparator with
a soft transfer characteristic and well-controlled
output limit voltage. Reference voltages V1 through
V8 are equally spaced over the 0V to 1.2V control
voltage range. As the control voltage rises through
the input range of each clipping amplifier, the
amplifier output rises from 0V (FET completely ON) to
VCM – VT (FET nearly OFF), where VCM is the
common source voltage and VT is the threshold
voltage of the FET. As each FET approaches its off
state and the control voltage continues to rise, the
next clipping amplifier/FET combination takes over for
the next portion of the piecewise-linear attenuation
characteristic.
Thus, low control voltages have most of the FETs
turned on, producing maximum signal attenuation.
Similarly, high control voltages turn the FETs off,
leading to minimal signal attenuation. Therefore, each
FET acts to decrease the shunt resistance of the
voltage divider formed by RS and the parallel FET
network.
The VCA is designed to have a linear-in-dB
attenuation characteristic; that is, the average gain
loss in dB is constant for each equal increment of the
control voltage (VCNTL). Figure 47 shows the
simplified schematic of this VCA stage.
A1-A8 Attenuator Stages
Attenuator
Input
RS
QS
Q1
VB
A1
Q2
A2
C1
V1
Q3
A3
C2
V2
Q4
A4
C3
V3
Attenuator
Output
Q5
A5
C4
V4
Q6
A6
C5
V5
Q7
A7
C6
A8
C7
V6
Q8
V7
C8
V8
VCNTL
Control
Input
C1-C8 Clipping Amplifiers
Figure 47. Voltage-Controlled Attenuator Simplified Schematic
38
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PROGRAMMABLE POST-GAIN AMPLIFIER
(PGA)
Following the VCA is a programmable post-gain
amplifier (PGA). Figure 48 shows a simplified
schematic of the PGA, including the clamping stage.
The gain of this PGA can be configured to four
different gain settings: 20dB, 25dB, 27dB, and 30dB,
programmable through the serial port; see Table 10.
The PGA structure consists of a differential,
programmable-gain
voltage-to-current
converter
stage followed by transimpedance amplifiers to buffer
each side of the differential output. Low input noise is
also a requirement for the PGA design as a result of
the large amount of signal attenuation that can be
applied in the preceding VCA stage. At minimum
VCA attenuation (used for small input signals), the
LNA noise dominates; at maximum VCA attenuation
(large input signals), the attenuator and PGA noise
dominate.
A1
From
Attenuator
Gain
Control
Bits
Clamp
Control
Bit
RG
Clamp
To
Low-Pass
Filter
PROGRAMMABLE CLAMPING
To further optimize the overload recovery behavior of
a complete TGC channel, the AFE5805 integrates a
programmable clamping stage, as shown in
Figure 49. This clamping stage precedes the
low-pass filter in order to prevent the filter circuit from
being driven into overload, the result of which would
be an extended recovery time. Programmable
through the serial interface, the clamping level can be
either set to clamp the signal level to approximately
1.7VPP differential, or be disabled. Disabling the
clamp function increases the current consumption on
the 3.3V analog supply (AVDD2) by about 3mA for
the full device. Note that with the clamp function
enabled, the third-harmonic distortion increases.
LOW-PASS FILTER
The AFE5805 integrates an anti-aliasing filter in the
form of a programmable low-pass filter (LPF) for each
channel. The LPF is designed as a differential, active,
second-order filter that approximates a Bessel
characteristic, with typically 12dB per octave roll-off.
Figure 49 shows the simplified schematic of half the
differential active low-pass filter. Programmable
through the serial interface, the –3dB frequency
corner can be set to either 10MHz or 15MHz. The
filter bandwidth is set for all channels simultaneously.
A2
Figure 48. Post-Gain Amplifier
(Simplified Schematic)
PGA
To ADC
Inputs
VCM
(+1.65V)
Figure 49. Clamping Stage and Low-Pass Filter (Simplified Schematic)
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ANALOG-TO-DIGITAL CONVERSION
The analog-to-digital converter (ADC) of the AFE5805
employs a pipelined converter architecture that
consists of a combination of multi-bit and single-bit
internal stages. Each stage feeds its data into the
digital error correction logic, ensuring excellent
differential linearity and no missing codes at the
12-bit level.
The 12 bits given out by each channel are serialized
and sent out on a single pair of pins in LVDS format.
All eight channels of the AFE5805 operate from a
common input clock (CLKP/M). The sampling clocks
for each of the eight channels are generated from the
input clock using a carefully matched clock buffer
tree. The 12x clock required for the serializer is
generated internally from CLKP/M using a
phase-locked loop (PLL). A 6x and a 1x clock are
also output in LVDS format, along with the data, to
enable easy data capture. The AFE5805 operates
from internally-generated reference voltages that are
trimmed to improve the gain matching across
devices, and provide the option to operate the
devices without having to externally drive and route
reference lines. The nominal values of REFT and
40
REFB are 2.5V and 0.5V, respectively. The
references are internally scaled down differentially by
a factor of 2. VCM (the common-mode voltage of
REFT and REFB) is also made available externally
through a pin, and is nominally 1.5V.
The ADC output goes to a serializer that operates
from a 12x clock generated by the PLL. The 12 data
bits from each channel are serialized and sent LSB
first. In addition to serializing the data, the serializer
also generates a 1x clock and a 6x clock. These
clocks are generated in the same way the serialized
data are generated, so these clocks maintain perfect
synchronization with the data. The data and clock
outputs of the serializer are buffered externally using
LVDS buffers. Using LVDS buffers to transmit data
externally has multiple advantages, such as a
reduced number of output pins (saving routing space
on the board), reduced power consumption, and
reduced effects of digital noise coupling to the analog
circuit inside the AFE5805.
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APPLICATION INFORMATION
The LNA closed-loop architecture is internally
compensated for maximum stability without the need
of external compensation components (inductors or
capacitors). At the same time, the total input
capacitance is kept to a minimum with only 16pF.
This architecture minimizes any loading of the signal
source
that
may
otherwise
lead
to
a
frequency-dependent voltage divider. Moreover, the
closed-loop design yields very low offsets and offset
drift; this consideration is important because the LNA
directly drives the subsequent voltage-controlled
attenuator.
ANALOG INPUT AND LNA
While the LNA is designed as a fully differential
amplifier, it is optimized to perform a single-ended
input to differential output conversion. A simplified
schematic of an LNA channel is shown in Figure 50.
A bias voltage (VB) of +2.4V is internally applied to
the LNA inputs through 8kΩ resistors. In addition, the
dedicated signal input (IN pin) includes a pair of
back-to-back diodes that provide a coarse input
clamping function in case the input signal rises to
very large levels, exceeding 0.7VPP. This
configuration prevents the LNA from being driven into
a severe overload state, which may otherwise cause
an extended overload recovery time. The integrated
diodes are designed to handle a dc current of up to
approximately 5mA. Depending on the application
requirements, the system overload characteristics
may be improved by adding external Schottky diodes
at the LNA input, as shown in Figure 50.
The LNA of the AFE5805 uses the benefits of a
bipolar process technology to achieve an
exceptionally low-noise voltage of 0.7nV/√Hz, and a
low current noise of only 3pA/√Hz. With these
input-referred noise specifications, the AFE5805
achieves very low noise figure numbers over a wide
range of source resistances and frequencies (see
Figure 16, Noise Figure vs Frequency vs RS in the
Typical Characteristics). The optimal noise power
matching is achieved for source impedances of
around 200Ω. Further details of the AFE5805 input
noise performance are shown in the Typical
Characteristic graphs.
As Figure 50 also shows, the complementary LNA
input (VBL pin) is internally decoupled by a small
capacitor. Furthermore, for each input channel, a
separate VBL pin is brought out for external
bypassing. This bypassing should be done with a
small, 0.1µF (typical) ceramic capacitor placed in
close proximity to each VBL pin. Attention should be
given to provide a low-noise analog ground for this
bypass capacitor. A noisy ground potential may
cause noise to be picked up and injected into the
signal path, leading to higher noise levels.
Table 16. Noise Figure versus Source Resistance
(RS) at 2MHz
RS (Ω)
NOISE FIGURE (dB)
50
2.6
200
1.0
400
1.1
1000
2.3
IN
T/R
A1
CIN
³ 0.1mF
8kW
VB
(+2.4V)
To
Attenuator
8kW
A2
VBL
0.1mF
7pF
AFE5805
Figure 50. LNA Channel (Simplified Schematic)
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OVERLOAD RECOVERY
are largely determined by the biasing current of the
diodes, which can be set by adjusting the 3kΩ
resistor values; for example, setting a higher current
level may lead to an improved switching characteristic
and reduced noise contribution. A typical front-end
protection circuitry may add in the order of 2nV/√Hz
of noise to the signal path. The increase in noise also
depends on the value of the termination resistor (RT).
The AFE5805 is designed in particular for ultrasound
applications where the front-end device is required to
recover very quickly from an overload condition. Such
an overload can either be the result of a transmit
pulse feed-through or a strong echo, which can cause
overload of the LNA, PGA, and ADC. As discussed
earlier, the LNA inputs are internally protected by a
pair of back-to-back diodes to prevent severe
overload of the LNA. Figure 51 illustrates an
ultrasound receive channel front-end that includes
typical external overload protection elements. Here,
four high-voltage switching diodes are configured in a
bridge configuration and form the transmit/receive
(T/R) switch. During the transmit period, high voltage
pulses from the pulser are applied to the transducer
elements and the T/R switch isolates the sensitive
LNA input from being damaged by the high voltage
signal. However, it is common that fast transients up
to several volts leak through the T/R switch and
potentially overload the receiver. Therefore, an
additional pair of clamping diodes is placed between
the T/R switch and the LNA input. In order to clamp
the over-voltage to small levels, Schottky diodes
(such as the BAS40 series by Infineon®) are
commonly used. For example, clamping to levels of
±0.3V can significantly reduce the overall overload
recovery performance. The T/R switch characteristics
As Figure 51 shows, the front-end circuitry should be
capacitively coupled to the LNA signal input (IN). This
coupling ensures that the LNA input bias voltage of
+2.4V is maintained and decoupled from any other
biasing voltage before the LNA.
Within the AFE5805, overload can occur in either the
LNA or the PGA. LNA overload can occur as the
result of T/R switch feed-through; and the PGA can
be driven into an overload condition by a strong echo
in the near-field while the signal gain is high. In any
case, the AFE5805 is optimized for very short
recovery times, as shown in Figure 51.
+5V
3kW
C1
Cable
C2
³ 0.1mF
IN
VBL
BAS40
3kW
Probe
Transducer
From
Pulser
LNA
RT
0.1mF
AFE5805
-5V
Figure 51. Typical Input Overload Protection Circuit of an Ultrasound System
42
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VCA—GAIN CONTROL
The attenuator (VCA) for each of the eight channels
of the AFE5805 is controlled by a single-ended
control signal input, the VCNTL pin. The control voltage
range spans from 0V to 1.2V, referenced to ground.
This control voltage varies the attenuation of the VCA
based on its linear-in-dB characteristic with its
maximum attenuation (minimum gain) at VCNTL = 0V,
and minimum attenuation (maximum gain) at VCNTL =
1.2V. Table 17 shows the nominal gains for each of
the four PGA gain settings. The total gain range is
typically 46dB and remains constant, independent of
the PGA selected; the Max Gain column reflects the
absolute gain of the full signal path comprised of the
fixed LNA gain of 20dB and the programmable PGA
gain.
When the AFE5805 operates in CW mode, the
attenuator stage remains connected to the LNA
outputs. Therefore, it is recommended to set the
VCNTL voltage to +1.2V in order to minimize the
internal loading of the LNA outputs. Small
improvements in reduced power dissipation and
improved distortion performance may also be
realized.
AFE5805
Attenuator
RS
IN
To
PGA
LNA
Table 17. Nominal Gain Control Ranges for Each
of the Four PGA Gain Settings
PGA GAIN
MIN GAIN AT VCNTL
= 0V
MAX GAIN AT
VCNTL = 1.2V
20dB
–4.5dB
41.5dB
25dB
–0.5dB
45.5dB
27dB
1.5dB
47.5dB
30dB
3.5dB
49.5dB
As previously discussed, the VCA architecture uses
eight attenuator segments that are equally spaced in
order to approximate the linear-in-dB gain-control
slope. This approximation results in a monotonic
slope; gain ripple is typically less than ±0.5dB.
The AFE5805 gain-control input has a –3dB
bandwidth of approximately 1.5MHz. This wide
bandwidth, although useful in many applications, can
allow high-frequency noise to modulate the gain
control input. In practice, this modulation can easily
be avoided by additional external filtering (RF and CF)
of the control input, as Figure 52 shows. Stepping the
control voltage from 0V to 1.2V, the gain control
response time is typically less than 500ns to settle
within 10% of the final signal level of 1VPP (–6dBFS)
output.
The control voltage input (VCNTL pin) represents a
high-impedance input. Multiple AFE5805 devices can
be connected in parallel with no significant loading
effects using the VCNTL pin of each device. Note that
when the VCNTL pin is left unconnected, it floats up to
a potential of about +3.7V. For any voltage level
above 1.2V and up to 5.0V, the VCA continues to
operate at its minimum attenuation level; however, it
is recommended to limit the voltage to approximately
1.5V or less.
RS
VCNTL
RF
CF
Figure 52. External Filtering of the VCNTL Input
CW DOPPLER PROCESSING
The AFE5805 integrates many of the elements
necessary to allow for the implementation of a CW
doppler processing circuit, such as a V/I converter for
each channel and a cross-point switch matrix with an
8-input into 10-output (8×10) configuration.
In order to switch the AFE5805 from the default TGC
mode operation into CW mode, bit D5 of the VCA
control register must be updated to low ('0'); see
Table 5. This setting also enables access to all other
registers that determine the switch matrix
configuration (see the Input Register Bit Map tables).
In order to process CW signals, the LNA internally
feeds into a differential V/I amplifier stage. The
transconductance of the V/I amplifier is typically
15.6mA/V with a 100mVPP input signal. For proper
operation, the CW outputs must be connected to an
external bias voltage of +2.5V. Each CW output is
designed to sink a small dc current of 0.9mA, and
can deliver a signal current of up to 2.9mAPP.
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The resulting signal current then passes through the
8×10 switch matrix. Depending on the programmed
configuration of the switch matrix, any V/I amplifier
current output can be connected to any of 10 CW
outputs. This design is a simple current-summing
circuit such that each CW output can represent the
sum of any or all of the channel currents. The CW
outputs are typically routed to a passive LC delay
line, allowing coherent summing of the signals.
L = 220mH
After summing, the CW signal path further consists of
a high dynamic range mixer for down-conversion to
I/Q base-band signals. The I/Q signals are then
band-limited (that is, low-frequency contents are
removed) in a filter stage that precedes a pair of
high-resolution, low sample rate ADCs.
VCM0
(+2.5V)
ADC
Amplifier
0
90
CW0
I and Q
Channel
ADC
CW1
CW2
CW3
AFE5805
CW4
CW Out
8 In By 10 Out CW5
Passive
Delay
Line
Clock
CW6
CW7
CW8
CW9
CW0
CW1
CW2
CW3
AFE5805
CW4
CW Out
8 In By 10 Out CW5
CW6
CW7
CW8
CW9
Figure 53. Conceptual CW Doppler Signal Path Using Current Summing and a Passive Delay Line for
Beamforming
44
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CLOCK INPUT
The eight channels on the device operate from a
single clock input. To ensure that the aperture delay
and jitter are the same for all channels, the AFE5805
uses a clock tree network to generate individual
sampling clocks to each channel. The clock paths for
all the channels are matched from the source point to
the sampling circuit. This architecture ensures that
the performance and timing for all channels are
identical. The use of the clock tree for matching
introduces an aperture delay that is defined as the
delay between the rising edge of FCLK and the actual
instant of sampling. The aperture delays for all the
channels are matched to the best possible extent. A
mismatch of ±20ps (±3σ) could exist between the
aperture instants of the eight ADCs within the same
chip. However, the aperture delays of ADCs across
two different chips can be several hundred
picoseconds apart.
The AFE5805 can operate either in CMOS
single-ended clock mode (default is DIFF_CLK = 0)
or differential clock mode (SINE, LVPECL, or LVDS).
In the single-ended clock mode, CLKM must be
forced to 0VDC, and the single-ended CMOS applied
on the CLKP pin. Figure 54 shows this operation.
CMOS Single-Ended
Clock
CLKP
0V
CLKM
CM
VCM
5kW
5kW
CLKP
CLKM
Figure 55. Internal Clock Buffer
0.1mF
CLKP
Differential Sine-Wave,
PECL, or LVDS Clock Input
0.1mF
CLKM
Figure 56. Differential Clock Driving Circuit
(DIFF_CLK = 1)
0.1mF
CMOS Clock Input
0.1mF
Figure 54. Single-Ended Clock Driving Circuit
(DIFF_CLK = 0)
When configured for the differential clock mode
(register bit DIFF_CLK = 1) the AFE5805 clock inputs
can be driven differentially (SINE, LVPECL, or LVDS)
with little or no difference in performance between
them, or with a single-ended (LVCMOS). The
common-mode voltage of the clock inputs is set to
VCM using internal 5kΩ resistors, as shown in
Figure
55.
This
method
allows
using
transformer-coupled drive circuits for a sine wave
clock or ac-coupling for LVPECL and LVDS clock
sources, as shown in Figure 56 and Figure 57. When
operating in the differential clock mode, the
single-ended CMOS clock can be ac-coupled to the
CLKP input, with CLKM connected to ground with a
0.1µF capacitor, as Figure 57 shows.
CLKP
CLKM
Figure 57. Single-Ended Clock Driving Circuit
When DIFF_CLK = 1
For best performance, the clock inputs must be
driven differentially, reducing susceptibility to
common-mode noise. For high input frequency
sampling, it is recommended to use a clock source
with very low jitter. Bandpass filtering of the clock
source can help reduce the effect of jitter. If the duty
cycle deviates from 50% by more than 2% or 3%, it is
recommended to enable the DCC through register bit
EN_DCC.
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REFERENCE CIRCUIT
3-state output. The external reference driving circuit
should be designed to provide the required switching
current for the eight ADCs inside the AFE5805. It
should be noted that in this mode, CM and ISET
continue to be generated from the internal bandgap
voltage, as in the internal reference mode. It is
therefore important to ensure that the common-mode
voltage of the externally-forced reference voltages
matches to within 50mV of VCM.
The digital beam-forming algorithm in an ultrasound
system relies on gain matching across all receiver
channels. A typical system would have about 12 octal
AFEs on the board. In such a case, it is critical to
ensure that the gain is matched, essentially requiring
the reference voltages seen by all the AFEs to be the
same. Matching references within the eight channels
of a chip is done by using a single internal reference
voltage buffer. Trimming the reference voltages on
each chip during production ensures that the
reference voltages are well-matched across different
chips.
The second method of forcing the reference voltages
externally can be accessed by pulling INT/EXT low,
and programming the serial interface to drive the
external reference mode through the CM pin (register
bit called EXT_REF_VCM). In this mode, CM
becomes configured as an input pin that can be
driven from external circuitry. The internal reference
buffers driving REFT and REFB are active in this
mode. Forcing 1.5V on the CM pin in the mode
results in REFT and REFB coming to 2.5V and 0.5V,
respectively. In general, the voltages on REFT and
REFB in this mode are given by Equation 3 and
Equation 4:
V
VREFT = 1.5V + CM
1.5V
(3)
VCM
VREFB = 1.5V 1.5V
(4)
All bias currents required for the internal operation of
the device are set using an external resistor to
ground at the ISET pin. Using a 56kΩ resistor on
ISET generates an internal reference current of 20µA.
This current is mirrored internally to generate the bias
current for the internal blocks. Using a larger external
resistor at ISET reduces the reference bias current
and thereby scales down the device operating power.
However, it is recommended that the external resistor
be within 10% of the specified value of 56kΩ so that
the internal bias margins for the various blocks are
proper.
Buffering the internal bandgap voltage also generates
the common-mode voltage VCM, which is set to the
midlevel of REFT and REFB. It is meant as a
reference voltage to derive the input common-mode if
the input is directly coupled. It can also be used to
derive the reference common-mode voltage in the
external reference mode. Figure 58 shows the
suggested decoupling for the reference pins.
The state of the reference voltage internal buffers
during various combinations of the ADS_PD,
INT/EXT, and EXT_REF_VCM register bits is
described in Table 18.
The device also supports the use of external
reference voltages. There are two methods to force
the references externally. The first method involves
pulling INT/EXT low and forcing externally REFT and
REFB to 2.5V and 0.5V nominally, respectively. In
this mode, the internal reference buffer goes to a
AFE5805
ISET
REFT
0.1mF
+
2.2mF
REFB
+
2.2mF
56.2kW
0.1mF
Figure 58. Suggested Decoupling on the Reference Pins
46
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Table 18. State of Reference Voltages for Various Combinations of ADS_PD and INT/EXT
PIN, REGISTER BIT
(1)
INTERNAL BUFFER STATE
ADS_PD pin
0
0
1
1
0
0
1
1
INT/EXT pin
0
1
0
1
0
1
0
1
EXT_REF_VCM
0
0
0
0
1
1
1
1
REFT buffer
3-state
2.5V
3-state
2.5V (1)
1.5V + VCM/1.5V
Do not use
2.5V (1)
Do not use
REFB buffer
3-state
0.5V
3-state
0.5V (1)
1.5V – VCM/1.5V
Do not use
0.5V (1)
Do not use
CM pin
1.5V
1.5V
1.5V
1.5V
Force
Do not use
Force
Do not use
Weakly forced with reduced strength.
POWER SUPPLIES
The AFE5805 operates on three supply rails: a digital
1.8V supply, and the 3.3V and 5V analog supplies. At
initial power-up, the part is operational in TGC mode,
with the registers in the respective default
configurations (see Table 2).
In TGC mode, only the VCA (attenuator) draws a low
current (typically 8mA) from the 5V supply. Switching
into the CW mode, the internal V/I-amplifiers are then
powered from the 5V rails as well, raising the
operating current on the 5V rail. At the same time, the
post-gain amplifiers (PGA) are being powered down,
thereby reducing the current consumption on the 3.3V
rail (refer to the Electrical Characteristics table for
details on TGC mode and CW mode current
consumption).
All analog supply rails for the AFE5805 should be low
noise, including the 3.3V digital supply DVDD that
connects to the internal logic blocks of the VCA within
the AFE5805. It is recommended to tie the DVDD
pins to the same 3.3V analog supply as the AVDD1/2
pins, rather than a different 3.3V rail that may also
provide power to other logic device in the system.
Transients and noise generated by those devices can
couple into the AFE5805 and degrade overall device
performance.
CLOCK JITTER, POWER NOISE, SNR, AND
LVDS TIMING
As explained in application note SLYT075, ADC clock
jitter can degrade ADC performance. Therefore, it is
always preferred to use a low jitter clock to drive the
AFE5805. To ensure the performance of the
AFE5805, a clock with a jitter of 1ps RMS or better is
expected. However, it might not be always possible to
use this clock configuration for practical reasons. With
a higher clock jitter, the SNR of the AFE5805 may be
degraded as well as the LVDS timing stability. In
addition, clean and stable power supplies are always
preferred to maximize device SNR performance and
ensure LVDS timing stability.
Poor RMS jitter (> 100ps), combined with inadequate
power-supply design (for example, supply voltage
drops and ripple increases), can affect LVDS timing.
As a result, occasional glitches might be observed on
the AFE5805 outputs. If this phenomenon is
observed, or if clock jitter and LVDD noise are
concerns in the overall system, the registers
described in Table 19 can be written as part of the
initialization sequence in order to stabilize LVDS
clock timing.
Table 19. Address and Data in Hexadecimal
ADDRESS
DATA
01
0010h
D1
0140h
DA
0001h
E1
0020h
01
0000h
Writing to these registers has the following additional
effects:
a. Total chip power increases by approximately
4mW—this includes a current increase of about
0.6mA on AVDD1 and about 1.1mA on LVDD.
b. With reference to the LVDS Timing Diagram and
the Definition of Setup and Hold Times,
LCLKP/LCLKM shift by about 100ps to the left
relative to CLK and OUTP/OUTM. This shift
causes the data setup time to reduce by 100ps
and the data hold time to increase by 100ps.
c. The clock propagation delay (tPROP) is reduced by
approximately 2ns. The typical and minimum
values for this specification are reduced by 2ns,
and the maximum value is reduced by 1.5ns.
Power-supply noise usually can be minimized if
grounding, bypassing, and printed circuit board (PCB)
layout are well managed. Some guidelines can be
found in the Grounding and Bypassing and Board
Layout sections.
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): AFE5805
47
AFE5805
SBOS421C – MARCH 2008 – REVISED OCTOBER 2008................................................................................................................................................. www.ti.com
GROUNDING AND BYPASSING
The AFE5805 distinguishes between three different
grounds: AVSS1 and AVSS2 (analog grounds), and
LVSS (digital ground). In most cases, it should be
adequate to lay out the printed circuit board (PCB) to
use a single ground plane for the AFE5805. Care
should be taken that this ground plane is properly
partitioned between various sections within the
system to minimize interactions between analog and
digital circuitry. Alternatively, the digital (LVDS)
supply set consisting of the LVDD and LVSS pins can
be placed on separate power and ground planes. For
this configuration, the AVSS and LVSS grounds
should be tied together at the power connector in a
star layout.
All bypassing and power supplies for the AFE5805
should be referenced to this analog ground plane. All
supply pins should be bypassed with 0.1µF ceramic
chip capacitors (size 0603 or smaller). In order to
minimize the lead and trace inductance, the
capacitors should be located as close to the supply
pins as possible. Where double-sided component
mounting is allowed, these capacitors are best placed
directly under the package. In addition, larger bipolar
decoupling capacitors (2.2µF to 10µF, effective at
lower frequencies) may also be used on the main
supply pins. These components can be placed on the
PCB in proximity (< 0.5in or 12.7mm) to the AFE5805
itself.
The AFE5805 internally generates a number of
reference voltages, such as the bias voltages (VB1
through VB6). Note that in order to achieve optimal
low-noise performance, the VB1 pin must be
bypassed with a capacitor value of at least 1µF; the
recommended value for this bypass capacitor is
2.2µF. All other designed reference pins can be
bypassed with smaller capacitor values, typically
0.1µF. For best results choose low-inductance
ceramic chip capacitors (size 402) and place them as
close as possible to the device pins as possible.
48
High-speed mixed signal devices are sensitive to
various types of noise coupling. One primary source
of noise is the switching noise from the serializer and
the output buffer/drivers. For the AFE5805, care has
been taken to ensure that the interaction between the
analog and digital supplies within the device is kept to
a minimal amount. The extent of noise coupled and
transmitted from the digital and analog sections
depends on the effective inductances of each of the
supply and ground connections. Smaller effective
inductance of the supply and ground pins leads to
improved noise suppression. For this reason, multiple
pins are used to connect each supply and ground
sets. It is important to maintain low inductance
properties throughout the design of the PCB layout by
use of proper planes and layer thickness.
BOARD LAYOUT
Proper grounding and bypassing, short lead length,
and the use of ground and power-supply planes are
particularly important for high-frequency designs.
Achieving
optimum
performance
with
a
high-performance device such as the AFE5805
requires careful attention to the PCB layout to
minimize the effects of board parasitics and optimize
component placement. A multilayer PCB usually
ensures best results and allows convenient
component placement.
In order to maintain proper LVDS timing, all LVDS
traces should follow a controlled impedance design
(for example, 100Ω differential). In addition, all LVDS
trace lengths should be equal and symmetrical; it is
recommended to keep trace length variations less
than 150mil (0.150in or 3.81mm).
Additional details on PCB layout techniques can be
found in the Texas Instruments Application Report
MicroStar BGA Packaging Reference Guide
(SSYZ015B), which can be downloaded from the TI
web site (www.ti.com).
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): AFE5805
PACKAGE OPTION ADDENDUM
www.ti.com
24-Oct-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
AFE5805ZCF
ACTIVE
BGA
ZCF
135
PAFE5805ZCF
PREVIEW
BGA
ZCF
135
160
Lead/Ball Finish
Green (RoHS &
no Sb/Br)
SNAGCU
TBD
Call TI
MSL Peak Temp (3)
Level-3-260C-168 HR
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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