® VFC320 Voltage-to-Frequency and Frequency-to-Voltage CONVERTER FEATURES DESCRIPTION ● HIGH LINEARITY, 12 to 14 bits ±0.005% max at 10kHz FS ±0.03% max at 100kHz FS ±0.1% typ at 1MHz FS ● V/F OR F/V CONVERSION The VFC320 monolithic voltage-to-frequency and frequency-to-voltage converter provides a simple low cost method of converting analog signals into digital pulses. The digital output is an open collector and the digital pulse train repetition rate is proportional to the amplitude of the analog input voltage. Output pulses are compatible with TTL, and CMOS logic families. ● 6-DECADE DYNAMIC RANGE ● 20ppm/°C max GAIN DRIFT High linearity (0.005%, max at 10kHz FS) is achieved with relatively few external components. Two external resistors and two external capacitors are required to operate. Full scale frequency and input voltage are determined by a resistor in series with –In and two capacitors (one-shot timing and input amplifier integration). The other resistor is a non-critical open collector pull-up (fOUT to +VCC). The VFC320 is available in three performance/temperature grades and two package configurations. The TO-100 versions are hermetically sealed, and specified for the –25°C to +85°C and –55°C to +125°C ranges, and the dual-in-line units are specified from –25°C to +85°C. ● OUTPUT TTL/CMOS COMPATIBLE APPLICATIONS ● INEXPENSIVE A/D AND D/A CONVERTER ● DIGITAL PANEL METERS ● TWO-WIRE DIGITAL TRANSMISSION WITH NOISE IMMUNITY ● FM MOD/DEMOD OF TRANSDUCER SIGNALS ● PRECISION LONG TERM INTEGRATOR ● HIGH RESOLUTION OPTICAL LINK FOR ISOLATION ● AC LINE FREQUENCY MONITOR ● MOTOR SPEED MONITOR AND CONTROL +VCC VOUT fIN –In +In Comparators –7.5V Ref Flipflop fOUT One-shot –VCC C1 Common International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1982 Burr-Brown Corporation PDS-483J Printed in U.S.A. August, 1993 SPECIFICATIONS At TA = +25°C and ±15VDC power supply, unless otherwise noted. VFC320BG/BM/SM PARAMETER CONDITIONS MIN Fig. 4 with e2 = 0 Fig. 4 with e1 = 0 IIN = VIN /RIN >0 <0 +0.25 TYP VFC320CG/CM MAX MIN TYP MAX UNITS ✻ V V µA V/F CONVERTER fOUT = VIN / 7.5 R1C1, Figure 4 INPUT TO OP AMP Voltage Range(1) Current Range(1) Bias Current Inverting Input Noninverting Input Offset Voltage(3) Offset Voltage Drift Differential Impedance Common-Mode Impedance ACCURACY Linearity Error (1) (4) (5) Offset Error Input Offset Voltage(3) Offset Drift(7) Gain Error(3) Gain Drift(7) Full Scale Drift (Offset Drift and Gain Drift) (7)(8)(9) Power Supply Sensitivity DYNAMIC RESPONSE Full Scale Frequency Dynamic Range Settling Time Overload Recovery OPEN COLLECTOR OUTPUT Voltage, Logic “0” Leakage Current, Logic “1” Voltage, Logic “1” Duty Cycle at FS Fall Time Note 2 –10 +750 4 10 300 || 5 ±5 650 || 5 300 || 3 500 || 3 Fig. 4 with e2 = 0(6) 0.01Hz ≤ fOUT ≤ 10kHz 0.1Hz ≤ fOUT ≤ 100kHz 1Hz ≤ fOUT ≤ 1MHz ±0.004 ±0.008 ±0.1 ±0.5 ±5 ✻ ✻ 8 30 ±0.15 ✻ ✻ ✻ ✻ ✻ kΩ || pF ±0.0015 ✻ ✻ ±15 ±10 50 50 ±VCC = 14VDC to 18VDC ±0.015 ✻ ✻ 1 % FSR % FSR % FSR ✻ ✻ 20 20 ppm FSR ppm FSR/°C % FSR ppm FSR/°C ppm FSR/°C ✻ % FSR% ✻ MHz Decades ✻ ✻ V µA ✻ V % ns ✻ ✻ Note 10 Note 10 ISINK = 8mA, max VO = 15V External Pull-up Resistor Required (See Figure 4) For Best Linearity IOUT = 5mA, CLOAD = 500pF ±0.002 ✻ ✻ 6 (V/F) to Specified Linearity For a Full Scale Input Step <50% Overload ✻ ✻ ✻ nA nA mV µV/°C kΩ || pF ±0.005 ±0.030 f = 10kHz f = 10kHz CLOAD ≤ 50pF ✻ 0.01 0.4 1.0 ✻ VPU ✻ ✻ 25 100 F/V CONVERTER VOUT = 7.5 R1C1 fIN, Figure 9 INPUT TO COMPARATOR Impedance Logic “1” Logic “0” Pulse-width Range OUTPUT FROM OP AMP Voltage Current Impedance Capacitive Load POWER SUPPLY Rated Voltage Voltage Range Quiescent Current 50 || 10 +1.0 –VCC 0.25 IO = 6mA VO = 7VDC Closed-Loop Without Oscillation +VCC –0.05 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ 0 to +10 +10 0.1 100 ±13 TEMPERATURE RANGE Specification B and C Grades S Grade Operating B and C Grades S Grade Storage 150 || 10 ±15 kΩ || pF V V µs ✻ ✻ V mA Ω pF ✻ ✻ V V mA ✻ ±20 ±7.5 ✻ –25 –55 +85 +125 ✻ ✻ °C °C –40 –55 –65 +85 +125 +150 ✻ ✻ ✻ ✻ °C °C °C ±6.5 ✻ ✻ Specification the same as for VFC320BG/BM/SM. NOTES: (1) A 25% duty cycle at full scale (0.25mA input current) is recommended where possible to achieve best linearity. (2) Determined by RIN and full scale current range constraints. (3) Adjustable to zero. See Offset and Gain Adjustment section. (4) Linearity error at any operating frequency is defined as the deviation from a straight line drawn between the full scale frequency and 0.1% of full scale frequency. See Discussion of Specifications section. (5) When offset and gain errors are nulled, at an operating temperature, the linearity error determines the final accuracy. (6) For e1 = 0 typical linearity errors are: 0.01% at 10kHz, 0.2% at 100kHz, 0.1% at 1MHz. (7) Exclusive of external components’ drift. (8) FSR = Full Scale Range (corresponds to full scale and full scale input voltage.) (9) Positive drift is defined to be increasing frequency with increasing temperature. (10) One pulse of new frequency plus 50ns typical. ® VFC320 2 CONNECTION DIAGRAM Top View TO-100 VOUT –In 1 Top View 10 +VCC 9 2 Input Amp –VCC (Case) Switch 3 One-Shot Capacitor DIP Oneshot 8 4 7 5 NC Common Comparator Input 6 fOUT NC = no internal connection External connection permitted. PRODUCT PACKAGE VFC320BG VFC320BM VFC320SM VFC320CG VFC320CM 14-Pin Ceramic DIP TO-100 TO-100 14-Pin Ceramic DIP TO-100 163 007 007 163 007 1 NC 2 NC 3 –VCC 4 One-Shot Capacitor 5 NC 6 fOUT 7 14 +In 13 VOUT Input Amp 12 +VCC 11 Common Oneshot 10 Comparator Input 9 NC 8 NC ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDERING INFORMATION PACKAGE DRAWING NUMBER(1) –In Switch +In TEMPERATURE RANGE –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Supply Voltage ................................................................................... ±20V Output Sink Current at fOUT ............................................................... 50mA Output Current at VOUT ................................................................... +20mA Input Voltage, –Input .......................................................................... ±VCC Input Voltage, +Input .......................................................................... ±VCC Storage Temperature Range .......................................... –65°C to +150°C Lead Temperature (soldering, 10s) ................................................ +300°C NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 VFC320 DISCUSSION OF SPECIFICATIONS FREQUENCY STABILITY VS TEMPERATURE The full scale frequency drift of the VFC320 versus temperature is expressed as parts per million of full scale range per °C. As shown in Figure 3, the drift increases above 10kHz. To determine the total accuracy drift over temperature, the drift coefficients of external components (especially R1 and C1) must be added to the drift of the VFC320. LINEARITY Linearity is the maximum deviation of the actual transfer function from a straight line drawn between the end points (100% full scale input or frequency and 0.1% of full scale called zero.) Linearity is the most demanding measure of voltage-to-frequency converter performance, and is a function of the full scale frequency. Refer to Figure 1 to determine typical linearity error for your application. Once the full scale frequency is chosen, the linearity is a function of operating frequency as it varies between zero and full scale. Examples for 10kHz full scale are shown in Figure 2. Best linearity is achieved at lower gains (∆fOUT/∆VIN) with operation as close to the chosen full scale frequency as possible Typical Full Scale Temp Drift (ppm of FSR/°C) 1000 The high linearity of the VFC320 makes the device an excellent choice for use as the front end of A/D converters with 12- to 14-bit resolution, and for highly accurate transfer of analog data over long lines in noisy environments (2-wire digital transmission.) Typical Linearity Error (% of FSR) B and S Grades C Grade 10 1k 10k 100k 1M Full Scale Frequency (Hz) Figure 3. Full Scale Drift vs Full Scale Frequency. 0.10 RESPONSE Response of the VFC320 to changes in input signal level is specified for a full scale step, and is 50ns plus 1 pulse of the new frequency. For a 10V input signal step with the VFC320 operating at 100kHz full scale, the settling time to within ±0.01% of full scale is 10µs. 0.01 TA = +25°C DFS = 0.25 THEORY OF OPERATION 0.001 1k 10k 100k 1M The VFC320 monolithic voltage-to-frequency converter provides a digital pulse train output whose repetition rate is directly proportional to the analog input voltage. The circuit shown in Figure 4 is composed of an input amplifier, two comparators and a flip-flop (forming a on-shot), two switched current sinks, and an open collector output transistor stage. Essentially the input amplifier acts as an integrator that produces a two-part ramp. The first part is a function of the input voltage, and the second part is dependent on the input voltage and current sink. When a positive input voltage is applied at VIN, a current will flow through the input resistor, causing the voltage at VOUT to ramp down toward zero, according to dV/dt = VIN/R1C1. During this time the constant current sink is disabled by the switch. Note, this period is only dependent on VIN and the integrating components. Full Scale Frequency (Hz) Figure 1. Linearity Error vs Full Scale Frequency. Figure 0.003 Typical Linearity jErrorf (% of FSR) 100 fFULL SCALE = 10kHz 0.002 B Grade 0.001 C Grade 0 –0.001 –0.002 Typical, TA = +25°C –0.003 0 1k 2k 3k 4k 5k 6k 7k 8k 9k When the ramp reaches a voltage close to zero, comparator A sets the flip-flop. This closes the current sink switches as well as changing fOUT from logic 0 to logic 1. The ramp now begins to ramp up, and 1mA charges through C1 until VC1 = –7.5V. Note this ramp period is dependent on the 1mA current sink, connected to the negative input of the op amp, as well as the input voltage. At this –7.5V threshold point C1, comparator B resets the flip-flop, and the ramp voltage 10k Operating Frequency (Hz) Figure 2. Linearity Error vs Operating Frequency. Figure ® VFC320 4 C2 Input Resistor R1 IIN e1 +VPULL-UP (VPU) (5V to 15V Typically) +VCC Integrating Capacitor VOUT 10 7 fIN 9 2 Input Amp 1 IB IA e2 Pull-up Resitor A –7.5V Ref Constant Current Sinks (1mA) 6 Flipflop Comparators R2 Q1 fOUT B fOUT = Switch VIN 7.5 R1 C1 One-shot 3 4 C1 –VCC 8 Common One-shot Capacitor Pin numbers shown for “M” package (TO-100) VIN: For Postive Input Voltages use e1, short e2. For Negative Input Voltages use e2, short e1. For Differental Input Voltages use e1 and e2. FIGURE 4. Functional Block Diagram of the VFC320. begins to ramp down again before the input amplifier has a chance to saturate. In effect the comparators and flip-flop form a one-shot whose period is determined by the internal reference and a 1mA current sink plus the external capacitor, C1. After the one-shot resets, fOUT changes back to logic 0 and the cycle begins again. In the time t1 + t2 the integrator capacitor C2 charges and discharges but the net voltage change is zero. fOUT = So that IIN (t1 + t2) = IA t2 (3) fOUT = (1) VIN 1 and IIN = fOUT R1 VIN (4), (5) (6) IA R2 R2 In the time t1, IB charges the one-shot capacitor C1 until its voltage reaches –7.5V and trips comparator B. CIN 7.5 Thus t2 = (7) IB VIN IB X Using (7) in (6) yield fOUT = (8) 7.5 R1 C1 IA t 1 + t2 One-shot VC1 0V Since IA = IB the result is –7.5V fOUT = VIN (9) 7.5 R1 C1 ∆VOUT t1 Since the integrating capacitor, C2, affects both the rising and falling segments of the ramp voltage, its tolerance and temperature coefficient do not affect the output frequency. It should, however, have a leakage current that is small compared to IIN, since this parameter will add directly to the gain error of the VFC. C1, which controls the one-shot period, should be very precise since its tolerance and temperature coefficient add directly to the errors in the transfer function. t2 VFC Output fOUT Integrator Output VOUT (2) But since t1 + t2 = The transfer function for the VFC320 is derived for the circuit shown in Figure 4. Detailed waveforms are shown in Figure 5. 1 Thus ∆Q = 0 = IIN t1 + (IIN – IA) t2 FIGURE 5. Integrator and VFC Output Timing. ® 5 VFC320 The operation of the VFC320 as a highly linear frequencyto-voltage converter, follows the same theory of operation as the voltage-to-frequency converter. e1 and e2 are shorted and FIN is disconnected from VOUT. FIN is then driven with a signal which is sufficient to trigger comparator A. The oneshot period will then be determined by C1 as before, but the cycle repetition frequency will be dictated by the digital input at FIN. C2 Gain Adjustment IIN 1 R1 NC 2 +15V R4 NC 3 The nominal value is R1 is VINmax R1 = 0.25mA (10) If gain trimming is to be done, the nominal value is reduced by the tolerance of C1 and the desired trim range. R1 should have a very-low temperature coefficient since its drift adds directly to the errors in the transfer function. 14 13 5 12 +VCC(1) One-Shot Capacitor, C1 11 Switch –VCC(1) 4 This capacitor determines the duration of the one-shot pulse. From equation (9) the nominal value is VIN C1 NOM = 7.5 R1 fOUT (11) For the usual 25% duty at fMAX = VIN/R1 = 0.25mA there is approximately 15pF of residual capacitance so that the design value is 10 C1 One-shot capacitor NC 6 +VPU Oneshot 7 R2 fOUT NOTE: (1) Bypass with 0.01µF 9 NC 8 NC Pin numbers in squares refer to DIP package. FIGURE 6. Connection Diagram for V/F Conversion, Positive Input Voltages. C1(pF) = ® VFC320 Pin numbers in squares refer to DIP package. The input resistance (R1 and R3 in Figures 6 and 7) is calculated to set the desired input current at full scale input voltage. This is normally 0.25mA to provide a 25% duty cycle at full scale input and output. Values other than DFS = 0.25 may be used but linearity will be affected. R1 –15V Offset Adj. NC Input Resistors R1 and R3 Integrator Capacitor NC 3 8 In general, the design sequence consists of: (1) choosing fMAX, (2) choosing the duty cycle at full scale (DFS = 0.25 typically), (3) determining the input resistor, R1 (Figure 4), (4) calculating the one-shot capacitor, C1, (5) selecting the integrator capacitor C2, and (6) selecting the output pull-up resistor, R2. IIN R4 NC EXTERNAL COMPONENT SELECTION Gain Adjustment R5 9 FIGURE 7. Connection Diagram for V/F Conversion, Negative Input Voltages. The VCF320 can be connected to operate as a V/F converter that will accept either positive or negative input voltages, or an input current. Refer to Figures 6 and 7. Input Amp fOUT NOTE: (1) Bypass with 0.01µF VOLTAGE-TO-FREQUENCY CONVERSION NC 2 Oneshot 7 R2 INSTALLATION AND OPERATING INSTRUCTIONS +15V NC 6 +VPU Thus DFS = 0.25 corresponds to IIN max = 0.25mA. 1 10 C1 One-shot Capacitor Best linearity is achieved when DFS is 25%. By reducing equations (7) and (9) it can be shown that IIN max VIN max / R1 DFS = = 1mA 1mA R3 5 12 +VCC(1) 11 Switch –15V Offset Adj. The duty cycle (D) of the VFC is the ratio of the one-shot period (t2) or pulse width, PW, to the total VFC period (t1 + t2). For the VFC320, t2 is fixed and t1 + t2 varies as the input voltage. Thus the duty cycle, D, is a function of the input voltage. Of particular interest is the duty cycle at full scale frequency, DFS, which occurs at full scale input. DFS is a user determined parameter which affects linearity. t2 DFS = = PW X fFS t1 + t2 VIN 13 Input Amp –VCC(1) 4 DUTY CYCLE VIN 14 R3 R5 C2 Integrator Capacitor 6 33 x 10 6 fFS – 15 (12) OFFSET AND GAIN ADJUSTMENT PROCEDURES where fFS is the full scale output frequency in Hz. The temperature drift of C1 is critical since it will add directly to the errors of the transfer function. An NPO ceramic type is recommended. Every effort should be made to minimize stray capacitance associated with C1. It should be mounted as close to the VFC320 as possible. Figure 8 shows pulse width and full scale frequency for various values of C1 at DFS = 25%. To null errors to zero, follow this procedure: 1. Apply an input voltage that should produce an output frequency of 0.001 X full scale. 2. Adjust R5 for proper output. 3. Apply the full scale input voltage. 4. Adjust R3 for proper output. 5. Repeat stems 1 through 4. If nulling is unnecessary for the application, delete R4 and R5, and replace R3 with a short circuit. 106 10,000 1000 105 100 104 Pulse Width 103 10 Full Scale Frequency (Hz) Pulse Width (µs) Full Scale Frequency POWER SUPPLY CONSIDERATIONS The power supply rejection ratio of the VFC320 is 0.015% of FSR/% max. To maintain ±0.015% conversion, power supplies which are stable to within ±1% are recommended. These supplies should be bypassed as close as possible to the converter with 0.01µF capacitors. Internal circuitry causes some current to flow in the common connection (pin 11 on DIP package). Current flowing into the fOUT pin (logic sink current) will also contribute to this current. It is advisable to separate this common lead ground from the analog ground associated with the integrator input to avoid errors produced by these currents flowing through any ground return impedance. 102 1 101 102 103 104 105 Capacitance C1(pF) FIGURE 8. Output Pulse Width (DFS = 0.25) and Full Scale Frequency vs External One-shot Capacitance. Integrating Capacitor, C2 DESIGN EXAMPLE Since C2 does not occur in the V/F transfer function equation (9), its tolerance and temperature stability are not important; however, leakage current in C2 causes a gain error. A ceramic type is sufficient for most applications. The value of C2 determines the amplitude of VOUT. Input amplifier saturation, noise levels for the comparators and slew rate limiting of the integrator determine a range of acceptable values, 100/fFS; if fFS ≤ 100kHz C2 (µF) = Given a full scale input of +10V, select the values of R1, R2, R3, C1, and C2 for a 25% duty cycle at 100kHz maximum operation into one TTL load. See Figure 6. Selecting C1 (DFS = 0.25) C1 = [(33 X 106)/fMAX] – 15 (13) [(66 X 106)/fMAX] – 15 if DFS = 0.5 0.001; if 100kHz < fFS ≤ 500kHz = [(33 X 0.0005; if fFS > 500kHz 106)/100kHz] – 15 = 315pF Choose a 300pF NPO ceramic capacitor with 1% to 10% tolerance. Output Pull Up Resistor R2 The open collector output can sink up to 8mA and still be TTL-compatible. Select R2 according to this equation: Selecting R1 and R3 (DRS = 0.25) R2 min (Ω) VPULLUP/(8mA – ILOAD) R1 + R3 = VIN max/0.25mA A 10% carbon film resistor is suitable for use as R2. VIN max/0.5mA if DFS = 0.5 Trimming Components R3, R4, R5 = 10V/0.25mA R5 nulls the offset voltage of the input amplifier. It should have a series resistance between 10kΩ and 100kΩ and a temperature coefficient less than 100ppm/°C. R4 can be a 10% carbon film resistor with a value of 10MΩ. = 40kΩ Choose 32.4kΩ metal film resistor with 1% tolerance and R3 = 10kΩ cermet potentiometer. Selecting C2 R3 nulls the gain errors of the converter and compensates for initial tolerances of R1 and C1. Its total resistance should be at least 20% of R1, if R1 is selected 10% low. Its temperature coefficient should be no greater than five times that of R1 to maintain a low drift of the R3 - R1 series combination. C2 = 102/FMAX = 102/100kHz = 0.001µF Choose a 0.001µF capacitor with ±5% tolerance. ® 7 VFC320 Selecting R2 pin 10 should be biased closer to zero to insure that the input signal at pin 10 crosses the zero threshold. R2 = VPULLUP/(8mA – ILOAD) Errors are nulled using 0.001 X full scale frequency to null offset, and full scale frequency to null the gain error. The procedure is given on this page. Use equations from V/F calculations to find R1, R3, R4, C1 and C2. =5V/(8mA – 1.6mA), one TTL-load = 1.6mA =781Ω Choose a 750Ω 1/4-watt carbon compensation resistor with ±5% tolerance. TYPICAL APPLICATIONS FREQUENCY-TO-VOLTAGE CONVERSION Excellent linearity, wide dynamic range, and compatible TTL, DTL, and CMOS digital output make the VFC320 ideal for a variety of VFC applications. High accuracy allows the VFC320 to be used where absolute or exact readings must be made. It is also suitable for systems requiring high resolution up to 14 bits To operate the VFC320 as a frequency-to-voltage converter, connect the unit as shown in Figure 9. To interface with TTL-logic, the input should be coupled through a capacitor, and the input to pin 10 biased near +2.5V. The converter will detect the falling edges of the input pulse train as the voltage at pin 10 crosses zero. Choose C3 to make t = 0.1t (see Figure 9). For input signals with amplitudes less than 5V, Figures 10-14 show typical applications of the VFC320. R1 R3 C2 +15V Integrator Capacitor R4 R5 1 14 NC 2 13 T –15V Input Amp NC 3 One-shot Capacitor 11 Switch –VCC(1) 4 12 5 10 +VCC(1) 12kΩ 2.5V C1 NC 6 fOUT Oneshot 7 NOTE: (1) Bypass with 0.01µF 9 NC 8 NC Pin numbers in squares refer to DIP package. VOUT R6 +1V 0V C3 (t) fIN 0.001µF R7 2.2kΩ FFS = 100kHz FIGURE 9. Connection Diagram for F/V Conversion. + Sensor INA101 VIN fOUT Counter VFC320 – High Noise Immunity Instrumentation Amp Computer Clock FIGURE 10. Inexpensive A/D with Two-Wire Digital Transmission Over Twisted Pair. e1 Differential e2 Input VIN VFC320 fOUT BDC Counter Clock FIGURE 11. Inexpensive Digital Panel Meter. ® VFC320 8 Driver/Display Parallel Data fIN VFC320 VOUT F/V Digital Output VIN INA101 Transducer VFC320 V/F fOUT FOT Analog Output BCD Counter FOR 0.005% Linearity Precision DC levels down to 10mV full scale Driver Instrumentation Amp Clock Display FIGURE 12. Remote Transducer Readout via Fiber Optic Link (Analog and Digital Output). R1 11kΩ +15V Gain Adjust +10V to –10V Input 8 0.01µF R2 100kΩ D1 IN4154 30kΩ 7 +15V 1 20kΩ 20kΩ REF101 4 6 10V 12 1 2kΩ 10 11 7 14 5 3 8.66kΩ e1 Bipolar Input 13 Integrator Current C2 R4 3510B VFC320 5 R3 40.2kΩ VIN + fOUT VFC320 Q1 C1 3270pF 2N2222 0 to 10kHz Output 0.01µF – Sign Bit Out 4.7kΩ 4.7kΩ 3300pF –15V +VCC FIGURE 13. Bipolar input is accomplished by offsetting the input to the VFC with a reference voltage. Accurately matched resistors in the REF101 provide a stable half-scale output frequency at zero volts input. FIGURE 14. Absolute value circuit with the VFC320. Op amp, D1 and Q1 (its base-emitter junction functioning as a diode) provide full-wave rectification of bipolar input voltages. VFC output frequency is proportional to | e1 |. The sign bit output provides indication of the input polarity. ® 9 VFC320