BB VSP2260

VSP2260
VSP
226
0
www.ti.com
CCD SIGNAL PROCESSOR for
DIGITAL CAMERAS
FEATURES
DESCRIPTION
● CCD SIGNAL PROCESSING:
Correlated Double Sampling (CDS)
Programmable Black Level Clamping
● PROGRAMMABLE GAIN AMPLIFIER (PGA):
–6dB to +42dB Gain Ranging
● 10-BIT DIGITAL DATA OUTPUT:
Up to 20MHz Conversion Rate
No Missing Codes
● 79dB SIGNAL-TO-NOISE RATIO
● PORTABLE OPERATION:
Low Voltage: 2.7V to 3.6V
Low Power: 83mW (typ) at 3.0V
Stand-By Mode: 6mW
The VSP2260 is a complete mixed-signal processing
IC for digital cameras, providing signal conditioning
and Analog-to-Digital (A/D) conversion for the output
of a CCD array. The primary CCD channel provides
Correlated Double Sampling (CDS) to extract video
information from the pixels, –6dB to +42dB gain
range with digital control for varying illumination
conditions, and black level clamping for an accurate
black level reference. Input signal clamping and offset
correction of the input CDS are also performed. The
stable gain control is linear in dB. Additionally, the
black level is quickly recovered after gain change. The
VSP2260Y is available in an LQFP-48 package and
operates from a single +3V/+3.3V supply.
CLPDM
SHP SHD
RESET
SLOAD SCLK SDATA
ADCCK
DRVDD
VCC
Serial Interface
Input
Clamp
Correlated
Double
Sampling
(CDS)
CCDIN
CCD
Output
Signal
Timing
Control
Preblanking
PBLK
Programmable
Gain
Amplifier
(PGA)
Optical Black (OB)
Level Clamping
COB
Copyright © 2000, Texas Instruments Incorporated
CLPOB
AnalogtoDigital
Converter
–6dB
to
+42dB
Output
Latch
10-Bit
Digital
Output
B[9:0]
Reference Voltage Generator
BYPP2
BYP
SBMS010
BYPM
REFN
CM
REFP
DRVGND
GNDA
Printed in U.S.A. November, 2000
SPECIFICATIONS
At TA = +25°C, VCC = +3.0V, DRVDD = +3.0V, Conversion Rate (fADCCK) = 20MHz, unless otherwise noted.
VSP2260Y
PARAMETER
CONDITIONS
MIN
RESOLUTION
Input Current
DIGITAL OUTPUT
Logic Family
Logic Coding
Output Voltage
MHz
TTL
1.7
1.0
LOW to HIGH Threshold Voltage (VT+)
HIGH to LOW Threshold Voltage (VT–)
Logic HIGH (IIH) VIN = +3V
Logic LOW (IIL) VIN = 0V
UNITS
Bits
20
DIGITAL INPUT
Logic Family
Input Voltage
±20
±20
V
V
µA
µA
CMOS
Straight Binary
Logic HIGH (VOH) IOH = –2mA
Logic LOW (VOL) IOL = 2mA
ADCCK Clock Duty Cycle
Input Capacitance
Maximum Input Voltage
2.4
5.3
V
V
%
pF
V
3.3
mV
pF
V
0.4
50
5
–0.3
ANALOG INPUT (CCDIN)
Input Signal Level for Full-Scale Out
Input Capitance
Input Limit
TRANSFER CHARACTERISTICS
Differential Non-Linearity (DNL)
Integral Non-Linearity (INL)
No Missing Codes
Step Response Settling Time
Overload Recovery Time
Data Latency
Signal-to-Noise Ratio(1)
PGA Gain = 0dB
900
15
–0.3
±0.5
±1
Guaranteed
1
2
9 (Fixed)
79
55
PGA Gain = 0dB
PGA Gain = 0dB
Full-Scale Step Input
Step Input from 1.8V to 0V
Grounded Input Cap, PGA Gain = 0dB
Grounded Input Cap, Gain = +24dB
CCD Offset Correction Range
–180
CDS
Reference Sample Settling Time
Data Sample Settling Time
Within 1LSB, Driver Impedance = 50Ω
Within 1LSB, Driver Impedance = 50Ω
INPUT CLAMP
Clamp-On Resistance
Clamp Level
PROGRAMMABLE GAIN AMP (PGA)
Gain-Control Resolution
Maximum Gain
High Gain
Medium Gain
Low Gain
Minimum Gain
Gain Control Error
OPTICAL BLACK CLAMP LOOP
Control DAC Resolution
Optical Black Clamp Level
Min Output Current for Control DAC
Max Output Current for Control DAC
Loop Time Constant
Slew Rate
CCOB
Gain
Gain
Gain
Gain
Gain
Code
Code
Code
Code
Code
=
=
=
=
=
1111111111
1101001000
1000100000
0010000000
0000000000
LSB
LSB
200
Pixel
Pixels
Clock Cycles
dB
dB
mV
11
11
ns
ns
400
1.5
Ω
V
10
42
34
20
0
–6
±0.5
Bits
dB
dB
dB
dB
dB
dB
10
Programmable Range of Clamp Level
OBCLP Level at CODE = 1000
COB Pin
COB Pin
CCOB = 0.1µF
= 0.1µF, Output Current from Control DAC is Saturated
32
±0.15
±153
40.7
1530
Bits
LSB
LSB
µA
µA
µs
V/s
1.75
1.25
V
V
0
REFERENCE
Positive Reference Voltage
Negative Reference Voltage
TEMPERATURE RANGE
Operating Temperature
Thermal Resistance
MAX
10
CONVERSION RATE
POWER SUPPLY
Supply Voltage
Power Dissipation
TYP
VCC, DRVDD
2.7
Normal Operation Mode: No Load, DAC0 and DAC1 are Suspended
Stand-By Mode: fADCCK = Not Apply
60
3.0
83
6
–25
θJA
LQFP-48
100
3.6
V
mW
mW
+85
°C
°C/W
NOTE: (1) SNR = 20 log(full-scale voltage/rms noise).
2
VSP2260
SBMS010
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
Supply Voltage: VCC, DRVDD ........................................................... +4.0V
Supply-Voltage Differences: Among VCC ......................................... ±0.1V
Ground-Voltage Differences: Among GNDA .................................... ±0.1V
Digital Input Voltage ............................................................ –0.3 to +5.3V
Analog Input Voltage .................................................. –0.3 to VCC + 0.3V
Input Current (Any Pins Except Supplies) ..................................... ±10mA
Ambient Temperature Under Bias ..................................... –40 to +125°C
Storage Temperature ......................................................... –55 to +125°C
Junction Temperature .................................................................... +150°C
Lead Temperature (Soldering, 5s) ................................................ +260°C
Package Temperature (IR Reflow, Peak, 10s) ............................. +235°C
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may
degrade device reliability.
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER
VSP2260Y
LQFP-48
340
0 to +85°C
VSP2260Y
"
"
"
"
"
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
VSP2260Y
VSP2260Y/2K
250-Piece Tray
Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces
of “VSP2260Y/2K” will get a single 2000 piece Tape and Reel.
DEMO BOARD ORDERING INFORMATION
PRODUCT
ORDERING NUMBER
VSP2260Y
DEM-VSP2260Y
VSP2260
SBMS010
3
PIN CONFIGURATION
GNDA
VCC
VCC
BYPM
BYP
CCDIN
BYPP2
COB
VCC
GNDA
GNDA
LQFP
GNDA
Top View
36
35
34
33
32
31
30
29
28
27
26
25
CM 37
24 VCC
REFP 38
23 CLPDM
REFN 39
22 SHD
VCC 40
21 SHP
GNDA 41
20 CLPOB
GNDA 42
19 PBLK
VSP2260
NC 43
18 VCC
NC 44
17 GNDA
RESET 45
16 ADCCK
SLOAD 46
15 GNDA
SDATA 47
14 DRVGND
5
6
7
8
B0 (LSB)
B1
B2
B3
B4
B5
9
10
11
12
B9 (MSB)
4
B8
3
B7
2
B6
1
NC
13 DRVDD
NC
SCLK 48
PIN DESCRIPTIONS
PIN
NAME
TYPE(1) DESCRIPTION
1
NC
2
NC
3 B0 (LSB)
4
B1
5
B2
6
B3
7
B4
8
B5
9
B6
10
B7
11
B8
12 B9 (MSB)
13 DRVDD
14 DRVGND
15
GNDA
16 ADCCK
17
GNDA
18
VCC
19
PBLK
–
–
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
P
P
P
DI
P
P
DI
20
21
22
23
DI
DI
DI
DI
CLPOB
SHP
SHD
CLPDM
Should be Left OPEN
Should be Left OPEN
Bit 0 (LSB), A/D Converter Output
Bit 1, A/D Converter Output
Bit 2, A/D Converter Output
Bit 3, A/D Converter Output
Bit 4, A/D Converter Output
Bit 5, A/D Converter Output
Bit 6, A/D Converter Output
Bit 7, A/D Converter Output
Bit 8, A/D Converter Output
Bit 9 (MSB), A/D Converter Output
Power Supply, Exclusively for Digital Output
Digital Ground, Exclusively for Digital Output
Analog Ground
Clock for Digital Output Buffer
Analog Ground
Analog Power Supply
Preblanking:
HIGH = Normal Operation Mode
LOW = Preblanking Mode: Digital Output “All Zero”
Optical Black Clamp Pulse (Default = Active LOW) (5)
CDS Reference Level Sampling Pulse (Default = Active LOW)(5)
CDS Data Level Sampling Pulse (Default = Active LOW) (5)
Dummy Pixel Clamp Pulse (Default = Active LOW)(5)
PIN
NAME
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
VCC
GNDA
GNDA
VCC
COB
BYPP2
CCDIN
BYP
BYPM
VCC
VCC
GNDA
GNDA
CM
REFP
REFN
VCC
GNDA
GNDA
NC
NC
RESET
SLOAD
SDATA
SCLK
TYPE(1) DESCRIPTION
P
P
P
P
AO
AO
AI
AO
AO
P
P
P
P
AO
AO
AO
P
P
P
–
–
DI
DI
DI
DI
Analog Power Supply
Analog Ground
Analog Ground
Analog Power Supply
Optical Black Clamp Loop Reference(2)
Internal Reference P(3)
CCD Signal Input
Internal Reference C(4)
Internal Reference N(3)
Analog Power Supply
Analog Power Supply
Analog Ground
Analog Ground
A/D Converter Common-Mode Voltage(4)
A/D Converter Positive Reference(4)
A/D Converter Negative Reference(4)
Analog Power Supply
Analog Ground
Analog Ground
Should be Left OPEN
Should be Left OPEN
Asynchronous System Reset (Active LOW)
Serial Data Latch Signal (Triggered at the Rising Edge)
Serial Data Input
Clock for Serial Data Shift (Triggered at the Rising Edge)
NOTES: (1) Type designators: P = Power Supply and Ground; DI = Digital Input; DO = Digital Output; AI = Analog Input; AO = Analog Output. (2) Should be
connected to ground with a bypass capacitor. We recommend the value of 0.1µF to 0.22 µF, however, it depends on the application environment. Refer to the “Optical
Black Level Clamp Loop” section for more detail. (3) Should be connected to ground with a bypass capacitor. We recommend the value of 400pF to 9000pF, however,
it depends on the application environment. Refer to the “Voltage Reference” section for more detail. (4) Should be connected to ground with a bypass capacitor
(0.1µF). Refer to the “Voltage Reference” section for more detail. (5) Refer to “Serial Interface” section for more detail.
4
VSP2260
SBMS010
CDS TIMING SPECIFICATIONS
CCD
Output
Signal
N
N+1
N+2
tWP
N+3
tCKP
tPD
SHP(1)
tDP
tS
tWD
tCKP
SHD(1)
tS
tINHIBIT
tADC
tADC
tCKP
ADCCK
tHOLD
B[9:0]
tOD
N – 11
N – 10
N–9
N–8
TYP
MAX
N–7
SYMBOL
PARAMETER
MIN
tCKP
Clock Period
48
UNITS
ns
tADC
ADCCK HIGH/LOW Pulse Width
20
ns
ns
tWP
SHP Pulse Width
14
tWD
SHD Pulse Width
11
ns
tPD
SHP Trailing Edge to SHD Leading Edge(1)
8
ns
tDP
SHD Trailing Edge to SHP Leading Edge(1)
12
tS
Sampling Delay
tINHIBIT
Inhibited Clock Period
20
ns
tHOLD
Output Hold Time
7
ns
tOD
Output Delay
DL
Data Latency, Normal Operation Mode
ns
5
ns
38
9 (fixed)
ns
Clock Cycles
NOTE: (1) The description and timing diagrams in this data sheet are all based on the polarity of Active LOW
(default value). The user can select the active polarity (Active LOW or Active HIGH) through the serial interface.
Refer to the “Serial Interface” section for more detail.
VSP2260
SBMS010
5
SERIAL INTERFACE TIMING SPECIFICATIONS
tXS
SLOAD
tXH
tCKL
tCKP
tCKH
SCLK
tDH
tDS
SDATA
LSB
MSB
2 Bytes
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
tCKP
Clock Period
100
tCKH
Clock HIGH Pulse Width
40
ns
ns
tCKL
Clcok LOW Pulse Width
40
ns
tDS
Data Setup Time
30
ns
tDH
Data Hold TIme
30
ns
tXS
SLOAD to SCLK Setup Time
30
ns
tXH
SCLK to SLOAD Hold Time
30
ns
NOTES: (1) Data shift operation should occur at the rising edge of SCLK while SLOAD is LOW. Two bytes of input
data are loaded to the parallel latch in the VSP2260 at the rising edge of SLOAD. (2) When the input serial data
is longer than two bytes (16 bits), the last two bytes become effective and the former bits are lost.
6
VSP2260
SBMS010
THEORY OF OPERATION
signal range at the CCDIN pin is 1Vp-p, and the appropriate
common-mode voltage for the CDS is around 0.5V to 1.5V.
INTRODUCTION
The VSP2260 is a complete mixed-signal IC that contains
all of the key features associated with the processing of the
CCD imager output signal in a video camera, a digital still
camera, security camera, or similar applications (see the
simplified block diagram on page 1 for details). The VSP2260
includes a Correlated Double Sampler (CDS), Programmable Gain Amplifier (PGA), Analog-to-Digital Converter
(ADC), input clamp, Optical Black (OB) level clamp loop,
serial interface, timing control, and reference voltage generator. We recommend an off-chip emitter follower buffer
between the CCD output and the VSP2260 CCDIN input.
The PGA gain control, clock polarity setting, and operation
mode can be selected through the serial interface. All parameters are reset to the default value when the RESET pin goes
LOW asynchronously from the clocks.
CORRELATED DOUBLE SAMPLER (CDS)
The output signal of a CCD imager is sampled twice during
one pixel period: once at the reference interval and the other
at the data interval. Subtracting these two samples from each
other extracts the video information of the pixel as well as
removes any noise that is common, or correlated, to both the
intervals. Thus, the CDS is very important in reducing the
reset noise and low-frequency noises that are present on the
CCD output signal. Figure 1 shows the simplified block
diagram of the CDS and input clamp.
VSP2260
SHP
C1
10pF
CIN
CCD
Output
CCDIN
OPA
CLPDM
SHD
C2
10pF
SHP
CM (1.5V)
FIGURE 1. Simplified Block Diagram of CDS and Input
Clamp.
The CDS is driven through an off-chip coupling capacitor
(CIN). AC coupling is strongly recommended because the
DC level of the CCD output signal is usually several volts
too high for the CDS to work properly.
A 0.1µF capacitor is recommended for CIN, depending on
the application environment. Additionally, we recommend
an off-chip emitter follower buffer that can drive more than
10pF, because the 10pF capacitor and a few pF of stray
capacitance can be seen at the input pin. The analog input
VSP2260
SBMS010
The reference level is sampled during SHP active period,
and the voltage level is held on sampling capacitor C1 at the
trailing edge of SHP. The data level is sampled during SHD
active period, and the voltage level is held on the sampling
capacitor C2 at the trailing edge of SHD. The switchedcapacitor amplifier then performs the subtraction of these
two levels.
The user can select the active polarity of SHP/SHD (Active
HIGH or Active LOW) through the serial interface (refer to
the “Serial Interface” section for more detail). The default
value of SHP/SHD is “Active LOW”. However, immediately after power ON, this value is Unknown. For this
reason, the appropriate value must be set by using the serial
interface, or reset to the default value by strobing the RESET
pin. The descriptions and the timing diagrams in this data
sheet are all based on the polarity of Active LOW (default
value).
INPUT CLAMP OR DUMMY PIXEL CLAMP
The buffered CCD output is capacitively coupled to the
VSP2260. The purpose of the input clamp is to restore the
DC component of the input signal that was lost with the AC
coupling and establish the desired DC bias point for the
CDS. A simplified block diagram of the input clamp is
shown in Figure 1. The input level is clamped to the internal
reference voltage, CM (1.5V), during the dummy pixel
interval. More specifically, when both CLPDM and SHP are
active, the dummy clamp function becomes active. If the
dummy pixels and/or the CLPDM pulse are not available in
your system, the CLPOB pulse can be used in place of
CLPDM, as long as the clamping takes place during black
pixels. In this case, both the CPLDM pin (active at same
timing as CLPOB) and SHP become active during the
optical black pixel interval, and then the dummy clamp
function becomes active.
The active polarity of CLPDM and SHP (Active HIGH or
Active LOW) can be selected through the serial interface
(refer to the “Serial Interface” section for more detail).
The default value of CLPDM and SHP is “Active LOW”.
However, immediately after power ON, this value is Unknown. For this reason, the appropriate value must be set by
using the serial interface, or reset to the default value by
strobing the RESET pin. The descriptions and the timing
diagrams in this data sheet are all based on the polarity of
Active LOW (default value).
HIGH PERFORMANCE ANALOG-TO-DIGITAL
CONVERTER (ADC)
The ADC utilizes a fully differential and pipelined architecture. This ADC is well suited for low-voltage operations,
low power consumption requirements, and high-speed applications. It guarantees 10-bit resolution with no missing
codes. The VSP2260 includes a reference voltage generator
for the ADC. REFP (Positive Reference, pin 38), REFN
7
(Negative Reference, pin 39), and CM (Common-Mode
Voltage, pin 37) should be bypassed to ground with a 0.1µF
ceramic capacitor and should not be used elsewhere in the
system, as they affect the stability of these reference levels,
which causes ADC performance degradation. Note that
these are analog output pins and, therefore, do not apply
external voltage.
PROGRAMMABLE GAIN AMPLIFIER (PGA)
Figure 2 shows the characteristics of the PGA gain. The PGA
provides a gain range of –6dB to +42dB, which is linear in dB.
The gain is controlled by a digital code with
10-bit resolution, and can be set through the serial interface
(refer to the “Serial Interface” section for more detail).
The default value of the gain control code is 128 (PGA
Gain = 0dB). However, immediately after power ON, this
value is Unknown. For this reason, the appropriate value must
be set by using the serial interface, or reset to the default value
by strobing the RESET pin.
equivalent to 1LSB of the DAC output current. When C is
0.1µF, time constant T is 40.7µs.
Additionally, the slew rate SR is given the following equation:
SR = IMAX/C
Where C is the capacitor value connected to COB, IMAX is
the maximum current (153µA) of the control DAC in the OB
level clamp loop, and 153µA is equivalent to 1023LSB of
the DAC output current.
Generally, OB level clampling at high speed causes “Clamp
Noise” (or “White Streak Noise”), however, the noise will
decrease by increasing C. On the other hand, an increased C
requires a much longer time to restore from Stand-By mode,
or right after power ON. Therefore, we consider 0.1µF to
0.22µF a reasonable value for C. However, it depends on the
application environment; we recommend making careful
adjustments using trial-and-error.
The “OB clamp level” (the pedestal level) is programmable
through the serial interface (refer to the “Serial Interface”
section for more detail). Table I shows the relationship
between input code and the OB clamp level.
50
40
Gain (dB)
30
20
10
0
1k
1023
900
800
700
600
500
400
300
200
100
0
–10
Input Code for Gain Control (0 to 1023)
FIGURE 2. The Characteristics of PGA Gain.
OPTICAL BLACK (OB) LEVEL CLAMP LOOP
To extract the video information correctly, the CCD signal
must be referenced to a well-established OB level. The
VSP2260 has an auto-calibration loop to establish the OB
level using the optical black pixels output from the CCD
imager. The input signal level of the OB pixels is identified
as the real “OB level”, and the loop should be closed while
CLPOB is active.
During the effective pixel interval, the reference level of the
CCD output signal is clamped to the OB level by the OB
level clamp loop. To determine the loop time constant, an
off-chip capacitor is required, and should be connected to
COB (pin 28). Time constant T is given in the following
equation:
T = C/(16384 • IMIN)
Where C is the capacitor value connected to COB, IMIN is the
minimum current (0.15µA) of the control Digital-to-Analog
Converter (DAC) in the OB level clamp loop, and 0.15µA is
8
INPUT CODE
OB CLAMP LEVEL, LSBs OF 10 BITS
0000
0001
0010
0011
0100
0101
0110
0111
1000 (Default)
1001
1010
1011
1100
1101
1110
0LSB
4LSB
8LSB
12LSB
16LSB
20LSB
24LSB
28LSB
32LSB
36LSB
40LSB
44LSB
48LSB
52LSB
56LSB
1111
60LSB
TABLE I. Programmable OB Clamp Level.
The active polarity of CLPOB (Active HIGH or Active
LOW) can be selected through the serial interface (refer to
the “Serial Interface” section for more detail). The default
value of CLPOB is “Active LOW”. However, immediately
after power ON, this value is Unknown. For this reason, the
appropriate value must be set by using the serial interface, or
reset to the default value by strobing the RESET pin. The
descriptions and the timing diagrams in this data sheet are all
based on the polarity of Active LOW (default value).
PREBLANKING AND DATA LATENCY
The VSP2260 has an input blanking, or preblanking, function. When PBLK goes LOW, all digital outputs will go to
ZERO at the 11th rising edge of ADCCK. In this mode, the
digital output data comes out on the rising edge of ADCCK
with a delay of 11 clock cycles (data latency is 11). This is
different from the preblanking mode in which the digital
VSP2260
SBMS010
output data comes out on the rising edge of ADCCK with a
delay of nine clock cycles (data latency is nine).
If the input voltage is higher than the supply rail by 0.3V, or
lower than the ground rail by 0.3V, the protection diodes
will be turned on to prevent the input voltage from going any
further. Such a high swing signal may cause device damage
to the VSP2260 and should be avoided.
STAND-BY MODE
For the purpose of saving power, the VSP2260 can be set to
Stand-by mode (or Power-Down mode) through the serial
interface when the VSP2260 is not in use. Refer to the
“Serial Interface” section for more detail. In this mode, all
the function blocks are disabled and the digital outputs will
go to all ZEROs, causing the current consumption to drop to
1mA. Since all the bypass capacitors will discharge during
this mode, a substantial time (usually of the order of 200ms
to 300ms) is required to power up from Stand-by mode.
VOLTAGE REFERENCE
All the reference voltages and bias currents needed in the
VSP2260 are generated by its internal bandgap circuitry.
The CDS and the ADC use mainly three reference voltages:
REFP (Positive Reference, pin 38), REFN (Negative Reference, pin 39) and CM (Common-Mode Voltage, pin 37).
REFP, REFN and CM should be heavily decoupled with
appropriate capacitors (e.g., 0.1µF ceramic capacitor). Do
not use these voltages elsewhere in the system as they affect
the stability of the reference level, and cause ADC performance degradation. Note that these are analog output pins
and do not apply external voltage.
BYPP2 (pin 29), BYP (pin 31), and BYPM (pin 32) are also
reference voltages to be used in the analog circuit. BYP
should be connected to ground with a 0.1µF ceramic capaci-
VSP2260
SBMS010
tor. Since the capacitor value for BYPP2 and BYPM affects
the step response, we consider 400pF to 9000pF to be a
reasonable value. However, as it depends on the application
environment, we recommend making careful adjustments
using trial-and-error.
BYPP2, BYP and BYPM should all be heavily decoupled
with appropriate capacitors, and not used elsewhere in the
system. They affect the stability of the reference levels, and
cause performance degradation. Note that these are analog
output pins and do not apply external voltage.
SERIAL INTERFACE
The serial interface has a 2-byte shift register and various
parallel registers to control all the digitally programmable
features of the VSP2260. Writing to these registers is controlled by four signals (SLOAD, SCLK, SDATA, and RESET). To enable the shift register, SLOAD must be pulled
LOW. SDATA is the serial data input and the SCLK is the
shift clock. The data at SDATA is taken into the shift
register at the rising edge of SCLK; the data length should
be two bytes. After the 2-byte shift operation, the data in the
shift register is transferred to the parallel latch at the rising
edge of SLOAD. In addition to the parallel latch, there are
several registers dedicated to the specific features of the
device and are synchronized with ADCCK. It takes five or
six clock cycles for the data in the parallel latch to be written
to those registers. Therefore, to complete the data updates, it
requires five or six clock cycles after parallel latching by the
rising edge of SLOAD.
See Table II for the serial interface data format. TEST is the
flag for the test mode (Texas Instruments proprietary only),
A0 to A2 is the address for the various registers, and D0 to
D11 is the data (or operand) field.
9
MSB
REGISTERS
Configuration
PGA Gain
OB Clamp Level
Clock Polarity
Reserved
Reserved
Reserved
Reserved
Reserved
LSB
TEST
A2
A1
A0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
x
0
0
1
1
0
0
1
1
x
0
1
0
1
0
1
0
1
x
0
0
0
0
x
x
x
x
x
0
0
0
0
x
x
x
x
x
0
G9
0
0
x
x
x
x
x
0
G8
0
0
x
x
x
x
x
0
G7
0
0
x
x
x
x
x
0
G6
0
0
x
x
x
x
x
0
G5
0
0
x
x
x
x
x
0
G4
0
0
x
x
x
x
x
0
G3
O3
0
x
x
x
x
x
0
G2
O2
P2
x
x
x
x
x
0
G1
O1
P1
x
x
x
x
x
C0
G0
O0
P0
x
x
x
x
x
x = Don’t Care.
TABLE II. Serial Interface Data Format.
REGISTER DEFINITIONS
C[0]
Operation Mode, Normal/Stand-By
Serial Interface and Registers are always active, independently from the operation mode.
C0 = Operation Mode for the entire chip except the serial interface and registers.
(C0 = 0 “Active”; C0 = 1 “Stand-by”)
G[9:0]
The Characteristics of PGA Gain (refer to Figure 2)
O[3:0]
Programmable OB Clamp Level (refer to Table I)
P[2:0]
Clock Polarity
P0 = Polarity for CLPDM
(P0 = 0 “Active LOW”; P0 = 1 “Active HIGH”)
P1 = for CLPOB
(P0 = 0 “Active LOW”; P0 = 1 “Active HIGH”)
P2 = for SHP/SHD
(P0 = 0 “Active LOW”; P0 = 1 “Active HIGH”)
Immediately after power ON, these values are Unknown. The appropriate value must be set by using the serial interface, or reset
to the default value by strobing the RESET pin.
Default values are:
C[2:0] = 0
Normal Operation Mode
G[9:0] = 0010000000
PGA Gain = 0dB
O[3:0] = 1000
OB Clamp Level = 32LSB
P[2:0] = 000
CLPDM, CLPOB, SHP/SHD are all “Active LOW” (1)
NOTE: (1) The descriptions and the timing diagrams in this data sheet are all based on the polarity of Active LOW (default value).
10
VSP2260
SBMS010
TIMINGS
The CDS and the ADC are operated by SHP/SHD and their
derivative timing clocks generated by the on-chip timing
generator. The digital output data is synchronized with
ADCCK. See the VSP2260 “CDS Timing Specifications” for
the timing relationship among the CCD signal, SHP/SHD,
ADCCK and the output data. CLPOB is used to activate the
black level clamp loop during the OB pixel interval, and
CLPDM is used to activate the input clamping during the
dummy pixel interval. If the CLPDM pulse is not available in
your system, the CLPOB pulse can be used in place of
CLPDM as long as the clamping takes place during black
pixels (refer to the “Input Clamp and Dummy Pixel Clamp”
section for more detail). The clock polarities of SHP/SHD,
CLPOB and CLPDM can be independently set through the
serial interface (refer to the “Serial Interface” section for more
detail). The descriptions and the timing diagrams in this data
sheet are all based on the polarity of Active LOW (default
value). In order to keep a stable and accurate OB clamp level,
we recommend CLPOB should not be activated during PBLK
active period. Refer to the “Preblanking and Data Latency”
section for more detail. In Stand-By mode, ADCCK, SHP,
SHD, CLPOB and CLPDM are internally masked and pulled
HIGH.
POWER-SUPPLY, GROUNDING, AND DEVICE
DECOUPLING RECOMMENDATIONS
The VSP2260 incorporates analog circuitry and a very
high-precision, high-speed ADC that are vulnerable to any
extraneous noise from the rails or elsewhere. For this reason,
it should be treated as an analog component and all supply
pins except for DRVDD should be powered by the only
analog supply of the system. This will ensure the most
consistent results, since digital power lines often carry high
levels of wideband noise that would otherwise be coupled
into the device and degrade the achievable performance.
Proper grounding, short lead length, and the use of ground
VSP2260
SBMS010
planes are also very important for high-frequency designs.
Multi-layer PC boards are recommended for the best performance, since they offer distinct advantages like minimizing
ground impedance, separation of signal layers by ground
layers, etc. It is highly recommended that analog and digital
ground pins of the VSP2260 be joined together at the IC and
be connected only to the analog ground of the system. The
driver stage of the digital outputs (B[9:0]) is supplied through
a dedicated supply pin (DRVDD) and it should be separated
from the other supply pins completely, or at least with a
ferrite bead.
It is also recommended to keep the capacitive loading on the
output data lines as low as possible (typically less than
15pF). Larger capacitive loads demand higher charging
current surges that can feed back into the analog portion of
the VSP2260 and affect the performance. If possible, external buffers or latches should be used, providing the added
benefit of isolating the VSP2260 from any digital noise
activities on the data lines. In addition, resistors in series
with each data line may help minimize the surge current.
Values in the range of 100Ω to 200Ω will limit the instantaneous current the output stage has to provide for recharging the parasitic capacitances as the output levels change
from LOW to HIGH, or HIGH to LOW. Due to high
operation speed, the converter also generates high-frequency
current transients and noises that are fed back into the supply
and reference lines. This requires the supply and reference
pins to be sufficiently bypassed. In most cases, 0.1µF ceramic chip capacitors are adequate to decouple the reference
pins. Supply pins should be decoupled to the ground plane
with a parallel combination of tantalum (1µF to 22µF) and
ceramic (0.1µF) capacitors. The effectiveness of the decoupling largely depends on the proximity to the individual pin.
DRVDD should be decoupled to the proximity of DRVGND.
Special attention must be paid to the bypassing of COB,
BYPP2 and BYPM, since these capacitor values determine
important analog performances of the device.
11
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jan-2004
PACKAGING INFORMATION
ORDERABLE DEVICE
STATUS(1)
PACKAGE TYPE
PACKAGE DRAWING
PINS
PACKAGE QTY
VSP2260Y
ACTIVE
LQFP
PT
48
250
VSP2260Y/2K
ACTIVE
LQFP
PT
48
2000
VSP2260Y/2KC
ACTIVE
LQFP
PT
48
2000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
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