VSP2212 ® VSP VSP 221 221 2 2 For most current data sheet and other product information, visit www.burr-brown.com CCD SIGNAL PROCESSOR For Digital Cameras FEATURES DESCRIPTION ● CCD SIGNAL PROCESSING: Correlated Double Sampling (CDS) Programmable Black Level Clamping The VSP2212 is a complete mixed-signal processing IC for digital cameras, providing signal conditioning and analog-to-digital conversion for the output of a CCD array. The primary CCD channel provides Correlated Double Sampling (CDS) to extract video information from the pixels, –6dB to +42dB gain ranging with digital control for varying illumination conditions, and black level clamping for an accurate black reference. Input signal clamping and offset correction of the input CDS is also performed. The stable gain control is linear in dB. Additionally, the black level is quickly recovered after gain change. The two on-chip general-purpose 8-bit digital-to-analog converters allow you to obtain analog various control voltage, such as VSUB control of CCD imager. The VSP2212 is the high-performance version of the VSP2000/2100 families. The VSP2212Y is available in an LQFP-48 package and the VSP2212M is avail able in a VQFN-48 package. Both products operate from a single +3V/ +3.3V supply. ● PROGRAMMABLE GAIN AMPLIFIER (PGA): –6 to +42dB Gain Ranging ● 12-BIT DIGITAL DATA OUTPUT: Up to 20MHz Conversion Rate No Missing Codes ● 79dB SIGNAL-TO-NOISE RATIO ● ON-CHIP GENERAL-PURPOSE 8-BIT DIGITAL-TO-ANALOG CONVERTERS ● PORTABLE OPERATION: Low Voltage: 2.7V to 3.6V Low Power: 99mW (typ) at 3.0V Stand-By Mode: 6mW CLPDM SHP SHD RESET SLOAD SCLK SDATA ADCCK DRVDD VCC Timing Control Input Clamp CCD Output Signal DACOUT1 8-Bit D/A Converter (DAC0) Serial Interface 8-Bit D/A Converter (DAC1) Correlated Double Sampling (CDS) CCDIN DACOUT0 Preblanking PBLK Programmable Gain Amplifier (PGA) Optical Black (OB) Level Clamping COB CLPOB Analog to Digital Converter –6dB to +42dB Output Latch 12-Bit Digital Output B[11:0] Reference Voltage Generator BYPP2 BYP BYPM REFN CM REFP DRVGND GNDA International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 2000 Burr-Brown Corporation 1 PDS-1598A Printed in U.S.A. May, 2000 VSP2212 SPECIFICATIONS At TA = full specified temperature range, VCC = +3.0V, DRVDD = +3.0V, conversion rate (fADDCK) = 20MHz, unless otherwise specified. VSP2212Y PARAMETER CONDITIONS MIN RESOLUTION TYP MAX 12 MAXIMUM CONVERSION RATE DIGITAL INPUT Logic Family Input Voltage Input Current ADCCK Clock Duty Cycle Input Capacitance Maximum Input Voltage TTL 1.7 1.0 Logic HIGH (VOH), IOH = –2mA Logic LOW (VOL), IOL = 2mA 2.4 PGA Gain = 0dB 900 V V 3.3 mV pF V 15 –0.3 ±0.5 ±1 Guaranteed 1 2 9 (fixed) 79 55 PGA Gain = 0dB PGA Gain = 0dB Full-Scale Step Input Step Input from 1.8V to 0V Grounded Input Cap, PGA Gain = 0dB Grounded Input Cap, Gain = +24dB CCD Offset Correction Range –180 Within 1 LSB, Driver Impedance = 50Ω Within 1 LSB, Driver Impedance = 50Ω INPUT CLAMP Clamp-On Resistance Clamp Level PROGRAMMABLE GAIN AMPLIFIER (PGA) Gain Control Resolution Maximum Gain High Gain Medium Gain Low Gain Minimum Gain Gain Control Error Gain Gain Gain Gain Gain Code Code Code Code Code = = = = = 1111111111 1101001000 1000100000 0010000000 0000000000 LSB LSB 200 Pixels Pixels Clock Cycles dB dB mV 11 11 ns ns 400 1.5 Ω V 10 42 34 20 0 –6 ±0.5 Bits dB dB dB dB dB dB 10 Programmable Range of Clamp Level OBCLP Level at CODE = 1000 COB Pin COB Pin CCOB = 0.1µF C COB = 0.1µF, Output Current from Control DAC is Saturated GENERAL-PURPOSE 8-BIT DAC (DAC0, DAC1) Minimum Output Voltage Maximum Output Voltage Differential Non-Linearity (DNL) Integral Non-Linearity (INL) Offset Error Gain Error Monotonicity Input Code = 00000000 Input Code = 11111111 At Input Code = 16 to 224 At Input Code = 16 to 192 NOTE: (1) SNR = 20 log (full-scale voltage/rms noise). ® VSP2212 0.4 CMOS Straight Binary TRANSFER CHARACTERISTICS Differential Non-Linearity (DNL) Integral Non-Linearity (INL) No Missing Codes Step Response Settling Time Overload Recovery Time Data Latency Signal-to-Noise Ratio(1) Minimum Output Current for Control DAC Maximum Output Current for Control DAC Loop Time Constant Slew Rate 5.3 V V µA µA % pF V ±20 ±20 –0.3 ANALOG INPUT (CCDIN) Input Signal Level for Full-Scale Out Input Capacitance Input Limit OPTICAL BLACK CLAMP LOOP Control DAC Resolution Optical Black Clamp Level MHz 50 5 DIGITAL OUTPUT Logic Family Logic Coding Output Voltage CDS Reference Sample Settling Time Data Sample Settling Time Bits 20 LOW to HIGH Threshold Voltage (VT+) HIGH to LOW Threshold Voltage (VT–) Logic HIGH (IIH), VIN = +3V Logic LOW (IIL), VIN = 0V UNITS 2 2 242 130 ±0.15 ±153 40.7 1530 0.1 2.9 ±0.25 ±1 ±200 ±5 Guaranteed Bits LSB LSB µA µA µs V/s V V LSB LSB mV % SPECIFICATIONS (Cont.) At TA = full specified temperature range, VCC = +3.0V, DRVDD = +3.0V, conversion rate (fADDCK) = 20MHz, unless otherwise specified. VSP2212Y PARAMETER CONDITIONS MIN TYP REFERENCE Positive Reference Voltage Negative Reference Voltage MAX 1.75 1.25 POWER SUPPLY Supply Voltage Power Dissipation Normal Operation Mode Stand-By Mode VCC , DRVDD 2.7 3.0 No Load, DAC0 and DAC1 are Suspended fADDCK = NOT Apply TEMPERATURE RANGE Operating Temperature Storage Temperature Thermal Resistance, θJA V V 3.6 99 6 –25 –55 100 ABSOLUTE MAXIMUM RATINGS(1) V mW mW +85 +125 LQFP-48 UNITS °C °C °C/W ELECTROSTATIC DISCHARGE SENSITIVITY Supply Voltage(2) .............................................................................................................. +4.0V Supply Voltage Differences(3) .................................................................................. ±0.1V Ground Voltage Differences(4) ................................................................................. ±0.1V Digital Input Voltage ............................................................ –0.3V to 5.3V Analog Input Voltage ................................................ –0.3V to VCC + 0.3V Input Current (any pins except supplies) ....................................... ±10mA Operating Temperature .................................................. –25°C to +85°C Storage Temperature ..................................................... –55°C to +125°C Junction Temperature .................................................................... +150°C Lead Temperature (soldering, 5s) ................................................. +260°C Package Temperature (IR reflow, peak, 10s) ............................... +235°C This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTES: (1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. (2) VCC, DRVDD. (3) Among VCC. (4) Among GNDA and DRVGND. PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER VSP2212Y LQFP-48 340 –25°C to +85°C VSP2212Y " " " " VQFN-48 369 –25°C to +85°C VSP2212M " " " " " VSP2212M " SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER(1) TRANSPORT MEDIA VSP2212Y VSP2212Y/2K VSP2212M VSP2212Y/2M 250-Piece Tray Tape and Reel 250-Piece Tray Tape and Reel NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of “VSP2212Y/2K” will get a single 2000-piece Tape and Reel. DEMO BOARD ORDERING INFORMATION PRODUCT ORDERING NUMBER VSP2212Y DEM-VSP2212Y The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 VSP2212 PIN CONFIGURATION RESET DACOUT1 DACOUT0 GNDA GNDA VCC REFN REFP CM SCLK SDATA SLOAD RESET DACOUT1 DACOUT0 GNDA GNDA VCC REFN REFP CM VQFN SLOAD Top View SDATA LQFP SCLK Top View 48 47 46 45 44 43 42 41 40 39 38 37 48 47 46 45 44 43 42 41 40 39 38 37 B0 (LSB) 1 36 GNDA B0 (LSB) 1 36 GNDA B1 2 35 GNDA B1 2 35 GNDA 34 VCC B2 3 34 VCC 33 VCC B3 4 33 VCC 32 BYPM B4 5 32 BYPM 31 BYP B5 6 30 CCDIN B6 7 29 BYPP2 B7 8 29 BYPP2 28 COB B8 9 28 COB 27 VCC B9 10 B2 B3 3 4 B4 5 B5 6 B6 7 B7 B8 VSP2212 8 9 B9 10 31 BYP VSP2212M 30 CCDIN 27 VCC CLPDM VCC 15 16 17 18 19 20 21 22 23 24 VCC SHP SHD 14 CLPDM CLPOB 13 SHD 24 SHP 23 CLPOB 22 PBLK 21 VCC 20 GNDA 19 GNDA 18 ADCCK 17 DRVDD 16 DRVGND 15 PBLK 14 VCC 13 GNDA 25 GNDA ADCCK 26 GNDA B11 (MSB) 12 GNDA B10 11 25 GNDA DRVDD 26 GNDA DRVGND B10 11 B11 (MSB) 12 PIN DESCRIPTIONS PIN NAME TYPE(1) DESCRIPTION 1 B0 (LSB) 2 B1 3 B2 4 B3 5 B4 6 B5 7 B6 8 B7 9 B8 10 B9 11 B10 12 B11 (MSB) 13 DRVDD 14 DRVGND 15 GNDA 16 ADCCK 17 GNDA 18 VCC 19 PBLK DO DO DO DO DO DO DO DO DO DO DO DO P P P DI P P DI 20 21 22 23 24 DI DI DI DI P CLPOB SHP SHD CLPDM VCC PIN Bit 0, A/D Converter Output, Least Significant Bit Bit 1, A/D Converter Output Bit 2, A/D Converter Output Bit 3, A/D Converter Output Bit 4, A/D Converter Output Bit 5, A/D Converter Output Bit 6, A/D Converter Output Bit 7, A/D Converter Output Bit 8, A/D Converter Output Bit 9, A/D Converter Output Bit 10, A/D Converter Output Bit 11, A/D Converter Output, Most Significant Bit Power Supply, Exclusively for Digital Output Digital Ground, Exclusively for Digital Output Analog Ground Clock for Digital Output Buffer Analog Ground Analog Power Supply Preblanking: HIGH = Normal Operation Mode LOW = Preblanking Mode: Digital Output “All Zero” Optical Black Clamp Pulse (Default = Active LOW (2)) CDS Reference Level Sampling Pulse (Default = Active LOW(2)) CDS Data Level Sampling Pulse (Default = Active LOW (2)) Dummy Pixel Clamp Pulse (Default = Active LOW (2)) Analog Power Supply NAME TYPE(1) DESCRIPTION 25 GNDA 26 GNDA 27 VCC 28 COB 29 BYPP2 30 CCDIN 31 BYP 32 BYPM 33 VCC 34 VCC 35 GNDA 36 GNDA 37 CM 38 REFP 39 REFN 40 VCC 41 GNDA 42 GNDA 43 DACOUT0 P P P AO AO AI AO AO P P P P AO AO AO P P P AO 44 DACOUT1 AO 45 46 47 48 DI DI DI DI RESET SLOAD SDATA SCLK Analog Ground Analog Ground Analog Power Supply Optical Black Clamp Loop Reference (Bypass to Ground (3)) Internal Reference P (Bypass to Ground (4)) CCD Signal Input Internal Reference C (Bypass to Ground (5)) Internal Reference N (Bypass to Ground (4)) Analog Power Supply Analog Power Supply Analog Ground Analog Ground A/D Converter Common-Mode Voltage (Bypass to Ground(5)) A/D Converter Positive Reference (Bypass to Ground (5)) A/D Converter Negative Reference (Bypass to Ground (5)) Analog Power Supply Analog Ground Analog Ground General-Purpose 8-Bit D/A Converter (DAC0) Output Voltage General-Purpose 8-Bit D/A Converter (DAC1) Output Voltage Asynchronous System Reset (Active LOW) Serial Data Latch Signal (Triggered at the Rising Edge) Serial Data Input Clock for Serial Data Shift (Triggered at the Rising Edge) NOTES: (1) Type designators: P = Power Supply and Ground; DI = Digital Input; DO = Digital Output; AI = Analog Input; AO = Analog Output. (2) Refer to the “Serial Interface” section for more detail. (3) Should be connected to ground with a bypass capacitor. We recommend the value of 0.1µF to 0.22 µF, however, it depends on the application environment. Refer to the “Optical Black Level Clamp Loop” section for more detail. (4) Should be connected to ground with a bypass capacitor. We recommend the value of 1000pF, however, it depends on the application environment. Refer to the “Voltage Reference” section for more detail. (5) Should be connected to ground with a bypass capacitor (0.1µF). Refer to the “Voltage Reference” section for more detail. ® VSP2212 4 CDS TIMING SPECIFICATIONS CCD Output Signal N N+1 N+2 tWP N+3 tCKP tPD SHP(1) tDP tS tWD tCKP SHD(1) tS tINHIBIT tADC tADC tCKP ADCCK tHOLD B0 to B11 tOD N – 11 N – 10 SYMBOL N–9 N–8 PARAMETER MIN TYP MAX N–7 UNITS tCKP Clock Period 48 tADC ADCCK HIGH/LOW Pulse Width 20 ns tWP SHP Pulse Width 14 ns tWD SHD Pulse Width 11 ns tPD SHP Trailing Edge to SHD Leading Edge(1) 8 ns tDP SHD Trailing Edge to SHP Leading Edge(1) 12 ns tS Sampling Delay tINHIBIT Inhibited Clock Period 20 t HOLD Output Hold Time 7 tOD Output Delay (No Load) DL Data Latency, Normal Operation Mode ns 5 ns ns ns 38 9 (fixed) ns Clock Cycles NOTE: (1) The description and timing diagrams in this data sheet are all based on the polarity of Active LOW (default value). The active polarity (Active LOW or Active HIGH) can be chosen through the serial interface. Refer to the “Serial Interface” section for more detail. ® 5 VSP2212 SERIAL INTERFACE TIMING SPECIFICATIONS tXS SLOAD tXH tCKL tCKP tCKH SCLK(1) tDH tDS SDATA LSB MSB 2 Bytes(2) SYMBOL PARAMETER MIN tCKP Clock Period 100 TYP MAX UNITS ns tCKH Clock HIGH Pulse Width 40 ns tCKL Clcok LOW Pulse Width 40 ns tDS Data Setup Time 30 ns t DH Data Hold TIme 30 ns tXS SLOAD to SCLK Setup Time 30 ns tXH SCLK to SLOAD Setup Time(1) 30 ns NOTES: (1) It is effective for the data shift operation at the rising edge of SCLK during SLOAD is LOW period. And Input 2 bytes data are loaded to the parallel latch in the VSP2212 at the rising edge of SLOAD. (2) When the input serial data is longer than 2 bytes (16 bits), the last 2 bytes become effective and the former bits are discarded. ® VSP2212 6 A 0.1µF capacitor is recommended for CIN, depending on the application environment. Additionally, we recommend an off-chip emitter follower buffer that can drive more than 10pF, because 10pF of the sampling capacitor and a few pF of stray capacitance can be seen at the input pin. The analog input signal range at the CCDIN pin is 1Vp-p, and the appropriate common mode voltage for the CDS is around 0.5V to 1.5V. THEORY OF OPERATION INTRODUCTION The VSP2212 is a complete mixed-signal IC that contains all of the key features associated with the processing of the CCD imager output signal in a video camera, a digital still camera, security camera, or similar applications. A simplified block diagram is shown in the front page of this data sheet. The VSP2212 includes a correlated double sampler (CDS), programmable gain amplifier (PGA), Analog-toDigital Converter (ADC), input clamp, optical black (OB) level clamp loop, serial interface, timing control, reference voltage generator, and general purpose 8-bit Digital-toAnalog Converters (DAC). We recommend an off-chip emitter follower buffer between the CCD output and the VSP2212 CCDIN input. The PGA gain control, clock polarity setting, and operation mode selection can be made through the serial interface. All parameters are reset to the default value when the RESET pin goes to LOW asynchronously from the clocks. The reference level is sampled during SHP active period, and the voltage level is held on sampling capacitor C1 at the trailing edge of SHP. The data level is sampled during SHD active period, and the voltage level is held on the sampling capacitor C2 at the trailing edge of SHD. The switchedcapacitor amplifier then performs the subtraction of these two levels. The active polarity of SHP/SHD (Active HIGH or Active LOW) can be selected through the serial interface (refer to “Serial Interface” section for more detail). The default value of SHP/SHD is “Active LOW”. However, immediately after power on, this value is “Unknown”. For this reason, the appropriate value must be set by using the serial interface, or reset to the default value by the RESET pin. The description and the timing diagrams in this data sheet are all based on the polarity of Active LOW (default value). CORRELATED DOUBLE SAMPLER (CDS) The output signal of a CCD imager is sampled twice during one pixel period: one at the reference interval and the other at the data interval. Subtracting these two samples extracts the video information of the pixel as well as removes any noise that is common, or correlated, to both the intervals. Therefore, the CDS is very important to reduce the reset noise and the low-frequency noises that are present on the CCD output signal. Figure 1 shows the simplified block diagram of the CDS and input clamp. INPUT CLAMP OR DUMMY PIXEL CLAMP The buffered CCD output is capacitively coupled to the VSP2212. The purpose of the input clamp is to restore the DC component of the input signal that was lost with the AC coupling and establish the desired DC bias point for the CDS. Figure 1 also shows a simplified block diagram of the input clamp. The input level is clamped to internal reference voltage CM (1.5V) during the dummy pixel interval. More specifically, when both CLPDM and SHP are active, the dummy clamp function becomes active. If the dummy pixels and/or the CLPDM pulse are not available in your system, the CLPOB pulse can be used in place of CLPDM, as long as the clamping takes place during black pixels. In this case, both the CPLDM pin (actives as same timing as CLPOB) and SHP become active during the optical black pixel interval, and then the dummy clamp function becomes active. VSP2212 SHP C1 10pF CIN CCD Output CCDIN OPA CLPDM SHD C2 10pF The active polarity of CLPDM and SHP (Active HIGH or Active LOW) can be selected through the serial interface (refer to the “Serial Interface” section for more detail). The default value of CLPDM and SHP is “Active LOW”. However, immediately after power on, this value is “Unknown”. For this reason, the appropriate value must be set by using the serial interface, or reset to the default value by the RESET pin. The description and the timing diagrams in this data sheet are all based on the polarity of Active LOW (default value). SHP CM (1.5V) FIGURE 1. Simplified Block Diagram of CDS and Input Clamp. The CDS is driven through an off-chip coupling capacitor (CIN). AC coupling is strongly recommended because the DC level of the CCD output signal is usually several volts too high for the CDS to work properly. ® 7 VSP2212 HIGH PERFORMANCE ANALOG-TO-DIGITAL CONVERTER (ADC) During the effective pixel interval, the reference level of the CCD output signal is clamped to the OB level by the OB level clamp loop. To determine the loop time constant, an off-chip capacitor is required, and should be connected to COB (pin 28). Time constant T is given in the following equation: The Analog-to-Digital Converter (ADC) utilizes a fully differential and pipelined architecture. This ADC is well suited for low-voltage operations, low-power consumption requirements, and high-speed applications. It guarantees 12-bit resolution of output data with no missing code. The VSP2212 includes a reference voltage generator for the ADC. REFP (Positive Reference, pin 38), REFN (Negative Reference, pin 39), and CM (Common-Mode Voltage, pin 37) should be bypassed to ground with a 0.1µF ceramic capacitor, and should not be used elsewhere in the system; they affect the stability of these reference levels, and cause ADC performance degradation. Note that these are analog output pins. T = C/(16384 • Imin) Where C is the capacitor value connected to COB, Imin is the minimum current (0.15µA) of the control DAC in the OB level clamp loop, and 0.15µA is equivalent to 1LSB of the DAC output current. When C is 0.1µF, the time constant T is 40.7µs. Additionally, the slew rate SR is given the following equation: SR = Imax/C PROGRAMMABLE GAIN AMPLIFIER (PGA) Figure 2 shows the characteristics of the PGA gain. The PGA provides a gain range of –6dB to +42dB, which is linear in dB. The gain is controlled by a digital code with 10-bit resolution, and can be set through the serial interface (refer to the “Serial Interface” section for more detail). The default value of the gain control code is 128 (PGA Gain = 0dB). However, immediately after power on, this value is “Unknown”. For this reason, the appropriate value must be set by using the serial interface, or reset to the default value by the RESET pin. Where C is the capacitor value connected to COB, Imax is the maximum current (153µA) of the control DAC in the OB level clamp loop, and 153µA is equivalent to 1023LSB of the DAC output current. Generally, OB level clampling at high speed causes “Clamp Noise” (or “White Streak Noise”), however, the noise will decrease by increasing C. On the other hand, an increased C requires a much longer time to restore from Stand-By mode, or right after power on. Therefore, we consider 0.1µF to 0.22µF a reasonable value for C. However, it depends on the application environment; we recommend making careful adjustments using trial-and-error. OPTICAL BLACK (OB) LEVEL CLAMP LOOP The “OB clamp level” (the pedestal level) is programmable through the serial interface (refer to the “Serial Interface” section for more detail). Table I shows the relationship between input code and the OB clamp level. 50 40 Gain (dB) 30 20 10 0 1k 1023 900 800 700 600 500 400 300 200 100 0 –10 Input Code for Gain Control (0 to 1023) FIGURE 2. Characteristics of PGA Gain. To extract the video information correctly, the CCD signal must be referenced to a well-established Optical Black (OB) level. The VSP2212 has an auto-calibration loop to establish the OB level using the optical black pixels output from the CCD imager. The input signal level of the OB pixels is identified as the real “OB level”, and the loop should be closed during this period while CLPOB is active. OB CLAMP LEVEL, LSBs OF 12 BITS 0000 2 LSB 0001 18 LSB 0010 34 LSB 0011 50 LSB 0100 66 LSB 0101 82 LSB 0110 98 LSB 0111 114 LSB 1000 (Default) 130 LSB 1001 146 LSB 1010 162 LSB 1011 178 LSB 1100 194 LSB 1101 210 LSB 1110 226 LSB 1111 242 LSB TABLE I. Programmable OB Clamp Level. ® VSP2212 INPUT CODE 8 VOLTAGE REFERENCE The active polarity of CLPOB (Active HIGH or Active LOW) can be selected through the serial interface (refer to the “Serial Interface” section for more detail). The default value of CLPOB is “Active LOW”. However, immediately after power on, this value is “Unknown”. For this reason, the appropriate value must be set by using serial interface, or reset to the default value by the RESET pin. The description and the timing diagrams in this data sheet are all based on the polarity of Active LOW (default value). All the reference voltages and bias currents needed in the VSP2212 are generated by its internal bandgap circuitry. The CDS and the ADC use mainly three reference voltages: REFP (Positive Reference, pin 38), REFN (Negative Reference, Pin 39) and CM (Common-Mode Voltage, pin 37). REFP, REFN and CM should be heavily decoupled with appropriate capacitors (e.g., 0.1µF ceramic capacitor), and should not be used elsewhere in the system; they affect the stability of the reference level, and cause ADC performance degradation. Note that these are analog output pins. PREBLANKING AND DATA LATENCY Some CCDs have large transient output signals during blanking intervals. Such signals may exceed the VSP2212’s 1Vp-p input signal range and would overdrive the VSP2212 into saturation. Recovery time from the saturation could be substantial. To avoid this, the VSP2212 has an input blanking (or preblanking) function (PBLK). When PBLK goes to LOW, the CCDIN input is disconnected from the internal CDS stage and large transients are prevented from passing through. The VSP2212’s digital outputs will go to all ZEROs at the 11th rising edge of ADCCK, from just after PBLK sets to LOW, to accommodate the clock latency of the VSP2212. In this mode, the digital output data come out at the rising edge of ADCCK with a delay of 11 clock cycles (data latency is 11). Note that in the normal operation mode, the digital output data come out at the rising edge of ADCCK with a delay of 9 clock cycles (data latency is 9). BYPP2 (pin 29), BYP(pin 31), BYPM(pin 32) are also reference voltages to be used in the analog circuit. BYP should be connected to ground with 0.1µF ceramic capacitor. The capacitor value for BYPP2 and BYPM affects the step response. Therefore, we consider 1000pF is the reasonable value. However, it depends on the application environment; we recommend making careful adjustments using trial-and-error. All of BYPP2, BYP and BYPM should be heavily decoupled with appropriate capacitors, and not used elsewhere in the system. They affect the stability of these reference level, and cause performance degradation. Note that these are analog output pins. SERIAL INTERFACE It is recommended that CLPOB should not be activated during PBLK active period in order to keep a stable and accurate OB clamp level. Since the CCDIN input is disconnected from the internal circuit, even if the auto-calibration loop is closed while CLPOB is active, the OB clamp level is different from the “actual” OB level established by CCD imager output. The missed OB clamp level would affect the picture quality. If the input voltage is higher than the supply rail by 0.3V, or lower than the ground rail by 0.3V, protection diodes will be turned on to prevent the input voltage from going further. Such a high swing signal may cause device damage to the VSP2212 and should be avoided. The serial interface has a 2-byte shift register and various parallel registers to control all the digitally programmable features of the VSP2212. Writing to these registers is controlled by four signals (SLOAD, SCLK, SDATA, RESET). To enable the shift register, SLOAD must be pulled LOW. SDATA is the serial data input and the SCLK is the shift clock. The data at SDATA is taken into the shift register at the rising edge of SCLK. The data length should be 2 bytes. After the 2-byte shift operation, the data in the shift register is transferred to the parallel latch at the rising edge of SLOAD. In addition to the parallel latch, there are several registers dedicated to the specific features of the device and they are synchronized with ADCCK. It takes 5 or 6 clock cycles for the data in the parallel latch to be written to those registers. Therefore, to complete the data updates, it requires 5 or 6 clock cycles after the parallel latching by the rising edge of SLOAD. STAND-BY MODE For the purpose of power saving, the VSP2212 can be set to Stand-By mode (or Power-Down mode) through the serial interface when the VSP2212 is not in use. Refer to “Serial Interface” section for more detail. In this mode, all the function blocks are disabled and the digital outputs will go to all ZEROs. The consumption current will drop to 1mA. Since all the bypass capacitors will discharge during this mode, a substantial time (usually of the order of 200ms to 300ms) is required to power up from Stand-By mode. See Table II for the serial interface data format. TEST is the flag for the test mode (Burr-Brown proprietary only), A0 to A2 is the address for the various registers, and D0 to D11 is the data or the operand field. ® 9 VSP2212 REGISTERS Configuration PGA Gain OB Clamp Level Clock Polarity DAC0 Data DAC1 Data Reserved Reserved TEST A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 x 0 0 1 1 0 0 1 x 0 1 0 1 0 1 0 x 0 0 0 0 0 0 x x 0 0 0 0 0 0 x x 0 G9 0 0 0 0 x x 0 G8 0 0 0 0 x x 0 G7 0 0 E7 F7 x x 0 G6 0 0 E6 F6 x x 0 G5 0 0 E5 F5 x x 0 G4 0 0 E4 F4 x x 0 G3 O3 0 E3 F3 x x C2 G2 O2 P2 E2 F2 x x C1 G1 O1 P1 E1 F1 x x C0 G0 O0 P0 E0 F0 x x x = Don’t Care. TABLE II. Serial Interface Data Format. REGISTER DEFINITIONS C[2:0] Operation Mode, Normal/Stand-By Serial Interface and Registers are always active, independently from the operation mode. C0 = Operation Mode for the entire chip except DAC0/DAC1 (C0 = 0 “Active”; C0 = 1 “Stand-by”) C1 = for DAC0 (C0 = 0 “Active”; C0 = 1 “Stand-by”) C2 = for DAC1 (C0 = 0 “Active”; C0 = 1 “Stand-by”) G[9:0] The Characteristics of PGA Gain (refer to Figure 2) O[3:0] Programmable OB Clamp Level (refer to Table I) P[2:0] Clock Polarity P0 = Polarity for CLPDM (P0 = 0 “Active LOW”; P0 = 1 “Active HIGH”) P1 = for CLPOB (P0 = 0 “Active LOW”; P0 = 1 “Active HIGH”) P2 = for SHP/SHD (P0 = 0 “Active LOW”; P0 = 1 “Active HIGH”) E[7:0] DAC0 Data (All ZEROs = Output Voltage Minimum; All ONEs = Output Voltage Maximum) F[7:0] DAC1 Data (All ZEROs = Output Voltage Minimum; All ONEs = Output Voltage Maximum) Immediately after power on, these values are “Unknown”. The appropriate value must be set by using the serial interface, or reset to the default value by the RESET pin. Default values are: C[2:0] = 000 Normal Operation Mode G[9:0] = 0010000000 PGA Gain = 0dB O[3:0] = 1000 OB Clamp Level = 130LSB P[2:0] = 000 CLPDM, CLPOB, SHP/SHD are all “Active LOW” (1) E[7:0] = 00000000 DAC0 Output Voltage = Minimum F[7:0] = 00000000 DAC1 Output Voltage = Minimum NOTE: (1) The description and the timing diagrams in this data sheet are all based on the polarity of Active LOW (default value). ® VSP2212 10 POWER SUPPLY, GROUNDING AND DEVICE DECOUPLING RECOMMENDATIONS TIMINGS The CDS and the ADC are operated by SHP/SHD and their derivative timing clocks generated by the on-chip timing generator. The digital output data is synchronized with ADCCK. The timing relationship among the CCD signal, SHP/SHD, ADCCK and the output data is shown in the VSP2212 “CDS Timing Specifications”. CLPOB is used to activate the black level clamp loop during the OB pixel interval, and CLPDM is used to activate the input clamping during the dummy pixel interval. If the CLPDM pulse is not available in your system, the CLPOB pulse can be used in place of CLPDM as long as the clamping takes place during black pixels (refer to the “Input Clamp and Dummy Pixel Clamp” section for more detail). The clock polarities of SHP/SHD, CLPOB and CLPDM can be independently set through the serial interface (refer to the “Serial Interface” section for more detail). The description and the timing diagrams in this data sheet are all based on the polarity of Active LOW (default value). In order to keep a stable and accurate OB clamp level, we recommend CLPOB should not be activated during PBLK active period. Refer to the “Preblanking and Data Latency” section for more detail. In Stand-By mode, all of ADCCK, SHP, SHD, CLPOB and CLPDM are internally masked and pulled HIGH. The VSP2212 incorporates a very high-precision and highspeed Analog-to-Digital converter and analog circuitry that are vulnerable to any extraneous noise from the rails or elsewhere. For this reason, it should be treated as an analog component and all supply pins except for DRVDD should be powered by the only analog supply of the system. This will ensure the most consistent results, since digital power lines often carry high level of wide band noise that would otherwise be coupled into the device and degrade the achievable performance. Proper grounding, short lead length and the use of ground planes are also very important for highfrequency designs. Multi-layer PC boards are recommended for the best performance, since they offer distinct advantages like minimizing ground impedance, separation of signal layers by ground layers, etc. It is highly recommended that analog and digital ground pins of the VSP2212 be joined together at the IC and be connected only to the analog ground of the system. The driver stage of the digital outputs (B[11:0]) is supplied through a dedicated supply pin (DRVDD) and it should be separated from the other supply pins completely, or at least with a ferrite bead. It is also recommended to keep the capacitive loading on the output data lines as low as possible (typically less than 15pF). Larger capacitive loads demand higher charging current surges that can feed back into the analog portion of the VSP2212 and affect the performance. If possible, external buffers or latches should be used, providing the added benefit of isolating the VSP2212 from any digital noise activities on the data lines. In addition, resistors in series with each data line may help minimizing the surge current. Values in the range of 100Ω to 200Ω will limit the instantaneous current the output stage has to provide for recharging the parasitic capacitances as the output levels change from LOW to HIGH, or HIGH to LOW. Due to high operation speed, the converter also generates high-frequency current transients and noises that are fed back into the supply and reference lines. This requires the supply and reference pins be sufficiently bypassed. In most cases, 0.1µF ceramic chip capacitors are adequate to decouple the reference pins. Supply pins should be decoupled to the ground plane with a parallel combination of tantalum (1µF to 22µF) and ceramic (0.1µF) capacitors. The effectiveness of the decoupling largely depends on the proximity to the individual pin. DRVDD should be decoupled to the proximity of DRVGND. Special attention must be paid to the bypassing of COB, BYPP2 and BYPM, since these capacitor values determine important analog performances of the device. GENERAL-PURPOSE 8-BIT DIGITAL-TO-ANALOG CONVERTER (DAC0,DAC1) The VSP2212 incorporates two identical 8-bit Digital-toAnalog converters (DACs). These DACs are for user-definable options such as iris control and sub-bias voltage control of the CCD imager. The input data for these DACs is set by the written data through the serial interface (refer to the “Serial Interface” section for more detail). DAC input data that is all ZEROs corresponds to a minimum output voltage of 0.1V. In a similar manner, all ONEs correspond to a maximum output voltage of 2.9V. Figure 3 shows the characteristics. 3.0 Output Voltage (V) 2.5 2.0 1.5 1.0 0.5 250 255 200 150 100 50 0 0 Input Control Code (0 to 255) FIGURE 3. Characteristics for general-purpose 8-bit DAC (DAC0, DAC1). ® 11 VSP2212