TI SN74LV161284DGGR

SN74LV161284
19-BIT BUS INTERFACE
SCLS426C – OCTOBER 1998 – REVISED NOVEMBER 2002
D
D
D
D
D
D
DGG OR DL PACKAGE
(TOP VIEW)
4.5-V to 5.5-V VCC Operation
1.4-kΩ Pullup Resistors Integrated on All
Open-Drain Outputs Eliminate the Need for
Discrete Resistors
Designed for IEEE Std 1284-I (Level-1 Type)
and IEEE Std 1284-II (Level-2 Type)
Electrical Specifications
Flow-Through Architecture Optimizes PCB
Layout
Latch-Up Performance Exceeds 250 mA Per
JEDEC 17
ESD Protection Exceeds JESD 22
– 4000-V Human-Body Model (A114-A)
– 300-V Machine Model (A115-A)
– 2000-V Charged-Device Model (C101)
HD
A9
A10
A11
A12
A13
VCC
A1
A2
GND
A3
A4
A5
A6
GND
A7
A8
VCC
PERI LOGIC IN
A14
A15
A16
A17
HOST LOGIC OUT
description/ordering information
The SN74LV161284 is designed for 4.5-V to
5.5-V VCC operation. This device provides
asynchronous two-way communication between
data buses. The control-function implementation
minimizes external timing requirements.
This device has eight bidirectional bits; data can
flow in the A-to-B direction when DIR is high, and
in the B-to-A direction when DIR is low. This
device also has five drivers, which drive the cable
side, and four receivers. The SN74LV161284 has
one receiver dedicated to the HOST LOGIC line
and a driver to drive the PERI LOGIC line.
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
DIR
Y9
Y10
Y11
Y12
Y13
VCC CABLE
B1
B2
GND
B3
B4
B5
B6
GND
B7
B8
VCC CABLE
PERI LOGIC OUT
C14
C15
C16
C17
HOST LOGIC IN
The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the B, Y, and
PERI LOGIC OUT outputs are in a totem-pole configuration, and in an open-drain configuration when HD is low.
This meets the drive requirements as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II
(level-2 type) parallel peripheral-interface specifications. Except for HOST LOGIC IN and PERI LOGIC OUT,
all cable-side pins have a 1.4-kΩ integrated pullup resistor. The pullup resistor is switched off if the associated
output driver is in the low state or if the output voltage is above VCC CABLE. If VCC CABLE is off,
PERI LOGIC OUT is set to low.
The device has two supply voltages. VCC is designed for 4.5-V to 5.5-V operation. VCC CABLE supplies the
output buffers of the cable side only and is designed for 4.5-V to 5.5-V operation.
ORDERING INFORMATION
–40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
SSOP – DL
Tube
SN74LV161284DL
Tape and reel
SN74LV161284DLR
TOP-SIDE
MARKING
LV161284
TSSOP – DGG
Tape and reel
SN74LV161284DGGR
LV161284
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN74LV161284
19-BIT BUS INTERFACE
SCLS426C – OCTOBER 1998 – REVISED NOVEMBER 2002
FUNCTION TABLE
INPUTS
DIR
HD
L
L
L
H
H
L
H
H
OUTPUT
MODE
Open drain
A9–A13 to Y9–Y13 and PERI LOGIC IN to PERI LOGIC OUT
Totem pole
B1–B8 to A1–A8 and C14–C17 to A14–A17
Totem pole
B1–B8 to A1–A8, A9–A13 to Y9–Y13, PERI LOGIC IN to PERI LOGIC OUT, and C14–C17 to A14–A17
Open drain
A1–A8 to B1–B8, A9–A13 to Y9–Y13, and PERI LOGIC IN to PERI LOGIC OUT
Totem pole
C14–C17 to A14–A17
Totem pole
A1–A8 to B1–B8, A9–A13 to Y9–Y13, C14–C17 to A14–A17, and PERI LOGIC IN to PERI LOGIC OUT
logic diagram (positive logic)
VCC CABLE
DIR
HD
42
48
See Note B
See Note B
1
See Note A
A1–A8
B1–B8
A9–A13
PERI LOGIC IN
Y9–Y13
19
30
A14–A17
HOST LOGIC OUT
PERI LOGIC OUT
C14–C17
24
25
HOST LOGIC IN
NOTES: A. The PMOS prevents backdriving current from the signal pins to VCC CABLE when VCC CABLE is open or at GND.
B. The PMOS prevents backdriving current from the signal pins to VCC CABLE when VCC CABLE is open or at GND. The PMOS
is turned off when the associated driver is in the low state.
2
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SN74LV161284
19-BIT BUS INTERFACE
SCLS426C – OCTOBER 1998 – REVISED NOVEMBER 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range: VCC CABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input and output voltage range, VI and VO: Cable side (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . –2 V to 7 V
Peripheral side (see Note 1) . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA
Output high sink current, ISK (VO = 5.5 V and VCC CABLE = 5.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 mA
Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The ac input voltage pulse duration is limited to 40 ns if the amplitude is more negative than –0.5 V.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
VCC CABLE
VCC
MIN
MAX
Supply voltage for the cable side, VCC CABLE ≥ VCC
4.5
5.5
V
Supply voltage
4.5
5.5
V
A, DIR, HD, and PERI LOGIC IN
VIH
High level input voltage
High-level
B
VCC × 0.7
2
C14–C17
2.3
HOST LOGIC IN
2.6
VIL
Low level input voltage
Low-level
B
C14–C17
0.8
HOST LOGIC IN
1.6
V
Peripheral side
0
Cable side
0
VCC
5.5
V
Open-drain output voltage
B, Y, and PERI LOGIC OUT (HD low)
0
5.5
V
High-level output current
A outputs and HOST LOGIC OUT
VI
Input voltage
VO
IOH
B and Y outputs (HD high)
PERI LOGIC OUT
B and Y outputs
IOL
V
VCC × 0.3
0.8
A, DIR, HD, and PERI LOGIC IN
UNIT
Low-level output current
A outputs and HOST LOGIC OUT
PERI LOGIC OUT
–14
–8
mA
–0.5
14
8
mA
84
TA
Operating free-air temperature
–40
85
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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3
SN74LV161284
19-BIT BUS INTERFACE
SCLS426C – OCTOBER 1998 – REVISED NOVEMBER 2002
electrical characteristics over recommended
VCC CABLE = VCC (unless otherwise noted)
PARAMETER
∆Vt
VIK
I
Input
th
hysteresis
t
i
Input clamp diode voltage
B and Y outputs
VOH
A outputs and HOST LOGIC OUT
PERI LOGIC OUT
B and Y outputs
VOL
A outputs and HOST LOGIC OUT
PERI LOGIC OUT
C inputs
II
B and C inputs
All inputs except the B or C inputs
B outputs
IOZ
A1–A8
Open-drain Y outputs
IOZPU
B and Y outputs
IOZPD
B and Y outputs
Ioff
ff
operating
free-air
TEST CONDITIONS
4.5 V to 5.5 V
0.4
VthH – VthL for the HOST LOGIC IN
VthH – VthL for the C inputs
5V
II = –18 mA
IOH = –14 mA (HD high)
3V
IOH = –8 mA (HD high)
IOH = –50 µA
4.5 V
IOH = –0.5 mA
IOL = 14 mA
4.5 V
ZO
R pullup
Cable side
Cable side
0.8
–1.2
V
3.8
V
4.45
0.77
0.1
45V
4.5
IOL = 84 mA
VI = VCC
0.44
V
0.7
VI = GND (pullup resistors)
VI = 5.5 V or GND
55V
5.5
350
µA
–5
mA
0 to 5.5 V
±5
mA
VI = VCC or GND
VO = VCC
5.5 V
±1
µA
5.5 V
350
µA
VO = GND (pullup resistors)
VO = VCC or GND
5.5 V
–5
mA
5.5 V
±20
µA
VO = GND (pullup resistors)
VO = 5.5 V
5.5 V
–5
mA
VO = GND
VO = 5.5 V
0 to 2 V
2 V to 0
VO = GND
350
µA
–5
mA
350
µA
–5
mA
100
µA
0
100
0.8
55V
5.5
70
mA
VI = VCC or GND
VO = VCC or GND
5V
5
pF
5V
9
pF
IOH = –35 mA
VO = 0 V (in Hi Z)
5V
5V
† All typical values are at VCC = 5 V, TA = 25°C.
‡ A maximum current of 170 µA per pin is added to ICC if the pullup resistor pin is above VCC.
4
V
0.3
4.4
VI = VCC,
IO = 0
VI = GND (12 × pullup)
I/O ports
MAX
3.73
IOL = 50 µA
IOL = 8 mA
VI = 5.5 V
All inputs
UNIT
VthH – VthL for all inputs except the
C inputs and HOST LOGIC IN
Power-down input leakage,
Inputs C14 – C17 and HOST
LOGIC IN
Cio
TYP†
MIN
VO = 5.5 V
Ci
range,
VCC
Power-down output leakage,
Outputs B1 – B8, Y9 – Y13, and
PERI LOGIC OUT
ICC‡
temperature
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Ω
45
1.15
1.65
kΩ
SN74LV161284
19-BIT BUS INTERFACE
SCLS426C – OCTOBER 1998 – REVISED NOVEMBER 2002
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figures 1 and 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
Totem pole
A or B
B or A
tPLH
tPHL
Totem pole
A
Y
tPLH
tPHL
Totem pole
C
A
tPLH
tPHL
Totem pole
PERI LOGIC IN
PERI LOGIC OUT
tPLH
tPHL
Totem pole
HOST LOGIC IN
HOST LOGIC OUT
tslew
Totem pole
ten
Totem pole
HD
tdis
Totem pole
HD
MIN
TYP
30
2
30
2
30
2
30
2
30
2
30
2
30
2
30
2
30
2
30
0.05
0.95
B, Y, and PERI LOGIC OUT
2
25
ns
B, Y, and PERI LOGIC OUT
2
25
ns
10
ns
ns
Cable-side outputs
DIR
tdis
di
tr, tf
DIR
Open drain
A
UNIT
2
ten–tdis
ten
MAX
A
2
25
A
2
15
B
2
25
B or Y
tsk(o)
B or A
A or B
† Skew is measured at 1/2 (VOH + VOL) for signals switching in the same direction.
1
ns
ns
ns
ns
ns
V/ns
ns
30
ns
6
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
Outputs enabled
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CL = 0,
f = 10 MHz
TYP
25
UNIT
pF
5
SN74LV161284
19-BIT BUS INTERFACE
SCLS426C – OCTOBER 1998 – REVISED NOVEMBER 2002
PARAMETER MEASUREMENT INFORMATION
VCC
tw
CL = 50 pF
(see Note A)
62 Ω
TP1
VCC/2
VCC/2
0V
tPLH
Sink Load
From
B or Y Output
Under Test
VCC
Input
(see Note B)
tPHL
tPHL
Output
(see Note B)
tPLH
VOH
VOH – 1.4 V
VOL
VOL + 1.4 V
Source Load
VOLTAGE WAVEFORMS MEASURED AT TP1
PROPAGATION DELAY TIMES (A to B)
CL = 50 pF
(see Note A)
62 Ω
SLEW RATE A-TO-B OR A-TO-Y LOAD (Totem Pole)
VCC
VCC
Input
(see Note C)
TP1
From
B or Y Output
VCC/2
VCC/2
0V
500 Ω
Output
(see Note C)
CL = 50 pF
(see Note A)
2V
VOH
2V
0.8 V
0.8 V
tr
VOL
tf
VOLTAGE WAVEFORMS MEASURED AT TP1, B SIDE
A-TO-B LOAD OR A-TO-Y LOAD (Open Drain)
NOTES: A. CL includes probe and jig capacitance.
B. Input rise and fall times are 3 ns, 150 ns < pulse duration < 10 µs for both low-to-high and high-to-low transitions.
Slew rate is measured between 0.4 V and 1.9 V for the rising edge and between 95% VCC and 50% VCC for the falling edge.
C. Input rise and fall times are 3 ns. Rise and fall times (open drain) < 120 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
6
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SN74LV161284
19-BIT BUS INTERFACE
SCLS426C – OCTOBER 1998 – REVISED NOVEMBER 2002
PARAMETER MEASUREMENT INFORMATION
500 Ω
From Output
Under Test
VCC × 2
Open
S1
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VCC × 2
GND
LOAD CIRCUIT
VCC
Output
Control
Input
(see Note B)
3V
1.5 V
1.5 V
0V
tPLH
tPHL
VCC/2
0V
tPLZ
tPZL
Output
Waveform 1
S1 at VCC × 2 V
(see Note C)
VOH
Output
VCC/2
VCC/2
VCC/2
VOL
VCC
VCC/2
VOL + 0.3 V
VOL
tPHZ
tPZH
Output
Waveform 2
S1 at GND
(see Note C)
VCC/2
VOH – 0.3 V
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (B to A)
B-TO-A LOAD (Totem Pole)
VCC
tw
CL = 50 pF
(see Note A)
500 Ω
Input
(see Note D)
VCC
VCC/2
VCC/2
0V
TP1
From
B or Y Output
Under Test
Sink Load
tPLH
tPHL
tPHL
Output
(see Note D)
tPLH
VOL + 1.4 V
Source Load
500 Ω
CL = 50 pF
(see Note A)
VOH
VOH – 1.4 V
VOL
VOLTAGE WAVEFORMS MEASURED AT TP1
PROPAGATION DELAY TIMES (A to B)
A-TO-B LOAD OR A-TO-Y LOAD (Totem Pole)
NOTES: A. CL includes probe and jig capacitance.
B. Input rise and fall times are 3 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. Input rise and fall times are 3 ns, 150 ns < pulse duration < 10 µs for both low-to-high and high-to-low transitions.
E. The outputs are measured one at a time with one transition per measurement.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
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7
PACKAGE OPTION ADDENDUM
www.ti.com
5-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
74LV161284DGGRE4
ACTIVE
TSSOP
DGG
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV161284DGGR
ACTIVE
TSSOP
DGG
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV161284DL
ACTIVE
SSOP
DL
48
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV161284DLR
ACTIVE
SSOP
DL
48
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
25
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
0.0135 (0,343)
0.008 (0,203)
48
0.005 (0,13) M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
1
0°–ā8°
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.110 (2,79) MAX
0.004 (0,10)
0.008 (0,20) MIN
PINS **
28
48
56
A MAX
0.380
(9,65)
0.630
(16,00)
0.730
(18,54)
A MIN
0.370
(9,40)
0.620
(15,75)
0.720
(18,29)
DIM
4040048 / E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-118
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MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
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amplifier.ti.com
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