SCES619 – DECEMBER 2004 D Operates as GTL-/GTL/GTL+ to LVTTL or D D D PW PACKAGE (TOP VIEW) LVTTL to GTL-/GTL/GTL+ Translator Series Termination on TTL Outputs of 30 Latch-Up Testing to JEDEC Standard JESD 78 Exceeds 500 mA ESD Performance Tested Per JESD 22 − 2000-V Human-Body Model (A114-B, Class II) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) VREF 1AO 2AO 5A 6A 8AI 11BI 11A 9BI 3AO 4AO 10AI1 10AI2 GND description The SN74GTL2006 is a 13-bit translator to interface between the 3.3-V LVTTL chipset I/O and the Xeon processor GTL-/GTL/GTL+ I/O. The device is designed for platform health management in dual-processor applications. 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 VCC 1BI 2BI 7BO1 7BO2 8BO 11BO 5BI 6BI 3BI 4BI 10BO1 10BO2 9AO PIN DESCRIPTION PIN NUMBER SYMBOL NAME AND FUNCTION 1 VREF 2–6, 8, 10–13, 15 GTL reference voltage nAn Data inputs/outputs (LVTTL) 7, 9, 16, 17–27 nBn Data inputs/outputs (GTL−/GTL/GTL+) 14 GND Ground (0 V) 28 VCC Positive supply voltage ORDERING INFORMATION −40°C to 85°C ORDERABLE PART NUMBER PACKAGE† TA TSSOP − PW TOP-SIDE MARKING Tube SN74GTL2006PW GK2006 Tape and reel SN74GTL2006PWR GK2006 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design, guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright 2004, Texas Instruments Incorporated !" # $%&" !# '%()$!" *!"&+ *%$"# $ " #'&$$!"# '& ",& "&# &-!# #"%&"# #"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0 !)) '!!&"&#+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCES619 – DECEMBER 2004 Function Tables INPUTS 1BI/2BI/3BI/4BI/9BI OUTPUTS 1AO/2AO/3AO/4AO/9AO L L H H INPUT 8AI OUTPUT 8BO L L H H INPUTS 10AI1/10AI2 9BI OUTPUTS 10BO1/10BO2 L L L L H L H L L H H H INPUTS 5BI/6BI L H INPUTS/OUTPUTS 5A/6A (OPEN DRAIN) L L‡ OUTPUTS 7BO1/7BO2 H† L H H H † The enable on 7BO1/7BO2 includes a delay that prevents a transient condition (when 5BI/6BI goes from low to high, and the low to high on 5A/6A lags up to 100 ns) from causing a low glitch on the 7BO1/7BO2 outputs. ‡ Open-drain input/output terminal is driven to a logic-low state by an external driver. INPUT 11BI L L INPUT/OUTPUT 11A (OPEN DRAIN) H L‡ OUTPUT 11BO L H H L H ‡ Open-drain input/output terminal is driven to a logic-low state by an external driver. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCES619 – DECEMBER 2004 logic symbol SN74GTL2006 GTL VREF 2 27 3 26 5A (Open Drain) 4 25 6A (Open Drain) 5 24 6 23 7 22 1AO LVTTL Outputs 2AO LVTTL I/Os 1 LVTTL Input 8AI GTL Input 11BI LVTTL I/O 11A (Open Drain) GTL Input 9BI 3AO 4AO LVTTL Inputs 10AI1 10AI2 2BI GTL Inputs 7BO1 7BO2 GTL Outputs 8BO 11BO Delay 8 21 5BI 9 Delay 20 LVTTL Outputs 1BI 10 19 11 18 17 12 16 13 15 6BI 3BI GTL Inputs 4BI 10BO1 10BO2 GTL Outputs 9AO LVTTL Output NOTE A: The enable on 7BO1/7BO2 includes a delay that prevents a transient conditon (where 5BI/6BI go from low to high, and the low to high on 5A/6A lags up to 100 ns) from causing a low glitch on the 7BO1/7BO2 outputs. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SCES619 – DECEMBER 2004 absolute maximum ratings over operating free-air temperature (unless otherwise noted)†‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to 4.6 V Input voltage range, VI (see Note 2): A port (LVTTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to 4.6 V B port (GTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to 4.6 V Output voltage range, VO (output in OFF or HIGH state)(see Note 2): A port . . . . . . . . . . . . . . . . −0.5 to 4.6 V B port . . . . . . . . . . . . . . . . −0.5 to 4.6 V Input diode current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Output diode current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Current into any output in the LOW state: A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 mA B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Current into any output in the HIGH state, A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −32 mA Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −60 to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ Voltages are referenced to GND (ground = 0 V). NOTES: 1. The performance capability of a high-performance integrated circuit, in conjunction with its thermal environment, can create junction temperatures that are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 2. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. recommended operating conditions VCC VTT VREF MIN NOM MAX 3 3.3 3.6 GTL− 0.85 0.9 0.95 GTL 1.14 1.2 1.26 GTL+ 1.35 1.5 1.65 Overall 0.5 2/3 VTT 1.8 GTL− 0.5 0.6 0.63 GTL 0.76 0.8 0.84 GTL+ 0.87 1 1.1 A port 0 3.3 3.6 B port 0 VTT 3.6 Supply voltage Termination voltage Reference voltage VI Input voltage VIH High-level input voltage VIL Low-level input voltage IOH High-level output current IOL Low-level output current TA Operating free-air temperature range A port 4 B port V V V V 2 V VREF + 50 mV A port 0.8 B port VREF − 50 mV −16 A port A port 16 B port 15 −40 POST OFFICE BOX 655303 UNIT • DALLAS, TEXAS 75265 85 V mA mA °C SCES619 – DECEMBER 2004 electrical characteristics over recommended operating conditions PARAMETER VOH‡ VOL‡ II ICC DICC§ CIO –40C TO 85C MIN TYP† MAX TEST CONDITIONS VCC = 3 V to 3.6 V, VCC = 3 V, IOH = –100 mA IOH = –16 mA VCC = 3 V, VCC = 3 V, IOL = 16 mA IOL = 15 mA 0.8 B port A port VCC = 3.6 V VI = VCC VI = 0 V ±1 B port VCC = 3.6 V, VCC = 3.6 V, VI = VTT or GND VI = VCC or GND, ±1 VCC = 3.6 V, VO = 3 V or 0, VI = VCC – 0.6 V VO = 3 V or 0 A port A port A or B port A port or control inputs A port VCC – 0.2 2.1 V 0.4 ±1 IO = 0 VO = VTT or 0, VO = VTT or 0 † All typical values are measured at VCC = 3.3 V and TA = 25°C. ‡ The input and output voltage ratings may be exceeded if the input and output current ratings are observed. § This is the increase in supply current for each input that is at the specified LVTTL voltage, rather than VCC or GND. V mA 12 mA 500 mA 5 B port UNIT pF 4 switching characteristics over recommended operating free-air temperature range PARAMETER WAVEFORM tPLH tPHL An to Bn 1 tPLH tPHL Bn to An 2 tPLH tPHL 9BI to 10BOn 3 tPLH tPHL¶ 11BI to 11BO 3 tPLH tPHL Bn to Bn 3 tPLZ tPZL Bn to An (I/O) 4 GTL− GTL GTL+ VCC = 3.3 V 0.3 V, VREF = 0.6 V MIN TYP† MAX VCC = 3.3 V 0.3 V, VREF = 0.8 V MIN TYP† MAX VCC = 3.3 V 0.3 V, VREF = 1 V MIN TYP† MAX 2 4 8 2 4 8 2 4 8 2 5.5 10 2 5.5 10 2 5.5 10 2 5.5 10 2 5.5 10 2 5.5 10 2 5.5 10 2 5.5 10 2 5.5 10 2 6 11 2 6 11 2 6 11 2 6 11 2 6 11 2 6 11 2 8 13 2 8 13 2 8 13 2 14 21 2 14 21 2 14 21 4 7 11 4 7 11 4 7 11 120 205 350 120 205 350 120 205 350 2 5 10 2 5 10 2 5 10 2 5 10 2 5 10 2 5 10 UNIT ns ns ns ns ns ns † All typical values are measured at VCC = 3.3 V and TA = 25°C. ¶ Includes ∼7.6-ns RC rise time of test-load pullup on 11-A, 1.5-kΩ pullup, and 21-pF load on 11 A has approximately 23-ns RC rise time. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SCES619 – DECEMBER 2004 PARAMETER MEASUREMENT INFORMATION VTT = 1.2 V, VREF = 0.8 V FOR GTL AND VTT = 1.5 V, VREF = 1 V FOR GTL+ S1 500 Ω From Output Under Test 2 VCC VTT Open 50 Ω TEST tPLH/tPHL tPLZ/tPZL GND CL = 50 pF (see Note A) 500 Ω S1 Open 2 VCC From Output Under Test CL = 30 pF (see Note A) LOAD CIRCUIT FOR B OUTPUTS LOAD CIRCUIT FOR A OUTPUTS 3V Input (see Note B) 1.5 V Test Point 1.5 V Input (see Note B) VTT VREF VREF 0V tPHL tPLH 0V tPHL tPLH VOH VTT Output VREF Output VREF 1.5 V 1.5 V VOL VOL VOLTAGE WAVEFORM 2 PROPAGATION DELAY TIMES (B port to A port)† VOLTAGE WAVEFORM 1 PROPAGATION DELAY TIMES (A port to B port)† VTT Input (see Note B) VTT VREF VREF Input (see Note B) VREF VREF 0V 0V tPZL VTT Output tPLZ tPHL tPLH VREF VREF VOL VCC 1.5 V Output S1 at 2 VCC VOL + 0.3 V VOL VOLTAGE WAVEFORM 4 PROPAGATION DELAY TIMES (B port to A (I/O) port)† VOLTAGE WAVEFORM 3 PROPAGATION DELAY TIMES (B port to B port)† † All control inputs are LVTTL levels. NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. C. The outputs are measured one at a time, with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCES619 – DECEMBER 2004 APPLICATION INFORMATION VTT VTT 56 56 R VCC 1.5 k to 1.2 k 1.5 k 2R Platform Health Management VCC CPU1 VREF VCC CPU1 1ERR_L 1AO 1BI 1ERR_L CPU1 THRMTRIP L 2AO 2BI CPU1 PROCHOT L 5A 7BO1 THRMTRIP L FORCEPR_L CPU2 PROCHOT L 6A 7BO2 FORCE PR_L 8AI 8BO 11BI 11B0 11A 5BI NMI_L 3AO CPU2 THRMTRIP L 4AO CPU1 SMI L CPU2 SMI L NMI CPU1 SMI L 9BI CPU2 1ERR_L PROCHOT L 6BI FORCEPR_L PROCHOT L 3BI 4BI 1ERR_L THRMTRIP L 10AI1 10BO1 NMI 10AI2 10BO2 CPU2 SMI L GND 9AO CPU2 SMI_BUFF_L SN74GTL2006 Southbridge NMI Southbridge SMI_L Optional Signal Line frequently asked questions Question 1: On SN74GTL2006 LVTTL inputs, specifically 10AI1 and 10AI2, when the device is powered down, these inputs may be pulled up to 3.3 V, and we want to ensure that there is no leakage path to the power rail under this condition. Are the LVTTL inputs high impedance when the device is powered down, and will there be any leakage? Answer 1: When the device is powered down, the LVTTL inputs are in a high-impedance state and do not leak to VDD if they are pulled high while the device is powered down. Question 2: Do all the LVTTL inputs have the same powered-down characteristic? Answer 2: Yes Question 3: What is the condition of the other GTL I/O and LVTTL output pins when the device is powered down? Answer 3: The open-drain outputs, both GTL and LVTTL, do not leak to the power supply if they are pulled high while the device is powered down. The GTL inputs also do not leak to the power supply under the same conditions. The LVTTL totem-pole outputs, however, are not open-drain type outputs, and there will be current flow on these pins if they are pulled high when VDD is at ground. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74GTL2006PW ACTIVE TSSOP PW 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTL2006PWE4 ACTIVE TSSOP PW 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTL2006PWG4 ACTIVE TSSOP PW 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTL2006PWR ACTIVE TSSOP PW 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTL2006PWRE4 ACTIVE TSSOP PW 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTL2006PWRG4 ACTIVE TSSOP PW 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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