CD54/74AC139, CD54/74ACT139 Data sheet acquired from Harris Semiconductor SCHS235A Dual 2-to-4-Line Decoder/Demultiplexer September 1998 - Revised May 2000 Features Description • Buffered Inputs The ’AC139 and ’ACT139 are dual 2-to-4-line decoders/demultiplexers that utilize Advanced CMOS Logic technology. These devices contain two independent binary to one-of-four decoders, each with a single active LOW enable input (1E or 2E). Data on the select inputs (1A0 and 1A1 or 2A0 and 2A1) cause one of the four normally HIGH outputs to go LOW. • Typical Propagation Delay - 5.4ns at VCC = 5V, TA = 25oC, CL = 50pF • Exceeds 2kV ESD Protection MIL-STD-883, Method 3015 [ /Title (CD74 AC139 , CD74 ACT13 9) /Subject (Dual 2-to-4Line Decod er/Dem ultiplexer) /Autho r () /Keywords (Harris Semiconductor, Advan ced CMOS ) /Creator () /DOCI NFO • SCR-Latchup-Resistant CMOS Process and Circuit Design If the enable input is HIGH, all four outputs remain HIGH. For demultiplexer operation, the enable input is the data input. The enable input also functions as a chip select when these devices are cascaded. • Speed of Bipolar FAST™/AS/S with Significantly Reduced Power Consumption • Balanced Propagation Delays Ordering Information • AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply PART NUMBER • ±24mA Output Drive Current - Fanout to 15 FAST™ ICs - Drives 50Ω Transmission Lines TEMP. RANGE (oC) CD54AC139F3A -55 to 125 PACKAGE 16 Ld CERDIP CD74AC139E 0 to 70oC, -40 to 85, -55 to 125 16 Ld PDIP CD74AC139M96 0 to 70oC, -40 to 85, -55 to 125 16 Ld SOIC CD54ACT139F3A -55 to 125 CD74ACT139E 0 to 70oC, -40 to 85, 16 Ld CERDIP 16 Ld PDIP -55 to 125 CD74ACT139M 0 to 70oC, -40 to 85, -55 to 125 16 Ld SOIC NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. Pinout CD54AC139, CD54ACT139 (CERDIP) CD74AC139, CD74ACT139 (PDIP, SOIC) TOP VIEW 1E 1 16 VCC 1A0 2 15 2E 1A1 3 14 2A0 1Y0 4 13 2A1 1Y1 5 12 2Y0 1Y2 6 11 2Y1 1Y3 7 10 2Y2 GND 8 9 2Y3 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. FAST™ is a Trademark of Fairchild Semiconductor. Copyright © 2000, Texas Instruments Incorporated. 1 CD54/74AC139, CD54/74ACT139 Functional Diagram 4 2 1A0 1Y0 5 DECODER 1 1Y1 6 1Y2 7 3 1A1 1Y3 1 1E 12 14 2A0 2Y0 11 DECODER 2 2Y1 10 2Y2 9 13 2A1 2Y3 15 2E GND = 8 VCC = 16 TRUTH TABLE INPUTS ENABLE SELECT OUTPUTS E A1 A0 Y3 Y2 Y1 Y0 L L L H H H L L L H H H L H L H L H L H H L H H L H H H H X X H H H H X = Don’t Care 2 CD54/74AC139, CD54/74ACT139 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA DC VCC or Ground Current, ICC or IGND (Note 3) . . . . . . . . .±100mA Thermal Resistance (Typical, Note 5) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC (Note 4) AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Slew Rate, dt/dv AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max) AC Types, 3.6V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max) ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 3. For up to 4 outputs per device, add ±25mA for each additional output. 4. Unless otherwise specified, all voltages are referenced to ground. 5. θJA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS PARAMETER -40oC TO 85oC 25oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) MIN MAX MIN MAX MIN MAX UNITS VIH - - 1.5 1.2 - 1.2 - 1.2 - V AC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage VIL VOH - VIH or VIL 3 2.1 - 2.1 - 2.1 - V 5.5 3.85 - 3.85 - 3.85 - V 1.5 - 0.3 - 0.3 - 0.3 V 3 - 0.9 - 0.9 - 0.9 V 5.5 - 1.65 - 1.65 - 1.65 V -0.05 1.5 1.4 - 1.4 - 1.4 - V -0.05 3 2.9 - 2.9 - 2.9 - V -0.05 4.5 4.4 - 4.4 - 4.4 - V -4 3 2.58 - 2.48 - 2.4 - V -24 4.5 3.94 - 3.8 - 3.7 - V -75 (Note 6, 7) 5.5 - - 3.85 - - - V -50 (Note 6, 7) 5.5 - - - - 3.85 - V - 3 CD54/74AC139, CD54/74ACT139 DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER Low Level Output Voltage -40oC TO 85oC 25oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) MIN MAX MIN MAX MIN MAX UNITS VOL VIH or VIL 0.05 1.5 - 0.1 - 0.1 - 0.1 V 0.05 3 - 0.1 - 0.1 - 0.1 V 0.05 4.5 - 0.1 - 0.1 - 0.1 V 12 3 - 0.36 - 0.44 - 0.5 V 24 4.5 - 0.36 - 0.44 - 0.5 V 75 (Note 6, 7) 5.5 - - - 1.65 - - V 50 (Note 6, 7) 5.5 - - - - - 1.65 V II VCC or GND - 5.5 - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - 8 - 80 - 160 µA High Level Input Voltage VIH - - 4.5 to 5.5 2 - 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 - 0.8 - 0.8 - 0.8 V High Level Output Voltage VOH VIH or VIL -0.05 4.5 4.4 - 4.4 - 4.4 - V -24 4.5 3.94 - 3.8 - 3.7 - V -75 (Note 6, 7) 5.5 - - 3.85 - - - V -50 (Note 6, 7) 5.5 - - - - 3.85 - V 0.05 4.5 - 0.1 - 0.1 - 0.1 V 24 4.5 - 0.36 - 0.44 - 0.5 V 75 (Note 6, 7) 5.5 - - - 1.65 - - V 50 (Note 6, 7) 5.5 - - - - - 1.65 V Input Leakage Current Quiescent Supply Current MSI ACT TYPES Low Level Output Voltage Input Leakage Current Quiescent Supply Current MSI Additional Supply Current per Input Pin TTL Inputs High 1 Unit Load VOL VIH or VIL II VCC or GND - 5.5 - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - 8 - 80 - 160 µA ∆ICC VCC -2.1 - 4.5 to 5.5 - 2.4 - 2.8 - 3 mA NOTES: 6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize power dissipation. 7. Test verifies a minimum 50Ω transmission-line-drive capability at 85oC, 75Ω at 125oC. ACT Input Load Table INPUT UNIT LOAD A0, A1 1 E 0.67 NOTE: Unit load is ∆ICC limit specified in DC Electrical Specifications Table, e.g., 2.4mA max at 25oC. 4 CD54/74AC139, CD54/74ACT139 Switching Specifications Input tr, tf = 3ns, CL = 50pF (Worst Case) -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN TYP MAX UNITS tPLH, tPHL 1.5 - - 119 - - 131 ns 3.3 (Note 9) 3.9 - 13.4 3.7 - 14.7 ns 5 (Note 10) 2.8 - 9.5 2.6 - 10.5 ns 1.5 - - 119 - - 131 ns 3.1 3.9 - 13.4 3.7 - 14.7 ns 5 2.8 - 9.5 2.6 - 10.5 ns CI - - - 10 - - 10 pF CPD (Note 11) - - 83 - - 83 - pF Propagation Delay, A0, A1 to Outputs tPLH, tPHL 5 (Note 10) 3.1 - 10.5 2.9 - 11.5 ns Propagation Delay, E to Outputs tPLH, tPHL 5 3.2 - 10.9 3 - 12 ns Input Capacitance CI - - - 10 - - 10 pF CPD (Note 11) - - 83 - - 83 - pF PARAMETER AC TYPES Propagation Delay, A0, A1 to Outputs Propagation Delay, E to Outputs tPLH, tPHL Input Capacitance Power Dissipation Capacitance ACT TYPES Power Dissipation Capacitance NOTES: 8. Limits tested at 100%. 9. 3.3V Min at 3.6V, Max at 3V. 10. 5V Min at 5.5V, Max at 4.5V. 11. CPD is used to determine the dynamic power consumption per decoder/demultiplexer. AC: PD = VCC2 fi (CPD + CL) ACT: PD = VCC2 fi (CPD + CL) + VCC ∆ICC where fi = input frequency, CL = output load capacitance, VCC = supply voltage. 3ns 3ns INPUT LEVEL 90% tr = 3ns VS tf = 3ns 90% VS 10% INPUT E A1 10% INPUT LEVEL GND tPHL GND tPLH tPHL tPLH INPUT Y3 VS OUTPUT Y3 VS FIGURE 2. FIGURE 1. 5 CD54/74AC139, CD54/74ACT139 OUTPUT RL (NOTE) 500Ω DUT OUTPUT LOAD CL 50pF NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ. AC ACT VCC 3V Input Switching Voltage, VS 0.5 VCC 1.5V Output Switching Voltage, VS 0.5 VCC 0.5 VCC Input Level FIGURE 3. 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