TI MSP430C1351IPM

SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004
D Low Supply-Voltage Range, 1.8 V to 3.6 V
D Ultralow-Power Consumption:
D
D
D
D
D
D On-Chip Comparator
D Serial Communication Interface (USART),
− Active Mode: 160 µA at 1 MHz, 2.2 V
− Standby Mode: 0.9 µA
− Off Mode (RAM Retention) : 0.1 µA
Five Power-Saving Modes
Wake-Up From Standby Mode in less
than 6 µs
16-Bit RISC Architecture,
125-ns Instruction Cycle Time
16-Bit Timer_B With Three
Capture/Compare-With-Shadow Registers
16-Bit Timer_A With Three
Capture/Compare Registers
D
D
D
D
D
Software Selects Asynchronous UART or
Synchronous SPI
Programmable Code Protection With
Security Fuse
Family Members Include:
− MSP430C1331: 8KB ROM, 256B RAM
− MSP430C1351: 16KB ROM, 512B RAM
Available in 64-Pin Quad Flat Pack (QFP)
Emulation: Use MSP430F13xIPM
For Complete Module Descriptions, See the
MSP430x1xx Family User’s Guide,
Literature Number SLAU049
description
The Texas Instruments MSP430 family of ultralow-power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low power
modes is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6 µs.
The MSP430C13x1 is a microcontroller configuration with two built-in 16-bit timers, one universal serial
synchronous/asynchronous communication interfaces (USART), and 48 I/O pins.
Typical applications include sensor systems that capture analog signals, convert them to digital values, and
process and transmit the data to a host system. The timers make the configurations ideal for industrial control
applications, hand-held meters, etc.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
−40°C to 85°C
PLASTIC 64-PIN QFP
(PM)
MSP430C1331IPM
MSP430C1351IPM
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2001 − 2004, Texas Instruments Incorporated
!" #!$% &"'
&! #" #" (" " " !"
&& )*' &! #"+ &" ""%* %!&"
"+ %% #""'
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AVCC
DVSS
AV SS
P6.2
P6.1
P6.0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
XT2IN
XT2OUT
P5.7/TBOUTH
PM PACKAGE
(TOP VIEW)
1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P1.5/TA0
P1.6/TA1
P1.7/TA2
P2.0/ACLK
P2.1/TAINCLK
P2.2/CAOUT/TA0
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.5/Rosc
P2.6
P2.7/TA0
P3.0/STE0
P3.1/SIMO0
P3.2/SOMI0
P3.3/UCLK0
P3.4/UTXD0
DVCC
P6.3
P6.4
P6.5
P6.6
P6.7
NC
XIN
XOUT
NC
NC
P1.0/TACLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
P5.6/ACLK
P5.5/SMCLK
pin designation, MSP430C1331, MSP430C1351
NC − No internal connection
2
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P5.4/MCLK
P5.3
P5.2
P5.1
P5.0
P4.7/TBCLK
P4.6
P4.5
P4.4
P4.3
P4.2/TB2
P4.1/TB1
P4.0/TB0
P3.7
P3.6
P3.5/URXD0
SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004
functional block diagrams
MSP430C13x1
XIN XOUT/TCLK
DVCC
DVSS
AVCC
P1
AVSS RST/NMI
8
ROSC
Oscillator
XT2IN
System
Clock
XT2OUT
ACLK
16KB ROM
512B RAM
SMCLK
8KB ROM
256B RAM
P2
P3
8
I/O Port 1/2
16 I/Os,
with
Interrupt
Capability
P4
8
P5
8
P6
8
I/O Port 3/4
16 I/Os
8
I/O Port 5/6
16 I/Os
MCLK
Test
MAB,
4 Bit
MAB,MAB,
16 Bit16-Bit
JTAG
CPU
Emulation
Module
MCB
Incl. 16 Reg.
Bus
Conv
MDB,
16-Bit
MDB,
16 Bit
MDB, 8 Bit
4
TMS
Watchdog
Timer
TCK
TDI
15/16-Bit
TDO/TDI
Timer_B3
Timer_A3
3 CC Reg
Shadow
Reg
3 CC Reg
POR
Comparator
A
USART0
UART Mode
SPI Mode
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AVCC
AVSS
64
Supply voltage, positive terminal. AVCC and DVCC are internally connected together.
62
Supply voltage, negative terminal. AVSS and DVSS are internally connected together.
DVCC
1
Supply voltage, positive terminal. AVCC and DVCC are internally connected together.
DVSS
63
Supply voltage, negative terminal. AVSS and DVSS are internally connected together.
P1.0/TACLK
12
I/O
General-purpose digital I/O pin/Timer_A, clock signal TACLK input
P1.1/TA0
13
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output
P1.2/TA1
14
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output
P1.3/TA2
15
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output
P1.4/SMCLK
16
I/O
General-purpose digital I/O pin/SMCLK signal output
P1.5/TA0
17
I/O
General-purpose digital I/O pin/Timer_A, compare: Out0 output
P1.6/TA1
18
I/O
General-purpose digital I/O pin/Timer_A, compare: Out1 output
P1.7/TA2
19
I/O
General-purpose digital I/O pin/Timer_A, compare: Out2 output
P2.0/ACLK
20
I/O
General-purpose digital I/O pin/ACLK output
P2.1/TAINCLK
21
I/O
General-purpose digital I/O pin/Timer_A, clock signal at INCLK
P2.2/CAOUT/TA0
22
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI0B input/Comparator_A output
P2.3/CA0/TA1
23
I/O
General-purpose digital I/O pin/Timer_A, compare: Out1 output/Comparator_A input
P2.4/CA1/TA2
24
I/O
General-purpose digital I/O pin/Timer_A, compare: Out2 output/Comparator_A input
P2.5/ROSC
P2.6
25
I/O
General-purpose digital I/O pin/input for external resistor defining the DCO nominal frequency
26
I/O
General-purpose digital I/O pin
P2.7/TA0
27
I/O
General-purpose digital I/O pin/Timer_A, compare: Out0 output
P3.0/STE0
28
I/O
General-purpose digital I/O pin/slave transmit enable – USART0/SPI mode
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Terminal Functions (Continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
P3.1/SIMO0
29
I/O
General-purpose digital I/O pin/slave in/master out of USART0/SPI mode
P3.2/SOMI0
30
I/O
General-purpose digital I/O pin/slave out/master in of USART0/SPI mode
P3.3/UCLK0
31
I/O
General-purpose digital I/O pin/external clock input − USART0/UART or SPI mode, clock output –
USART0/SPI mode
P3.4/UTXD0
32
I/O
General-purpose digital I/O pin/transmit data out – USART0/UART mode
P3.5/URXD0
33
I/O
General-purpose digital I/O pin/receive data in – USART0/UART mode
P3.6
34
I/O
General-purpose digital I/O pin
P3.7
35
I/O
General-purpose digital I/O pin
P4.0/TB0
36
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI0A/B input, compare: Out0 output
P4.1/TB1
37
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI1A/B input, compare: Out0 output
P4.2/TB2
38
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI2A/B input, compare: Out0 output
P4.3
39
I/O
General-purpose digital I/O pin
P4.4
40
I/O
General-purpose digital I/O pin
P4.5
41
I/O
General-purpose digital I/O pin
P4.6
42
I/O
General-purpose digital I/O pin
P4.7/TBCLK
43
I/O
General-purpose digital I/O pin/Timer_B, clock signal TBCLK input
P5.0
44
I/O
General-purpose digital I/O pin
P5.1
45
I/O
General-purpose digital I/O pin
P5.2
46
I/O
General-purpose digital I/O pin
P5.3
47
I/O
General-purpose digital I/O pin
P5.4/MCLK
48
I/O
General-purpose digital I/O pin/main system clock MCLK output
P5.5/SMCLK
49
I/O
General-purpose digital I/O pin/submain system clock SMCLK output
P5.6/ACLK
50
I/O
General-purpose digital I/O pin/auxiliary clock ACLK output
P5.7/TBOUTH
51
I/O
General-purpose digital I/O pin/switch all PWM digital output ports to high impedance − Timer_B7 TB0
to TB2
P6.0
59
I/O
General-purpose digital I/O pin
P6.1
60
I/O
General-purpose digital I/O pin
P6.2
61
I/O
General-purpose digital I/O pin
P6.3
2
I/O
General-purpose digital I/O pin
P6.4
3
I/O
General-purpose digital I/O pin
P6.5
4
I/O
General-purpose digital I/O pin
P6.6
5
I/O
General-purpose digital I/O pin
P6.7
6
I/O
General-purpose digital I/O pin
RST/NMI
58
I
Reset input, nonmaskable interrupt input port
TCK
57
I
Test clock. TCK is the clock input port for device programming test.
TDI/TCLK
55
I
Test data input or test clock input. TDI is used as a data input port. The device protection fuse is
connected to TDI.
TDO/TDI
54
I/O
56
I
TMS
Test data output port. TDO/TDI data output
Test mode select. TMS is used as an input port for device test.
NC
7, 10, 11
XIN
8
I
Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT
9
O
Output terminal of crystal oscillator XT1
XT2IN
53
I
Input port for crystal oscillator XT2. Only standard crystals can be connected.
XT2OUT
52
O
Output terminal of crystal oscillator XT2
4
No internal connection
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short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
Program Counter
PC/R0
Stack Pointer
SP/R1
SR/CG1/R2
Status Register
Constant Generator
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
Table 1. Instruction Word Formats
Dual operands, source-destination
e.g. ADD R4,R5
R4 + R5 −−−> R5
Single operands, destination only
e.g. CALL
PC −−>(TOS), R8−−> PC
Relative jump, un/conditional
e.g. JNE
R8
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
S D
Indirect
D
D
D
D
D
Indirect
autoincrement
Register
Indexed
Symbolic (PC relative)
Absolute
Immediate
NOTE: S = source
D
D
D
D
SYNTAX
EXAMPLE
MOV Rs,Rd
MOV R10,R11
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
OPERATION
R10
−−> R11
M(2+R5)−−> M(6+R6)
MOV EDE,TONI
M(EDE) −−> M(TONI)
MOV &MEM,&TCDAT
M(MEM) −−> M(TCDAT)
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) −−> M(Tab+R6)
D
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) −−> R11
R10 + 2−−> R10
D
MOV #X,TONI
MOV #45,TONI
#45
−−> M(TONI)
D = destination
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operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D Active mode AM;
−
All clocks are active
D Low-power mode 0 (LPM0);
−
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
D Low-power mode 1 (LPM1);
−
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
DCO’s dc-generator is disabled if DCO not used in active mode
D Low-power mode 2 (LPM2);
−
CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator remains enabled
ACLK remains active
D Low-power mode 3 (LPM3);
−
CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
ACLK remains active
D Low-power mode 4 (LPM4);
−
6
CPU is disabled
ACLK is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
Crystal oscillator is stopped
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interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh − 0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Power-up
External reset
Watchdog
WDTIFG
(see Note 1)
Reset
0FFFEh
15, highest
NMI
Oscillator fault
NMIIFG (see Notes 1 & 4)
OFIFG (see Notes 1 & 4)
(Non)maskable
(Non)maskable
0FFFCh
14
Timer_B3
TBCCR0 CCIFG
(see Note 2)
Maskable
0FFFAh
13
Timer_B3
TBCCR1 and TBCCR2
CCIFGs, TBIFG
(see Notes 1 & 2)
Maskable
0FFF8h
12
Comparator_A
CAIFG
Maskable
0FFF6h
11
Watchdog timer
WDTIFG
Maskable
0FFF4h
10
USART0 receive
URXIFG0
Maskable
0FFF2h
9
USART0 transmit
UTXIFG0
Maskable
0FFF0h
8
0FFEEh
7
Timer_A3
TACCR0 CCIFG
(see Note 2)
Maskable
0FFECh
6
Timer_A3
TACCR1 and TACCR2
CCIFGs, TAIFG
(see Notes 1 & 2)
Maskable
0FFEAh
5
I/O port P1 (eight flags)
P1IFG.0 to P1IFG.7
(see Notes 1 & 2)
Maskable
0FFE8h
4
0FFE6h
3
0FFE4h
2
0FFE2h
1
0FFE0h
0, lowest
I/O port P2 (eight flags)
NOTES: 1.
2.
3.
4.
P2IFG.0 to P2IFG.7
(see Notes 1 & 2)
Maskable
Multiple source flags
Interrupt flags are located in the module.
Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable can not disable
it.
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special function registers
Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits
not allocated to a functional purpose are not physically present in the device. This arrangement provides simple
software access.
interrupt enable 1 and 2
7
Address
0h
6
UTXIE0
rw-0
5
4
URXIE0
3
2
NMIIE
rw-0
1
0
OFIE
rw-0
rw-0
WDTIE
rw-0
WDTIE:
Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog
Timer is configured in interval timer mode.
OFIE:
Oscillator-fault-interrupt enable
NMIIE:
Nonmaskable-interrupt enable
URXIE0:
USART0: UART and SPI receive-interrupt enable
UTXIE0:
USART0: UART and SPI transmit-interrupt enable
7
Address
6
5
4
3
2
4
3
2
1
0
01h
interrupt flag register 1 and 2
7
Address
02h
6
UTXIFG0
rw-1
5
URXIFG0
NMIIFG
rw-0
1
0
OFIFG
rw-0
rw-1
WDTIFG
rw-(0)
WDTIFG:
Set on Watchdog Timer overflow (in watchdog mode) or security key violation. Reset on VCC
power-up or a reset condition at RST/NMI pin in reset mode.
OFIFG:
Flag set on oscillator fault
NMIIFG:
Set via RST/NMI pin
URXIFG0: USART0: UART and SPI receive flag
UTXIFG0: USART0: UART and SPI transmit flag
7
Address
6
5
4
3
2
1
0
5
4
3
2
1
0
03h
module enable registers 1 and 2
7
UTXE0
Address
04h
rw-0
8
6
URXE0
USPIE0
rw-0
URXE0:
USART0: UART receive enable
UTXE0:
USART0: UART transmit enable
USPIE0:
USART0: SPI (synchronous peripheral interface) transmit and receive enable
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7
Address
6
5
4
3
2
1
0
05h
Legend: rw:
rw-0,1:
rw-(0,1):
Bit Can Be Read and Written
Bit Can Be Read and Written. It Is Reset or Set by PUC.
Bit Can Be Read and Written. It Is Reset or Set by POR.
SFR Bit Not Present in Device
memory organization
MSP430C1331
MSP430C1351
Size
ROM
ROM
8KB
0FFFFh − 0FFE0h
0FFFFh − 0E000h
16KB
0FFFFh − 0FFE0h
0FFFFh − 0C000h
Size
256 Byte
02FFh − 0200h
512 Byte
03FFh − 0200h
16-bit
8-bit
8-bit SFR
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
Memory
Interrupt vector
Code memory
RAM
Peripherals
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, see the MSP430x1xx Family User’s Guide, literature number
SLAU049.
digital I/O
There are six 8-bit I/O ports implemented—ports P1 through P6:
D
D
D
D
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
Read/write access to port-control registers is supported by all instructions.
oscillator and system clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The basic clock
module is designed to meet the requirements of both low system cost and low-power consumption. The internal
DCO provides a fast turn-on clock source and stabilizes in less than 6 µs. The basic clock module provides the
following clock signals:
D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.
D Main clock (MCLK), the system clock used by the CPU.
D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
watchdog timer
The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
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USART0
The MSP430C13x1 devices have one hardware universal synchronous/asynchronous receive transmit
(USART0) peripheral module that is used for serial data communication. The USART supports synchronous
SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive
channels.
comparator_A
The primary function of the comparator_A module is to support precision slope analog−to−digital conversions,
battery−voltage supervision, and monitoring of external analog signals.
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections
Input Pin Number
Device Input Signal
Module Input Name
12 - P1.0
TACLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
21 - P2.1
TAINCLK
INCLK
13 - P1.1
TA0
CCI0A
TA0
CCI0B
DVSS
DVCC
GND
22 - P2.2
14 - P1.2
15 - P1.3
TA1
VCC
CCI1A
CAOUT (internal)
CCI1B
DVSS
DVCC
GND
TA2
VCC
CCI2A
ACLK (internal)
CCI2B
DVSS
DVCC
10
GND
Module Block
Module Output Signal
Timer
NA
13 - P1.1
17 - P1.5
CCR0
TA0
27 - P2.7
14 - P1.2
18 - P1.6
CCR1
TA1
23 - P2.3
15 - P1.3
19 - P1.7
CCR2
VCC
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TA2
24 - P2.4
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timer_B3
Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_B3 Signal Connections
Input Pin Number
Device Input Signal
Module Input Name
43 - P4.7
TBCLK
TBCLK
ACLK
ACLK
SMCLK
SMCLK
43 - P4.7
TBCLK
INCLK
36 - P4.0
TB0
CCI0A
36 - P4.0
TB0
CCI0B
DVSS
DVCC
GND
37 - P4.1
37 - P4.1
TB1
VCC
CCI1A
TB1
CCI1B
DVSS
DVCC
GND
38 - P4.2
TB2
VCC
CCI2A
38 - P4.2
TB2
CCI2B
DVSS
DVCC
GND
Module Block
Module Output Signal
Timer
NA
Output Pin Number
36 - P4.0
CCR0
TB0
37 - P4.1
CCR1
TB1
38 - P4.2
CCR2
TB2
VCC
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11
SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004
peripheral file map
PERIPHERALS WITH WORD ACCESS
Watchdog
Watchdog Timer control
WDTCTL
0120h
Timer_B3
Timer_B interrupt vector
TBIV
011Eh
Timer_B control
TBCTL
0180h
Capture/compare control 0
TBCCTL0
0182h
Capture/compare control 1
TBCCTL1
0184h
Capture/compare control 2
TBCCTL2
0186h
Reserved
0188h
Reserved
018Ah
Reserved
018Ch
Reserved
018Eh
Timer_B register
TBR
0190h
Capture/compare register 0
TBCCR0
0192h
Capture/compare register 1
TBCCR1
0194h
Capture/compare register 2
TBCCR2
0196h
Reserved
0198h
Reserved
019Ah
Reserved
019Ch
Reserved
Timer_A3
019Eh
Timer_A interrupt vector
TAIV
012Eh
Timer_A control
TACTL
0160h
Capture/compare control 0
TACCTL0
0162h
Capture/compare control 1
TACCTL1
0164h
Capture/compare control 2
TACCTL2
0166h
Reserved
0168h
Reserved
016Ah
Reserved
016Ch
Reserved
016Eh
Timer_A register
TAR
0170h
Capture/compare register 0
TACCR0
0172h
Capture/compare register 1
TACCR1
0174h
Capture/compare register 2
TACCR2
0176h
Reserved
0178h
Reserved
017Ah
Reserved
017Ch
Reserved
017Eh
PERIPHERALS WITH BYTE ACCESS
USART0
12
Transmit buffer
U0TXBUF
077h
Receive buffer
U0RXBUF
076h
Baud rate
U0BR1
075h
Baud rate
U0BR0
074h
Modulation control
U0MCTL
073h
Receive control
U0RCTL
072h
Transmit control
U0TCTL
071h
USART control
U0CTL
070h
POST OFFICE BOX 655303
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SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
Comparator_A
Basic Clock
Port P6
Port P5
Port P4
Port P3
Port P2
Port P1
Special Functions
Comparator_A port disable
CAPD
05Bh
Comparator_A control2
CACTL2
05Ah
Comparator_A control1
CACTL1
059h
Basic clock system control2
BCSCTL2
058h
Basic clock system control1
BCSCTL1
057h
DCO clock frequency control
DCOCTL
056h
Port P6 selection
P6SEL
037h
Port P6 direction
P6DIR
036h
Port P6 output
P6OUT
035h
Port P6 input
P6IN
034h
Port P5 selection
P5SEL
033h
Port P5 direction
P5DIR
032h
Port P5 output
P5OUT
031h
Port P5 input
P5IN
030h
Port P4 selection
P4SEL
01Fh
Port P4 direction
P4DIR
01Eh
Port P4 output
P4OUT
01Dh
Port P4 input
P4IN
01Ch
Port P3 selection
P3SEL
01Bh
Port P3 direction
P3DIR
01Ah
Port P3 output
P3OUT
019h
Port P3 input
P3IN
018h
Port P2 selection
P2SEL
02Eh
Port P2 interrupt enable
P2IE
02Dh
Port P2 interrupt-edge select
P2IES
02Ch
Port P2 interrupt flag
P2IFG
02Bh
Port P2 direction
P2DIR
02Ah
Port P2 output
P2OUT
029h
Port P2 input
P2IN
028h
Port P1 selection
P1SEL
026h
Port P1 interrupt enable
P1IE
025h
Port P1 interrupt-edge select
P1IES
024h
Port P1 interrupt flag
P1IFG
023h
Port P1 direction
P1DIR
022h
Port P1 output
P1OUT
021h
Port P1 input
P1IN
020h
SFR module enable 2
ME2
005h
SFR module enable 1
ME1
004h
SFR interrupt flag 2
IFG2
003h
SFR interrupt flag 1
IFG1
002h
SFR interrupt enable 2
IE2
001h
SFR interrupt enable 1
IE1
000h
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13
SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to + 4.1 V
Voltage applied to any pin (see Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC+0.3 V
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA
Storage temperature (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
Storage temperature (programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE: All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied
to the TDI/TCLK pin when blowing the JTAG fuse.
recommended operating conditions
PARAMETER
MIN
NOM
MAX
UNITS
Supply voltage during program execution, VCC (AVCC = DVCC = VCC)
1.8
3.6
Supply voltage, VSS (AVSS = DVSS = VSS)
0.0
0.0
V
Operating free-air temperature range, TA
−40
85
°C
450
8000
kHz
1000
8000
kHz
450
8000
1000
8000
DC
4.15
DC
8
LFXT1 crystal frequency, f(LFXT1)
(see Notes 1 and 2)
LF selected, XTS=0
Watch crystal
XT1 selected, XTS=1
Ceramic resonator
XT1 selected, XTS=1
Crystal
Ceramic resonator
XT2 crystal frequency, f(XT2)
Crystal
VCC = 1.8 V
VCC = 3.6 V
Processor frequency (signal MCLK), f(System)
32768
V
Hz
kHz
MHz
NOTES: 1. In LF mode, the LFXT1 oscillator requires a watch crystal and the LFXT1 oscillator requires a 5.1-MΩ resistor from XOUT to VSS
when VCC < 2.5 V. In XT1 mode, the LFXT1. and XT2 oscillators accept a ceramic resonator or a 4-MHz crystal frequency at
VCC ≥ 2.2 V. In XT1 mode, the LFXT1 and XT2 oscillators accept a ceramic resonator or an 8-MHz crystal frequency at VCC ≥ 2.8 V.
2. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, FXT1 accepts a ceramic resonator or a crystal.
f(System) MHz
8.0 MHz
4.15 MHz
1.8 V
2.7 V 3 V
Supply Voltage − V
3.6 V
Figure 1. Frequency vs Supply Voltage
14
POST OFFICE BOX 655303
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SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
supply current into AVCC + DVCC excluding external current
PARAMETER
TEST CONDITIONS
Active mode, (see Note 1)
f(MCLK) = f(SMCLK) = 1 MHz,
f(ACLK) = 32,768 Hz, XTS=0, SELM=(0,1)
TA = −40°C to 85°C
Active mode, (see Note 1)
f(MCLK) = f(SMCLK) = 4 096 Hz,
f(ACLK) = 4,096 Hz
XTS=0, SELM=(0,1), XTS=0, SELM=3
TA = −40°C to 85°C
I(LPM0)
Low-power mode, (LPM0) (see Note 1)
TA = −40°C to 85°C
I(LPM2)
Low-power mode, (LPM2),
f(MCLK) = f (SMCLK) = 0 MHz,
f(ACLK) = 32.768 Hz, SCG0 = 0
TA = −40°C to 85°C
I(AM)
I(LPM3)
I(LPM4)
TA = −40°C
TA = 25°C
Low-power mode, (LPM3)
f(MCLK) = f(SMCLK) = 0 MHz,
f(ACLK) = 32,768 Hz, SCG0 = 1
(see Note 2)
NOM
MAX
VCC = 2.2 V
160
200
VCC = 3 V
240
300
VCC = 2.2 V
2.5
7
VCC = 3 V
2.5
7
VCC = 2.2 V
VCC = 3 V
32
45
55
70
VCC = 2.2 V
11
14
VCC = 3 V
17
22
0.8
1.5
0.9
1.5
1.6
2.8
1.8
2.2
1.8
2.2
2.3
3.9
0.1
0.5
0.1
0.5
0.8
2.5
0.1
0.5
UNIT
µA
A
A
µA
VCC = 2.2 V
TA = 85°C
TA = −40°C
Low-power mode, (LPM4)
f(MCLK) = 0 MHz, f(SMCLK) = 0 MHz,
f(ACLK) = 0 Hz, SCG0 = 1
MIN
TA = 25°C
TA = 85°C
TA = −40°C
VCC = 3 V
TA = 25°C
TA = 85°C
VCC = 2.2 V
TA = −40°C
TA = 25°C
µA
A
µA
A
µA
µA
µA
0.1
0.5
VCC = 3 V
µA
TA = 85°C
0.8
2.5
NOTES: 1. Timer_B is clocked by f(DCOCLK) = 1 MHz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
2. Timer_B is clocked by f(ACLK) = 32,768 Hz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The current
consumption in LPM2 and LPM3 are measured with ACLK selected.
Current consumption of active mode versus system frequency
I(AM) = I(AM) [1 MHz] × f(System) [MHz]
Current consumption of active mode versus supply voltage
I(AM) = I(AM) [3 V] + 175 µA/V × (VCC – 3 V)
POST OFFICE BOX 655303
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15
SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
SCHMITT-trigger inputs − Ports P1, P2, P3, P4, P5, and P6
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT−
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ − VIT−)
MIN
TYP
MAX
VCC = 2.2 V
VCC = 3 V
VCC = 2.2 V
1.1
1.5
1.5
1.9
0.4
0.9
VCC = 3 V
VCC = 2.2 V
0.90
1.3
0.3
1.1
0.4
1
VCC = 3 V
UNIT
V
V
V
standard inputs − RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI
PARAMETER
VIL
VIH
TEST CONDITIONS
Low-level input voltage
VCC = 2.2 V / 3 V
High-level input voltage
MIN
TYP
VSS
0.8×VCC
MAX
UNIT
VSS+0.6
VCC
V
V
input frequency − Ports P1, P2, P3, P4, P5, and P6
PARAMETER
TEST CONDITIONS
f(IN)
MIN
TYP
VCC = 2.2 V
VCC = 3 V
t(h) = t(L)
MAX
8
10
UNIT
MHz
capture timing _ Timer_A3: TA0, TA1, TA2; Timer_B3: TB0, TB1, TB2
PARAMETER
t(int)
TEST CONDITIONS
Ports P2, P4:
External trigger signal for the interrupt flag (see Notes 1 and 2)
VCC = 2.2 V/3 V
VCC = 2.2 V
MIN
TYP
MAX
1.5
UNIT
Cycle
62
VCC = 3 V
50
NOTES: 1. The external signal sets the interrupt flag every time t(int) is met. It may be set even with trigger signals shorter than t(int).
The conditions to set the flag must be met independently of this timing constraint. t(int) is defined in MCLK cycles.
2. The external signal needs additional timing because of the maximum input-frequency constraint.
ns
external interrupt timing
PARAMETER
t(int)
TEST CONDITIONS
Ports P1, P2:
External trigger signal for the interrupt flag (see Notes 1 and 2)
VCC = 2.2 V/3 V
VCC = 2.2 V
MIN
TYP
MAX
1.5
UNIT
Cycle
62
VCC = 3 V
50
NOTES: 1. The external signal sets the interrupt flag every time t(int) is met. It may be set even with trigger signals shorter than t(int).
The conditions to set the flag must be met independently of this timing constraint. t(int) is defined in MCLK cycles.
2. The external signal needs additional timing because of the maximum input-frequency constraint.
ns
leakage current (see Note 1)
PARAMETER
Ilkg(P1.x)
Ilkg(P2.x)
Leakage
current
TEST CONDITIONS
Port P1
Port P2
V(P1.x) (see Note 2)
V(P2.3) V(P2.4) (see Note 2)
MIN
TYP
VCC = 2.2 V/3 V
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The port pin must be selected as input and there must be no optional pullup or pulldown resistor.
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MAX
±50
±50
UNIT
nA
SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs − Ports P1, P2, P3, P4, P5, and P6
PARAMETER
VOH
VOL
High-level output voltage
Low-level output voltage
TEST CONDITIONS
MIN
IOH(max) = −1.5 mA,
IOH(max) = −6 mA,
VCC = 2.2 V,
VCC = 2.2 V,
See Note 1
IOH(max) = −1.5 mA,
IOH(max) = −6 mA,
VCC = 3 V,
VCC = 3 V,
See Note 1
IOL(max) = 1.5 mA,
IOL(max) = 6 mA,
VCC = 2.2 V,
VCC = 2.2 V,
See Note 1
IOL(max) = 1.5 mA,
IOL(max) = 6 mA,
VCC = 3 V,
VCC = 3 V,
See Note 1
See Note 2
See Note 2
TYP
MAX
VCC−0.25
VCC−0.6
VCC
VCC
VCC−0.25
VCC−0.6
VCC
VCC
VSS
VSS
VSS+0.25
VSS+0.6
VSS
VSS
VSS+0.25
VSS+0.6
See Note 2
See Note 2
UNIT
V
V
NOTES: 1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to satisfy the maximum
specified voltage drop.
2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to satisfy the maximum
specified voltage drop.
output frequency
PARAMETER
TEST CONDITIONS
fTAx, fTBx
TA0..2, TB0..2
Internal clock source, SMCLK signal
applied (see Note 1)
fACLK,
fMCLK,
fSMCLK
P5.6/ACLK, P5.4/MCLK,
P5.5/SMCLK
CL = 20 pF
TYP
DC
MAX
UNIT
fSystem
MHz
CL = 20 pF
fSystem
P2.0/ACLK
CL = 20 pF,
VCC = 2.2 V / 3 V
tXdc
MIN
Duty cycle of output frequency
P1.4/SMCLK,
CL = 20 pF,
VCC = 2.2 V / 3 V
fACLK = fLFXT1 = fXT1
fACLK = fLFXT1 = fLF
fACLK = fLFXT1/n
fSMCLK = fLFXT1 = fXT1
fSMCLK = fLFXT1 = fLF
40%
60%
30%
70%
50%
40%
60%
35%
65%
fSMCLK = fLFXT1/n
50%−
15 ns
50%
50%−
15 ns
fSMCLK = fDCOCLK
50%−
15 ns
50%
50%−
15 ns
NOTE 1: The limits of the system clock MCLK has to be met; the system (MCLK) frequency should not exceed the limits. MCLK and SMCLK
frequencies can be different.
POST OFFICE BOX 655303
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17
SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs − Ports P1, P2, P3, P4, P5, and P6 (continued)
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
50
30
−40°C
25
VCC = 3 V
45
I OL− Low-Level Output Current − mA
I OL− Low-Level Output Current − mA
VCC = 2.2 V
25°C
85°C
20
15
10
5
−40°C
40
25°C
35
85°C
30
25
20
15
10
5
0
0
0.5
1
1.5
2
0
2.5
0
0.5
1
1.5
2
2.5
3
VOL − Low-Level Output Voltage − V
VOL − Low-Level Output Voltage − V
Figure 2
Figure 3
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
−35
−60
−40°C
−30
I OH− High-Level Output Current − mA
I OH− High-Level Output Current − mA
VCC = 2.2 V
−40°C
−25
85°C
25°C
−20
−15
−10
−5
0
0
0.5
1
1.5
2
2.5
VCC = 3 V
−50
85°C
−40
25°C
−30
−20
−10
0
0
0.5
1
1.5
Figure 5
Figure 4
POST OFFICE BOX 655303
2
2.5
3
VOH − High-Level Output Voltage − V
VOH − High-Level Output Voltage − V
18
3.5
• DALLAS, TEXAS 75265
3.5
SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
wake-up LPM3
PARAMETER
TEST CONDITIONS
MIN
TYP
f = 1 MHz
t(LPM3)
f = 2 MHz
Delay time
MAX
UNIT
6
6
VCC = 2.2 V/3 V
f = 3 MHz
µs
6
RAM
PARAMETER
TEST CONDITIONS
VRAMh
CPU HALTED (see Note 1)
MIN
TYP
MAX
1.6
UNIT
V
NOTE 1: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution
should take place during this supply voltage condition.
Comparator_A (see Note 1)
PARAMETER
TEST CONDITIONS
TYP
MAX
VCC = 2.2 V
VCC = 3 V
MIN
30
47
55
74
I(DD)
CAON=1, CARSEL=0, CAREF=0
CAON=1, CARSEL=0,
CAREF=1/2/3, no load at
P2.3/CA0/TA1 and P2.4/CA1/TA2
VCC = 2.2 V
40
57
I(Refladder/Refdiode)
VCC = 3 V
60
87
CAON =1
VCC = 2.2 V/3 V
0
PCA0=1, CARSEL=1, CAREF=1,
no load at P2.3/CA0/TA1 and
P2.4/CA1/TA2
VCC = 2.2 V/3 V
0.23
0.24
0.25
PCA0=1, CARSEL=1, CAREF=2,
no load at P2.3/CA0/TA1 and
P2.4/CA1/TA2
VCC = 2.2 V/3 V
0.47
0.48
0.5
PCA0=1, CARSEL=1, CAREF=3,
no load at P2.3/CA0/TA1 and
P2.4/CA1/TA2 TA = 85°C
VCC = 2.2 V
390
480
540
VCC = 3 V
400
490
550
V(IC)
V(Ref025)
V(Ref050)
Common-mode input
voltage
Voltage at 0.25 V
V
node
CC
Voltage at 0.5V
V
CC
CC
node
CC
VCC−1
UNIT
µA
µA
V
V(RefVT)
(see Figure 6 and Figure 7)
V(offset)
Vhys
Offset voltage
See Note 2
30
mV
CAON=1
VCC = 2.2 V/3 V
VCC = 2.2 V/3 V
−30
Input hysteresis
0
0.7
1.4
mV
TA = 25
25°C,
C, Overdrive 10 mV,
Without filter: CAF=0
VCC = 2.2 V
VCC = 3 V
130
210
300
80
150
240
TA = 25
25°C,
C, Overdrive 10 mV,
With filter: CAF=1
VCC = 2.2 V
VCC = 3 V
1.4
1.9
3.4
0.9
1.5
2.6
25°C,
TA = 25
C, Overdrive 10 mV,
Without filter: CAF=0
VCC = 2.2 V
VCC = 3 V
130
210
300
80
150
240
TA = 25
25°C,
C, Overdrive 10 mV,
With filter: CAF=1
VCC = 2.2 V
VCC = 3 V
1.4
1.9
3.4
0.9
1.5
2.6
t(response LH)
t(response HL)
mV
ns
µs
ns
µs
NOTES: 1. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification.
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.
The two successive measurements are then summed together.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
650
650
VCC = 2.2 V
V(REFVT) − Reference Volts −mV
V(REFVT) − Reference Volts −mV
VCC = 3 V
600
Typical
550
500
450
400
−45
−25
−5
15
35
55
75
600
Typical
550
500
450
400
−45
95
−25
−5
15
35
55
TA − Free-Air Temperature − °C
0 V VCC
1
CAF
CAON
Low Pass Filter
V+
V−
+
_
0
0
1
1
To Internal
Modules
CAOUT
Set CAIFG
Flag
τ ≈ 2.0 µs
Figure 8. Block Diagram of Comparator_A Module
VCAOUT
Overdrive
V−
400 mV
V+
t(response)
Figure 9. Overdrive Definition
20
95
Figure 7. V(RefVT) vs Temperature, VCC = 2.2 V
Figure 6. V(RefVT) vs Temperature, VCC = 3 V
0
75
TA − Free-Air Temperature − °C
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
PUC/POR
PARAMETER
TEST CONDITIONS
t(POR_Delay)
Internal time delay to release POR
VPOR
VCC threshold at which POR
release delay time begins
(see Note 1)
TA = −40°C
TA = 25°C
VCC threshold required to
generate a POR (see Note 2)
VCC |dV/dt| ≥ 1V/ms
V(min)
MIN
VCC = 2.2 V/3 V
TA = 85°C
TYP
MAX
UNIT
150
250
µs
1.4
1.8
V
1.1
1.5
V
0.8
1.2
V
0.2
V
t(reset)
RST/NMI low time for PUC/POR
Reset is accepted internally
2
µs
NOTES: 1. VCC rise time dV/dt ≥ 1V/ms.
2. When driving VCC low in order to generate a POR condition, VCC should be driven to 200mV or lower with a dV/dt equal to or less
than −1V/ms. The corresponding rising VCC must also meet the dV/dt requirement equal to or greater than +1V/ms.
V
Vcc
V
POR
No POR
POR
V
(min)
POR
t
Figure 10. Power-On Reset (POR) vs Supply Voltage
2
1.8
1.8
1.5
V POR − V
1.6
1.4
1.2
1.4
1.2
1
1.2
0.8
0.8
0.6
0.4
25°C
0.2
0
−40
−20
0
20
40
60
80
TA − Temperature − °C
Figure 11. VPOR vs Temperature
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
21
SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
DCO (see Note 1)
PARAMETER
f(DCO03)
f(DCO13)
f(DCO23)
f(DCO33)
f(DCO43)
f(DCO53)
f(DCO63)
f(DCO73)
TEST CONDITIONS
MIN
Rsel = 0, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C
Rsel = 1, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C
Rsel = 2, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C
Rsel = 3, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C
Rsel = 4, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C
Rsel = 5, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C
Rsel = 6, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C
MAX
UNIT
VCC = 2.2 V
VCC = 3 V
0.08
0.12
0.15
0.08
0.13
0.16
VCC = 2.2 V
VCC = 3 V
0.14
0.19
0.23
0.14
0.18
0.22
VCC = 2.2 V
VCC = 3 V
0.22
0.30
0.36
0.22
0.28
0.34
VCC = 2.2 V
VCC = 3 V
0.37
0.49
0.59
0.37
0.47
0.56
VCC = 2.2 V
VCC = 3 V
0.61
0.77
0.93
0.61
0.75
0.90
VCC = 2.2 V
VCC = 3 V
1
1.2
1.5
1
1.3
1.5
VCC = 2.2 V
VCC = 3 V
Rsel = 7, DCO = 3, MOD = 0, DCOR = 0, TA = 25°C
NOM
1.6
1.9
2.2
1.69
2.0
2.29
2.4
2.9
3.4
2.7
3.2
3.65
fDCO40
× 1.7
fDCO40
× 2.1
fDCO40
× 2.5
VCC = 2.2 V
VCC = 3 V
f(DCO47)
Rsel = 4, DCO = 7, MOD = 0, DCOR = 0, TA = 25°C
VCC = 2.2 V/3 V
f(DCO77)
Rsel = 7, DCO = 7, MOD = 0, DCOR = 0, TA = 25°C
VCC = 2.2 V
VCC = 3 V
S(Rsel)
S(DCO)
SR = fRsel+1 / fRsel
SDCO = fDCO+1 / fDCO
VCC = 2.2 V/3 V
VCC = 2.2 V/3 V
Dt
Temperature drift, Rsel = 4, DCO = 3, MOD = 0
(see Note 2)
VCC = 2.2 V
VCC = 3 V
DV
Drift with VCC variation, Rsel = 4, DCO = 3, MOD = 0
(see Note 2)
VCC = 2.2 V/3 V
4
4.5
4.9
4.4
4.9
5.4
1.35
1.65
2
1.07
1.12
1.16
−0.31
−0.36
−0.40
−0.33
−0.38
−0.43
0
5
10
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
%/°C
%/V
Frequency Variance
NOTES: 1. The DCO frequency may not exceed the maximum system frequency defined by parameter processor frequency, f(System).
2. This parameter is not production tested.
Max
f DCO_7
Min
Max
f DCO_0
Min
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
1
f DCOCLK
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
2.2
3
VCC − V
0
1
Figure 12. DCO Characteristics
22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2
3
4
5
6
7
DCO
SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
main DCO characteristics
D Individual devices have a minimum and maximum operation frequency. The specified parameters for
f(DCOx0) to f(DCOx7) are valid for all devices.
D All ranges selected by Rsel(n) overlap with Rsel(n+1): Rsel0 overlaps Rsel1, ... Rsel6 overlaps Rsel7.
D DCO control bits DCO0, DCO1, and DCO2 have a step size as defined by parameter SDCO.
D Modulation control bits MOD0 to MOD4 select how often f(DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency f(DCO) is used for the remaining cycles. The frequency is an average equal to:
f average +
MOD
32 f (DCO) f (DCO)1)
f (DCO))(32*MOD) f (DCO)1)
DCO when using ROSC (see Note 1)
PARAMETER
TEST CONDITIONS
fDCO, DCO output frequency
Rsel = 4, DCO = 3, MOD = 0, DCOR = 1,
TA = 25°C
Dt, Temperature drift
Rsel = 4, DCO = 3, MOD = 0, DCOR = 1
Dv, Drift with VCC variation
Rsel = 4, DCO = 3, MOD = 0, DCOR = 1
VCC
2.2 V
MIN
NOM
MAX
UNIT
2.0±15%
MHz
2.1±15%
MHz
2.2 V/3 V
±0.1
%/°C
2.2 V/3 V
10
%/V
3V
NOTES: 1. ROSC = 100kΩ. Metal film resistor, type 0257. 0.6 watt with 1% tolerance and TK = ±50ppm/°C.
crystal oscillator, LFXT1 oscillator (see Note 1)
PARAMETER
CXIN
Integrated input capacitance
CXOUT
Integrated output capacitance
VIL
VIH
Input levels at XIN
TEST CONDITIONS
MIN
NOM
XTS=0; LF oscillator selected VCC = 2.2 V/3 V
UNIT
12
XTS=1; XT1 oscillator selected VCC = 2.2 V/3 V
pF
2
XTS=0; LF oscillator selected VCC = 2.2 V/3 V
12
XTS=1; XT1 oscillator selected VCC = 2.2 V/3 V
VCC = 2.2 V/3 V (see Note 2)
MAX
pF
2
VSS
0.8 × VCC
0.2 × VCC
V
VCC
V
NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.
2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
crystal oscillator, XT2 oscillator (see Note 1)
PARAMETER
CXIN
Integrated input capacitance
CXOUT
Integrated output capacitance
VIL
VIH
Input levels at XT2IN
TEST CONDITIONS
MIN
NOM
VCC = 2.2 V/3 V
VCC = 2.2 V/3 V
MAX
2
pF
2
VCC = 2.2 V/3 V (see Note 2)
VSS
0.8 × VCC
UNIT
pF
0.2 × VCC
V
VCC
V
NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.
2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
USART0 (see Note 1)
PARAMETER
t(τ)
( )
USART0: deglitch time
TEST CONDITIONS
VCC = 2.2 V
VCC = 3 V
MIN
NOM
MAX
200
430
800
150
280
500
UNIT
ns
NOTE 1: The signal applied to the USART0 receive signal/terminal (URXD0) should meet the timing requirements of t(τ) to ensure that the URXS
flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t(τ). The operating conditions to
set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on the
URXD0 line.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
JTAG Interface
TEST
CONDITIONS
PARAMETER
fTCK
TCK input frequency
see Note 1
VCC
MIN
2.2 V
3V
RInternal
Internal pull-up resistance on TMS, TCK, TDI/TCLK see Note 2
2.2 V/ 3 V
NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected.
2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.
NOM
MAX
UNIT
0
5
MHz
0
10
MHz
kΩ
25
60
90
VCC
MIN
NOM
MAX
3.6V
5
JTAG Fuse (see Note 1)
TEST
CONDITIONS
PARAMETER
VFB
IFB
Voltage level on TDI/TCLK for fuse-blow
Supply current into TDI/TCLK during fuse blow
UNIT
5.5
V
100
mA
tFB
Time to blow fuse
20
ms
NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched
to bypass mode.
24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
input/output schematic
port P1, P1.0 to P1.7, input/output with Schmitt-trigger
P1SEL.x
0
P1DIR.x
Direction Control
From Module
1
Pad Logic
P1.0/TACLK ..
0
P1OUT.x
Module X OUT
1
P1.7/TA2
P1IN.x
EN
Module X IN
D
P1IRQ.x
P1IE.x
Q
P1IFG.x
EN
Set
Interrupt
Flag
Interrupt
Edge
Select
P1IES.x
P1SEL.x
PnSel.x
PnDIR.x
Dir. CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
PnIE.x
PnIFG.x
PnIES.x
P1Sel.0
P1DIR.0
P1DIR.0
P1OUT.0
DVSS
P1IN.0
P1IE.0
P1IFG.0
P1IES.0
P1IN.1
TACLK†
CCI0A†
P1IE.1
P1IFG.1
P1IES.1
P1IE.2
P1IFG.2
P1IES.2
P1IE.3
P1IFG.3
P1IES.3
P1Sel.1
P1DIR.1
P1DIR.1
P1OUT.1
P1Sel.2
P1DIR.2
P1DIR.2
P1OUT.2
Out0 signal†
Out1 signal†
P1Sel.3
P1DIR.3
P1DIR.3
P1OUT.3
Out2 signal†
P1IN.3
CCI1A†
CCI2A†
P1Sel.4
P1DIR.4
P1DIR.4
P1OUT.4
unused
P1IE.4
P1IFG.4
P1IES.4
P1DIR.5
P1DIR.5
P1OUT.5
P1IN.5
unused
P1IE.5
P1IFG.5
P1IES.5
P1Sel.6
P1DIR.6
P1DIR.6
P1OUT.6
SMCLK
Out0 signal†
Out1 signal†
P1IN.4
P1Sel.5
P1IN.6
unused
P1IE.6
P1IFG.6
P1IES.6
P1Sel.7
P1DIR.7
P1DIR.7
P1OUT.7
Out2 signal†
P1IN.7
unused
P1IE.7
P1IFG.7
P1IES.7
P1IN.2
† Signal from or to Timer_A
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P2, P2.0 to P2.2, P2.6, and P2.7 input/output with Schmitt-trigger
P2SEL.x
0
P2DIR.x
Direction Control
From Module
0: Input
1: Output
1
0
P2OUT.x
Module X OUT
1
P2.0/ACLK
P2.1/TAINCLK
P2.2/CAOUT/TA0
Pad Logic
P2.6
P2.7/TA0
P2IN.x
EN
Module X IN
Bus Keeper
D
P2IE.x
P2IRQ.x
P2IFG.x
Set
Interrupt
Flag
CAPD.X
Interrupt
Edge
Select
EN
Q
P2IES.x
P2SEL.x
x: Bit Identifier 0 to 2, 6, and 7 for Port P2
PnSel.x
PnDIR.x
Dir. CONTROL
FROM MODULE
PnOUT.x
P2Sel.0
P2DIR.0
P2DIR.0
P2Sel.1
P2DIR.1
P2DIR.1
MODULE X OUT
PnIN.x
MODULE X IN
PnIE.x
PnIFG.x
PnIES.x
P2OUT.0
ACLK
P2IN.0
P2IE.0
P2IFG.0
P2IES.0
P2OUT.1
DVSS
P2IN.1
P2IE.1
P2IFG.1
P2IES.1
P2Sel.2
P2DIR.2
P2DIR.2
P2OUT.2
CAOUT†
P2IN.2
unused
INCLK‡
CCI0B‡
P2IE.2
P2IFG.2
P2IES.2
P2Sel.6
P2DIR.6
P2DIR.6
P2OUT.6
DVSS
P2IN.6
unused
P2IE.6
P2IFG.6
P2IES.6
P2Sel.7
P2DIR.7
P2DIR.7
P2OUT.7
Out0 signal§
P2IN.7
unused
P2IE.7
P2IFG.7
P2IES.7
† Signal from Comparator_A
‡ Signal to Timer_A
§ Signal from Timer_A
26
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P2, P2.3 to P2.4, input/output with Schmitt-trigger
P2SEL.3
0: Input
1: Output
0
P2DIR.3
Direction Control
From Module
1
Pad Logic
P2.3/CA0/TA1
0
P2OUT.3
Module X OUT
1
P2IN.3
EN
Module X IN
Bus Keeper
D
P2IRQ.3
P2IE.3
P2IFG.3
EN
Set
Q
Interrupt
Edge
Select
CAPD.3
Comparator_A
Interrupt
Flag
P2IES.3
P2SEL.3
CAREF
CAF
+
CCI1B
To Timer_A3
−
P2SEL.4
P2IES.4
Interrupt
Flag
P2IFG.4
P2IRQ.4
CAEX
P2CA
Set
EN
Q
P2IE.4
CAREF
Reference Block
Edge
Select
Interrupt
CAPD.4
D
Module X IN
Bus Keeper
EN
P2IN.4
Module X OUT
P2OUT.4
From Module
Direction Control
P2DIR.4
1
0
1
P2.4/CA1/TA2
Pad Logic
1: Output
0: Input
0
P2SEL.4
PnSel.x
PnDIR.x
DIRECTION
CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
PnIE.x
PnIFG.x
PnIES.x
P2Sel.3
P2DIR.3
P2DIR.3
P2OUT.3
P2IN.3
unused
P2IE.3
P2IFG.3
P2IES.3
P2Sel.4
P2DIR.4
† Signal from Timer_A
P2DIR.4
P2OUT.4
Out1 signal†
Out2 signal†
P2IN.4
unused
P2IE.4
P2IFG.4
P2IES.4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
27
SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P2, P2.5, input/output with Schmitt-trigger and Rosc function for the basic clock module
0: Input
1: Output
P2SEL.5
0
P2DIR.5
Direction Control
From Module
Pad Logic
1
P2.5/Rosc
0
P2OUT.5
Module X OUT
1
Bus Keeper
P2IN.5
EN
Module X IN
P2IRQ.5
D
P2IE.5
Q
P2IFG.5
EN
Set
Interrupt
Flag
VCC
Edge
Select
Interrupt
Internal to
Basic Clock
Module
0
1
To DC Generator
P2IES.5
P2SEL.5
DCOR
CAPD.5
DCOR: Control Bit From Basic Clock Module
If it Is Set, P2.5 Is Disconnected From P2.5 Pad
PnSel.x
PnDIR.x
DIRECTION
CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
PnIE.x
PnIFG.x
PnIES.x
P2Sel.5
P2DIR.5
P2DIR.5
P2OUT.5
DVSS
P2IN.5
unused
P2IE.5
P2IFG.5
P2IES.5
28
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P3, P3.0 and P3.4 to P3.7, input/output with Schmitt-trigger
P3SEL.x
0: Input
1: Output
0
P3DIR.x
Direction Control
From Module
1
Pad Logic
P3OUT.x
Module X OUT
0
P3.0/STE0
1
P3.4/UTXD0
P3.5/URXD0
P3.6
P3.7
P3IN.x
EN
D
Module X IN
x: Bit Identifier, 0 and 4 to 7 for Port P3
PnSel.x
PnDIR.x
P3Sel.0
P3DIR.0
P3Sel.4
P3DIR.4
P3Sel.5
P3DIR.5
P3Sel.6
P3DIR.6
P3Sel.7
P3DIR.7
DIRECTION
CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
DVSS
DVCC
DVSS
P3OUT.0
DVSS
UTXD0†
P3IN.0
STE0
P3OUT.4
P3IN.4
P3OUT.5
DVSS
P3IN.5
Unused
URXD0‡
DVCC
DVSS
P3OUT.6
DVSS
P3IN.6
Unused
P3OUT.7
DVSS
P3IN.7
Unused
† Output from USART0 module
‡ Input to USART0 module
port P3, P3.1, input/output with Schmitt-trigger
P3SEL.1
SYNC
MM
STC
STE
0
P3DIR.1
0: Input
1: Output
1
DCM_SIMO
Pad Logic
P3.1/SIMO0
0
P3OUT1
(SI)MO0
From USART0
1
P3IN.1
EN
SI(MO)0
To USART0
D
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
29
SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P3, P3.2, input/output with Schmitt-trigger
P3SEL.2
SYNC
MM
STC
STE
0
P3DIR.2
0: Input
1: Output
1
DCM_SOMI
Pad Logic
P3.2/SOMI0
0
P3OUT.2
SO(MI)0
From USART0
1
P3IN.2
EN
(SO)MI0
To USART0
D
port P3, P3.3, input/output with Schmitt-trigger
P3SEL.3
SYNC
MM
STC
STE
0
P3DIR.3
0: Input
1: Output
1
DCM_UCLK
Pad Logic
P3.3/UCLK0
0
P3OUT.3
UCLK.0
From USART0
1
P3IN.3
EN
UCLK0
D
To USART0
NOTE: UART mode:
The UART clock can only be an input. If UART mode and UART function are selected, the P3.3/UCLK0 is always
an input.
SPI, slave mode:
The clock applied to UCLK0 is used to shift data in and out.
SPI, master mode: The clock to shift data in and out is supplied to connected devices on pin P3.3/UCLK0 (in slave mode).
30
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P4, P4.0 to P4.6, input/output with Schmitt-trigger
P4SEL.x
0
P4DIR.x
Direction Control
From Module
TBOUTHiZ
0: Input
1: Output
1
Pad Logic
0
P4OUT.x
Module X OUT
1
P4.0/TB0
P4.1/TB1
P4.2/TB2
P4.3
P4.4
P4.5
P4.6
Bus Keeper
P4IN.x
EN
Module X IN
D
x: bit identifier, 0 to 6 for Port P4
PnSel.x
PnDIR.x
DIRECTION
CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
P4Sel.0
P4DIR.0
P4DIR.0
P4OUT.0
P4IN.0
P4Sel.1
P4DIR.1
P4DIR.1
P4OUT.1
Out0 signal†
Out1 signal†
P4IN.1
CCI0A / CCI0B‡
CCI1A / CCI1B‡
P4Sel.2
P4DIR.2
P4DIR.2
P4OUT.2
Out2 signal†
P4IN.2
CCI2A / CCI2B‡
P4Sel.3
P4DIR.3
P4DIR.3
P4OUT.3
DVSS
P4IN.3
Unused
P4Sel.4
P4DIR.4
P4DIR.4
P4OUT.4
DVSS
P4IN.4
Unused
P4Sel.5
P4DIR.5
P4DIR.5
P4OUT.5
DVSS
P4IN.5
Unused
P4Sel.6
P4DIR.6
P4DIR.6
P4OUT.6
DVSS
P4IN.6
Unused
† Signal from Timer_B
‡ Signal to Timer_B
NOTE: TBoutHiZ signal is used by port module P4, pins P4.0 to P4.6. The function TBoutHiZ is mainly used with Timer_B. Port pins P4.3 to P4.6
have the TBoutHiZ function, but no Timer_B output is available for secondary functions. The port selection function can be used to get
the port pin to high impedance and to use the P4DIR.x bits.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
31
SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P4, P4.7, input/output with Schmitt-trigger
P4SEL.7
0: Input
1: Output
0
P4DIR.7
1
Pad Logic
P4.7/TBCLK
0
P4OUT.7
DVSS
1
P4IN.7
EN
Timer_B,
D
TBCLK
port P5, P5.0 to P5.7, input/output with Schmitt-trigger
P5SEL.x
0: Input
1: Output
0
P5DIR.x
Direction Control
From Module
1
Pad Logic
0
P5OUT.x
Module X OUT
1
P5.0
P5.1
P5.2
P5.3
P5.4/MCLK
P5IN.x
P5.5/SMCLK
EN
Module X IN
P5.6/ACLK/
TBOUTH
D
x: Bit Identifier, 0 to 7 for Port P5
PnSel.x
PnDIR.x
Dir. CONTROL FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
P5Sel.0
P5DIR.0
P5OUT.0
DVSS
P5IN.0
unused
P5Sel.1
P5DIR.1
DVSS
DVCC
P5OUT.1
DVSS
P5IN.1
unused
P5Sel.2
P5DIR.2
DVSS
P5IN.2
unused
P5DIR.3
DVCC
DVCC
P5OUT.2
P5Sel.3
P5OUT.3
DVSS
P5IN.3
unused
P5Sel.4
P5DIR.4
MCLK
P5IN.4
unused
P5DIR.5
DVCC
DVCC
P5OUT.4
P5Sel.5
P5OUT.5
SMCLK
P5IN.5
unused
P5Sel.6
P5DIR.6
DVCC
DVSS
P5OUT.6
ACLK
P5IN.6
unused
P5Sel.7
P5DIR.7
P5OUT.7
DVSS
P5IN.7
TBOUTHiZ
NOTE: TBOUTHiZ signal is used by port module P4, pins P4.0 to P4.6. The function of TBOUTHiZ is mainly useful when used with Timer_B.
32
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
input/output schematic (continued)
port P6, P6.0 to P6.7, input/output with Schmitt-trigger
P6SEL.x
0
P6DIR.x
Direction Control
From Module
0: Input
1: Output
1
Pad Logic
P6.0 .. P6.7
0
P6OUT.x
Module X OUT
1
Bus Keeper
P6IN.x
EN
Module X IN
D
x: Bit Identifier, 0 to 7 for Port P6
PnSel.x
PnDIR.x
DIR. CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
P6Sel.0
P6DIR.0
P6DIR.0
P6OUT.0
DVSS
P6IN.0
unused
P6Sel.1
P6DIR.1
P6DIR.1
P6OUT.1
DVSS
P6IN.1
unused
P6Sel.2
P6DIR.2
P6DIR.2
P6OUT.2
DVSS
P6IN.2
unused
P6Sel.3
P6DIR.3
P6DIR.3
P6OUT.3
DVSS
P6IN.3
unused
P6Sel.4
P6DIR.4
P6DIR.4
P6OUT.4
DVSS
P6IN.4
unused
P6Sel.5
P6DIR.5
P6DIR.5
P6OUT.5
DVSS
P6IN.5
unused
P6Sel.6
P6DIR.6
P6DIR.6
P6OUT.6
DVSS
P6IN.6
unused
P6Sel.7
P6DIR.7
P6DIR.7
P6OUT.7
DVSS
P6IN.7
unused
NOTE: Direction control bits P6DIR.x and P6SEL.x control whether the port function is active (P6DIR.x=0) or whether the input P6.x is in the
high-impedance state. This is identical to the port P6 function in the MSP430F13x devices (used for emulation/prototyping), but different
from other digital-only ports such as P5.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
33
SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
JTAG pins TMS, TCK, TDI, TDO/TDI, input/output with Schmitt-trigger
TDO
Controlled by JTAG
Controlled by JTAG
JTAG
TDO/TDI
Controlled
by JTAG
DVCC
TDI
Fuse
Burn & Test
Fuse
TDI/TCLK
Test
and
Emulation
Module
DVCC
TMS
TMS
DVCC
During Blowing of the Fuse, Pin
TDO/TDI Is Used to Apply the Test
Input Data for JTAG Circuitry
TCK
TCK
JTAG fuse check mode
MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity
of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, ITF , of 1 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be
taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see
Figure 13). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
Time TMS Goes Low After POR
TMS
ITDI/TCLK
ITF
Figure 13. Fuse Check Mode Current
34
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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