TPS2490 TPS2491 Actual Size 3,0 mm X 4,88 mm www.ti.com SLVS503 – NOVEMBER 2003 POSITIVE HIGH-VOLTAGE POWER-LIMITING HOTSWAP CONTROLLER FEATURES APPLICATIONS • • • • • • • • • • • • • Programmable Power Limiting and Current Limiting for Complete SOA Protection Wide Operating Range: +9 V to +80 V Latched Operation (TPS2490) and Automatic Retry (TPS2491) High-side Drive for Low-RDS(on) External N-channel MOSFET Programmable Fault Timer to Protect the MOSFET and Eliminate Nuisance Shutdowns Power Good Open-Drain Output for Downstream DC/DC Coordination Enable can be used as a Programmable Undervoltage Lockout or Logic Control Small, Space-saving 10-pin MSOP Package Server Backplanes Storage Area Networks (SAN) Medical Systems Plug-in Modules Base Stations DGS Package (Top View) EN VREF PROG TIMER GND 1 10 2 9 3 8 4 7 5 6 VCC SENSE GATE OUT PG DESCRIPTION The TPS2490 and TPS2491 are easy-to-use, positive high voltage, 10-pin Hot Swap Power Manager™ devices that safely drive an external N-channel MOSFET switch. The power limit and current limit (both are adjustable and independent of each other) ensure that the external MOSFET operates inside a selected safe operating area (SOA) under the harshest operating conditions. Applications include inrush current limiting, electronic circuit breaker protection, controlled load turn-on, interfacing to down-stream dc-to-dc converters, and power feed protection. These devices are available in a small, space-saving 10-pin MSOP package and significantly reduce the number of external devices, saving precious board space. The TPS2490/91 is supported by application notes, an evaluation module, and a design tool. Typical Application and Corresponding SOA M1 IRF540NS RS VI = 48 Vdc 0.01 Ω C1 0.1 µF D1 SMAJ60A VO at 4 A R6 470 kΩ R5 10 Ω R1 324 kΩ 10 VCC 9 8 7 SENSE GATE OUT 1 EN R2 13.3 kΩ 6 Power Good PG TPS2490/91 2 VREF R3 41.2 kΩ PROG 3 ILIM = 5 A, VON/VOFF = 34.2 V/31.7 V, PLIM = 34 W, Timeout = 16 mS GND TIMER 5 4 R4 8.25 kΩ CT 0.1 µF CO 220 µF Programmed SOA, 16mS Hot Swap Power Manager is a trademark of Texas Instruments. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002–2003, Texas Instruments Incorporated TPS2490 TPS2491 www.ti.com SLVS503 – NOVEMBER 2003 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION TA -40°C to 85°C (1) FUNCTION PACKAGE PART NUMBER (1) Latched VSSOP-10 TPS2490DGS BIY Retry (MSOP) TPS2491DGS BIX SYMBOL Add an R suffix to the device type for tape and reel packaging. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) UNIT Input voltage range, VCC, SENSE, EN, OUT -0.3 to 100 V Output voltage range, GATE, PG -0.3 to 100 V Input voltage range, PROG -0.3 to 6 V Output voltage range, TIMER, VREF -0.3 to 6 V Sink current, PG 10 mA Source current, VREF 0 to 2 mA Sink Current, PROG 2 mA ESD - human body model 2 kV ESD - charged device model 500 V Maximum junction temperature, TJ 150 °C Storage temperature, TST –65 to 150 °C Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds 260 °C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT VVCC Input voltage range 9 80 V VPROG Input voltage range 0 4 V IVREF Operating current range (sourcing), VREF 0 1 mA TJ Operating junction temperature -40 125 °C TA Operating free-air temperature -40 85 °C DISSIPATION RATING TABLE 2 PACKAGE TA <25°C POWER RATING mW DERATING FACTOR ABOVE TA= 25°C (mW/°C) TA = 70°C POWER RATING (mW) TA = 85°C POWER RATING (mW) VSSOP-10 (MSOP) 376 3.76 207 150 TPS2490 TPS2491 www.ti.com SLVS503 – NOVEMBER 2003 ELECTRICAL CHARACTERISTICS unless otherwise noted, minimum and maximum limits apply across the recommended operating junction temperature and voltage range, VTIMER = 0 V, and all outputs unloaded; typical specifications are at TJ = 25°C, VVCC = 48 V, VTIMER = 0 V, and all outputs unloaded; positive currents are into pins. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT (VCC) Enabled VEN = Hi, VSENSE = VOUT = VVCC 450 1000 µA Disabled VEN = Lo, VSENSE = VVCC = VOUT = 0 90 250 µA VSENSE = VVCC, VOUT = VVCC 7.5 20 µA 4 4.1 V 5 µA 375 600 Ω CURRENT SENSE INPUT (SENSE) ISENSE Input bias current REFERENCE VOLTAGE OUTPUT (VREF) VREF Reference voltage 0 < IVREF < 1 mA 3.9 POWER LIMITING INPUT (PROG) IPROG Input bias current, device enabled, sourcing or sinking 0 < VPROG < 4 V, VEN = 48 V RPROG Pulldown resistance, device disabled IPROG = 200 µA, VEN = 0 V POWER LIMITING AND CURRENT LIMITING (SENSE) VCL Current sense threshold V(VCC-SENSE) with power limiting trip VPROG = 2.4 V, VOUT = 0 V or VPROG = 0.9 V, VOUT = 30 V, VVCC = 48 V 17 25 33 mV VSENSE Current sense threshold V(VCC-sense) without power limiting trip VPROG = 4 V, VSENSE = VOUT 45 50 55 mV tF_TRIP Large overload response time to GATE low (1) VPROG = 4 V, VOUT = VSENSE, V(VCC-SENSE): 0 → 200 mV, C(GATE-OUT) = 2 nF, V(GATE-OUT) = 1 V 1.2 µS 34.0 µA TIMER OPERATION (TIMER) Charge current (sourcing) Discharge current (sinking) VTIMER = 0 V 15.0 25.0 VTIMER = 0 V, TJ = 25°C 20.0 25.0 30.0 µA VTIMER = 5 V 1.50 2.5 3.70 µA VTIMER = 5 V, TJ = 25°C 2.10 2.5 3.10 µA 3.9 4 4.1 V 0.96 1.0 1.04 V 0.5% 0.75% 1.0% TIMER upper threshold voltage DRETRY TIMER lower reset threshold voltage TPS2491 only Fault retry duty cycle TPS2491 only GATE DRIVE OUTPUT (GATE) IGATE GATE sourcing current GATE sinking current VSENSE = VVCC, V(GATE-OUT) = 7 V, VEN = Hi 15 VEN = Lo, VGATE = VVCC 1.8 VEN = Hi, VGATE = VVCC, V(VCC-SENSE)≥ 200 mV 75 GATE output voltage, V(GATE-OUT) 22 35 µA 2.4 2.8 mA 125 250 mA 16 V 12 tD_ON Propagation delay: EN going true to GATE output high (1) VEN = 0 → 2.5 V, 50% of VEN to 50% of VGATE, VOUT = VVCC, R(GATE-OUT)= 1 MΩ 25 40 µS tD_OFF Propagation delay: EN going false (0 V) to GATE output low (1) VEN = 2.5 V → 0, 50% of VEN to 50% of VGATE, VOUT = VVCC, R(GATE-OUT)= 1 MΩ, tFALL < 0.1 µS 0.5 1 µS Propagation delay: TIMER expires to GATE output low (1) VTIMER: 0 → 5 V, tRISE < 0.1 µS, 50% of VTIMER to 50% of VGATE, VOUT = VVCC, R(GATE-OUT) = 1 MΩ, 0.8 1 µS IPG = 2 mA 0.1 0.25 V IPG = 4 mA 0.25 0.5 V 1.25 1.7 V POWER GOOD OUTPUT (PG) VPG_L Low voltage (sinking) VPGTL PG threshold voltage, VOUT rising, PG goes open drain (1) VSENSE = VVCC, measure V(VCC-OUT) 0.8 Not tested in production. 3 TPS2490 TPS2491 www.ti.com SLVS503 – NOVEMBER 2003 ELECTRICAL CHARACTERISTICS (continued) unless otherwise noted, minimum and maximum limits apply across the recommended operating junction temperature and voltage range, VTIMER = 0 V, and all outputs unloaded; typical specifications are at TJ = 25°C, VVCC = 48 V, VTIMER = 0 V, and all outputs unloaded; positive currents are into pins. PARAMETER TEST CONDITIONS VPGTH PG threshold voltage, VOUT falling, PG goes low VSENSE = VVCC, measure V(VCC-OUT) ∆VPGT PG threshold hysteresis voltage, V(SENSE-OUT) VSENSE = VVCC tDPG PG deglitch delay, detection to output, rising and falling edges (2) VSENSE = VVCC MIN TYP MAX 2.2 2.7 3.2 1.4 5 9 UNIT V V 15 ms 10 µA 8 20 µA 18 40 µA V Leakage current, PG false, open drain OUTPUT VOLTAGE FEEDBACK INPUT (OUT) IOUT Bias current VOUT = VVCC, VEN = Hi, sinking VOUT = GND, VEN = Lo, sourcing ENABLE INPUT (EN) VEN_H Threshold, VEN going high 1.32 1.35 1.38 VEN_L Threshold, VEN going low 1.22 1.25 1.28 VEN hysteresis (2) Leakage current 100 VEN = 48 V V mV 1 µA 8.8 V INPUT SUPPLY UVLO (VCC) VVCC turn on Rising VVCC turn off Falling Hysteresis (2) (2) 4 Not tested in production. 8.4 7.5 8.3 V 75 mV TPS2490 TPS2491 www.ti.com SLVS503 – NOVEMBER 2003 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs SUPPLY VOLTAGE CURRENT LIMIT TRIP vs SUPPLY VOLTAGE 600 55 I VCC− Supply Current − A − Current Limit Trip − mV V( VCC − Sense) TJ = 125C 550 500 TJ = 25C 450 400 TJ = −40C 350 300 250 200 53 52 TJ = −40C 51 50 TJ = 25C 49 48 TJ = 125C 47 46 45 9 19 29 39 49 59 VCC − Supply Voltage − V 69 79 9 19 29 39 49 59 VCC − Supply Voltage − V 69 Figure 1. Figure 2. GATE PULLUP CURRENT vs SUPPLY VOLTAGE GATE PULLDOWN CURRENT(EN = 0 V) vs SUPPLY VOLTAGE 79 2.6 I Gate − Gate Pullup Current (EN = OV) − mA 35 33 I Gate − Gate Pullup Current − A 54 31 29 27 TJ = 125C 25 23 TJ = 25C 21 19 TJ = −40C 17 TJ = 125C 2.5 TJ = 25C 2.4 2.3 TJ = −40C 2.2 2.1 2 15 9 19 29 39 49 59 VCC − Supply Voltage − V Figure 3. 69 79 9 19 29 39 49 59 69 79 VCC − Supply Voltage − V Figure 4. 5 TPS2490 TPS2491 www.ti.com SLVS503 – NOVEMBER 2003 TYPICAL CHARACTERISTICS (continued) GATE PULLDOWN CURRENT vs SUPPLY VOLTAGE (EN = 4 V, V(vcc – sense) = 200 mV) CURRENT LIMIT RESPONSE TIME vs SUPPLY VOLTAGE (EN = 4 V, V(vcc – sense) = 200 mV) 215 1200 195 T − Current Limit Response Time − nS I Gate − Gate Pulldown Current − mA TJ = 125C TJ = −40C 175 TJ = 25C 155 135 TJ = 125C 115 95 75 9 19 29 39 49 59 VCC − Supply Voltage − V 69 1000 TJ = 25C 800 600 TJ = −40C 400 200 0 79 9 14 19 24 29 34 39 VCC − Supply Voltage − V Figure 5. Figure 6. GATE OUTPUT VOLTAGE vs SUPPLY VOLTAGE TIMER PULLUP CURRENT vs SUPPLY VOLTAGE 44 49 14.50 32 TJ = 125C I Timer − Timer Pullup Current − µ A VGate − Gate Output Voltage − V TJ = 125C 14.25 TJ = 25C 14 TJ = −40C 13.75 28 TJ = 25C 26 24 TJ = −40C 22 20 18 13.50 9 19 29 39 49 59 VCC − Supply Voltage − V Figure 7. 6 30 69 79 9 19 29 39 49 59 VCC − Supply Voltage − V Figure 8. 69 79 TPS2490 TPS2491 www.ti.com SLVS503 – NOVEMBER 2003 TYPICAL CHARACTERISTICS (continued) TIMER CHARGE/DISCHARGE RATIO vs SUPPLY VOLTAGE AND TEMPERATURE EN THRESHOLD VOLTAGE (FALLING) vs SUPPLY VOLTAGE VEN − EN Threshold Voltage (Falling) − V 1.255 9.75 TJ = 25C TJ = −40C 9.70 TJ = 125C 9.65 1.254 1.253 1.252 TJ = 125C 1.251 TJ = 25C 1.250 1.249 TJ = −40C 1.248 1.247 1.246 9.60 9 19 29 39 49 59 VCC − Supply Voltage − V 69 1.245 79 9 19 29 39 49 59 VCC − Supply Voltage − V Figure 9. 69 79 Figure 10. EN THRESHOLD VOLTAGE (RISING) vs SUPPLY VOLTAGE 1.351 VEN − EN Threshold Voltage (Rising) − V ITimer − Charge/Discharge Ratio 9.80 TJ = 125C 1.350 TJ = 25C 1.349 1.348 TJ = −40C 1.347 1.346 1.345 9 19 29 39 49 59 VCC − Supply Voltage − V 69 79 Figure 11. 7 TPS2490 TPS2491 www.ti.com SLVS503 – NOVEMBER 2003 FUNCTIONAL BLOCK DIAGRAM 4V Reference 10 VCC Enable 2 VREF Charge Pump Constant Power Engine 22 A A 3 PROG 50 mV max A 2B V (DS) Detector + Gate Control Amplifier + _ 8 GATE B 14 V − 2 mA I (D) Detector + Power/Current Amplifier − 9 SENSE 2.25 V and 1.25 V 8.4 V and 8.3 V 1 EN 1.35 V and 1.25 V Inrush Complete + _ + _ 7 OUT 6 PG 9 mS Deglitch Enable 25 A Fault Logic UVLO 4V and 1V + _ Enable + _ Timer 2.5 A POR For Autoretry Opion with Duty Cycle of 0.75% 5 GND 4 TIMER TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION EN 1 I Device enable VREF 2 O Reference voltage output, used to set power threshold on PROG pin PROG 3 I TIMER 4 I/O GND 5 PG 6 O Power good reporting output, open-drain OUT 7 I Output voltage feedback GATE 8 O Gate output SENSE 9 I Current-limit sense input VCC 10 I Supply input 8 Power-limit setting input Fault timing capacitor Ground www.ti.com TPS2490 TPS2491 SLVS503 – NOVEMBER 2003 DETAILED PIN DESCRIPTION The following description relies on the typical application diagram shown on page 1, and the functional block diagram. VCC: This pin is associated with three functions: 1) biasing power to the integrated circuit, 2) input to power on reset (POR) and under voltage lockout (UVLO) functions, and 3) voltage sense at one terminal of RS for M1 current measurement. The voltage must exceed the POR (about 6 V for roughly 400µ S) and the internal UVLO (about 8 V) before normal operation (driving the GATE) may begin. Connections to VCC should be designed to minimize RS voltage sensing errors and to maximize the effect of C1 and D1; place C1 at RS rather than at the IC pin to eliminate transient sensing errors. GATE, PROG, PG, and TIMER are held low when either UVLO or POR are active. SENSE: Monitors the voltage at the drain of M1, and the downstream side of RS providing the constant power limit engine with feedback of both M1 current (ID) and voltage (VDS). Voltage is determined by the difference between SENSE and OUT, while the current analog is the difference between VCC and SENSE. The constant power engine uses VDS to compute the allowed ID and is clamped to 50 mV, acting like a traditional current limit at low VDS. The current limit is set by the following equation: I LIM 50 mV RS Design the connections to SENSE to minimize RS voltage sensing errors. Don’t drive SENSE to a large voltage difference from VCC because it is internally clamped to VCC. The current limit function can be disabled by connecting SENSE to VCC. GATE: Provides the high side (above VCC) gate drive for M1. It is controlled by the internal gate drive amplifier, which provides a pull-up of 22 µA from an internal charge pump and a strong pull-down to ground of 75 mA (min). The pull-down current is a non-linear function of the amplifier overdrive; it provides small drive for small overloads, but large overdrive for fast reaction to an output short. There is a separate pull-down of 2 mA to shut M1 off when EN or the UVLO cause this to happen. An internal clamp protects the gate of M1 (to OUT) and generally eliminates the need for an external clamp in almost all cases for devices with 20 V VGS(MAX) ratings; an external Zener may be required to protect the gate of devices with VGS(MAX) < 16 V. A small series resistance (R5) of 10 Ω should be inserted in the gate lead if the CISSof M1 > 200 pF, otherwise use 33 Ω for small MOSFETs. A capacitor can be connected from GATE to ground to create a slower inrush with a constant current profile without affecting the amplifier stability. Add a series resistor of about 1 kΩ to the gate capacitor to maintain the gate clamping and current limit response time. OUT: This input pin is used by the constant power engine and the PG comparator to measure VDS of M1 as V(VCC–SENSE). Internal protection circuits leak a small current from this pin when it is low. If the load circuit can drive OUT below ground, connect a clamp (or freewheel) diode such as an S1B from OUT (cathode) to GND (anode). EN: The GATE driver is enabled if the positive threshold is exceeded and the internal POR and UVLO thresholds have been satisfied. EN can be used as a logic control input, an analog input voltage monitor as illustrated by R1/R2 in the typical application circuit on page 1, or it can be tied to VCC to always enable the TPS2490/91. The hysteresis associated with the internal comparator makes this a stable method of detecting a low input condition and shutting the downstream circuits off. A TPS2490 that has latched off can be reset by cycling EN below its negative threshold and back high. VREF: Provides a 4.0-V reference voltage for use in conjunction with R3/R4 of the typical application circuit to set the voltage on the PROG pin. The reference voltage is available once the internal POR and UVLO thresholds have been met. It is not designed as a supply voltage for other circuitry, therefore ensure that no more than 1 mA is drawn. Bypass capacitance is not required, but if a special application requires one, less than 1000 pF can be placed on this pin. PROG: The voltage applied to this pin (0–4 V) programs the power limit used by the constant power engine. Normally, a resistor divider R3/R4 is connected from VREF to PROG to set the power limit according to the following equation: 9 TPS2490 TPS2491 SLVS503 – NOVEMBER 2003 V PROG www.ti.com P LIM 10 I LIM where PLIM is the desired power limit of M1 and ILIM is the current limit setpoint (see SENSE). PLIM is determined by the desired thermal stress on M1: T J(MAX) T S(MAX) P LIM R JC(MAX) where TJ(MAX) is the maximum desired transient junction temperature of M1 and TS(MAX) is the maximum case temperature prior to a start or restart. VPROG is used in conjunction with VDS to compute the (scaled) current, ID_ALLOWED, by the constant power engine. ID_ALLOWED is compared by the gate amplifier to the actual ID, and used to generate a gate drive. If ID < ID_ALLOWED, the amplifier turns the gate of M1 full on because there is no overload condition; otherwise GATE is regulated to maintain the ID = ID_ALLOWED relationship. A capacitor may be tied from PROG to ground to alter the natural constant power inrush current shape. If properly designed, the effect is to cause the leading step of current in Figure 12 to look like a ramp. PROG is internally pulled to ground whenever EN, POR, or UVLO are not satisfied or the TPS2490 is latched off. This feature serves to discharge any capacitance connected to the pin. Do not apply voltages greater than 4 V to PROG. If the constant power limit is not used, PROG should be tied to VREF through a 47-kΩ resistor. TIMER: An integrating capacitor, CT, connected to the TIMER pin provides a timing function that controls the fault-time for both versions and the restart interval for the TPS2491. The timer charges at 25 µA whenever the TPS2490/91 is in power limit or current limit and discharges at 2.5 µA otherwise. The charge-to-discharge current ratio is constant with temperature even though there is a positive temperature coefficient to both. If TIMER reaches 4 V, the TPS2490 pulls GATE to ground, latch off, and discharge CT. The TPS2491 pulls GATE to ground and attempt a restart (re-enable GATE) after a timing sequence consisting of discharging CT down to 1 V followed by 15 more charge and discharge cycles. The TPS2490 can be reset by either cycling the EN pin or the UVLO (e.g. power cycling). TIMER discharges when EN is low or UVLO or POR are active. The TIMER pin should be tied to ground if this feature is not used. PG: This open-drain output is intended to interface to downstream dc/dc converters or monitoring circuits. PG goes open-drain (high voltage with a pull-up) after VDS of M1 has fallen to about 1.25 V and a 9 ms deglitch time period has elapsed. PG is false (low or low resistance to ground) whenever EN is false, VDS of M1 is above 2.5 V, or UVLO is active. PG can also be viewed as having an input and output voltage monitor function. The 9-ms deglitch circuit operates to filter short events that could cause PG to go inactive (low) such as a momentary overload or input voltage step. VPG voltage can be greater than VVCC because it’s ESD protection is only with respect to ground. GND: This pin is connected to system ground. 10 TPS2490 TPS2491 www.ti.com SLVS503 – NOVEMBER 2003 APPLICATION INFORMATION BASIC OPERATION The TPS2490/91 provides all the features needed for a positive hotswap controller. These features include: 1) under-voltage lockout; 2) adjustable (system-level) enable; 3) turn-on inrush limit; 4) high-side gate drive for an external N-channel MOSFET; 5) MOSFET protection (power limit and current limit); 6) adjustable overload timeout—also called an electronic circuit breaker; 7) charge-complete indicator for downstream converter coordination; and 8) an optional automatic restart mode. The TPS2490/91 features superior power-limiting MOSFET protection that allows independent control of current limit (to set maximum full-load current), power limit (to control junction temperature rise), and overload time (to control case temperature rise). The typical application circuit, and oscilloscope plots of Figures 12–16 demonstrate many of the functions described above. Board Plug-In (Figure 12) Only the bypass capacitor charge current and small bias currents are evident when a board is first plugged in. The TPS2490/91 is held inactive, and GATE, PROG, TIMER, and PG are held low for less than 1 ms while internal voltages stabilize. A startup cycle is ready to take place after the stabilization. GATE, PROG, TIMER, and PG are released after stabilization in this example because both the internal UVLO threshold and the external EN (enable) thresholds have been exceeded. The part begins sourcing current from the GATE pin and M1 begins to turn on while the voltage across it, V(SENSE–OUT), and current through it, V(VCC–SENSE), are monitored. Current initially rises to the value which satisfies the power limit engine (PLIM÷ VVCC) since the output capacitor was discharged. TIMER and PG Operation (Figure 12) The TIMER pin charges CT as long as limiting action continues, and discharges at a 1/10 charge rate when limiting stops. If the voltage on CT reaches 4 V before the output is charged, M1 is turned off and either a latch-off or restart cycle commences, depending on the part type. The open-drain PG output provides a deglitched end-of-charge indication which is based on the voltage across M1. PG is useful for preventing a downstream dc/dc converter from starting while CO is still charging. PG goes active (open drain) about 9 ms after CO is charged. This delay allows M1 to fully turn on and any transients in the power circuits to end before the converter starts up. The resistor pull-up shown on pin PG in the typical application diagram only demonstrates operation; the actual connection to the converter depends on the application. Timing can appear to terminate early in some designs if operation transitions out of the power limit mode into a gate charge limited mode at low VDS values. VCC VCC CH1 10 V/div PG 10 V/div IIN 1 A/div Timer 1 V/div OUT 10 V/div Figure 12. Basic Board Insertion 11 TPS2490 TPS2491 www.ti.com SLVS503 – NOVEMBER 2003 APPLICATION INFORMATION (continued) Action of the Constant Power Engine (Figure 13) The calculated power dissipated in M1, VDS × ID, is computed under the same startup conditions as Figure 12. The current of M1, labeled IIN, initially rises to the value that satisfies the constant power engine; in this case it is 34 W ÷ 48 V = 0.7 A. The 34 W value is programmed into the engine by setting the PROG voltage using the equation given in the PROG pin description. VDSof M1, which is calculated as V(VCC–OUT) , falls as CO charges, thus allowing the M1 drain current to increase. This is the result of the internal constant power engine adjusting the current limit reference to the GATE amplifier as CO charges and VDS falls. The calculated device power in Figure 13, labeled FET PWR, is seen to be flat-topped and constant within the limitations of circuit tolerance and acquisition noise. A fixed current limit is implemented by clamping the constant power engine’s output to 50 mV when VDS is low. This protection technique can be viewed as a specialized form of foldback limiting; the benefit over linear foldback is that it yields the maximum output current from a device over the full range of VDS and still protects the device. VCC − OUT 10 V/div FET PWR 10 W/div VOUT 10 V/div IIN 1 A/div M1 Power Measured 29.6 W, Calculated 34.4 W Figure 13. Computation of M1 Stress During Startup Response to a Hard Output Short (Figure 14 and Figure 15) Figure 14 shows the short circuit response over the full time-out period that begins when the output voltage falls and ends when M1 is turned off. M1 current is actively controlled by the power limiting engine and gate amplifier circuit while the TIMER pin charges CT to the 4 V threshold that causes M1 to be turned off. The TPS2490 latches off after the threshold is reached until either the input voltage drops below the UVLO threshold or EN cycles through the false (low) state. The TPS2491 goes through a timing sequence before attempting a restart. 12 TPS2490 TPS2491 www.ti.com SLVS503 – NOVEMBER 2003 APPLICATION INFORMATION (continued) IIN 5 A/div TIMER 1 V/div GATE 10 V/div OUT 10 V/div Figure 14. Current Limit Overview The TPS2490/91 responds rapidly to the short circuit as seen in Figure 15. The falling OUT voltage is the result of M1 and CO currents through the short’s impedance at this time scale. The internal GATE clamp causes the GATE voltage to follow the output voltage down and subsequently limits the negative VDS to 1–2 V. The rapidly rising fault current overdrives the GATE amplifier causing it to overshoot and rapidly turn M1 off by sinking current to ground. M1 slowly turns back on as the GATE amplifier recovers; M1 then settles to an equilibrium operating point determined by the power limiting circuit. GATE 10 V/div VCC 10 V/div OUT 10 V/div IIN 5A/div Figure 15. Current Limit Onset Minimal input voltage overshoot appears in Figure 15 because a local 100-µF bypass capacitor and very short input leads were used. The input voltage would overshoot as the input current abruptly drops in a typical application due to the stored energy in the input distribution’s inductance. The exact waveforms seen in an application depend upon many factors including parasitics of the voltage distribution, circuit layout, and the short itself. 13 TPS2490 TPS2491 www.ti.com SLVS503 – NOVEMBER 2003 APPLICATION INFORMATION (continued) Automatic Restart (Figure 16) The TPS2491 automatically initiates a restart after a fault has caused it to turn off M1. Internal control circuits use CT to count 16 cycles before re-enabling M1. This sequence continues to repeat if the fault persists. The TIMER has a 1:10 charge-to-discharge current ratio, and uses a 1-V lower threshold. The fault-retry duty cycle specification quantifies this behavior. This small duty cycle often reduces the average short-circuit power dissipation to levels associated with normal operation and eliminates special thermal considerations for surviving a prolonged output short. GATE 10 V/div OUT 10 V/div TIMER 1 V/div IIN .5 A/div Figure 16. TPS2491 Restart Cycle Timing DESIGN PROCEDURE This design procedure seeks to control the junction temperature of M1 under both static and transient conditions by selecting the device’s package, cooling, RDSON, current limit, fault timeout, and power limit. The following procedure assumes that a unit running at full load and maximum ambient temperature experiences a brief input power interruption sufficient to discharge CO, but short enough to keep M1 from cooling. A full CO recharge then takes place. Adjust this procedure to fit your application and design criteria. This procedure assumes that CO is the only load during inrush. Only simple first-order thermal models, natural convection and a large PCB pad for M1 are assumed. The assumptions build generous safety margins into the design to allow for the inherent inaccuracies of the models and variations of real-world conditions. Other tools and applications information are available on the TI website that supplement the following procedure. STEP 1. Choose RS Given the maximum operating current, IMAX, compute the current sense resistance, RS. 0.05 RS 1.2 I MAX This equation allows for minimum current limit, a sense resistor tolerance of 5%, and 5% margin. Round the result down to the nearest available standard value. STEP 2. Choose M1 First select a VDS rating that allows for the maximum input voltage and transients. Next select an operating RDSON, package, and cooling to control operating temperature. The following equation computes the value of RDSON(MAX)at a junction temperature of TJ(MAX). Most manufacturers list RDSON(MAX) at 25°C and provide a derating curve from which values at other temperatures can be derived. Compute the maximum allowable on-resistance, RDSon(MAX), using the equation: 14 TPS2490 TPS2491 www.ti.com SLVS503 – NOVEMBER 2003 APPLICATION INFORMATION (continued) R DSON(MAX) T J(MAX) T A(MAX) R JA I 2 MAX where TJ(MAX) is the desired maximum steady-state junction temperature (typically 125°C), and TA(MAX) is the maximum ambient temperature. RθJA, the junction-to-ambient thermal resistance, depends upon the package style chosen and the details of heat-sinking and cooling. Note the RθJC and RθJA for use below. STEP 3. Choose PLIM, R3, R4 M1 dissipates large amounts of power during power-up or output short circuit. The power limit PLIM of the TPS2940/91 should be set to prevent the die temperature from exceeding a short term maximum temperature, TJ(MAX)2. The short-term TJ(MAX)2 could be set as high as 150°C while still leaving ample margin to the usual manufacturer’s rating of 175°C. An expression for calculating PLIM is: T J(MAX)2 P LIM 0.7 I 2MAX RDSON RCA TA(MAX) RJC where RθJC is M1 junction-to-case thermal resistance, RDSON is the channel resistance at the maximum operating temperature, and the factor of 0.7 represents the tolerance of the constant power engine. Next calculate VPROG and the divider resistors R3 and R4. R3 must be greater than 4 kΩ, but it is recommended that 10 kΩ or greater be used. P LIM V PROG where I LIM 0.05 10 I LIM RS V R4 PROG VREF R3 R4 STEP 4. Choose tON, CT The on-time, tON, set by capacitor CT must suffice to fully charge the load capacitance CO without triggering the fault circuitry. Assuming that only the load capacitance draws current during startup: C O P LIM t ON 2 I2 LIM C O C O V 2VCC(MAX) 2 PLIM V VCC(MAX) I LIM if P LIM I LIMV VCC(MAX) if PLIM I LIM V VCC(MAX) Using this value of tON, CTis computed as: C T 8.5 10 6 t ON 1 COUT_TOL C T_TOL where CT_TOL and COUT_TOL are the tolerances associated with each capacitor. Assuming CO is a 20% tolerance part, COUT_TOL has a value of 0.2. This expression assures the worst case set of parts will always start. STEP 5. Choose The Turn On Voltage, R1 & R2 Assuming that EN is used as an analog input, the turn-on voltage, VON and turn-off voltage, VOFF are defined as: V ON 1.35 V VOFF 1.25 V R2 R2 R1R2 R1R2 Use caution in selecting very large values of R1 and R2 because the leakage current causes errors in the threshold voltages. 15 TPS2490 TPS2491 www.ti.com SLVS503 – NOVEMBER 2003 APPLICATION INFORMATION (continued) STEP 6. Choose R5, R6, & C1 R5 is intended to suppress high-frequency oscillations; a resistor of 10Ω will serve for most applications but if M1 has a CISS below 200 pF, then use 33 Ω. Applications with larger MOSFETs and very short wiring may not require R5. R6 is required only if the PG output drives a circuit that requires it. It is recommended that the sink current be less than 2 mA. C1 is a bypass capacitor to help with control of transient voltages, unit emissions, and local supply noise while in the disabled state. Where acceptable, a value in the range of 0.001 µF to 0.1 µF is recommended. STEP 7. Choose D1 Transient voltage suppressor D1 is required in applications where there will be enough energy in the distribution inductance to cause a voltage surge above the TPS2490/91 rated maximum. Such transients can be caused by card insertions or shorts on the input or output of the TPS2490/91. ALTERNATIVE INRUSH DESIGNS Gate Capacitor (dV/dt) Control The TPS2490/91 can be used with applications that require constant turn-on currents. The current is controlled by a single capacitor from the GATE terminal to ground with a series resistor. M1 appears to operate as a source follower (following the gate voltage) in this implementation. Choose a time to charge, ∆t, based on the output capacitor, input voltage VI, and desired charge current, ICHARGE. Select ICHARGE to be less than PLIM ÷ VVCC if the power limit feature is kept. C V VCC t O I CHARGE To select the gate capacitance: C G I GATE t CISS VVCC where CISS is the gate capacitance of M1, and IGATE is the nominal gate charge current. The TIMER capacitor can then be selected to be much smaller as the current and power limit is not active during initial power on. A series resistor of about 1 kΩ should be used in conjunction with CG. PROG Inrush Control A capacitor can be connected from the PROG pin to ground to reduce the initial current step seen in Figure 12 based on the typical application circuit on page 1. This method maintains a relatively fast turn-on time without the drawbacks of a gate-to-ground capacitor that include increased short circuit response time and less predictable gate clamping. ADDITIONAL DESIGN CONSIDERATIONS Use of PG Use the PG pin to control and coordinate a downstream dc/dc converter. A long time delay is needed to allow CO to fully charge before the converter starts if this is not done. An undesirable latchup condition can be created between the TPS2490 output characteristic and the dc/dc converter input characteristic if the converter starts while CO is still charging; the PG pin is one way to avoid this. Faults and Backplane Voltage Droop A hard short at the output of the TPS2490/91 during normal operation could result in activation of the enable or UVLO circuit instead of the current limit if the input voltage droops sufficiently. The lower GATE drive in this condition will cause a prolonged, larger over-current spike. This can be eliminated by filtering EN, or distributing capacitance on the bus itself. Capacitance from adjacent plugged-in units may help with this as well. 16 www.ti.com TPS2490 TPS2491 SLVS503 – NOVEMBER 2003 APPLICATION INFORMATION (continued) Output Clamp Diode Inductive loads on the output may drive the OUT pin below GND when the circuit is unplugged or during a current limit. The OUT pin ratings can be maintained with a small diode, such as an S1B, across TPS2490/91 OUT to GND. Gate Clamp Diode The TPS2490/91 has a relatively well-regulated gate voltage of 12–16 V, even with low supply voltages. A small clamp Zener from gate to source of M1, such as a BZX84C7V5, is recommended if VGS of M1 is rated below this. High Gate Capacitance Applications Gate voltage overstress and abnormally large fault current spikes can be caused by large gate capacitance. An external gate clamp Zener diode is recommended if the total gate capacitance of M1 exceeds about 4000 pF. When gate capacitor inrush control is used, a 1-kΩ resistor in series with CG is recommended. If the series R-C combination is used for MOSFETs with CISS less than 3000 pF, then a Zener is not necessary. Output Short Circuit Measurements Repeatable short-circuit testing results are difficult to obtain. The many details of source bypassing, input leads, circuit layout and component selection, output shorting method, relative location of the short, and instrumentation all contribute to obtaining different results. The actual short itself exhibits a certain degree of randomness as it microscopically bounces and arcs. Care in configuration and methods must be used to obtain realistic results. Do not expect to see waveforms exactly like those in the data sheet—every setup differs. Layout Considerations Good layout practice places the power devices D1, RS, M1, and CO so power flows in a sequential fashion, and preferably in a straight line. A ground plane under the power and the TPS2490/91 is desirable. The TPS2490/91 should be placed close to the sense resistor and the MOSFET; a Kelvin connection is recommended to achieve accurate current sensing across RS. A low-impedance GND connection is required because the TPS2490/91 can momentarily sink upwards of 100 mA from the gate of M1. The GATE amplifier has high bandwidth while active, so keep the gate trace length short. The PROG, TIMER, and EN pins have high input impedances, therefore keep their input leads short. Oversize power traces and power device connections to assure low voltage drop and good thermal performance. 17 PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS2490DGS ACTIVE MSOP DGS 10 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2490DGSG4 ACTIVE MSOP DGS 10 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2490DGSR ACTIVE MSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2490DGSRG4 ACTIVE MSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2491DGS ACTIVE MSOP DGS 10 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2491DGSG4 ACTIVE MSOP DGS 10 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2491DGSR ACTIVE MSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2491DGSRG4 ACTIVE MSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 30-Jun-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device 30-Jun-2007 Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS2490DGSR DGS 10 NSE 330 12 5.3 3.3 1.3 8 12 Q1 TPS2491DGSR DGS 10 NSE 330 12 5.3 3.3 1.3 8 12 Q1 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) TPS2490DGSR DGS 10 NSE 370.0 355.0 75.0 TPS2491DGSR DGS 10 NSE 370.0 355.0 75.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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