TI SN65HVD51DG4

SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
www.ti.com
SLLS666 – SEPTEMBER 2005
HIGH OUTPUT FULL-DUPLEX RS-485 DRIVERS AND RECEIVERS
FEATURES
•
•
•
•
•
•
•
•
1/8 Unit-Load Option Available (Up to 256
Nodes on the Bus)
Bus-Pin ESD Protection Exceeds 15 kV HBM
Optional Driver Output Transition Times for
Signaling Rates (1) of 1 Mbps, 5 Mbps and 25
Mbps
Low-Current Standby Mode < 1 µA
Glitch-Free Power-Up and Power-Down Bus
I/Os
Bus Idle, Open, and Short Circuit Failsafe
Meets or exceeds the requirements of ANSI
TIA/EIA-485-A and RS-422 Compatible
3.3-V Devices available, SN65HVD30-39
The SN65HVD50, SN65HVD51, SN65HVD52,
SN65HVD56 and SN65HVD57 are fully enabled with
no external enabling pins. The SN65HVD56 and
SN65HVD57
implement
receiver
equalization
technology for improved performance in long distance
applications.
The SN65HVD53, SN65HVD54, SN65HVD55,
SN65HVD58, and SN65HVD59 have active-high
driver enables and active-low receiver enables. A
very low, less than 1 uA, standby current can be
achieved by disabling both the driver and receiver.
The SN65HVD58 and SN65HVD59 implement
receiver equalization technology for improved
performance in long distance applications.
All devices are characterized for operation from -40°
C to +85°.
100
APPLICATIONS
Utility Meters
Chassis-to-Chassis Interconnects
DTE/DCE Interfaces
Industrial, Process, and Building Automation
Point-of-Sale (POS) Terminals and Networks
DESCRIPTION
The SN65HVD5X devices are 3-state differential line
drivers and differential-input line receivers that
operate with a 5-V power supply. Each driver and
receiver has separate input and output pins for
full-duplex bus communication designs. They are
designed for balanced transmission lines and
interoperation
with
ANSI
TIA/EIA-485A,
TIA/EIA-422-B, ITU-T v.11 and ISO 8482:1993
standard-compliant devices.
(1)
The signaling rate of a line is the number of voltage
transitions that are made per second expressed in the units
bps (bits per second).
SN65HVD50
SN65HVD53
Signalling Rate (Mbps)
•
•
•
•
•
SN65HVD56
SN65HVD58
10
SN65HVD57
SN65HVD51
SN65HVD59
SN65HVD54
1
SN65HVD52
SN65HVD55
0.1
10
100
1000
Cable Length (meters)
The SN65HVD56 and SN65HVD58 implement
receiver equalization technology for improved jitter
performance on differential bus applications with data
rates up to 20 Mbps at cable lengths up to 160
meters.
The SN65HVD57 and SN65HVD59 implement
receiver equalization technology for improved jitter
performance on differential bus applications with data
rates in the range of 1 to 5 Mbps at cable lengths up
to 1000 meters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
www.ti.com
SLLS666 – SEPTEMBER 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
SN65HVD50, SN65HVD51, SN65HVD52, SN65HVD56,
SN65HVD57
SN65HVD53, SN65HVD54, SN65HVD55, SN65HVD58,
SN65HVD59
D PACKAGE (TOP VIEW)
VCC
R
D
GND
R
D
1
8
2
7
3
6
4
5
8
2
A
7
6
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
VCC
A
B
Z
Y
NC
NC - No internal connection
B
5
3
NC
R
RE
DE
D
GND
GND
A
B
Z
Y
Y
Z
AVAILABLE OPTIONS
2
SIGNALING
RATE
UNIT LOADS
RECEIVER
EQUALIZATION
ENABLES
BASE
PART NUMBER
SOIC MARKING
25 Mbps
1/2
No
No
SN65HVD50
PREVIEW
5 Mbps
1/8
No
No
SN65HVD51
PREVIEW
1 Mbps
1/8
No
No
SN65HVD52
PREVIEW
25 Mbps
1/2
No
Yes
SN65HVD53
65HVD53
5 Mbps
1/8
No
Yes
SN65HVD54
65HVD54
1 Mbps
1/8
No
Yes
SN65HVD55
65HVD55
25 Mbps
1/2
Yes
No
SN65HVD56
PREVIEW
5 Mbps
1/8
Yes
No
SN65HVD57
PREVIEW
25 Mbps
1/2
Yes
Yes
SN65HVD58
PREVIEW
5 Mbps
1/8
Yes
Yes
SN65HVD59
PREVIEW
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
www.ti.com
SLLS666 – SEPTEMBER 2005
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1) (2)
UNIT
VCC
Supply voltage range
–0.3 V to 6 V
Voltage range at any bus terminal (A, B, Y, Z)
–9 V to 14 V
Voltage input, transient pulse through 100 Ω. See Figure 12 (A, B, Y,
VI
Z) (3)
–50 to 50 V
Voltage input range (D, DE, RE)
-0.5 V to 7 V
Continuous total power dissipation
IO
(1)
(2)
(3)
Internally limited
Output current (receiver output only, R)
11 mA
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
This tests survivability only and the output state of the receiver is not specified.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
VCC
Supply voltage
VI or
VIC
Voltage at any bus terminal (separately or common mode)
1/tUI
Signaling rate
NOM
MAX
4.5
5.5
–7 (1)
12
SN65HVD50, SN65HVD53, SN65HVD56, SN65HVD58
25
SN65HVD51, SN65HVD54, SN65HVD57, SN65HVD59
5
SN65HVD52, SN65HVD55
VIH
High-level input voltage
D, DE, RE
2
VCC
VIL
Low-level input voltage
D, DE, RE
0
0.8
VID
Differential input voltage
-12
12
IOL
Low-level output current
TJ (2)
Junction temperature
(1)
(2)
Mbps
54
Ω
Differential load resistance
High-level output current
V
1
RL
IOH
UNIT
Driver
60
-60
Receiver
mA
–8
Driver
60
Receiver
8
–40
V
150
mA
°C
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
See thermal characteristics table for information regarding this specification.
ELECTROSTATIC DISCHARGE PROTECTION
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
UNIT
±16
Human body model
Bus terminals and GND
Human body model (2)
All pins
±4
Charged-device-model (3)
All pins
±1
(1)
(2)
(3)
MAX
kV
All typical values at 25°C and with a 5-V supply.
Tested in accordance with JEDEC Standard 22, Test Method A114-A.
Tested in accordance with JEDEC Standard 22, Test Method C101.
3
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
www.ti.com
SLLS666 – SEPTEMBER 2005
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
VI(K)
TEST CONDITIONS
Input clamp voltage
II = –18 mA
Steady-state differential output voltage
4
1.7
2.6
RL = 100 Ω, See Figure 1 (RS-422)
2.4
3.2
Vtest = –7 V to 12 V, See Figure 2
1.6
Change in magnitude of steady-state
differential output voltage between states
RL = 54 Ω, See Figure 1 and
Figure 2
VOD(RING)
Differential Output Voltage overshoot
and undershoot
RL = 54 Ω, CL = 50 pF, See
Figure 5
See Figure 3 for definition
VOC(PP)
Peak-to-peak
common-mode
output voltage
VOC(SS)
Steady-state common-mode
output voltage
–0.2
HVD50, HVD53,
HVD56, HVD58
Change in steady-state common-mode
output voltage
0.2
0.05 |VOD(SS)|
See Figure 4
0.4
0.4
2.2
3.3
–0.1
0.1
See Figure 4
VCC = 0 V, VZ or VY = 12 V,
Other input at 0 V
VCC = 0 V, VZ or VY = –7 V,
Other input at 0 V
IZ(Z) or IY(Z)
High-impedance state
output current
HVD53, HVD54,
HVD55, HVD58,
HVD59
IZ(S) or IY(S)
Short Circuit output Current
II
Input current
C(OD)
(1)
4
VCC = 5 V or 0 V,
DE = 0 V
VZ or VY = 12 V
VCC = 5 V or 0 V,
DE = 0 V
VZ or VY = –7 V
VZ or VY = –7 V
VZ or VY = 12 V
All typical values are at 25°C and with a 5-V supply.
90
–10
90
µA
Other input
at 0 V
–10
Other input
at 0 V
D, DE
Differential output capacitance
V
0.5
HVD52, HVD55
∆VOC(SS)
UNIT
VCC
RL = 54 Ω, See Figure 1 (RS-485)
∆|VOD(SS)|
HVD51, HVD54,
HVD57, HVD59
MAX
–1.5
IO = 0
|VOD(SS)|
MIN TYP (1)
VOD = 0.4 sin (4E6πt) + 0.5 V,
DE at 0 V
–250
250
–250
250
0
100
16
mA
µA
pF
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
www.ti.com
SLLS666 – SEPTEMBER 2005
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
MIN
TYP (1)
MAX
HVD50, HVD53, HVD56, HVD58
4
8
12
HVD51, HVD54, HVD57, HVD59
20
29
46
HVD52, HVD55
PARAMETER
Propagation delay time,
low-to-high-level output
tPLH
Propagation delay time,
high-to-low-level output
tPHL
Differential output signal
rise time
tr
90
143
230
HVD50, HVD53, HVD56, HVD58
4
8
12
HVD51, HVD54, HVD57, HVD59
20
30
46
HVD52, HVD55
90
143
230
HVD50, HVD53, HVD56, HVD58
3
6
12
HVD51, HVD54, HVD57, HVD59
25
34
60
130
197
300
3
6
11
25
33
60
130
192
300
HVD52, HVD55
HVD50, HVD53, HVD56, HVD58
Differential output signal fall
time
tf
TEST CONDITIONS
RL = 54 Ω, CL = 50 pF,
See Figure 5
HVD51, HVD54, HVD57, HVD59
HVD52, HVD55
tsk(p)
Pulse skew (|tPHL - tPLH|)
HVD50, HVD53, HVD56, HVD58
2
HVD51, HVD54, HVD57, HVD59
2
HVD52, HVD55
8
HVD50, HVD53, HVD56, HVD58
tsk(pp) (2)
Part-to-part skew
Propagation delay time,
high-level-to-highimpedance output
tPHZ
tPZL1
4
30
180
HVD53, HVD58
HVD54, HVD59
tPZH2
tPZL2
RL = 110 Ω, RE at 0 V,
See Figure 6
D = 3 V and S1 = Y,
D = 0 V and S1 = Z
HVD55
HVD53, HVD58
Propagation delay time,
high-impedance-to-low-level HVD54, HVD59
output
HVD55
ns
ns
ns
ns
HVD54, HVD59
HVD55
ns
22
HVD53, HVD58
HVD53, HVD58
Propagation delay time,
low-level-to-high-impedance HVD54, HVD59
output
HVD55
tPLZ
(1)
(2)
Propagation delay time,
high-impedance-to-highlevel output
ns
1
HVD51, HVD54, HVD57, HVD59
HVD52, HVD55
tPZH1
UNIT
ns
380
16
40
ns
110
23
RL = 110 Ω, RE at 0 V,
See Figure 7
D = 3 V and S1 = Z,
D = 0 V and S1 = Y
200
ns
420
19
70
ns
160
Propagation delay time, standby-to-high-level output
RL = 110 Ω, RE at 3 V,
See Figure 6
D = 3 V and S1 = Y,
D = 0 V and S1 = Z
3300
ns
Propagation delay time, standby-to-low-level output
RL = 110 Ω, RE at 3 V,
See Figure 7
D = 3 V and S1 = Z,
D = 0 V and S1 = Y
3300
ns
All typical values are at 25°C and with a 5-V supply.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
5
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
www.ti.com
SLLS666 – SEPTEMBER 2005
RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
VIT+
Positive-going differential input
threshold voltage
IO = –8 mA
VIT-
Negative-going differential input
threshold voltage
IO = 8 mA
Vhys
Hysteresis voltage (VIT+ - VIT-)
VIK
Enable-input clamp voltage
Output voltage
IO(Z)
High-impedance-state output
current
Bus input current
HVD51,
HVD52,
HVD54,
HVD55,
HVD57,
HVD59
IIH
Input current, RE
CID
Differential input capacitance
HVD50,
HVD51,
HVD52
Supply current
50
II = –18 mA
–1.5
VO = 0 or VCCRE at VCC
0.3
1
VA or VB = 12 V
0.19
0.3
VA or VB = 12 V, VCC = 0 V
0.24
0.4
VA or VB = -7 V
Other input
at 0 V
VA or VB = -7 V, VCC = 0 V
–0.35
–0.19
–0.25
–0.14
VA or VB = 12 V
0.05
0.10
VA or VB = 12 V, VCC = 0 V
0.06
0.10
VA or VB = -7 V
Other input
at 0 V
VA or VB = -7 V, VCC = 0 V
–0.10
–0.05
–0.10
–0.03
VIH = 2 V
–60
VIL = 0.8 V
–60
VID = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V
HVD58
pF
8.0
D at 0 V or VCC and No Load
RE at 0 V, D at 0 V or VCC, DE at 0 V,
No load (Receiver enabled and
driver disabled)
mA
2.9
4.5
RE at VCC, D at VCC, DE at 0 V,
No load (Receiver disabled and
driver disabled)
0.08
1
µA
2.7
RE at 0 V, D at 0 V or VCC, DE at VCC,
No load (Receiver enabled and
driver enabled)
8.0
4.3
9.7
HVD53
2.3
HVD58
mA
µA
16
HVD59
HVD54,
HVD55
µA
µA
2.3
HVD53,
HVD54,
HVD55,
HVD58,
HVD59
V
mA
HVD53
HVD54,
HVD55
RE at VCC, D at 0 V or VCC, DE at VCC
No load (Receiver disabled and
driver enabled)
HVD59
6
V
4.0
–1
HVD53
(1)
mV
9.5
HVD58,
HVD59
UNIT
V
HVD56,
HVD57
HVD54,
HVD55
ICC
MAX
–0.20
VID = –200 mV, IO = 8 mA, See Figure 8
HVD50,
HVD53,
HVD56,
HVD58
IA or IB
TYP (1)
–0.02
VID = 200 mV, IO = –8 mA, See Figure 8
VO
MIN
All typical values are at 25°C and with a 5-V supply.
7.7
3.2
8.5
mA
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
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SLLS666 – SEPTEMBER 2005
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
MIN TYP (1)
MAX
HVD50, HVD53, HVD56, HVD58
24
40
HVD51, HVD52, HVD54, HVD55,
HVD57, HVD59
43
55
HVD50, HVD53, HVD56, HVD58
26
35
HVD51, HVD52, HVD54, HVD55,
HVD57, HVD59
47
60
PARAMETER
tPLH
Propagation delay time,
low-to-high-level output
tPHL
Propagation delay time,
high-to-low-level output
tsk(p)
Pulse skew (|tPHL - tPLH|)
tsk(pp) (2)
Part-to-part skew
TEST CONDITIONS
HVD50, HVD53, HVD56, HVD57, VID = -1.5 V to 1.5 V,
CL = 15 pF,
HVD58, HVD59
See Figure 9
HVD51, HVD54, HVD52, HVD55
5
7
HVD50, HVD53, HVD56, HVD58
5
HVD51, HVD54, HVD57, HVD59
6
HVD52, HVD55
6
tr
Output signal rise time
2.3
tf
Output signal fall time
2.4
tPHZ
Output disable time from high level
tPZH1
Output enable time to high level
tPZH2
Propagation delay time, standby-to-high-level output
tPLZ
Output disable time from low level
tPZL1
Output enable time to low level
tPZL2
(1)
(2)
Propagation delay time, standby-to-low-level output
DE at 3 V, CL = 15 pF
See Figure 10
DE at 0 V, CL = 15 pF
See Figure 10
DE at 3 V, CL = 15 pF
See Figure 11
DE at 0 V, CL = 15 pF
See Figure 11
UNIT
ns
4
4
17
10
3300
13
10
3300
All typical values are at 25°C and with a 5-V supply
.tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
7
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
www.ti.com
SLLS666 – SEPTEMBER 2005
RECEIVER EQUALIZATION CHARACTERISTICS
over recommended operating conditions unless otherwise noted (1)
PARAMETER
TEST CONDITIONS
0m
100 m
25 Mbps
150 m
200 m
200 m
tj(pp)
Peak-to-peak
eye-pattern
jitter
Pseudo-random NRZ
code with a bit pattern
length o 216-1, Belden
3105A cable
10 Mbps
300 m
5 Mbps
3 Mbps
1 Mbps
(1)
(2)
8
250 m
500 m
500 m
1000 m
MIN
TYP (2)
HVD56, HVD58
PREVIEW
HVD53
PREVIEW
HVD56, HVD58
PREVIEW
HVD53
PREVIEW
HVD56, HVD58
PREVIEW
HVD53
PREVIEW
HVD56, HVD58
PREVIEW
HVD53
PREVIEW
HVD56, HVD58
PREVIEW
HVD53
PREVIEW
HVD56, HVD58
PREVIEW
HVD53
PREVIEW
HVD56, HVD58
PREVIEW
HVD54
PREVIEW
HVD57, HVD59
PREVIEW
HVD53
PREVIEW
HVD54
PREVIEW
HVD56, HVD58
PREVIEW
HVD57, HVD59
PREVIEW
HVD54
PREVIEW
HVD57, HVD59
PREVIEW
The HVD53 and HVD54 do not have receiver equalization but are specified for comparison.
All typical values are at VCC = 5 V, and temperature = 25°C.
MAX
UNIT
ns
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
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SLLS666 – SEPTEMBER 2005
THERMAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted (1)
PARAMETER
TEST CONDITIONS
(3)
Junction–to–ambient Low-K board , No airflow
(2)
thermal resistance
θJA
Junction–to–ambient High-K
thermal resistance (2)
θJB
Junction–to–board
thermal resistance
θJC
Junction–to–case
thermal resistance
No airflow
High-K board
No board
Device power
dissipation
PD
board (4),
(1)
(2)
(3)
(4)
HVD53, HVD54, HVD55, HVD58, HVD59
162.6
HVD50, HVD51, HVD52, HVD56, HVD57
135.1
HVD53, HVD54, HVD55, HVD58, HVD59
92.1
HVD50, HVD51, HVD52, HVD56, HVD57
44.4
HVD53, HVD54, HVD55, HVD58, HVD59
61.1
HVD50, HVD51, HVD52, HVD56, HVD57
43.5
HVD53, HVD54, HVD55, HVD58, HVD59
58.6
420
HVD51, HVD57 (10Mbps)
404
HVD52 (1Mbps)
383
RL= 60Ω, CL = 50 pF,
DE at VCCRE at 0 V,
Input to D a 50% duty cycle
square wave at indicated
signaling rate
HVD53, HVD58 (25Mbps)
420
HVD54, HVD59 (10Mbps)
404
HVD55 (1Mbps)
383
Low-K board, No airflow
HVD50, HVD56
–40
55
HVD51, HVD52, HVD57
–40
84
HVD53, HVD54, HVD55, HVD58, HVD59
–40
85
HVD50, HVD51, HVD52, HVD56, HVD57
–40
85
HVD53, HVD54, HVD55, HVD58, HVD59
–40
Thermal shutdown junction temperature
UNIT
°C/W
HVD50, HVD56 (25Mbps)
High-K board, No airflow
TJSD
TYP MAX
230.8
RL= 60Ω, CL = 50 pF,
Input to D a 50% duty cycle
square wave at indicated
signaling rate
Ambient air
temperature
TA
MIN
HVD50, HVD51, HVD52, HVD56, HVD57
mW
°C
85
165
See Application Information section for an explanation of these parameters.
The intent of θJA specification is solely for a thermal performance comparison of one package to another in a standardized environment.
This methodology is not meant to and will not predict the performance of a package in an application-specific environment.
In accordance with the Low-K thermal metric definitions of EIA/JESD51-3.
In accordance with the High-K thermal metric definitions of EIA/JESD51-7.
PARAMETER MEASUREMENT INFORMATION
VCC
II
DE
375 Ω ±1%
VCC
Y
IY
DE
VOD
0 or 3 V
Z
RL
IZ
D
Y
VOD
0 or 3 V
60 Ω ±1%
+
_ −7 V < V(test) < 12 V
Z
VI
VZ
VY
Figure 1. Driver VOD Test Circuit: Voltage and Current
Definitions
375 Ω ±1%
Figure 2. Driver VOD With Common-Mode Loading Test
Circuit
9
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
www.ti.com
SLLS666 – SEPTEMBER 2005
PARAMETER MEASUREMENT INFORMATION (continued)
VOD(RING) is measured at four points on the output waveform, corresponding to overshoot and undershoot from
theVOD(H) and VOD(L) steady state values.
VOD(SS)
VOD(RING)
0 V Differential
VOD(RING)
-VOD(SS)
Figure 3. VOD(RING) Waveform and Definitions
VCC
DE
Input
D
27 Ω ± 1%
Y
Y
VY
Z
VZ
VOC(PP)
Z
27 Ω ± 1%
CL = 50 pF ±20%
VOC
∆VOC(SS)
VOC
CL Includes Fixture and
Instrumentation Capacitance
Input: PRR = 500 kHz, 50% Duty Cycle,t r <6ns, t f <6ns, ZO = 50 Ω
Figure 4. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
Y
W
Z
»
W
»
W
Figure 5. Driver Switching Test Circuit and Voltage Waveforms
10
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
www.ti.com
SLLS666 – SEPTEMBER 2005
PARAMETER MEASUREMENT INFORMATION (continued)
D
3V
0V
3V
S1
Y
Z
Y
S1
D
VO
1.5 V
1.5 V
VI
0.5 V
t PZH(1 & 2)
Z
0V
V OH
DE
Input
Generator
50 W
VI
RL = 110 W
±1%
CL = 50 pF
±20%
VO
2.3 V
~0V
tPHZ
Generator: PRR = 500kHz, 50% Duty Cycle, t r<6 ns, t f < 6ns, Z 0 = 50 W
CL Includes Fixture and Instrumentation Capacitance
Figure 6. Driver High-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
D
3V
0V
VCC
S1
Z
Y
RL = 110 Ω
± 1%
Y
1.5 V
1.5 V
VO
DE
VI
VI
S1
D
Input
Generator
3V
0V
Z
t PZL(1&2)
t PLZ
VCC
CL = 50 pF ±20%
50 Ω
0.5 V
CL Includes Fixture
and Instrumentation
Capacitance
VO
2.3 V
VOL
Generator: PRR = 500 kHz, 50% Duty Cycle, t r <6 ns, t f <6 ns, Zo = 50 Ω
Figure 7. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
IA
A
VID
VA+ VB
2
VIC
VA
B
VB
IB
IO
R
VO
RE
II
VI
Figure 8. Receiver Voltage and Current Definitions
11
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
www.ti.com
SLLS666 – SEPTEMBER 2005
PARAMETER MEASUREMENT INFORMATION (continued)
A
Input
Generator
VI
3 V
R
50 W
1.5 V
1.5 V
VI
1.5 V
0 V
B
VO
RE
0V
CL = 15 pF
±20%
tPLH
tPHL
90 %
VO
Generator : PRR = 500 kHz , 50 %
CL Includes Fixture
and Instrumentation
Capacitance
Duty Cycle , t < 6 ns , t < 6 ns ,
Z = 50 W
1.5 V
10%
t
VOH
90 %
1.5 V
10%
t
r
VOL
f
Figure 9. Receiver Switching Test Circuit and Voltage Waveforms
V CC
A
1.5 V
VO
R
B
0V
Input
Generator
VI
1 kW ±1%
3V
A
S1
VI
C L = 15 pF
±20%
1.5 V
1.5 V
0V
B
t
PHZ
PZH(1 & 2)
V OH
50 W
VO
C L Includes Fixture and
Instrumentation Capacitance
1.5 V
0.5 V
~0 V
Generator: PRR = 500 kHz, 50%, Duty Cycle, tr < 6 ns, tf < 6 ns, Z0 = 50 W
Figure 10. Receiver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
VCC
0V
A
R
1.5 V
B
RE
Input
Generator
VI
VO
1 kW ±1%
C L = 15 pF
3V
A
S1
VI
1.5 V
1.5 V
B
±20%
50 W
C L Includes Fixture
and Instrumentation
Capacitance
0V
t PZL(1 & 2)
VO
t PLZ
1.5 V
V CC
0.5 V
VOL
Generator: PRR = 500 kHz, 50%, Duty Cycle, tr < 6 ns, tf < 6 ns, Z0 = 50 W
Figure 11. Receiver Low-Level Enable and Disable Time Test Circuit and Voltage Waveforms
12
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
www.ti.com
SLLS666 – SEPTEMBER 2005
PARAMETER MEASUREMENT INFORMATION (continued)
0 V or 3 V
DE
A
Y
D
R
Z
100 W
±1%
+
-
100 W
±1%
Pulse Generator
15 ms duration
1% Duty Cycle
tr, tf £ 100 ns
B
RE
0 V or 3 V
+
-
Figure 12. Test Circuit, Transient Overvoltage Test
DEVICE INFORMATION
LOW-POWER SHUTDOWN MODE
When both the driver and receiver are disabled (DE low and RE high) the device is in shutdown mode. If the
enable inputs are in this state for less than 60 ns, the device does not enter shutdown mode. This guards against
inadvertently entering shutdown mode during driver/receiver enabling. Only when the enable inputs are held in
this state for 300 ns or more, the device is assured to be in shutdown mode. In this low-power shutdown mode,
most internal circuitry is powered down, and the supply current is typically less than 1 nA. When either the driver
or the receiver is re-enabled, the internal circuitry becomes active.
12
A
2
R
11
B
RE
3
Low-Power
Shutdown
DE
4
9
Y
5
D
10
Z
Figure 13. Low-Power Shutdown Logic Diagram
If only the driver is re-enabled (DE transitions to high) the driver outputs are driven according to the D input after
the enable times given by tPZH2 and tPZL2 in the driver switching characteristics. If the D input is open when the
driver is enabled, the driver outputs defaults to A high and B low, in accordance with the driver failsafe feature.
If only the receiver is re-enabled (RE transitions to low) the receiver output is driven according to the state of the
bus inputs (A and B) after the enable times given by tPZH2 and tPZL2 in the receiver switching characteristics. If
there is no valid state on the bus the receiver responds as described in the failsafe operation section.
If both the receiver and driver are re-enabled simultaneously, the receiver output is driven according to the state
of the bus inputs (A and B) and the driver output is driven according to the D input. Note that the state of the
active driver affects the inputs to the receiver. Therefore, the receiver outputs are valid as soon as the driver
outputs are valid.
13
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
www.ti.com
SLLS666 – SEPTEMBER 2005
DEVICE INFORMATION (continued)
FUNCTION TABLES
SN65HVD53, SN65HVD54, SN65HVD55, SN65HVD58,
SN65HVD59 DRIVER
INPUTS
OUTPUTS
D
DE
Y
Z
H
H
H
L
H
L
H
L
X
L or open
Z
Z
Open
H
L
H
SN65HVD53, SN65HVD54, SN65HVD55, SN65HVD58,
SN65HVD59 RECEIVER
DIFFERENTIAL INPUTS
VID = VA - VB
ENABLE
RE
OUTPUT
R
VID ≤ –0.2 V
L
L
–0.2 V < VID < –0.02 V
L
?
–0.02 V ≤ VID
L
H
X
H or open
Z
Open Circuit
L
H
Idle circuit
L
H
Short Circuit, VA = VB
L
H
SN65HVD50, SN65HVD51, SN65HVD52, SN65HVD56,
SN65HVD57 DRIVER
OUTPUTS
INPUT
D
Y
Z
H
H
L
L
L
H
Open
L
H
SN65HVD50, SN65HVD51, SN65HVD52, SN65HVD56,
SN65HVD57 RECEIVER
14
DIFFERENTIAL INPUTS
VID = VA - VB
OUTPUT
R
VID ≤ –0.2 V
L
–0.2 V < VID < –0.02 V
?
–0.02 V ≤ VID
H
Open Circuit
H
Idle circuit
H
Short Circuit, VA = VB
H
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
www.ti.com
SLLS666 – SEPTEMBER 2005
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
D and DE Input
RE Input
VCC
VCC
130 kW
Input
470 W
Input
9V
470 W
9V
125 kW
A Input
B Input
VCC
VCC
R1
22 V
R1
22 V
R3
R3
Input
Input
22 V
R2
22 V
R2
R Output
Y and Z Outputs
VCC
VCC
16 V
5W
Output
16 V
SN65HVD50, SN65HVD53, SN65HVD56, SN65HVD58
Output
9V
R1/R2
R3
9 kΩ
45 kΩ
SN65HVD51, SN65HVD52, SN65HVD54, SN65HVD55 SN65HVD57, 36 kΩ
SN65HVD58, SN65HVD59
180 kΩ
15
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
www.ti.com
SLLS666 – SEPTEMBER 2005
TYPICAL CHARACTERISTICS
HVD50, HVD53
RMS Supply Current
vs
Signaling Rate
HVD51, HVD54
RMS Supply Current
vs
Signaling Rate
70
70
TA =25°C
RL = 54 W
RE = VCC CL = 50 pF
DE = VCC
65
ICC (RMS Supply Current, mA)
ICC (RMS Supply Current, mA)
65
60
VCC = 5.0 VDC
55
50
TA =25°C
RL = 54 W
RE = VCC CL = 50 pF
DE = VCC
60
55
VCC = 5.0 VDC
50
45
45
40
40
0
5
10
15
20
0
25
1
2
Signaling Rate (Mbps)
Signaling Rate (Mbps)
Figure 14.
Figure 15.
HVD52, HVD55
RMS Supply Current
vs
Signaling Rate
75
TA =25°C
RL = 54 W
RE = VCC CL = 50 pF
DE = VCC
ICC (RMS Supply Current, mA)
70
65
60
VCC = 5.0 VDC
55
50
45
40
0
0.2
0.4
0.6
Signaling Rate (Mbps)
Figure 16.
16
3
0.8
1
4
5
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
www.ti.com
SLLS666 – SEPTEMBER 2005
TYPICAL CHARACTERISTICS (continued)
HVD50, HVD53
Bus Input Current
vs
Input Voltage
HVD51, HVD52, HVD54, HVD55
Bus Input Current
vs
Input Voltage
60
250
200
TA = 25°C
RE = 0 V
DE = 0 V
TA = 25°C
RE = 0 V
DE = 0 V
40
II - Bus Input Current - µA
II - Bus Input Current - µA
150
100
50
0
VCC = 5 V
-50
-100
20
0
VCC = 5 V
-20
-150
-40
-200
-250
-60
-7
-4
-1
2
5
8
11
14
-7
-4
-1
5
8
11
Figure 17.
Figure 18.
Driver Low-Level Output Current
vs
Low-Level Output Voltage
Driver High-Level Output Current
vs
High-Level Output Voltage
0.12
14
0.01
VCC = 5 V
DE = VCC
D=0V
0.1
VCC = 5 V
DE = VCC
D=0V
-0.01
0.08
IOH - High-level Output Current - A
IOL - Low-level Output Current - A
2
VI - Bus Input Voltage - V
VI - Bus Input Voltage - V
0.06
0.04
0.02
0
-0.02
-0.03
-0.05
-0.07
-0.09
-0.11
-0.13
0
1
2
3
4
VOL - Low-Level Output Voltage - V
Figure 19.
5
0
1
2
3
4
5
VOH - High-Level Output Voltage - V
Figure 20.
17
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
www.ti.com
SLLS666 – SEPTEMBER 2005
TYPICAL CHARACTERISTICS (continued)
Driver Differential Output Voltage
vs
Free-Air Temperature
Driver Output Current
vs
Supply Voltage
60
VCC = 5 V
DE at VCC
D at VCC
2.8
2.7
2.6
40
30
VCC = 5 V
20
2.5
10
0
2.4
-40
-15
10
35
TA - Free-Air Temperature - °C
Figure 21.
18
TA = 25°C
RL = 54 W
D = VCC
DE = VCC
50
IO - Driver Output Current - mA
VOD - Driver Differential Voltage - V
2.9
60
85
0
1
2
3
4
VCC - Supply Voltage - V)
Figure 22.
5
6
SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59
www.ti.com
SLLS666 – SEPTEMBER 2005
APPLICATION INFORMATION
THERMAL CHARACTERISTICS OF IC PACKAGES
θJA (Junction-to-Ambient Thermal Resistance) is defined as the difference in junction temperature to ambient
temperature divided by the operating power.
θJA is not a constant and is a strong function of:
• the PCB design (50% variation)
• altitude (20% variation)
• device power (5% variation)
θJA can be used to compare the thermal performance of packages if the specific test conditions are defined and
used. Standardized testing includes specification of PCB construction, test chamber volume, sensor locations,
and the thermal characteristics of holding fixtures. θJA is often misused when it is used to calculate junction
temperatures for other installations.
TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use condition
thermal performance, and it consists of a single copper trace layer 25 mm long and 2-oz thick. The high-k board
gives best case in-use condition, and it consists of two 1-oz buried power planes with a single copper trace layer
25 mm long and 2-oz thick. A 4% to 50% difference in θJA can be measured between these two test cards
θJC (Junction-to-Case Thermal Resistance) is defined as difference in junction temperature to case divided by
the operating power. It is measured by putting the mounted package up against a copper block cold plate to
force heat to flow from die, through the mold compound into the copper block.
θJC is a useful thermal characteristic when a heatsink applied to package. It is not a useful characteristic to
predict junction temperature because it provides pessimistic numbers if the case temperature is measured in a
nonstandard system and junction temperatures are backed out. It can be used with θJB in 1-dimensional thermal
simulation of a package system.
θJB (Junction-to-Board Thermal Resistance) is defined as the difference in the junction temperature and the
PCB temperature at the center of the package (closest to the die) when the PCB is clamped in a cold-plate
structure. θJB is only defined for the high-k test card.
θJB provides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermal
resistance (especially for BGA’s with thermal balls) and can be used for simple 1-dimensional network analysis of
package system, see Figure 23.
Figure 23. Thermal Resistance
19
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
SN65HVD53D
PREVIEW
SOIC
D
14
50
TBD
Call TI
Call TI
SN65HVD53DR
PREVIEW
SOIC
D
14
2500
TBD
Call TI
Call TI
SN65HVD54D
PREVIEW
SOIC
D
14
50
TBD
Call TI
Call TI
SN65HVD54DR
PREVIEW
SOIC
D
14
2500
TBD
Call TI
Call TI
SN65HVD55D
PREVIEW
SOIC
D
14
50
TBD
Call TI
Call TI
SN65HVD55DR
PREVIEW
SOIC
D
14
2500
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Nov-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN65HVD53D
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD53DG4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD53DR
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD53DRG4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD54D
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD54DG4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD54DR
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD54DRG4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD55D
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD55DG4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD55DR
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD55DRG4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
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