TI TPS53127RGET

TPS53127
www.ti.com
SLVSA93 – MARCH 2010
DUAL SYNCHRONOUS STEP-DOWN CONTROLLER
FOR LOW VOLTAGE POWER RAILS
Check for Samples: TPS53127
FEATURES
1
•
2
•
•
•
•
•
•
•
•
D-CAP2™ Mode Control
– Fast Transient Response
– No External Parts Required for Loop
Compensation
– Compatible With Ceramic Output
Capacitors
High Initial Reference Accuracy (±1%)
Low Output Ripple
Wide Input Voltage Range: 4.5 V to 24 V
Output Voltage Range: 0.76 V to 5.5 V
Low-Side RDS(ON) Loss-Less Current Sensing
Adaptive Gate Drivers with Integrated Boost
Diode
Adjustable Soft Start
Non-Sinking Pre-Biased Soft Start
•
•
•
•
700-kHz Switching Frequency
Cycle-by-Cycle Over-Current Limiting Control
30-mV to 300-mV OCP Threshold Voltage
Thermally Compensated OCP by 4000 ppm/°C
at ITRIP
APPLICATIONS
•
Point-of-Load Regulation in Low Power
Systems for Wide Range of Applications
– Digital TV Power Supply
– Networking Home Terminal
– Digital Set-Top Box (STB)
– DVD Player/Recorder
– Gaming Consoles
DESCRIPTION
The TPS53127 is a dual, adaptive on-time D-CAP2™ mode synchronous buck controller. The part enables
system designers to cost effectively complete the suite of various end equipment's power bus regulators with a
low external component count and low standby consumption. The main control loop for the TPS53127 uses the
D-CAP2™ Mode topology which provides a very fast transient response with no external component.
The TPS53127 also has a proprietary circuit that enables the device to adapt not only low equivalent series
resistance (ESR) output capacitors such as POSCAP/SP-CAP, but also ceramic capacitor. The part provides a
convenient and efficient operation with conversion voltages from 4.5 V to 24 V and output voltage from 0.76 V to
5.5 V.
The TPS53127 is available in the 24 pin RGE/PW package, and is specified from –40°C to 85°C ambient
temperature range.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
D-CAP2 is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
TPS53127
SLVSA93 – MARCH 2010
www.ti.com
TYPICAL APPLICATION CIRCUITS
Input Voltage
4.5V to 24V
C9
10uF
C10
4700pF
C6
10uF
VO2
1.05V/4A
R5
10kΩ
Q3
FDS8878
L2
SPM6530T
1.5uH
C5
0.1uF
VBST2
9
DRVH2
10
SW2
3
2
1
VFB1
VO1
VFB2
EN2
8
4
SS1
5
GND
6
7
SGND
R1
13.5kΩ
R2
10kΩ
VO2
R4
3.63kΩ
PGND
EN1
24
Power PAD
Q1
FDS8878
L1
SPM6530T
1.5uH
C2
0.1uF
VBST1 23
DRVH1 22
TPS53127 RGE
SW1
21
L1
DRVL2
DRVL1 20
PGND2
PGND1 19
Q2
FDS8690
C3
10uF
VO1
1.8V/4A
PGND
R6
4.7kΩ
VIN
TRIP1
13
VREG5
C4
22uFx2
SS2
12
V5FILT
11
TRIP2
(QFN )
Q4
FDS8690
14
15
16
17
18
C7
4.7uF
C８
1uF
C1
22uFx2
R３
4.3kΩ
PGND
PGND
C11
4700pF
SGND
Figure 1. QFN
Q1
FDS8878
L1
SPM6530T
1.5uH
C2
0.1uF
1
R1
13.5k
Ω
R2
10kΩ
EN1
PGND1
22
4
VO1
TRIP1
21
VIN
20
R4
3.63kΩ
GND
7
SS1
8
VFB2
Q2
FDS8690
DRVL1 23
VBST1
VFB1
VO1
1.8V/4A
24
3
5
C10
SGND4700pF
SW1
2
6
R5
10kΩ
DRVH1
TPS53127PW
TSSOP24
C3
10uF
C1
22uFx2
R３
4.3kΩ
PGND
Input Voltage
VREG5 19
V5FILT 18
SS2
17
9
VO2
TRIP2 16
10
EN2
PGND2 15
11
VBST2
DRVL2
14
12
DRVH2
SW2
13
C7
4.7uF
4.5V to 24V
C9
10uF
C８
1uF
PGND
C11
4700pF
R6
4.7kΩ
SGND
PGND
Q4
FDS8690
C5
0.1uF
L2
SPM6530T
1.5uH
Q3
FDS8878
C4
22uFx2
C6
10uF
VO2
1.05V/4A
Figure 2. TSSOP
2
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Product Folder Link(s): TPS53127
TPS53127
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SLVSA93 – MARCH 2010
ORDERING INFORMATION (1)
PACKAGE (2)
TA
ORDERING
PART NUMBER
(3)
24
TPS53127PWR
TSSOP
ECO PLAN
Tape-and-Reel
TPS53127RGER
–40°C to 85°C
(2)
(3)
OUTPUT SUPPLY
TPS53127RGET
Plastic Quad
Flat Pack (QFN)
(1)
PINS
Tape-and-Reel
Green
(RoHS and no Sb/Br)
Tape-and-Reel
TPS53127PW
Tube
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
All packaging options have Cu NIPDAU lead/ball finish.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
VI
Input voltage range
UNIT
VIN, EN1, EN2
–0.3 to 26
VBST1, VBST2
–0.3 to 32
VBST1 - SW1, VBST2 - SW2
–0.3 to 6
V5FILT, VFB1, VFB2, TRIP1, TRIP2,
VO1, VO2
–0.3 to 6
SW1, SW2
–2 to 26
DRVH1, DRVH2
–1 to 32
DRVH1 - SW1, DRVH2 - SW2
–0.3 to 6
DRVL1, DRVL2, VREG5, SS1, SS2
–0.3 to 6
V
VO
Output voltage range
TA
Operating ambient temperature range
–40 to 85
°C
TSTG
Storage temperature range
–55 to 150
°C
TJ
Junction temperature range
–40 to 150
°C
PGND1, PGND2
(1)
V
–0.3 to 0.3
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS
2-oz. trace and copper pad with solder
PACKAGE
TA < 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 85°C
POWER RATING
24-pin QFN
2.33 W
23.3 mW/°C
0.93 W
24-pin TSSOP
0.778 W
7.8 mW/°C
0.31 W
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
VIN
VI
Supply input voltage
Input voltage
MAX
VIN
4.5
24
V5FILT
4.5
5.5
VBST1, VBST2
–0.1
30
VBST1 - SW1, VBST2 - SW2
–0.1
5.5
VFB1, VFB2, VO1, VO2
–0.1
5.5
TRIP1, TRIP2
–0.1
0.3
EN1, EN2
–0.1
24
SW1, SW2
–1.8
24
UNIT
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V
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SLVSA93 – MARCH 2010
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RECOMMENDED OPERATING CONDITIONS (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
VO
Output voltage
MAX
DRVH1, DRVH2
–0.1
30
VBST1 - SW1, VBST2 - SW2
–0.1
5.5
DRVL1, DRVL2, VREG5, SS1, SS2
–0.1
5.5
PGND1, PGND2
–0.1
0.1
UNIT
V
TA
Operating free-air temperature
–40
85
°C
TJ
Operating junction temperature
–40
125
°C
TYP
MAX
UNIT
450
800
mA
30
60
mA
1
%
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
SUPPLY CURRENT
IIN
VIN supply current
VIN current, TA = 25°C, VREG5 tied
to V5FILT, EN1 = EN2 = 5 V,
VFB1 = VFB2 = 0.8 V,
SW1 = SW2 = 0.5 V
IVINSDN
VIN shutdown current
VIN current, TA = 25°C,
no load , EN1 = EN2 = 0 V,
VREG5 = ON
VFB VOLTAGE AND DISCHARGE RESISTANCE
VBG
Bandgap initial regulation accuracy
TA = 25°C
TA = 25°C, SWinj = OFF
VVFBTHx
VFBx threshold voltage
TA = 0°C to 70°C,
SWinj = OFF (1)
TA = -40°C to 85°C,
SWinj = OFF (1)
IVFB
VFB input current
VFBx = 0.8 V, TA = 25°C
RDischg
VO discharge resistancee
ENx = 0 V, VOx = 0.5 V, TA = 25°C
–1
748
758
768
746.6
769.4
745
771
–100
mV
–10
100
nA
40
80
Ω
5.0
5.2
V
VREG5 OUTPUT
VVREG5
VREG5 output voltage
TA = 25°C, 5.5 V < VIN < 24 V,
0 < IVREG5 < 10 mA
VLN5
Line regulation
5.5 V < VIN < 24 V, IVREG5 = 10 mA
20
mV
VLD5
Load regulation
1 mA < IVREG5 < 10 mA
40
mV
Output current
VIN = 5.5 V, VREG5 = 4.0 V,
TA = 25°C
IVREG5
4.8
170
mA
OUTPUT: N-CHANNEL MOSFET GATE DRIVERS
RDRVH
DRVH resistance
RDRVL
DRVL resistance
TD
Dead time
Source, IDRVHx = –100 mA
5.5
11
Sink, IDRVHx = 100 mA
2.5
5
Source, IDRVLx = –100 mA
4
8
Sink, IDRVLx = 100 mA
2
4
Ω
Ω
DRVHx-low to DRVLx-on
20
50
80
DRVLx-low to DRVHx-on
20
40
80
Forward voltage
VVREG5-VBSTx, IF = 10 mA, TA = 25°C
0.7
0.8
0.9
V
VBST leakage current
VBSTx = 29 V, SWx = 24 V,
TA = 25°C
0.1
1
mA
ns
INTERNAL BOOST DIODE
VFBST
IVBSTLK
ON-TIME TIMER CONTROL
TON1L
CH1 on time
SW1 = 12 V, VO1 = 1.8 V
165
ns
TON2L
CH2 on time
SW2 = 12 V, VO2 = 1.8 V
140
ns
(1)
4
Not production tested - ensured by design.
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TOFF1L
CH1 min off time
SW1 = 0.7 V, TA = 25°C,
VFB1 = 0.7 V
216
ns
TOFF2L
CH2 min off time
SW2 = 0.7 V, TA = 25°C,
VFB2 = 0.7 V
216
ns
SOFT START
ISSC
SS1/SS2 charge current
VSS1/VSS2 = 0 V, TA = 25°C
TCISSC
ISSC temperature coefficient
On the basis of 25°C (1)
–1.5
–2
ISSD
SS1/SS2 discharge current
VSS1/VSS2 = 0.5 V
100
150
Wake up
3.7
4.0
4.3
Hysteresis
0.2
0.3
0.4
2.0
–4
–2.5
3
mA
nA/°C
mA
UVLO
VUV5VFILT
V5FILT UVLO threshold
V
LOGIC THRESHOLD
VENH
ENx high-level input voltage
EN 1/2
VENL
ENx low-level input voltage
EN 1/2
V
0.3
V
CURRENT SENSE
ITRIP
TRIP source current
VTRIPx = 0.1 V, TA = 25°C
TCITRIP
ITRIP temperature coefficient
On the basis of 25°C
VOCLoff
OCP compensation offset
VRtrip
Current limit threshold setting range
8.5
10
11.5
4000
mA
ppm/°C
(VTRIPx-GND-VPGNDx-SWx) voltage,
VTRIPx-GND = 60 mV, TA = 25°C
–15
(VTRIPx-GND-VPGNDx-SWx) voltage,
VTRIPx-GND = 60 mV
–20
20
30
300
mV
120
%
VTRIPx-GND voltage
0
15
mV
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP
Output OVP trip threshold
TOVPDEL
Output OVP prop delay
VUVP
Output UVP trip threshold
TUVPDEL
Output UVP delay
TUVPEN
Output UVP enable delay
OVP detect
110
UVP detect
65
115
1.5
Hysteresis (recover < 20 ms)
UVP enable delay / soft-start time
70
ms
75
10
%
17
30
40
ms
x1.4
x1.7
x2.0
ms
THERMAL SHUTDOWN
TSDN
(2)
Thermal shutdown threshold
Shutdown temperature
Hysteresis
(2)
(2)
150
20
°C
Not production tested - ensured by design.
TERMINAL FUNCTIONS
PIN Fucntion Table
TERMINAL
NAME
QFN
24
TSSOP
24
I/O
DESCRIPTION
VBST1,
VBST2
23, 8
2, 11
I
Supply input for high-side NFET driver. Bypass to SWx with a high-quality
0.1-mF ceramic capacitor. An external schottky diode can be added from
VREG5 if forward drop is critical to drive the high-side FET.
EN1, EN2
24, 7
3, 10
I
Enable. Pull High to enable SMPS.
VO1, VO2
1, 6
4, 9
I
Output voltage inputs for on-time adjustment and output discharge. Connect
directly to the output voltage.
VFB1,
VFB2
2, 5
5, 8
I
D-CAP2 feedback inputs. Connect to output voltage with resistor divider.
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PIN Fucntion Table (continued)
TERMINAL
QFN
24
TSSOP
24
I/O
3
6
I
Signal ground pin. Connect to PGND1, PGND2 and system ground at a single
point.
DRVH1,
DRVH2
22, 9
1, 12
O
High-side N-Channel MOSFET gate driver outputs. SWx referenced drivers
switch between SWx (OFF) and VBSTx (ON).
SW1, SW2
21, 10
24, 13
I/O
Switch node connections for both the high-side drivers and the over current
comparators.
DRVL1,
DRVL2
20, 11
23, 14
O
Low-side N-Channel MOSFET gate driver outputs. PGND referenced drivers
switch between PGNDx (OFF) and VREG5 (ON).
PGND1,
PGND2
19, 12
22, 15
I/O
Power ground connections for both the low-side drivers and the over current
comparators. Connect PGND1, PGND2 and GND strongly together near the
IC.
TRIP1,
TRIP2
18, 13
21, 16
I
Over current threshold programming pin. Connect to GND with a resistor to
GND to set threshold for low-side RDS(ON) current limit.
VIN
17
20
I
Supply Input for 5-V linear regulator. Bypass to GND with a minimum
high-quality 0.1-mF ceramic capacitor.
V5FILT
15
18
I
5-V supply input for the entire control circuitry except the MOSFET drivers.
Bypass to GND with a minimum high-quality 1.0-mF ceramic capacitor. V5FILT
is connected to VREG5 via an internal 10-Ω resistor.
VREG5
16
19
O
Output of 5-V linear regulator and supply for MOSFET drivers. Bypass to GND
with a minimum high-quality 4.7-mF ceramic capacitor. VREG5 is connected to
V5FILT via an internal 10-Ω resistor.
4,14
7, 17
O
Soft-start programming pin. Connect capacitor from SSx pin to GND to program
soft-start time.
NAME
GND
SS1, SS2
DESCRIPTION
TSSOP PACKAGE
(TOP VIEW)
6
PGND1
DRVH1
VBST1
EN1
VO1
VFB1
GND
19
DRVL1
20
SW1
21
DRVH1
22
VBST1
23
24
EN1
QFN PACKAGE
(TOP VIEW)
SS1
4
15
V5 FILT
VFB2
5
14
SS 2
EN2
VBST2
VO2
6
13
TRIP2
DRVH2
12
VREG5
11
16
DRVL2
3
PGND2
GND
10
VIN
SW2
17
9
2
DRVH2
VFB1
8
TRIP1
VBST2
18
7
1
EN2
VO1
SS1
VFB2
VO2
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1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
SW1
DRVL1
PGND1
TRIP1
VIN
VREG5
V5FILT
SS2
TRIP2
PGND2
DRVL2
SW2
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TPS53127
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SLVSA93 – MARCH 2010
FUNCTIONAL BLOCK DIAGRAM
SS2
SW
SS1
SW
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ERR
COMP
SWx
8
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DETAILED DESCRIPTION
PWM Operation
The main control loop of the TPS53127 is an adaptive on-time pulse width modulation (PWM) controller using a
proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with an internal
compensation circuit for pseudo-fixed frequency and low external component count configuration with both low
ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the synchronous high-side MOSFET is turned on. After an internal one-shot timer
expires, this MOSFET is turned off. When the feedback voltage falls below the reference voltage, the one-shot
timer is reset and the high-side MOSFET is turned back on. The one shot is set by the converter input voltage
VIN, and the output voltage VO, to maintain a pseudo-fixed frequency over the input voltage range. An internal
ramp is added to the reference voltage to simulate output ripple, eliminating the need for ESR induced output
ripple from D-CAP mode control.
Drivers
Each channel of the TPS53127 contains two high-current resistive MOSFET gate drivers. The low-side driver is a
PGND referenced, VREG5 powered driver designed to drive the gate of a high-current, low RDS(ON) N-channel
MOSFET whose source is connected to PGND. The high-side driver is a floating SWx referenced VBST powered
driver designed to drive the gate of a high-current, low RDS(ON) N-channel MOSFET. To maintain the VBST
voltage during the high-side driver ON time, a capacitor is placed from SWx to VBSTx. Each driver draws
average current equal to gate charge (Qg at Vgs = 5 V) times switching frequency (fSW).
To prevent cross-conduction, there is a narrow dead-time when both high-side and low-side drivers are OFF
between each driver transition. During this time the inductor current is carried by one of the MOSFETs body
diodes.
PWM Frequency and Adaptive On-Time Control
TPS53127 employs adaptive on-time control scheme and does not have a dedicated on board oscillator.
TPS53127 runs with pseudo-constant frequency by using the input voltage and output voltage to set the on-time
one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the output voltage.
Therefore, when the duty ratio is VOUT/VIN, the frequency is constant.
5-Volt Regulator
The TPS53127 has an internal 5-V low-dropout (LDO) regulator to provide a regulated voltage for all both drivers
and the IC's internal logic. A high-quality 4.7-mF or greater ceramic capacitor from VREG5 to GND is required to
stabilize the internal regulator. An internal 10-Ω resistor from VREG5 filters the regulator output to the IC's
analog and logic input voltage, V5FILT. An additional high-quality 1.0-mF ceramic capacitor is required from
V5FILT to GND to filter switching noise from VREG5.
Soft Start
The TPS53127 has a programmable soft-start . When the ENx pin becomes high, 2.0-mA current begins charging
the capacitor connected from the SS pin to GND. The internal reference for the D-CAP2™ mode control
comparator is overridden by the soft-start voltage until the soft-start voltage is greater than the internal reference
for smooth control of the output voltage during start up.
Pre-Bias Support
The TPS53127 supports pre-bias start-up without sinking current from the output capacitor. When enabled, the
low-side driver is held off until the soft-start commands a voltage higher than the pre-bias level (internal soft-start
becomes greater than feedback voltage (VFB)), then the TPS53127 slowly activates synchronous rectification by
limiting the first DRVL pulses with a narrow on-time. This limited on-time is then incremented on a cycle-by-cycle
basis until it coincides with the full 1-D off-time. This scheme prevents the initial sinking of current from the
pre-bias output, and ensure that the output voltage (VOUT) starts and ramps up smoothly into regulation and the
control loop is given time to transition from pre-biased start-up to normal mode operation.
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Output Discharge Control
TPS53127 discharges the outputs when ENx is low, or the controller is turned off by the protection functions
(OVP, UVP, UVLO, and thermal shutdown). The device discharges output using an internal 40-Ω MOSFET which
is connected to VOx and PGNDx. The external low-side MOSFET is not turned on during the output discharge
operation to avoid the possibility of causing negative voltage at the output. This discharge ensures that on start
the regulated voltage always initializes from 0 V.
Over Current Limit
TPS53127 has cycle-by-cycle over current limit feature. The over current limits the inductor valley current by
monitoring the voltage drop across the low-side MOSFET RDS(ON) during the low-side driver on-time. If the
inductor current is larger than the over current limit (OCL), the TPS53127 delays the start of the next switching
cycle until the sensed inductor current falls below the OCL current. MOSFET RDS(ON) current sensing is used to
provide an accuracy and cost effective solution without external devices. To program the OCL, the TRIP pin
should be connected to GND through a trip voltage setting resistor, according to the following equations.
(
)
(VIN - VO) VO
VTRIP = IOCL - ¾
· ¾
2 · L1 · fSW VIN
·
RDS(ON)
(1)
VTRIP (mV)
RTRIP (kW) = ¾
ITRIP (mA)
(2)
The trip voltage should be between 30 mV to 300 mV over all operational temperature, including the
4000-ppm/°C temperature slope compensation for the temperature dependency of the RDS(ON).
If the load current exceeds the over current limit, the voltage will begin to drop. If the over current conditions
continues the output voltage will fall below the under voltage protection threshold and the TPS53127 will shut
down.
In an over current condition, the current to the load exceeds the current to the output capacitor; thus the output
voltage tends to fall off. Eventually, it will end up with crossing the under voltage protection threshold and
shutdown.
Over/Under Voltage Protection
TPS53127 monitors a resistor divided feedback voltage to detect over and under voltage. If the feedback voltage
is higher than 115% of the reference voltage, the OVP comparator output goes high and the circuit latches the
high-side MOSFET driver OFF and the low-side MOSFET driver ON.
When the feedback voltage is lower than 70% of the reference voltage, the UVP comparator output goes high
and an internal UVP delay counter begins counting. After 30 ms, TPS53127 latches OFF both top and bottom
MOSFET drivers. This function is enabled approximately 1.7 x TSS after power-on. The OVP and UVP latch off is
reset when EN goes low level.
UVLO Protection
TPS53127 has V5FILT under voltage lock out protection (UVLO) that monitors the voltage of V5FILT pin.
When the V5FILT voltage is lower than UVLO threshold voltage, the device is shut off. All output drivers are OFF
and output discharge is ON. The UVLO is non-latch protection.
Thermal Shutdown
The TPS53127 includes an over temperature protection shut-down feature. If the TPS53127 die temperature
exceeds the OTP threshold (typically 150°C), both the high-side and low-side drivers are shut off, the output
voltage discharge function is enabled and then the device is shut off until the die temperature drops. Thermal
shutdown is a non-latch protection.
10
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TYPICAL CHARACTERISTICS
VIN SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
VIN SHUTDOWN CURRENT
vs
JUNCTION TEMPERATURE
800
60
IVINSDN - Shutdown Current - mA
IIN - Supply Current - mA
700
600
500
400
300
200
50
40
30
20
10
100
VREG5=ON
0
-50
0
50
100
0
-50
150
0
50
TJ - Junction Temperature - °C
100
150
100
150
TJ - Junction Temperature - °C
Figure 3.
Figure 4.
TRIP SOURCE CURRENT
vs
JUNCTION TEMPERATURE
VREG5 VOLTAGE
vs
JUNCTION TEMPERATURE
20
5.070
5.060
VREG5 Voltage - V
ITRIP - Source Current - mA
15
10
5.050
5.040
5.030
5.020
5
5.010
0
-50
0
50
100
150
5.000
-50
0
50
TJ - Junction Temperature - °C
TJ - Junction Temperature - °C
Figure 5.
Figure 6.
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TYPICAL CHARACTERISTICS (continued)
VREG5 VOLTAGE
vs
INPUT VOLTAGE
VFB1 VOLTAGE
vs
JUNCTION TEMPERATURE
0.790
5.500
0.785
0.780
VFB1 Voltage - V
VREG5 Voltage - V
5.300
5.100
4.900
0.775
0.770
0.765
0.760
0.755
0.750
4.700
0.745
0.740
4.500
0
5
10
15
20
25
-50
0
100
Figure 7.
Figure 8.
VFB2 VOLTAGE
vs
JUNCTION TEMPERATURE
VFB1 VOLTAGE
vs
INPUT VOLTAGE
0.790
0.790
0.785
0.785
0.780
0.780
0.775
0.775
0.770
0.765
0.760
0.755
150
0.770
0.765
0.760
0.755
0.750
0.750
0.745
0.745
0.740
0.740
-50
0
50
100
150
0
TJ - Junction Temperature - °C
Figure 9.
12
50
TJ - Junction Temperature - °C
VFB1 Voltage - V
VFB2 Voltage - V
VIN - Input Voltage - V
5
10
15
20
25
VIN - Input Voltage - V
Figure 10.
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TYPICAL CHARACTERISTICS (continued)
VFB2 VOLTAGE
vs
INPUT VOLTAGE
0.790
0.785
VFB2 Voltage - V
0.780
0.775
0.770
0.765
0.760
0.755
0.750
0.745
0.740
0
5
10
15
20
25
VIN - Input Voltage - V
Figure 11.
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APPLICATION INFORMATION
Input Voltage
4.5V to 24V
C9
10uF
C10
4700pF
C5
0.1uF
3
2
1
VFB1
VO1
VO2
VFB2
4
SS1
5
GND
6
SGND
R1
13.5kΩ
7
EN2
8
VBST2
9
DRVH2
10
SW2
21
L1
11
DRVL2
DRVL1 20
12
PGND2
PGND1 19
Q2
FDS8690
EN1
24
VBST1 23
Power PAD
C2
0.1uF
DRVH1 22
TPS53127 RGE
SW1
Q1
FDS8878
L1
SPM6530T
1.5uH
C3
10uF
VO1
1.8V/4A
PGND
VREG5
VIN
TRIP1
C4
22uFx2
V5FILT
(QFN )
Q4
FDS8690
SS2
VO2
1.05V/4A
Q3
FDS8878
L2
SPM6530T
1.5uH
R2
10kΩ
TRIP2
C6
10uF
R5
10kΩ
R4
3.63kΩ
PGND
13
14
15
16
17
18
R6
4.7kΩ
C7
4.7uF
C８
1uF
C1
22uFx2
R３
4.3kΩ
PGND
PGND
C11
4700pF
SGND
Figure 12. TPS53127 Typical Application Circuit
14
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TYPICAL APPLICATION PERFORMANCE
SWITCHING FREQUENCY (IO1 = 3 A)
vs
INPUT VOLTAGE (CH1)
SWITCHING FREQUENCY (IO2 = 3 A)
vs
INPUT VOLTAGE (CH2)
800
800
VO1 = 2.5 V
600
VO1 = 1.8 V
500
VO1 = 1.2 V
400
VO1 = 1.05 V
300
200
700
fSW - Switching Frequency - kHz
VO1 = 3.3 V
fSW - Switching Frequency - kHz
VO2 = 5 V
VO1 = 5 V
700
VO2 = 3.3 V
VO2 = 2.5 V
600
VO2 = 1.8 V
500
VO2 = 1.2 V
400
VO2 = 1.05 V
300
200
100
100
0
0
0
5
10
15
20
0
25
5
10
15
VIN - Input Voltage - V
20
Figure 13.
Figure 14.
SWITCHING FREQUENCY (VIN = 12 V)
vs
OUTPUT CURRENT (CH1)
SWITCHING FREQUENCY (VIN = 12 V)
vs
OUTPUT CURRENT (CH2)
800
800
700
700
fSW - Switching Frequency - kHz
fSW - Switching Frequency - kHz
VIN - Input Voltage - V
600
500
400
300
200
25
600
500
400
300
200
100
100
VO2 = 1.05 V
VO1 = 1.8 V
0
0.0
0.5
0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
IO - Output Current - A
IO - Output Current - A
Figure 15.
Figure 16.
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OUTPUT VOLTAGE (VIN = 12 V)
vs
OUTPUT CURRENT (CH2)
1.850
1.100
1.840
1.090
1.830
1.080
VOUT - Output Voltage - V
VOUT - Output Voltage - V
OUTPUT VOLTAGE (VIN = 12 V)
vs
OUTPUT CURRENT (CH1)
1.820
1.810
1.800
1.790
1.070
1.060
1.050
1.040
1.030
1.780
1.020
1.770
1.010
1.760
VO2 = 1.05 V
1.000
VO1 = 1.8 V
0.0
1.750
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.5
1.0
4.0
1.5
2.0
2.5
3.0
3.5
4.0
IOUT - Output Current - A
Figure 17.
Figure 18.
OUTPUT VOLTAGE (VIN = 12 V)
vs
INPUT VOLTAGE (CH1)
OUTPUT VOLTAGE (VIN = 12 V)
vs
INPUT VOLTAGE (CH2)
1.850
1.100
1.840
1.090
1.830
1.080
VOUT - Output Voltage - V
VOUT - Output Voltage - V
IOUT - Output Current - A
1.820
1.810
1.800
1.790
1.780
1.070
1.060
1.050
1.040
1.030
1.020
1.770
1.010
1.760
VO1 = 1.8 V
VO2 = 1.05 V
1.000
1.750
0
0
5
10
15
20
25
5
10
15
20
25
VIN - Input Voltage - V
VIN - Input Voltage - V
Figure 19.
16
Figure 20.
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LOAD TRANSIENT RESPONSE
LOAD TRANSIENT RESPONSE
VO1 = 1.8 V (50mv/div)
VO2 = 1.05 V (50mv/div)
Iout1 (2A/div)
Iout2 (2A/div)
Figure 21.
Figure 22.
START-UP WAVEFORMS
START-UP WAVEFORMS
EN1 (5V/div)
EN2 (5V/div)
SS1 (0.2V/div)
SS2 (0.2V/div)
VO1 = 1.8 V (0.5V/div)
Figure 23.
VO2 = 1.05 V (0.5V/div)
Figure 24.
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1.05-V EFFICIENCY
vs
OUTPUT CURRENT (CH2)
100
100
80
80
Efficiency - %
Efficiency - %
1.8-V EFFICIENCY
vs
OUTPUT CURRENT (CH1)
60
40
60
40
20
20
VO1 = 1.8 V
VO2 = 1.05 V
0
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.0
0.5
1.5
2.0
2.5
3.0
Figure 25.
Figure 26.
1.8-V OUTPUT RIPPLE VOLTAGE
1.05-V OUTPUT RIPPLE VOLTAGE
VO1 (20mv/div)
VO1 = 1.8 V
3.5
4.0
IOUT - Output Current - A
IOUT - Output Current - A
VO2 (20mv/div)
VO2 = 1.05 V
Figure 27.
18
1.0
Figure 28.
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APPLICATION INFORMATION
1. Choose inductor.
The inductance value is selected to provide approximately 30% peak to peak ripple current at maximum load.
Larger ripple current increases output ripple voltage, improve S/N ratio and contribute to stable operation.
Equation 3 can be used to calculate L1.
L1 =
(VIN(MAX) - VO1) VO1
(VIN(MAX) - VO1)
¾ · ¾ = ¾
IL1(RIPPLE) · fSW VIN(MAX)
0.3 · IO1 · fSW
·
Vo1
¾
VIN(MAX)
(3)
The inductors current ratings needs to support both the RMS (thermal) current and the Peak (saturation)
current. The RMS and peak inductor current can be estimated as follows.
VIN(MAX) - VO1
IL1(RIPPLE) = ¾
L1 · fSW
·
Vo1
¾
VIN(MAX)
(4)
VTRIP
¾
IL1(PEAK) = R
+ IL1(RIPPLE)
DS(ON)
¾
2
1 (I
IL1(RMS) = IO 12 + ¾
)
12 L1(RIPPLE)
(5)
Ö
(6)
Note: The calculation above shall serve as a general reference. To further improve transient response, the
output inductance could be reduced further. This needs to be considered along with the selection of the
output capacitor.
2. Choose output capacitor.
The capacitor value and ESR determines the amount of output voltage ripple and load transient response. it
is recommended to use a ceramic output capacitor.
IL1(RIPPLE)
C1 = ¾
8 · VO1(RIPPLE)
·
1
¾
fSW
(7)
2
D Iload · L1
C1 = ¾
2 · VO1 · DVOS
(8)
2
load ·
L1
DI
C1 = ¾
2 · K · DVUS
(9)
Where
Ton1
K = (VIN - VO 1) · ¾
Ton1 + Tmin(off)
(10)
Select the capacitance value greater than the largest value calculated from Equation 7, Equation 8 and
Equation 9. The capacitance for C1 should be greater than 66 mF.
Where
ΔVOS = The allowable amount of overshoot voltage in load transition
ΔVUS = The allowable amount of undershoot voltage in load transition
Tmin(off) = Minimum off time
3. Choose input capacitor.
The TPS53127 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A minimum 10-mF high-quality ceramic capacitor is recommended for the input capacitor. The
capacitor voltage rating needs to be greater than the maximum input voltage.
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4. Choose bootstrap capacitor.
The TPS53127 requires a bootstrap capacitor from SW to VBST to provide the floating supply for the
high-side drivers. A minimum 0.1-mF high-quality ceramic capacitor is recommended. The voltage rating
should be greater than 10 V.
5. Choose VREG5 and V5FILT capacitor.
The TPS53127 requires both the VREG5 regulator and V5FILT input are bypassed. A minimum 4.7-mF
high-quality ceramic capacitor must be connected between the VREG5 and GND for proper operation. A
minimum 1-mF high-quality ceramic capacitor must be connected between the V5FILT and GND for proper
operation. Both of these capacitors’ voltage ratings should be greater than 10 V.
6. Choose output voltage divider resistors.
The output voltage is set with a resistor divider from the output voltage node to the VFBx pin. It is
recommended to use 1% tolerance or better resisters. Select R2 between 10 kΩ and 100 kΩ and use
Equation 11 or Equation 12 to calculate R1.
Vswinj = (VIN - VO1 · 0.5875) ·
R1 =
( )( )
1
¾
fSW
(
VO1
¾
VIN
·
)
VO 1
-1
¾
VFB(RIPPLE) + Vswinj
VFB + ¾
2
·
·
10127
(11)
R2
(12)
Where
VFB(RIPPLE) = Ripple voltage at VFB
Vswinj = Ripple voltage at error comparator
7. Choose register setting for over current limit.
VTRIP =
(
)
(VIN - VO) VO
·¾
IOCL - ¾
2 · L1 · fSW VIN
·
RDS(ON)
(13)
VTRIP (mV) - VOCLoff
RTRIP (kW) = ¾
ITRIP(min) (mA)
(14)
Where
RDS(ON) = Low side FET on-resistance
ITRIP(min) = TRIP pin source current （8.5 mA）
VOCL0ff = Minimum over current limit offset voltage (–20 mV)
IOCL = Over current limit
8. Choose soft start capacitor.
Soft start time equation is as follows.
TSS · ISSC
CSS = ¾
VFB
20
(15)
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LAYOUT SUGGESTIONS
•
•
•
•
•
•
Keep the input switching current loop as small as possible.
Place the input capacitor (C3,C6) close to the top switching FET. The output current loop should also be kept
as small as possible.
Keep the SW node as physically small and short as possible as to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the
feedback pin (FBx) of the device.
Keep analog and non-switching components away from switching components.
Make a single point connection from the signal ground to power ground.
Do not allow switching current to flow under the device.
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PACKAGE OPTION ADDENDUM
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16-Mar-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
TPS53127PW
PREVIEW
24
TBD
Call TI
Call TI
TPS53127PWR
PREVIEW
24
TBD
Call TI
Call TI
TPS53127RGER
PREVIEW
24
TBD
Call TI
Call TI
TPS53127RGET
PREVIEW
24
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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