TPS2206A www.ti.com SLVS449 – DECEMBER 2002 DUAL-SLOT PC CARD POWER-INTERFACE SWITCH WITH RESET FOR SERIAL PCMCIA CONTROLLER FEATURES APPLICATIONS D Fully Integrated VCC and VPP Switching for D D D D D Dual-Slot PC Card Interface D P2C 3-Lead Serial Interface Compatible With CardBus Controller D Meets PC Card Standard D RESET for System Initialization of PC Cards D 12-V Supplies Can Be Disabled Except During 12-V Flash Programming D Short-Circuit and Thermal Protection D 30-Pin SSOP (DB) D Compatible With 3.3-V, 5-V, AND 12-V PC Cards D Low rDS(on) (95-mΩ, 5-V VCC Switch; 85-mΩ 3.3-V VCC Switch) D Break-Before-Make Switching Notebook and Desktop Computers Set-Top Boxes Personal Digital Assistants(PDAs) Digital Cameras Bar Code Scanners DESCRIPTION The TPS2206A PC CardBus power-interface switch provides an integrated power-management solution for two PC Card sockets. This device allows the controlled distribution of 3.3 V, 5 V, and 12 V to each card slot. The current-limiting and thermal-protection features eliminate the need for fuses. Current-limit reporting helps the user isolate a system fault. The switch rDS(on) and current-limit values are set for the peak and average current requirements stated in the PC Card specification, and are optimized for cost. The TPS2206A is pin and/or functionally compatible with the TPS2206, TPS2216, TPS2216A, TPS2226, TPS2226A, and TPS2228 with a few exceptions, as shown in the Available Options table. AVAILABLE OPTIONS PIN VARIATION PART NUMBER INDEPENDENT VPP SWITCHING RESET RESET SHDN MODE STBY INPUT VOLTAGES TPS2206 No Yes Yes No No No 3.3 V, 5 V, 12 V TPS2206A Yes No Yes No No 3.3 V, 5 V, 12 V Yes Yes No Yes Yes 3.3 V, 5 V, 12 V TPS2216A No Yes/No(1) Yes/No(1) Yes Yes No Yes Yes 3.3 V, 5 V, 12 V TPS2226 Yes Yes No Yes No No 3.3 V, 5 V, 12 V TPS2226A Yes Yes No Yes No No 3.3 V, 5 V, 12 V TPS2228 Yes (1) Selected by MODE pin. Yes No Yes No No 1.8 V, 3.3 V, 5 V TPS2216 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. P2C is a trademark of Texas Instruments. PC Card and CardBus are trademarks of PCMCIA (Personal Computer Memory Card International Association). PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2002, Texas Instruments Incorporated TPS2206A www.ti.com SLVS449 – DECEMBER 2002 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION PACKAGED DEVICE TA PLASTIC SMALL OUTLINE (DB) – 40°C to 85°C TPS2206ADB (1) The DB package is available taped and reeled. Add R suffix to device type (e.g., TPS2206ADBR) for taped and reeled. PACKAGE DISSIPATION RATINGS TA ≤ 25°C POWER RATING DERATING FACTOR TA = 70°C TA = 85°C ABOVE TA = 25°C POWER RATING POWER RATING DB (30) 821.46 mW 10.95 mW/°C 328.58 164.29 (1) These devices are mounted on an JEDEC low-k board (2-oz. traces on surface). PACKAGE(1) ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) UNITS Input In ut voltage range for card power ower VI(3.3V) VI(5V) – 0.3 V to 5.5 V – 0.3 V to 5.5 V VI(12V) – 0.3 V to 14 V – 0.3 V to 6 V – 0.3 V to 6 V – 0.3 V to 14 V Logic input/output voltage Output voltage VO(xVCC) VO(xVPP) Continuous total power dissipation Output current See Dissipation Rating Table IO(xVCC) IO(xVPP) Internally Limited Internally Limited Operating virtual junction temperature range, TJ – 40°C to 100 °C Storage temperature range, TSTG – 55°C to 150 °C 260 °C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds) OC sink current 10 mA (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS IInputt voltage, lt VI(3.3V) is i required i d ffor allll circuit i it operations. ti 5 V and d 12 V are only required for their respective functions. functions O t t current, Output t IO MIN MAX VI(3.3V)(1) VI(5V) 3 3.6 3 5.5 VI(12V) IO(xVCC) at TJ = 100°C 7 13.5 1 IO(xVPP) at TJ = 100°C Clock frequency, f(clock) Pulse duration duration, tw Data 200 Latch 250 Clock 100 Reset 100 UNIT V A 100 mA 2.5 MHz ns Data-to-clock hold time, th (see Figure 2) 100 ns Data-to-clock setup time, tsu (see Figure 2) 100 ns Latch delay time, td(latch) (see Figure 2) 100 ns Clock delay time, td(clock) (see Figure 2) 250 ns Operating virtual junction temperature, TJ (maximum to be calculated at worst case PD at 85°C ambient) –40 100 °C (1) It is understood that for VI(3.3V)< 3 V, voltages within the absolute maximum ratings applied to pin 5 V or pin 12 V will not damage the IC. 2 TPS2206A www.ti.com SLVS449 – DECEMBER 2002 ELECTRICAL CHARACTERISTICS TJ = 25°C, VI(5V) = 5 V, VI(3.3V) = 3.3 V, VI(12V) = 12 V, all outputs unloaded (unless otherwise noted) POWER SWITCH PARAMETER TEST CONDITIONS(1) rDS(on) Static drainsource on-state on state resistance Out ut discharge Output resistance IOS 3.3V to xVCC , with two switches on IO = 750 mA each IO = 750 mA each, 5V to xVCC , with two switches on IO = 500 mA each IO = 500 mA each, 3.3V or 5V to xVPP , with two switches on IO = 50 mA each IO = 50 mA each, 12V to xVPP , with two switches on IO = 50 mA each IO = 50 mA each, Discharge at xVCC IO(disc) = 1 mA IO(disc) = 1 mA Discharge at xVPP Short circuit output current Short-circuit Thermal shutdown temperature(2) Thermal trip point, TJ In ut current, Input quiescent Shutdown Sh td mode Ilkg Leakage current, output off state TJ = 100°C TJ = 100°C TJ = 100°C Shutdown mode TYP MAX 85 110 110 140 95 130 120 160 0.8 1 1 1.3 2 2.5 2.5 3.4 0.5 0.7 1 0.2 0.4 0.5 Limit (steady-state value), output powered into a short circuit IOS(xVCC) 1 1.4 2 IOS(xVPP) 120 200 300 Limit (steady-state value), output powered into a short circuit, TJ = 100°C Rising temperature IOS(xVCC) 1 1.4 2 IOS(xVPP) 120 200 300 135 II(3.3V) II(5V) 5V to xVCC = 5 V, with 100-mΩ short to GND 10 5V to xVPP = 5 V, with 100-mΩ short to GND 3 140 VO(xVCC) ( VCC) = VO(xVPP) ( VPP) = 3.3 3 3 V and d also for RESET = 0 V II(12V) II(3.3V) II(5V) II(12V) VO(xVCC) = VO(xVPP) = Hi-Z Hi Z VO(xVCC) = 5 V, VI(5V) = VI(12V) = 0 V VO(xVPP) = 12 V, VI(5V) = VI(12V) = 0 V mΩ Ω kΩ A mA A mA µss 200 8 12 100 180 0.3 2 0.1 2 0.3 UNIT °C 10 Current limit response time (2)(3) Current-limit II TJ = 100°C Hysteresis, TJ Normall N operation MIN µA A 2 10 TJ = 100°C 50 10 µA A TJ = 100°C 50 (1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately. (2) Specified by design; not tested in production. (3) From application of short to 110% of final current limit. 3 TPS2206A www.ti.com SLVS449 – DECEMBER 2002 ELECTRICAL CHARACTERISTICS Continued TJ = 25°C, VI(5V) = 5 V, VI(3.3V) = 3.3 V, VI(12V) = 12 V, all outputs unloaded (unless otherwise noted) LOGIC SECTION (CLOCK, DATA, LATCH, RESET, SHDN, OC) PARAMETER TEST CONDITIONS RESET = 5.5 V II(RESET)(1) II Input In ut current, logic RESET = 0 V SHDN = 5.5 V II(SHDN) (S )(1) SHDN = 0 V TYP –1 –30 II(CLOCK, DATA) MAX –20 –10 –1 1 –50 –3 µA 50 LATCH = 0 V –1 1 0 V to 5.5 V –1 1 High-level input voltage, logic UNIT 1 LATCH = 5.5 V II(LATCH)(1) VIH VIL MIN 2 V Low-level input voltage, logic VO(sat) Output saturation voltage at OC IO = 2 mA Ilkg Leakage current at OC VO(/OC) = 5.5 V (1) LATCH has low current pulldown. RESET and SHDN have low-current pullup. 0.8 V 0.14 0.4 V 0 1 µA TYP MAX 2.7 2.9 UVLO AND POR (POWER-ON RESET) PARAMETER TEST CONDITIONS VI(3.3V) Vhys(3.3V) Input voltage at 3.3V pin, UVLO UVLO hysteresis voltage at VA (1) 3.3-V level below which all switches are Hi-Z VI(5V) Vhys(5V) Input voltage at 5V pin, UVLO 5-V level below which only 5V switches are Hi-Z tdf Delay time for falling response, UVLO(1) Delay from voltage hit (step from 3 V to 2.3 V) to Hi-Z control (90% VG to GND) Input voltage, power-on reset(1) 3.3-V voltage below which POR is asserted causing a RESET internally with all line switches open and all discharge switches closed. VI(POR) 4 2.4 100 UVLO hysteresis voltage at 5 V(1) (1) Specified by design; not tested in production. MIN 2.3 2.5 UNIT V mV 2.9 V 100 mV 4 µs 1.7 V TPS2206A www.ti.com SLVS449 – DECEMBER 2002 SWITCHING CHARACTERISTICS VCC = 5 V, TA = 25°C, VI(3.3V) = 3.3 V, VI(5V) = 5 V, VI(12) = 12 V (not applicable for TPS2223A) all outputs unloaded (unless otherwise noted) PARAMETER(1) LOAD CONDITION MIN TYP MAX UNIT TEST CONDITIONS(2) tr tf Output rise times(3) Output fall times(3) CL(xVCC)= 0.1 µF, CL(xVPP)= 0.1 µF, IO(xVCC) = 0 A, IO(xVPP) = 0 A VO(xVCC) = 5 V VO(xVPP) = 12 V CL(xVCC)= 150 µF, CL(xVPP)= 10 µF, IO(xVCC) = 0.75 A, IO(xVPP) = 50 mA VO(xVCC) = 5 V VO(xVPP) = 12 V CL(xVCC)= 0.1 µF, CL(xVPP)= 0.1 µF, IO(xVCC) = 0 A, IO(xVPP) = 0 A CL(xVCC)= 150 µF, CL(xVPP)= 10 µF, IO(xVCC) = 0.75 A, IO(xVPP) = 50 mA CL(xVCC)= 0.1 µF, CL(xVPP)= 0.1 µF, IO(xVCC) = 0 A, IO(xVPP) = 0 A tpd 1.1 ms 0.6 VO(xVCC) = 5 V, Discharge switches ON 0.5 VO(xVPP) = 12 V, Discharge switches ON 0.2 VO(xVCC) = 5 V VO(xVPP) = 12 V ms 2.35 3.9 Latch↑ to xVPP (12 V) tpdon tpdoff tpdon tpdoff 0.77 Latch↑ to xVPP (5 V) 0.75 Latch↑ to xVPP (3.3 (3 3 V) tpdon tpdoff tpdon tpdoff 0.3 Latch↑ to xVCC (5 V) tpdon tpdoff 0.3 Latch↑ to xVCC (3.3V) (3 3V) tpdon tpdoff 2.2 Latch↑ to xVPP (12 V) 0.8 Latch↑ to xVPP (5 V) tpdon tpdoff 0.8 Latch↑ to xVPP (3.3 (3 3 V) tpdon tpdoff tpdon tpdoff 0.6 Latch↑ to xVCC (5 V) 0.5 Latch↑ to xVCC (3.3V) (3 3V) tpdon tpdoff Pro agation delay Propagation times(3) CL(xVCC)= 150 µF, CL(xVPP)= 10 µF, IO(xVCC) = 0.75 A, IO(xVPP) = 50 mA 0.9 0.26 2 0.62 0.51 0.52 ms 2.5 2.8 0.8 0.6 0.6 ms 2.5 2.6 (1) Refer to Parameter Measurement Information in Figure 1. (2) No card inserted, assumes a 0.1-µF output capacitor (see Figure 1). (3) Specified by design; not tested in production. 5 TPS2206A www.ti.com SLVS449 – DECEMBER 2002 PIN ASSIGNMENTS DB PACKAGE (TOP VIEW) 5V 1 5V 2 DATA 3 CLOCK 4 LATCH 5 NC 6 12V 7 AVPP 8 AVCC 9 AVCC 10 AVCC 11 GND 12 NC 13 RESET 14 3.3V 15 NC – No internal connection 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5V NC NC NC NC SHDN 12V BVPP BVCC BVCC BVCC NC OC 3.3V 3.3V TERMINAL FUNCTIONS TERMINAL NAME 3.3V NO. I/O DESCRIPTION 15, 16, 17 I 3.3-V input for card power and chip power 5V 1, 2, 30 I 5-V VCC input for card power 12V 7, 24 I 12-V VPP input for card power (xVPP). The two 12-V pins must be externally connected. AVCC 9, 10, 11 O Switched output that delivers 0 V, 3.3 V, 5 V, or high impedance to card. AVPP 8 O Switched output that delivers 0 V, 3.3 V, 5 V, 12 V, or high impedance to card. BVCC 20, 21, 22 O Switched output that delivers 0 V, 3.3 V, 5 V, or high impedance. BVPP 23 O Switched output that delivers 0 V, 3.3 V, 5 V, 12 V, or high impedance. CLOCK 4 I Logic-level clock for serial data word DATA 3 I Logic-level serial data word GND 12 LATCH 5 Ground I Logic-level latch for serial data word, internal pulldown NC 13, 19, 25, 26– 29 OC 18 O Open-drain overcurrent reporting output that goes low when an overcurrent condition exists. An external pullup is required. SHDN 25 I Hi-Z (open) all switches. Identical function to serial D8. Asynchronous active-low command, internal pullup RESET 14 I Logic-level RESET input active low. Do not connect if terminal 6 is used. No internal connection TYPICAL PC CARD POWER–DISTRIBUTION APPLICATION Power Supply TPS2206A 12 V 12 V AVPP 5V 3.3 V 5V 3.3 V AVCC RESET SHDN Supervisor 3 PCMCIA Controller 6 VPP1 VPP2 PC VCC Card A AVCC AVCC VCC BVPP VPP1 VPP2 PC VCC Card b Serial Interface BVCC BVCC BVCC OC VCC TPS2206A www.ti.com SLVS449 – DECEMBER 2002 PARAMETER MEASUREMENT INFORMATION xVPP xVCC IO(xVPP) IO(xVCC) LOAD CIRCUIT (xVPP) LATCH LOAD CIRCUIT (xVCC) VDD 50% LATCH VDD 50% GND GND tpd(off) tpd(on) tpd(on) VI(12V/5V/3.3V) 90% VO(xVPP) Propagation Delay (xVCC) tf tr VI(12V/5V/3.3V) VI(5V/3.3V) VO(xVCC) 90% 90% GND 10% GND 10% Rise/Fall Time (xVCC) Rise/Fall Time (xVPP) VDD 50% GND 10% tf LATCH 90% GND Propagation Delay (xVPP) VO(xVPP) VI(5V/3.3V) VO(xVCC) 10% tr tpd(off) VDD 50% LATCH GND GND toff ton VI(12V/5V/3.3V) VO(xVPP) toff ton VI(5V/3.3V) VO(xVCC) 90% 90% GND 10% 10% Turnon/off Time (xVPP) GND Turnon/off Time (xVCC) VOLTAGE WAVEFORMS Figure 1. Test Circuits and Voltage Waveforms DATA D8 D7 D6 D5 D4 D3 D2 D1 D0 LATCH CLOCK NOTE: Data is clocked in on the positive edge of the clock. The latch should occur before the next positive leading edge of the clock. For definition of D0to D8, see the control logic table. Figure 2. Serial-Interface Timing for TPS2206A 7 TPS2206A www.ti.com SLVS449 – DECEMBER 2002 TABLE OF GRAPHS FIGURE Short-circuit response, short applied to powered-on 5-V xVCC-switch output vs Time 3 Short-circuit response, short applied to powered-on 12-V xVPP-switch output vs Time 4 OC response with ramped overcurrent-limit load on 5-V xVCC-switch output vs Time 5 OC response with ramped overcurrent-limit load on 12-V xVPP-switch output vs Time 6 Turnon propagation delay time, xVCC (CL = 150 µF) vs Junction temperature 7 Turnoff propagation delay time, xVCC (CL = 150 µF) vs Junction temperature 8 Turnon propagation delay time, xVPP (CL = 10 µF) vs Junction temperature 9 Turnoff propagation delay time, xVPP (CL = 10 µF) vs Junction temperature 10 Turnon propagation delay time, xVCC (TJ = 25°C) vs Load capacitance 11 Turnoff propagation delay time, xVCC (TJ = 25°C) vs Load capacitance 12 Turnon propagation delay time, xVPP (TJ = 25°C) vs Load capacitance 13 Turnoff propagation delay time, xVPP (TJ = 25°C) vs Load capacitance 14 Rise time, xVCC (CL = 150 µF) vs Junction temperature 15 Fall time, xVCC (CL = 150 µF) vs Junction temperature 16 Rise time, xVPP (CL = 10 µF) vs Junction temperature 17 Fall time, xVPP (CL = 10 µF) vs Junction temperature 18 Rise time, xVCC (TJ = 25°C) vs Load capacitance 19 Fall time, xVCC (TJ = 25°C) vs Load capacitance 20 Rise time, xVPP (TJ = 25°C) vs Load capacitance 21 Fall time, xVPP (TJ = 25°C) vs Load capacitance 22 SHORT-CIRCUIT RESPONSE, SHORT APPLIED TO POWERED-ON 5-V xVCC-SWITCH OUTPUT vs TIME SHORT-CIRCUIT RESPONSE, SHORT APPLIED TO POWERED-ON 12-V xVPP-SWITCH OUTPUT vs TIME VO(/OC) 5 V/div VO(/OC) 2 V/div VIN(5V) 2 V/div IO(xVPP) 2 A/div IO(VCC) 5 A/div 0 100 200 300 t – Time – µs Figure 3 8 400 500 0 1 2 3 t – Time – ms Figure 4 4 5 TPS2206A www.ti.com SLVS449 – DECEMBER 2002 OC RESPONSE WITH RAMPED OVERCURRENT-LIMIT LOAD ON 5-V xVCC-SWITCH OUTPUT vs TIME OC RESPONSE WITH RAMPED OVERCURRENT-LIMIT LOAD ON 12-V xVPP-SWITCH OUTPUT vs TIME VO(/OC) 5 V/div VO(/OC) 5 V/div IO(xVCC) 1 A/div IO(xVPP) 100 mA/div 0 10 20 30 40 50 0 6 Figure 5 Figure 6 0.8 xVCC = 5 V IO = 0.75 A CL = 150 µF 0.7 0.6 0.5 0.4 0.3 0.2 0.1 –20 10 40 70 TJ – Junction Temperature – °C Figure 7 100 8 10 TURNOFF PROPAGATION DELAY TIME, xVCC vs JUNCTION TEMPERATURE t pd(off) – Turnoff Propagation Delay Time, xVCC – ms t pd(on) – Turnon Propagation Delay Time, xVCC – ms 4 t – Time – ms TURNON PROPAGATION DELAY TIME, xVCC vs JUNCTION TEMPERATURE 0 –50 2 t – Time – ms 2.6 xVCC = 5 V IO = 0.75 A CL = 150 µF 2.55 2.5 2.45 2.4 2.35 2.3 2.25 –50 –20 10 40 70 TJ – Junction Temperature – °C 100 Figure 8 9 TPS2206A www.ti.com SLVS449 – DECEMBER 2002 TURNOFF PROPAGATION DELAY TIME, xVPP vs JUNCTION TEMPERATURE 3 xVPP = 12 V IO = 0.05 A CL = 10 µF 2.5 2 1.5 1 0.5 0 –50 –20 10 40 70 TJ – Junction Temperature – °C 100 t pd(off) – Turnoff Propagation Delay Time, xVCC – ms t pd(on) – Turnon Propagation Delay Time, xVPP – ms TURNON PROPAGATION DELAY TIME, xVPP vs JUNCTION TEMPERATURE 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.1 0 –50 Figure 9 xVCC = 5 V IO = 0.75 A TJ = 25°C 0.5 0.4 0.3 0.2 0.1 0.1 1 10 100 CL – Load Capacitance – µF Figure 11 10 100 1000 TURNOFF PROPAGATION DELAY TIME, xVCC vs LOAD CAPACITANCE t pd(off) – Turnoff Propagation Delay Time, xVCC – ms t pd(on) – Turnon Propagation Delay Time, xVCC – ms 0.7 0 –20 10 40 70 TJ – Junction Temperature – °C Figure 10 TURNON PROPAGATION DELAY TIME, xVCC vs LOAD CAPACITANCE 0.6 xVCC = 12 V IO = 0.05 A CL = 10 µF 0.2 2.55 2.5 xVCC = 5 V IO = 0.75 A TJ = 25°C 2.45 2.4 2.35 2.3 2.25 0.1 1 10 100 CL – Load Capacitance – µF Figure 12 1000 TPS2206A www.ti.com SLVS449 – DECEMBER 2002 TURNOFF PROPAGATION DELAY TIME, xVPP vs LOAD CAPACITANCE 2.25 2.2 xVPP = 12 V IO = 0.05 A TJ = 25°C 2.15 2.1 2.05 2 1.95 0.1 1 CL – Load Capacitance – µF 10 t pd(off) – Turnoff Propagation Delay Time, xVPP – ms t pd(on) – Turnon Propagation Delay Time, xVPP – ms TURNON PROPAGATION DELAY TIME, xVPP vs LOAD CAPACITANCE 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.1 Figure 13 1 CL – Load Capacitance – µF 10 Figure 14 FALL TIME, xVCC vs JUNCTION TEMPERATURE RISE TIME, xVCC vs JUNCTION TEMPERATURE 1.22 2.41 xVCC = 5 V IO = 0.75 A CL = 150 µF 1.18 2.4 t f – Fall Time xVCC – ms 1.2 t r – Rise Time, xVCC – ms xVPP = 12 V IO = 0.05 A TJ = 25°C 1.16 1.14 1.12 1.1 xVCC = 5 V IO = 0.75 A CL = 150 µF 2.39 2.38 2.37 2.36 1.08 2.35 1.06 1.04 –50 –20 10 40 70 TJ – Junction Temperature – °C Figure 15 100 2.34 –50 –20 10 40 70 TJ – Junction Temperature – °C 100 Figure 16 11 TPS2206A www.ti.com SLVS449 – DECEMBER 2002 FALL TIME, xVPP vs JUNCTION TEMPERATURE RISE TIME, xVPP vs JUNCTION TEMPERATURE 4.15 0.605 xVPP = 12 V IO = 0.05 A CL = 10 µF t f – Fall Time, xVPP – ms t r – Rise Time xVPP – ms 0.6 4.1 0.595 0.59 0.585 4.05 4 3.95 3.9 0.58 0.575 –50 xVPP = 12 V IO = 0.05 A CL = 10 µF –20 10 40 70 TJ – Junction Temperature – °C 3.85 –50 100 –20 10 40 70 TJ – Junction Temperature – °C Figure 17 Figure 18 FALL TIME, xVCC vs LOAD CAPACITANCE RISE TIME, xVCC vs LOAD CAPACITANCE 1.2 2.5 t f – Fall Time xVCC – ms t r – Rise Time, xVCC – ms 1 0.8 0.6 0.4 xVCC = 5 V IO = 0.75 A TJ = 25°C 0.2 0 0.1 1 10 100 CL – Load Capacitance – µF Figure 19 12 100 xVCC = 5 V IO = 0.75 A TJ = 25°C 2 1.5 1 0.5 1000 0 0.1 1 10 100 CL – Load Capacitance – µF Figure 20 1000 TPS2206A www.ti.com SLVS449 – DECEMBER 2002 FALL TIME, xVPP vs LOAD CAPACITANCE RISE TIME, xVPP vs LOAD CAPACITANCE 4.5 0.7 4 t f – Fall Time, xVPP – ms t r – Rise Time, xVPP – ms 0.6 xVPP = 12 V IO = 0.05 A TJ = 25°C 0.5 0.4 0.3 0.2 xVPP = 12 V IO = 0.05 A TJ = 25°C 3.5 3 2.5 2 1.5 1 0.1 0 0.1 0.5 1 CL – Load Capacitance – µF Figure 21 10 0 0.1 1 CL – Load Capacitance – µF 10 Figure 22 13 TPS2206A www.ti.com SLVS449 – DECEMBER 2002 TYPICAL CHARACTERISTICS TABLE OF GRAPHS FIGURE Input current, xVCC = 3.3 V 23 Input current, xVCC = 5 V II vs Junction tem temperature erature 25 Static drain-source on-state resistance, 3.3 V to xVCC switch 26 Static drain-source on-state resistance, 5 V to xVCC switch rDS(on) vs Junction tem temperature erature Static drain-source on-state resistance, 12 V to xVPP switch 29 xVCC switch voltage drop, 5-V input vs Load current xVPP switch voltage drop, 12-V input 32 Short-circuit current limit, 5 V to xVCC vs Junction tem temperature erature Short-circuit current limit, 12 V to xVPP INPUT CURRENT, xVCC = 5 V vs JUNCTION TEMPERATURE 14 180 I I – Input Current, xVCC = 5 V – µ A 160 I I – Input Current, xVCC = 3.3 V – µ A 33 34 INPUT CURRENT, xVCC = 3.3 V vs JUNCTION TEMPERATURE 140 120 100 80 60 40 12 10 8 6 4 2 20 0 –50 –20 10 40 70 TJ – Junction Temperature – °C Figure 23 14 30 31 Short-circuit current limit, 3.3 V to xVCC IOS 27 28 xVCC switch voltage drop, 3.3-V input VO 24 Input current, xVPP = 12 V 100 0 –50 –20 10 40 70 TJ – Junction Temperature – °C Figure 24 100 TPS2206A www.ti.com SLVS449 – DECEMBER 2002 STATIC DRAIN-SOURCE ON-STATE RESISTANCE, 3.3 V TO xVCC SWITCH vs JUNCTION TEMPERATURE rDS(on) – Static Drain-Source On-State Resistance, 3.3 V to xVCC Switch – Ω INPUT CURRENT, xVPP = 12 V vs JUNCTION TEMPERATURE I I – Input Current, xVPP = 12 V – µ A 120 100 80 60 40 20 0 –50 –20 10 40 70 TJ – Junction Temperature – °C 100 0.12 0.1 0.08 0.06 0.04 0.02 0 –50 Figure 25 STATIC DRAIN-SOURCE ON-STATE RESISTANCE, 12 V TO xVPP SWITCH vs JUNCTION TEMPERATURE rDS(on) – Static Drain-Source On-State Resistance, 12 V to xVPP Switch – Ω rDS(on) – Static Drain-Source On-State Resistance, 5 V to xVCC Switch – Ω 0.14 0.12 0.1 0.08 0.06 0.04 0.02 –20 10 40 70 TJ – Junction Temperature – °C Figure 27 100 Figure 26 STATIC DRAIN-SOURCE ON-STATE RESISTANCE, 5 V TO xVCC SWITCH vs JUNCTION TEMPERATURE 0 –50 –20 10 40 70 TJ – Junction Temperature – °C 100 3 2.5 2 1.5 1 0.5 0 –50 –20 10 40 70 TJ – Junction Temperature – °C 100 Figure 28 15 TPS2206A www.ti.com SLVS449 – DECEMBER 2002 xVCC SWITCH VOLTAGE DROP, 5-V INPUT vs LOAD CURRENT xVCC SWITCH VOLTAGE DROP, 3.3-V INPUT vs LOAD CURRENT 0.14 0.1 VO – xVCC Switch Voltage Drop, 5-V Input – V VO – xVCC Switch Voltage Drop, 3.3-V Input – V 0.12 TJ = 100°C 0.08 TJ = 0°C TJ = 25°C 0.06 TJ = –40°C 0.04 TJ = 85°C 0.02 0 0.12 TJ = 0°C 0.08 TJ = 25°C 0.06 TJ = –40°C 0.04 0.2 0.4 0.6 IL – Load Current – A 0.8 TJ = 85°C 0.02 0 0 TJ = 100°C 0.1 1 0 Figure 29 0.12 TJ = 100°C TJ = 0°C TJ = 25°C 0.06 0.04 TJ = –40°C 0.02 0 TJ = 85°C 0 0.01 0.02 0.03 IL – Load Current – A Figure 31 16 0.8 1 0.04 0.05 SHORT-CIRCUIT CURRENT LIMIT, 3.3 V TO xVCC vs JUNCTION TEMPERATURE I OS – Short-Circuit Current Limit, 3.3 V to xVCC – A VO – xVPP Switch Voltage Drop, 12-V Input – V 0.14 0.08 0.4 0.6 IL – Load Current – A Figure 30 xVPP SWITCH VOLTAGE DROP, 12-V INPUT vs LOAD CURRENT 0.1 0.2 1.395 1.39 1.385 1.38 1.375 1.37 1.365 1.36 1.355 –50 –20 10 40 70 TJ – Junction Temperature – °C Figure 32 100 TPS2206A www.ti.com SLVS449 – DECEMBER 2002 1.435 1.43 1.425 1.42 1.415 1.41 1.405 1.4 1.395 1.39 1.385 –50 SHORT-CIRCUIT CURRENT LIMIT, 12 V TO xVPP vs JUNCTION TEMPERATURE I OS – Short-Circuit Current Limit, 12 V to xVPP – A I OS – Short-Circuit Current Limit, 5 V to xVCC – A SHORT-CIRCUIT CURRENT LIMIT, 5 V TO xVCC vs JUNCTION TEMPERATURE –20 10 40 70 TJ – Junction Temperature – °C Figure 33 100 0.208 0.206 0.204 0.202 xVPP = 12 V 0.2 0.198 0.196 0.194 0.192 0.19 –50 –20 10 40 70 TJ – Junction Temperature – °C 100 Figure 34 17 TPS2206A www.ti.com SLVS449 – DECEMBER 2002 APPLICATION INFORMATION OVERVIEW PC Cards were initially introduced as a means to add flash memory to portable computers. The idea of add-in cards quickly took hold, and modems, wireless LANs, global positioning satellite system (GPS), multimedia, and hard-disk versions were soon available. As the number of PC Card applications grew, the engineering community quickly recognized the need for a standard to ensure compatibility across platforms. To this end, the PCMCIA (Personal Computer Memory Card International Association) was established, comprising members from leading computer, software, PC Card, and semiconductor manufacturers. One key goal was to realize the plug-and-play concept, so that cards and hosts from different vendors would be transparently compatible. PC CARD POWER SPECIFICATION System compatibility also means power compatibility. The most current set of specifications (PC Card Standard) set forth by the PCMCIA committee states that power is to be transferred between the host and the card through eight of the 68 terminals of the PC Card connector. This power interface consists of two VCC, two Vpp, and four ground terminals. Multiple VCC and ground terminals minimize connector-terminal and line resistance. The two Vpp terminals were originally specified as separate signals, but are normally tied together in the host to form a single node to minimize voltage losses. Card primary power is supplied through the VCC terminals; flash-memory programming and erase voltage are supplied through the Vpp terminals. DESIGNING FOR VOLTAGE REGULATION The current PCMCIA specification for output voltage regulation, VO(reg), of the 5-V output is 5% (250 mV). In a typical PC power-system design, the power supply has an output-voltage regulation, VPS(reg), of 2% (100 mV). Also, a voltage drop from the power supply to the PC Card results from resistive losses, VPCB, in the PCB traces and the PCMCIA connector. A typical design would limit the total of these resistive losses to less than 1% (50 mV) of the output voltage. Therefore, the allowable voltage drop, VDS, for the TPS2206A would be the PCMCIA voltage regulation less the power supply regulation and less the PCB and connector resistive drops: V DS +V O(reg) –V PS(reg) –V PCB Typically, this would leave 100 mV for the allowable voltage drop across the TPS2206A. The voltage drop is the output current multiplied by the switch resistance of the TPS2206A. Therefore, the maximum output current, IO max, that can be delivered to the PC Card in regulation is the allowable voltage drop across the TPS2206A, divided by the output-switch resistance. V I max + r DS O DS(on) The xVCC outputs have been designed to deliver the peak and average currents defined by the PC Card specification within regulation over the operating temperature range. The xVPP outputs of the TPS2206A have been designed to deliver 100 mA continuously. 18 TPS2206A www.ti.com SLVS449 – DECEMBER 2002 OVERCURRENT AND OVERTEMPERATURE PROTECTION PC Cards are inherently subject to damage that can result from mishandling. Host systems require protection against short-circuited cards that could lead to power-supply or PCB trace damage. Even extremely robust systems could undergo rapid battery discharge into a damaged PC Card, resulting in the rather sudden and unacceptable loss of system power. The reliability of fused systems is poor, in comparison, as blown fuses require troubleshooting and repair, usually by the manufacturer. The TPS2206A takes a two-pronged approach to overcurrent protection. Overcurrent protection is designed to activate if an output is shorted or when an overcurrent condition is present when switches are powered up. First, instead of fuses, sense FETs monitor each of the xVCC and xVPP power outputs. Unlike sense resistors or polyfuses, these FETs do not add to the series resistance of the switch; therefore voltage and power losses are reduced. Overcurrent sensing is applied to each output separately. Excessive current generates an error signal that limits the output current of only the affected output, preventing damage to the host. Each xVCC output overcurrent limits from 1 A to 2.2 A, typically around 1.6 A; the xVPP outputs limit from 100 mA to 250 mA, typically around 200 mA. Second, when an overcurrent condition is detected, the TPS2206A asserts an active low OC signal that can be monitored by the microprocessor or controller to initiate diagnostics and/or send the user a warning message. If an overcurrent condition persists, causing the IC to exceed its maximum junction temperature, thermal-protection circuitry activates, shutting down all power outputs until the device cools to within a safe operating region, which is ensured by a thermal shutdown hysteresis. Thermal limiting prevents destruction of the IC from overheating beyond the package power-dissipation ratings. During power up, the devices control the rise times of the xVCC and xVPP outputs and limit the inrush current into a large load capacitance, faulty card, or connector. 12-V SUPPLY NOT REQUIRED Some PC Card switches use the externally supplied 12 V to power gate drive and other chip functions, which requires that power be present at all times. The TPS2206A offers considerable power savings by using an internal charge pump to generate the required higher gate drive voltages from the VA input (3.3 V). Therefore, the external 12-V supply can be disabled except when needed by the PC Card in the slot, thereby extending battery lifetime. A special feature in the 12-V circuitry actually helps to reduce the supply current demanded from the 3.3-V input. When 12 V is supplied and requested at the Vpp output, a voltage selection circuit draws the charge-pump drive current for the 12-V FETs from the 12-V input. This selection is automatic and effectively reduces demand fluctuations on the normal 3.3-V VCC rail. For proper operation of this feature, a minimum 3.3-V input capacitance of 4.7 µF is recommended, and a minimum 12-V input ramp-up rate of 12 V/50 ms (240 V/s) is required. Additional power savings are realized by theTPS2206A during a software shutdown in which quiescent current drops to a maximum of 1 µA. BACKWARD COMPATIBILITY The TPS2206A is backward compatible with the TPS2206 product, with the following considerations. An active low /SHDN is added to provide fast shutdown capability. Also, the TPS2206A does not have the active–high RESET input, which is left as no connect. 3.3–V input is required for device operation of TPS2206A. VOLTAGE-TRANSITIONING REQUIREMENT PC Cards, like portables, are migrating from 5 V to 3.3 V to minimize power consumption, optimize board space, and increase logic speeds. The TPS2206A meets all combinations of power delivery as currently defined in the PCMCIA standard. The latest protocol accommodates mixed 3.3-V/5-V systems by first powering the card with 5 V, then polling it to determine its 3.3-V compatibility. The PCMCIA specification requires that the capacitors on 3.3-V-compatible cards be discharged to below 0.8 V before applying 3.3-V power. This action ensures that sensitive 3.3-V circuitry is not subjected to any residual 5-V charge and functions as a power RESET. PC Card specification requires that VCC be discharged within 100 ms. PC Card resistance cannot be relied on to provide a discharge path for voltages stored on PC Card capacitance because of possible high-impedance isolation by power-management schemes. The devices include discharge transistors on all xVCC and xVPP outputs to meet the specification requirement. 19 TPS2206A www.ti.com SLVS449 – DECEMBER 2002 SHUTDOWN MODE In the shutdown mode, which can be controlled by SHDN or bit D8 of the input serial DATA word, each of the xVCC and xVPP outputs is forced to a high-impedance state. In this mode, the chip quiescent current is reduced to 1 µA or less to conserve battery power. POWER-SUPPLY CONSIDERATIONS These switchesTPS2206Ahave multiple pins for each 3.3-V and 5-V power input and for the switched xVCC outputs. Any individual pin can conduct the rated input or output current. Unless all pins are connected in parallel, the series resistance is higher than that specified, resulting in increased voltage drops and power loss. It is recommended that all input and output power pins be paralleled for optimum operation. To increase the noise immunity of the TPS2206A, the power-supply inputs should be bypassed with at least a 4.7-µF electrolytic or tantalum capacitor paralleled by a 0.047-µF to 0.1-µF ceramic capacitor. It is strongly recommended that the switched outputs be bypassed with a 0.1-µF (or larger) ceramic capacitor; doing so improves the immunity of the IC to electrostatic discharge (ESD). Care should be taken to minimize the inductance of PCB traces between the devices and the load. High switching currents can produce large negative voltage transients, which forward biases substrate diodes, resulting in unpredictable performance. Similarly, no pin should be taken below –0.3 V. RESET INPUT To ensure that cards are in a known state after power brownouts or system initialization, the PC Cards should be reset at the same time as the host by applying low-impedance paths from xVCC and xVPP terminals to ground. A low-impedance output state allows discharging of residual voltage remaining on PC Card filter capacitance, permitting the system (host and PC Cards) to be powered up concurrently. The active low RESET input closes internal switches S1, S4, S7, and S11 with all other switches left open. The TPS2206A remains in the low-impedance output state until the signal is deasserted and new data is clocked in and latched. The input serial data cannot be latched during reset mode. RESET is provided for direct compatibility with systems that use an active-low reset voltage supervisor. The RESET pin has an internal 150-kΩ pullup resistor. CALCULATING JUNCTION TEMPERATURE The switch resistance, rDS(on), is dependent on the junction temperature, TJ, of the die. The junction temperature is dependent on both rDS(on) and the current through the switch. To calculate TJ, first find rDS(on) from Figures 26 through 28, using an initial temperature estimate about 30°C above ambient. Then calculate the power dissipation for each switch, using the formula: P D +r DS(on) I2 Next, sum the power dissipation of all switches and calculate the junction temperature: T + J ǒȍ PD R qJA Ǔ ) TA, RqJA + 108°CńW Compare the calculated junction temperature with the initial temperature estimate. If the temperatures are not within a few degrees of each other, recalculate using the calculated temperature as the initial estimate. LOGIC INPUTS AND OUTPUTS The serial interface consists of the DATA, CLOCK, and LATCH leads. The data is clocked in on the positive edge of the clock (see Figure 2). The 9-bit (D0–D8) serial data word is loaded during the positive edge of the latch signal. The latch signal should occur before the next positive edge of the clock. The shutdown bit of the data word places all VCC and Vpp outputs in a high-impedance state and reduces chip quiescent current to 1 µA to conserve battery power. The TPS2206A serial interface is designed to be compatible with serial-interface PCMCIA controllers and current PCMCIA and Japan Electronic Industry Development Association (JEIDA) standards. An overcurrent output (OC) is provided to indicate an overcurrent or overtemperature condition in any of the VCC and VPP outputs as previously discussed. 20 TPS2206A www.ti.com SLVS449 – DECEMBER 2002 see Note A S2 3.3 V AVCC CS S5 AVCC S1 3.3 V S3 5V 5V 5V AVCC S6 CS See Note A BVCC S4 BVCC BVCC S8 12 V See Note B See Note A AVPP CS S9 S7 S10 S12 12 V See Note B See Note A BVPP CS S13 S11 S14 Discharge Element Control Logic Current Limit SHDN RESET Thermal Limit DATA CLOCK LATCH GND UVLO OC POR NOTES: A. Current sense B. The two 12-V pins must be externally connected. Figure 35. Internal Switching Matrix TPS2206A CONTROL LOGIC AVPP BVPP CONTROL SIGNALS OUTPUT CONTROL SIGNALS OUTPUT D8 (SHDN) D0 D1 VAVPP D8 SHDN) D4 D5 VBVPP 1 0 0 0 0 0 1 0V VCC(1) 1 1 1 0 1 0V VCC(1) 1 1 0 VPP(12 V) 1 1 0 VPP(12 V) 1 1 1 Hi–Z 1 1 1 Hi–Z X Hi–Z X Hi–Z 0 X (1) Output depends on AVCC AVCC 0 X (1)Output depdends on BVCC BVCC CONTROL SIGNALS OUTPUT CONTROL SIGNALS OUTPUT D8 SHDN) D3 D2 VAVCC D8 SHDN) D6 D7 VBVCC 1 0 0 0V 1 0 0 0V 1 0 1 3.3 V 1 0 1 3.3 V 1 1 0 5V 1 1 0 5V 1 1 1 0V 1 1 1 0V 0 X X Hi–Z 0 X X Hi–Z 21 TPS2206A www.ti.com SLVS449 – DECEMBER 2002 USING THE TPA2206A WITH 11-BIT SERIAL DATA INTERFACE CONTROLLERS Even though the TPS2206A control logic table only shows a 9-bit interface, it can be used with most 11-bit serial data interface controllers. With the use of the latch input, the TPS2206A only latches the last 9 bits from the serial stream. This means that for an 11-bit serial stream, bits 9 and 10 are ignored. 11-bit serial interface controllers use bits 9 and 10 for independent voltage selection of 3.3 V and 5 V between xVCC and xVPP. ESD PROTECTIONS (see FIGURE 36) All TPS2206A inputs and outputs of these devices incorporate ESD-protection circuitry designed to withstand a 2-kV human-body-model discharge as defined in MIL-STD-883C, Method 3015. The xVCC and xVPP outputs can be exposed to potentially higher discharges from the external environment through the PC Card connector. Bypassing the outputs with 0.1-µF capacitors protects the devices from discharges up to 10 kV. TPS2206A AVCC AVCC 0.1 µF see Note A 0.1 µF see Note A 12 V 4.7 µF 0.1 µF 5V 4.7 µF 0.1 µF 12 V BVCC 0.1 µF 12 V BVCC 5V BVCC 5V BVPP 5V 3.3 V 4.7 µF 0.1 µF 3.3 V 3.3 V SHDN Vpp1 Vpp2 VCC VCC PC Card Connector B 0.1 µF From PCI or System Shutdown Vpp1 Vpp2 Controller DATA DATA CLOCK CLOCK LATCH LATCH RESET OC NOTE A: see Note A see Note A 3.3 V VCC PC Card Connector A AVCC AVPP VCC From PCI or System RST GPI/O Maximum recommended output capacitance for xVCC is 220 µF including card capacitance, and for xVPP is 10 µF, without OC glitch when switches are powered on. Figure 36. Detailed Interconnections and Capacitor Recommendations 22 TPS2206A www.ti.com SLVS449 – DECEMBER 2002 12-V FLASH MEMORY SUPPLY The TPS6734 is a fixed 12-V output boost converter capable of delivering 120 mA from inputs as low as 2.7 V. The device is pin-for-pin compatible with the MAX734 regulator and offers the following advantages: lower supply current, wider operating input-voltage range, and higher output currents. As shown in Figure 36, the only external components required are: an inductor, a Schottky rectifier, an output filter capacitor, an input filter capacitor, and a small capacitor for loop compensation. The entire converter occupies less than 0.7 in2 of PCB space when implemented with surface-mount components. An enable input is provided to shut the converter down and reduce the supply current to 3 µA when 12 V is not needed. The TPS6734 is a 170-kHz current-mode PWM (pulse-width modulation) controller with an n-channel MOSFET power switch. Gate drive for the switch is derived from the 12-V output after start-up to minimize the die area needed to realize the 0.7-Ω MOSFET and improve efficiency at input voltages below 5 V. Soft start is accomplished with the addition of one small capacitor. A 1.22-V reference, pin 2 of TPS6734, is brought out for external use. For additional information, see the TPS6734 data sheet (SLVS127). TPS2206A AVCC 3.3 V or 5 V Enable (see Note A) R1 10 kΩ 1 2 C1 33 µF 20 V + 3 4 C2 0.01 µF AVCC TPS6734 EN VCC REF FB SS OUT COMP GND 8 L1 18 µH AVCC 7 6 5 AVPP D1 33 µF, 20 V + C1 12 V 0.1 µF 12 V 12 V BVCC BVCC C4 0.001 µF 5V 1 µF 0.1 µF 5V 5V BVCC BVPP 5V 3.3 V 4.7 µF 0.1 µF 3.3 V 3.3 V 3.3 V DATA CLOCK LATCH SHDN RESET OC NOTE A: The enable terminal can be tied to a general-purpose I/O terminal on the PCMCIA controller or tied high. Figure 37. TPS2206A With TPS6734 12-V, 120-mA Supply 23 TPS2206A www.ti.com SLVS449 – DECEMBER 2002 MECHANICAL DATA DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 28 PIN SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,15 NOM 5,60 5,00 8,20 7,40 Gage Plane 1 14 0,25 A 0°–ā8° 1,03 0,63 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 / D 02/98 NOTES: A. B. C. D. 24 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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