ETC TPS2202IDBR

TPS2202, TPS2202Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103B – DECEMBER 1994 – REVISED JANUARY 2001
D
D
D
D
D
D
D
D
D
D
D
Fully Integrated VCC and Vpp Switching for
Dual-Slot PC Card Interface
Saves PCMCIA Controller I/O Leads by
Utilizing 3-Lead Serial Interface
Meets PCMCIA Standards
Internal Charge Pump (No External
Capacitors Required) – 12-V Supply Can Be
Disabled Except for Flash Programming
Short-Circuit and Thermal Protection
Space-Saving 30-Pin SSOP(DB) Package
For 3.3-V, 5-V and 12-V PC Cards
Power Saving IDD = 83 µA Typ, IQ = 1 µA
Low rDS(on) (160-mΩ VCC Switch)
Break-Before-Make Switching
ESD Protection Up to 2 kV Per
Mil-STD-883C, Method 3015
DB OR DF PACKAGE
(TOP VIEW)
5V
5V
DATA
CLOCK
LATCH
NC
12V
AVPP
AVCC
AVCC
AVCC
GND
APWR_GOOD
NC
3V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
5V
NC
NC
NC
NC
VDD
12V
BVPP
BVCC
BVCC
BVCC
BPWR_GOOD
OC
3V
3V
NC – No internal connection
description
The TPS2202 PC Card (PCMCIA) power-interface switch provides an integrated power-management solution
for two PC Cards. All of the discrete power MOSFETs, a logic section, current limiting, thermal protection, and
power-good reporting for PC Card control are combined on a single integrated circuit, using Texas Instruments
LinBiCMOS process. The circuit allows the distribution of 3-V, 5-V, and/or 12-V card power by means of a
reduced I/O serial interface. The current-limiting feature eliminates the need for fuses, which reduces
component count and improves reliability; current-limit reporting can help the user isolate a system fault to a
bad card.
The TPS2202 maximizes battery life by using an internal charge pump to generate its own switch-drive voltage.
Therefore, the 12-V supply can be powered down and only brought out of standby when flash memory needs
to be written to or erased. End equipment for the TPS2202 includes notebook computers, desktop computers,
personal digital assistants (PDAs), digital cameras, handiterminals, and bar-code scanners.
typical PC-card power-distribution application
VDD
Power Supply
12V
5V
3V
12 V
5V
3V
TPS2202
AVPP
AVCC
AVCC
Vpp1
Vpp2
VCC
VCC
PC
Card A
Vpp1
Vpp2
VCC
VCC
PC
Card B
AVCC
3
PCMCIA
Controller
Serial Interface
APWR_GOOD
BPWR_GOOD
OC
BVPP
BVCC
BVCC
BVCC
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PC Card is a trademark of PCMCIA (Personal Computer Memory Card International Association).
LinBiCMOS is a trademark of Texas Instruments.
Copyright  2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TPS2202, TPS2202Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103B – DECEMBER 1994 – REVISED JANUARY 2001
AVAILABLE OPTIONS
PACKAGED DEVICES
TJ
SHINK SMALL-OUTLINE
(DB)†
SMALL-OUTLINE
(DF)†
CHIP FORM
(Y)
– 40°C to 150°C
TPS2202IDBR
TPS2202IDFR
TPS2202Y
† The DB and DF packages are only available taped and reeled, indicated by the R suffix on the device type.
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
3V
15, 16, 17
I
3-V VCC input for card power
5V
1, 2, 30
I
5-V VCC input for card power
12V
7, 24
I
12-V Vpp input for card power
AVCC
9, 10, 11
O
Switched output that delivers 0 V, 3.3 V, 5 V, or high impedance
AVPP
8
O
Switched output that delivers 0 V, 3.3 V, 5 V, 12 V, or high impedance
APWR_GOOD
13
O
Logic-level power-ready output that stays low as long as AVPP is within limits.
BVCC
20, 21, 22
O
Switched output that delivers 0 V, 3.3 V, 5 V, or high impedance
BVPP
23
O
Switched output that delivers 0 V, 3.3 V, 5 V, 12 V, or high impedance
BPWR_GOOD
19
O
Logic-level power-ready output that stays low as long as BVPP is within limits.
4
I
Logic-level clock for serial data word
DATA
3
I
Logic-level serial data word
GND
12
CLOCK
LATCH
5
NC
6, 14, 26,
27, 28, 29
OC
18
VDD
25
2
Ground
I
Logic-level latch for serial data word
No internal connection
O
Logic-level overcurrent reporting output that goes low when an overcurrent condition exists.
5-V power to chip
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS2202, TPS2202Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103B – DECEMBER 1994 – REVISED JANUARY 2001
TPS2202Y chip information
This chip, when properly assembled, displays characteristics similar to the TPS2202. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
(19)
(13)
(18)
(12)
(16)
(17)
(15)
5V
5V
DATA
CLOCK
LATCH
(20)
(11)
NC
12V
AVPP
(21)
(10)
AVCC
AVCC
204
AVCC
(22)
(9)
GND
APWR_GOOD
(8)
(23)
NC
3V
(1)
(30)
(2)
(29)
(3)
(28)
(4)
(27)
(5)
(26)
(6)
(25)
(7)
(24)
(8)
(23)
TPS2201Y
(9)
(22)
(10)
(21)
(11)
(20)
(12)
(19)
(13)
(18)
(14)
(17)
(15)
(16)
5V
NC
NC
NC
NC
VDD
12V
BVPP
BVCC
BVCC
BVCC
BPWR_GOOD
OC
3V
3V
(7)
(24)
(25)
CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 × 4 MILS MINIMUM
(30)
(1)
(2)
(5)
(3)
(4)
TJmax = 150°C
TOLERANCES ARE ± 10%
ALL DIMENSIONS ARE IN MILS
142
TERMINALS 6, 14, 26, 27, 28, AND 29
ARE NOT CONNECTED
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
TPS2202, TPS2202Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103B – DECEMBER 1994 – REVISED JANUARY 2001
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Input voltage range for card power: VI(5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
VI(3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VI(5V)
VI(12V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 14 V
Logic input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Output current (each card): IO(xVCC)
internally limited
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS2202, TPS2202Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103B – DECEMBER 1994 – REVISED JANUARY 2001
electrical characteristics, TA = 25°C, VDD = 5 V (unless otherwise noted)
dc characteristics
PARAMETER
Switch resistances†
TPS2202
TEST CONDITIONS
MIN
TYP
5 V to xVCC
160
3 V to xVCC
225
5 V to xVPP
6
3 V to xVPP
6
12 V to xVPP
1
Clamp low voltage
Ipp at 10 mA
ICC at 10 mA
Clamp low voltage
Ipp High-impedance
High impedance state
TA = 25°C
TA = 85°C
1
High impedance state
ICC High-impedance
TA = 25°C
TA = 85°C
1
IDD
VO(AVCC) = VO(BVCC) = 5 V,
VO(AVPP) = VO(BVPP) = 12 V
IDD in shutdown
VO(BVCC) = VO(AVCC) = VO(AVPP)
= VO(BVPP) = Hi-Z
Leakage current
Input current
mΩ
Ω
V
0.8
V
10
10
µA
50
83
10.72
Power-ready hysteresis, PWR_GOOD (12-V mode)
IO(xVCC)
IO(xVPP)
UNIT
0.8
50
Power-ready threshold, PWR_GOOD
Short circuit output-current
Short-circuit
output current limit
MAX
11.05
150
µA
1
µA
11.4
50
TJ = 85°C,,
Output powered up into a short to GND
V
mV
0.75
1.3
1.9
A
120
200
400
mA
† Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
switching characteristics‡
PARAMETER
TPS2202
TEST CONDITIONS
MIN
TYP
tr
Output rise time
VO(xVCC)
VO(xVPP)
1.2
tf
Output fall time
VO(xVCC)
VO(xVPP)
10
tpd
d
Propagation delay (see Figure 1§)
5
14
ton
toff
5.8
LATCH↑ to VO(
O(xVPP))
ton
toff
5.8
LATCH↑ to xVCC (3 V)
LATCH↑ to xVCC (5 V)
ton
toff
18
28
4
30
MAX
UNIT
ms
ms
ms
ms
ms
‡ Refer to Parameter Measurement Information
§ Propagation delays are with CL = 100 µF.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
TPS2202, TPS2202Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103B – DECEMBER 1994 – REVISED JANUARY 2001
electrical characteristics, TA = 25°C, VDD = 5 V (unless otherwise noted) (continued)
logic section
PARAMETER
TPS2202
TEST CONDITIONS
MIN
MAX
Logic input current
1
Logic input high level
2.7
0.8
IO = 1 mA
Logic output low level
µA
V
Logic input low level
Logic output high level
UNIT
VDD – 0.4
V
V
0.4
V
dc characteristics
PARAMETER
TPS2202Y
TEST CONDITIONS
Leakage current
Ipp High-impedance state
ICC High-impedance state
Input current
IDD
MIN
TYP
MAX
1
µA
1
VO(AVCC) = VO(BVCC) = 5 V,
VO(AVPP) = VO(BVPP) = 12 V
µA
83
Power-ready threshold, PWR_GOOD
11.05
Power-ready hysteresis, PWR_GOOD (12-V mode)
UNIT
V
50
mV
switching characteristics†
PARAMETER
TPS2202Y
TEST CONDITIONS
MIN
TYP
tr
Output rise time
VO(xVCC)
VO(xVPP)
1.2
tf
Output fall time
VO(xVCC)
VO(xVPP)
10
tpd
d
Propagation delay (see Figure 1‡)
POST OFFICE BOX 655303
14
ton
toff
5.8
LATCH↑ to VO(xVPP)
O(
)
ton
toff
5.8
LATCH↑ to xVCC
LATCH↑ to xVCC
ton
toff
† Refer to Parameter Measurement Information
‡ Propagation delays are with CL = 100 µF.
6
5
• DALLAS, TEXAS 75265
18
28
4
30
MAX
UNIT
ms
ms
ms
ms
ms
TPS2202, TPS2202Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103B – DECEMBER 1994 – REVISED JANUARY 2001
PARAMETER MEASUREMENT INFORMATION
Vpp
VCC
CL
CL
LOAD CIRCUIT
LOAD CIRCUIT
VDD
LATCH
VDD
50%
50%
LATCH
GND
GND
toff
toff
ton
ton
VI(12V)
90%
VO(xVPP)
10%
VI(5V)
90%
VO(xVCC)
10%
GND
VOLTAGE WAVEFORMS
GND
VOLTAGE WAVEFORMS
Figure 1. Test Circuits and Voltage Waveforms
Table of Timing Diagrams
FIGURE
DATA
Serial-Interface Timing
2
xVCC Propagation Delay and Rise Times With 1-µF Load, 3-V Switch
3
xVCC Propagation Delay and Fall Times With 1-µF Load, 3-V Switch
4
xVCC Propagation Delay and Rise Times With 100-µF Load, 3-V Switch
5
xVCC Propagation Delay and Fall Times With 100-µF Load, 3-V Switch
6
xVCC Propagation Delay and Rise Times With 1-µF Load, 5-V Switch
7
xVCC Propagation Delay and Fall Times With 1-µF Load, 5-V Switch
8
xVCC Propagation Delay and Rise Times With 100-µF Load, 5-V Switch
9
xVCC Propagation Delay and Fall Times With 100-µF Load, 5-V Switch
10
xVPP Propagation Delay and Rise Times With 1-µF Load, 12-V Switch
11
xVPP Propagation Delay and Fall Times With 1-µF Load, 12-V Switch
12
xVPP Propagation Delay and Rise Times With 100-µF Load, 12-V Switch
13
xVPP Propagation Delay and Fall Times With 100-µF Load, 12-V Switch
14
D8
D7
D6
D5
D4
D3
D2
D1
D0
LATCH
CLOCK
NOTE A: Data is clocked in on the a positive leading edge of the clock. The latch should occur before next positive leading edge of
the clock. For definition of D0 – D8, see control logic table.
Figure 2. Serial-Interface Timing
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
TPS2202, TPS2202Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103B – DECEMBER 1994 – REVISED JANUARY 2001
PARAMETER MEASUREMENT INFORMATION
LATCH (2 V/div)
LATCH (2 V/div)
xVCC (1 V/div)
0
1
2
xVCC (1 V/div)
3
4
5
6
7
8
9
0
5
10
15
20
25
35
40
t – Time – ms
Figure 3. xVCC Propagation Delay and
Rise Times With 1-µF Load, 3-V Switch
Figure 4. xVCC Propagation Delay and
Fall Times With 1-µF Load, 3-V Switch
LATCH (2 V/div)
0
1
2
3
45
LATCH (2 V/div)
xVCC (1 V/div)
xVCC (1 V/div)
4
5
6
7
8
9
0
t – Time – ms
5
10
15
20
25
30
35
40
45
t – Time – ms
Figure 5. xVCC Propagation Delay and
Rise Times With 100-µF Load, 3-V Switch
8
30
t – Time – ms
POST OFFICE BOX 655303
Figure 6. xVCC Propagation Delay and
Fall Times With 100-µF Load, 3-V Switch
• DALLAS, TEXAS 75265
TPS2202, TPS2202Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103B – DECEMBER 1994 – REVISED JANUARY 2001
PARAMETER MEASUREMENT INFORMATION
LATCH (2 V/div)
LATCH (2 V/div)
xVCC (1 V/div)
0
xVCC (1 V/div)
1
2
3
4
0
5
10
15
20
25
30
35
40
45
t – Time – ms
t – Time – ms
Figure 7. xVCC Propagation Delay and
Rise Times With 1-µF Load, 5-V Switch
Figure 8. xVCC Propagation Delay and
Fall Times With 1-µF Load, 5-V Switch
LATCH (2 V/div)
LATCH (2 V/div)
xVCC (1 V/div)
xVCC (1 V/div)
0
1
2
3
4
5
6
7
8
9
0
5
t – Time – ms
10
15
20
25
30
35
40
45
t – Time – ms
Figure 9. xVCC Propagation Delay and
Rise Times With 100-µF Load, 5-V Switch
POST OFFICE BOX 655303
Figure 10. xVCC Propagation Delay and
Fall Times With 100-µF Load, 5-V Switch
• DALLAS, TEXAS 75265
9
TPS2202, TPS2202Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103B – DECEMBER 1994 – REVISED JANUARY 2001
PARAMETER MEASUREMENT INFORMATION
LATCH (2 V/div)
LATCH (2 V/div)
xVPP (5 V/div)
xVPP (5 V/div)
0
0.2
0.4 0.6
0.8
1.0
1.2
1.4
1.6
1.8
0
1
2
t – Time – ms
3
4
5
6
7
8
9
t – Time – ms
Figure 11. xVPP Propagation Delay and
Rise Times With 1-µF Load, 12-V Switch
Figure 12. xVPP Propagation Delay and
Fall Times With 1-µF Load, 12-V Switch
LATCH (2 V/div)
LATCH (2 V/div)
xVPP (5 V/div)
xVPP (5 V/div)
0
1
2
3
4
5
6
7
8
9
0
t – Time – ms
10
15
20
25
30
35
40
45
t – Time – ms
Figure 13. xVPP Propagation Delay and
Rise Times With 100-µF Load, 12-V Switch
10
5
POST OFFICE BOX 655303
Figure 14. xVPP Propagation Delay and
Fall Times With 100-µF Load, 12-V Switch
• DALLAS, TEXAS 75265
TPS2202, TPS2202Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103B – DECEMBER 1994 – REVISED JANUARY 2001
TYPICAL CHARACTERISTICS†
Table of Graphs
FIGURE
IDD
rDS(on)
Supply current
vs Junction temperature
15
Static drain-source on-state resistance, 3-V switch
vs Junction temperature
16
rDS(on)
Static drain-source on-state resistance, 5-V switch
vs Junction temperature
17
rDS(on)
Static drain-source on-state resistance, 12-V switch
vs Junction temperature
18
VO(xVCC)
VO(xVCC)
Output voltage, 5-V switch
vs Output current
19
Output voltage, 3-V switch
vs Output current
20
xVPP
Output voltage, Vpp switch
vs Output current
21
ISC(xVCC)
ISC(xVPP)
Short-circuit current, 5-V switch
vs Junction temperature
22
Short-circuit current, 12-V switch
vs Junction temperature
23
SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
100
VO(AVCC) = VO(BVCC) = 5 V
VO(AVPP) = VO(BVPP) = 12 V
No load
I DD – Supply Current – µ A
95
ÁÁ
ÁÁ
ÁÁ
90
85
80
75
– 50
50
0
100
150
TJ – Junction Temperature – °C
Figure 15
† t = pulse tested
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
TPS2202, TPS2202Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103B – DECEMBER 1994 – REVISED JANUARY 2001
3-V SWITCH
5-V SWITCH
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
400
VDD = 5 V
VCC = 3.3 V
350
300
250
200
150
100
50
0
– 50
– 25
25
50
75
100
0
TJ – Junction Temperature – °C
125
r DS(on) – Static Drain-Source On-State Resistance – m Ω
r DS(on) – Static Drain-Source On-State Resistance – m Ω
TYPICAL CHARACTERISTICS†
240
VDD = 5 V
VCC = 5 V
220
200
180
160
140
120
100
80
– 50
– 25
0
25
50
75
100
TJ – Junction Temperature – °C
Figure 17
12-V SWITCH
5-V SWITCH
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
5.05
1700
VDD = 5 V
VCC = 5 V
VDD = 5 V
Vpp = 12 V
5
1500
– 40°C
VO(xVCC) – Output Voltage – V
r DS(on) – Static Drain-Source On-State Resistance – m Ω
Figure 16
1300
1100
900
700
500
– 50
4.99
4.9
25°C
4.85
85°C
125°C
4.8
4.75
– 25
0
25
50
75
100
125
0
TJ – Junction Temperature – °C
Figure 18
0.1
0.2
0.3
0.4
0.5
0.6
IO(xVCC) – Output Current – A
Figure 19
† t = pulse tested
12
125
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
0.7
TPS2202, TPS2202Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103B – DECEMBER 1994 – REVISED JANUARY 2001
TYPICAL CHARACTERISTICS†
3-V SWITCH
Vpp SWITCH
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
12.05
3.35
VDD = 5 V
Vpp = 12 V
3.3
12
xVpp – Output Voltage – V
VO(xVCC) – Output Voltage – V
VDD = 5 V
VCC = 3.3 V
– 40°C
3.25
25°C
3.2
3.15
– 40°C
25°C
11.95
11.90
85°C
11.85
3.1
125°C
125°C
85°C
11.80
3.05
0
0.1
0.2
0.3
0.4
0.5
0.6
0
0.7
0.02
0.04
Figure 20
0.08
0.1
0.12
Figure 21
5-V SWITCH
12-V SWITCH
SHORT-CIRCUIT CURRENT
vs
JUNCTION TEMPERATURE
SHORT-CIRCUIT CURRENT
vs
JUNCTION TEMPERATURE
400
2
VDD = 5 V
VCC = 5 V
I SC(xVPP) – Short-Circuit Current – mA
I SC(xVCC) – Short-Circuit Current – A
0.06
IO(xVPP) – Output Current – A
IO(xVCC) – Output Current – A
1.5
1
0.5
– 50
0
50
100
150
VDD = 5 V
Vpp = 12 V
350
300
250
200
150
100
– 50
TJ – Junction Temperature – °C
Figure 22
100
0
50
TJ – Junction Temperature – °C
150
Figure 23
† t = pulse tested
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
TPS2202, TPS2202Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103B – DECEMBER 1994 – REVISED JANUARY 2001
APPLICATION INFORMATION
overview
PC Cards were initially introduced as a means to add EEPROM (flash memory) to portable computers with
limited on-board memory. The idea of add-in cards quickly took hold: modems, wireless LANs, GPS systems,
multimedia, and hard-disk versions were soon available. As the number of PC Card applications grew, the
engineering community quickly recognized the need for a standard to ensure compatibility across platforms.
To this end, the PCMCIA (Personal Computer Memory Card International Association) was established and was
comprised of members from leading computer, software, PC card, and semiconductor manufacturers. One key
goal was to realize the concept of plug-and-play, cards and hosts from different vendors should be compatible
and able to communicate with one another transparently.
PC Card power specification
System compatibility also means power compatibility. The most current set of specifications (PC Card Standard)
set forth by the PCMCIA committee states that power is to be transferred between the host and the card through
eight of the PC Card connector’s 68 pins. This power interface consists of two VCC, two Vpp, and four ground
pins. Multiple VCC and ground pins minimize connector-pin and line resistance. The two Vpp pins were originally
specified as separate signals but are commonly tied together in the host to form a single node to minimize
voltage losses. Card primary power is supplied through the VCC pins; flash-memory programming and erase
voltage is supplied through the Vpp pins. As each pin is rated to 0.5 A, VCC and Vpp can theoretically supply up
to 1 A, assuming equal pin resistance and no pin failure. A conservative design would limit current to 500 mA.
Some applications, however, require higher VCC currents; disk drives, for example, may need as much as
750-mA peak current to create the initial torque necessary to spin up the platter. Vpp currents, on the other hand,
are defined by flash-memory programming requirements, typically under 120 mA.
future power trends
The 1-A physical-pin current alluded to in the PC Card specification has caused some host-system engineers
to believe they are required to deliver 1 A within the voltage tolerance of the card. Future applications, such as
RF cards, could use the extra power for their radio transmitters. The 5 W needed for these cards will require
very robust power supplies and special cooling considerations. The limited number of host sockets that will be
able to support them makes the market for these high-powered PC Cards uncertain. The vast majority of the
cards require less than 600 mA continuous current and the trend is towards even lower-powered PC Cards that
will assure compatibility with a greater number of host systems. Recognizing the need for power derating, an
adhoc committee of the PCMCIA is currently working to limit the amount of steady-state dc current to the
PC Card to something less than the currently implied 1 A. If a system is designed to support 1 A, then the switch
rDS(on), power supply requirements, and PC Card cooling need to be carefully considered.
designing around 1-A delivery
Delivering 1 A means minimizing voltage (and power) losses across the PC Card power interface, which
requires that designers trade off switch resistance and the cost associated with large-die (low rDS(on)) MOSFET
transistors. The PC Card standard requires that 5 V ±5%, or 3.3 V ±0.3 V be supplied to the card. The
approximate 10% tolerance for the 3.3-V supply makes the 3.3-V rDS(on) less critical than the 5-V switch. A
conservative approach is to allow 2% for voltage-regulator tolerance and 1% for etch- and terminal-resistance
drops, which leaves 2% (100 mV) voltage drop for the 5-V switch, and at least 6% (198 mV) for the 3.3-V switch.
Calculating the rDS(on) necessary to support a 100 mV or 198 mV switch loss, using R = E/I and setting I = 1 A,
the 5-V and 3.3-V switches would need to be 100 mΩ and 198 mΩ respectively. One solution would be to pay
for a more expensive switch with lower rDS(on). A second, less expensive approach is to increase the headroom
of the power supply–for example, to increase the 5-V supply 1.5% or to 5.075 ±2%. Working through the
numbers once more, the 2% for the regulator plus 1 % for etch and terminal losses leaves 97% or 4.923 V.
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS2202, TPS2202Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103B – DECEMBER 1994 – REVISED JANUARY 2001
APPLICATION INFORMATION
designing around 1-A delivery (continued)
The allowable voltage loss across the power distribution switch is now 4.923 V minus 4.750 V or 173 mV.
Therefore, a switch with 173 mΩ or less could deliver 1 A or greater. Setting the power supply high is a common
practice for delivering voltages to allow for system switch, connector, and etch losses and has a minimal effect
on overall battery life. In the example above, setting the power supply 1.5% high would only decrease a 3-hour
battery life by approximately 2.7 minutes, trivial when compared with the decrease in battery life when running
a 5-W PC Card.
heat dissipation
A greater concern in delivering 1 A or 5 W is the ability of the host to dissipate the heat generated by the PC
Card. For desktop computers the solution is simpler: locate the PC Card cage such that it receives convection
cooling from the forced air of the fan. Notebooks and other handheld equipment are not be able to rely on
convection, but must rely on conduction of heat away from the PC Card through the rails into the card cage.
This is difficult because PC Card/card cage heat transfer is very poor. A typical design scenario would require
the PC Card to be held at 60°C maximum with the host platform operating as high as 50°C. Preliminary testing
reveals that a PC Card can have a 20°C rise, exceeding the 10°C differential in the example, when dissipating
less than 2 W of continuous power. The 60°C temperature was chosen because it is the maximum operating
temperature allowable by PC Card specification. Power handling requirements and temperature rises are topics
of concern and are currently being addressed by the PCMCIA committee.
overcurrent and overtemperature protection
PC Cards are inherently subject to damage that can result from mishandling. Host systems require protection
against short-circuited cards that could lead to power supply or PCB-trace damage. Even systems sufficiently
robust to withstand a short circuit would still undergo rapid battery discharge into the damaged PC Card,
resulting in the rather sudden and unacceptable loss of system power. This can be particularly frustrating to the
consumer who has already experienced problems with shortened battery life due to improper Nicad conditioning
or memory effect. Most hosts include fuses for protection. The reliability of fused systems is poor, though, as
blown fuses require troubleshooting and repair, usually by the manufacturer. The TPS2202 takes a two-pronged
approach to overcurrent protection. First, instead of fuses, sense FETs monitor each of the power outputs.
Excessive current generates an error signal that linearly limits the output current, preventing host damage or
failure. Sense FETs, unlike sense resistors or polyfuses, have the added advantage that they do not add to the
series resistance of the switch and thus produce no additional voltage losses. Second, when an overcurrent
condition is detected, the TPS2202 asserts a signal at OC that can be monitored by the microprocessor to initiate
diagnostics and/or send the user a warning message. In the event that an overcurrent condition persists,
causing the IC to exceed its maximum junction temperature, thermal-protection circuitry engages, shutting
down all power outputs until the device cools to within a safe operating region.
12-V supply not required
Most PC Card switches use the externally supplied 12-V Vpp power for switch-gate drive and other chip
functions, requiring that it be present at all times. The TPS2202 offers considerable power savings by using an
internal charge pump to generate the required higher voltages from the 5-V VDD supply; therefore, the external
12-V supply can be disabled except when needed for flash-memory functions, thereby extending battery
lifetime. Additional power savings are realized by the TPS2202 during a software shutdown, in which quiescent
current drops to a maximum of 1 µA.
voltage transitioning requirement
PC Cards, like portables, are migrating from 5 V to 3.3 V to minimize power consumption, optimize board space,
and increase logic speeds. The TPS2202 is designed to meet all combinations of power delivery as currently
defined in the PCMCIA standard. The latest protocol accommodates mixed 3.3-V/5-V systems by first powering
the card with 5 V, then polling it to determine its 3.3-V compatibility. The PCMCIA specification requires that the
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
TPS2202, TPS2202Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103B – DECEMBER 1994 – REVISED JANUARY 2001
APPLICATION INFORMATION
voltage transitioning requirement (continued)
capacitors on 3.3-V compatible cards be discharged to below 0.8 V before applying 3.3-V power. This ensures
that sensitive 3.3-V circuitry is not subjected to any residual 5-V charge and functions as a power reset. The
TPS2202 offers a selectable VCC and VPP ground state, in accordance with PCMCIA 3.3-V/5-V switching
specifications, to fully discharge the card capacitors while switching between VCC voltages.
output ground switches
Several PCMCIA power-distribution switches on the market do not have an active-grounding FET switch. These
devices do not meet the PC Card specification requiring a discharge of VCC within 100 ms. PC Card resistance
can not be relied on to provide a discharge path for voltages stored on PC Card capacitance because of possible
high-impedance isolation by power-management schemes. A method commonly shown to alleviate this
problem is to add to the switch output an external 100-kΩ resistor in parallel with the PC Card. Considering that
this is the only discharge path to ground, a timing analysis will reveal that the RC time constant delays the
required discharge time to over 2 seconds. The only way to ensure timing compatibility with PC Card standards
is to use a power-distribution switch that has an internal ground switch, like that of the TPS22xx family, or add
an external ground FET to each of the output lines with the control logic necessary to select it.
In summary, the TPS2202 is a complete single-chip dual-slot PC Card power interface. It meets all currently
defined PCMCIA specifications for power delivery in 5-V, 3.3-V, and mixed systems, and offers a serial controller
interface. The TPS2202 offers functionality, power savings, overcurrent and thermal protection, and fault
reporting in one 30-pin SSOP surface-mount package for maximum value added to new portable designs.
power-supply considerations
The TPS2202 has multiple terminals for each of its 3.3-V, 5-V, and 12-V power inputs and for the switched VCC
outputs. Any individual terminal can conduct the rated input or output current. Unless all terminals are connected
in parallel, the series resistance is significantly higher than that specified, resulting in increased voltage drops
and lost power. Both 12 V inputs must be connected for proper Vpp switching; it is recommended that all input
and output power terminals be paralleled for optimum operation. The VDD input lead must be connected to the
5V input leads.
Although the TPS2202 is fairly immune to power input fluctuations and noise, it is generally considered good
design practice to bypass power supplies typically with a 1-µF electrolytic or tantalum capacitor paralleled by
a 0.047-µF to 0.1-µF ceramic capacitor. It is strongly recommended that the switched VCC and Vpp outputs be
bypassed with a 0.1-µF or larger capacitor; doing so improves the immunity of the TPS2202 to electrostatic
discharge (ESD). Care should be taken to minimize the inductance of PCB traces between the TPS2202 and
the load. High switching currents can produce large negative-voltage transients, which forward biases substrate
diodes, resulting in unpredictable performance.
The TPS2202, unlike other PC Card power-interface switches, does not use the 12-V power supply for switching
or other chip functions. Instead, an internal charge pump generates the necessary voltage from VDD, allowing
the 12-V input supply to be shut down except when the Vpp programming or erase voltage is needed. Careful
system design making use of this feature reduces power consumption and extends battery lifetime.
The 3.3-V power input should not be taken higher than the 5-V input. Doing so, though nondestructive, results
in high current flow into the device, and could result in abnormal operation. In any case, this occurrence indicates
a malfunction of one input voltage or both, which should be investigated.
Similarly, no terminal should be taken below – 0.3 V; forward biasing the parasitic-substrate diode results in
substrate currents and unpredictable performance.
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS2202, TPS2202Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103B – DECEMBER 1994 – REVISED JANUARY 2001
APPLICATION INFORMATION
overcurrent and thermal protection
The TPS2202 uses sense FETs to check for overcurrent conditions in each of the VCC and Vpp outputs. Unlike
sense resistors or polyfuses, these FETs do not add to the series resistance of the switch; therefore, voltage
and power losses are reduced. Overcurrent sensing is applied to each output separately. When an overcurrent
condition is detected, only the power output affected is limited; all other power outputs continue to function
normally. The OC indicator, normally a logic high, is a logic low when any overcurrent condition is detected,
providing for initiation of system diagnostics and/or sending a warning message to the user.
During power up, the TPS2202 controls the rise time of the VCC and Vpp outputs and limits the current into a
faulty card or connector. If a short circuit is applied after power is established (e.g., hot insertion of a bad card),
current is initially limited only by the impedance between the short and the power supply. In extreme cases, as
much as 10 A to 15 A may flow into the short before the current limiting of the TPS2202 engages. If the VCC
or Vpp outputs are driven below ground, the TPS2202 may latch nondestructively in an off state. Cycling power
reestablishes normal operation.
Overcurrent limiting for the VCC outputs is designed to engage if powered up into a short in the range of
0.75 A to 1.9 A, typically at about 1.3 A; the Vpp outputs limit from 120 mA to 400 mA, typically around 200 mA.
The protection circuitry acts by linearly limiting the current passing through the switch, rather than initiating a
full shutdown of the supply. Shutdown occurs only during thermal limiting.
Thermal limiting prevents destruction of the IC from overheating when the package power-dissipation ratings
are exceeded. Thermal limiting, disables all power outputs (both A and B slots) until the device has cooled.
calculating junction temperature
The switch resistance, rDS(on), is dependent on the junction temperature, TJ, of the die. The junction temperature
is dependent on both rDS(on) and the current through the switch. To calculate TJ, first find rDS(on) from Figures
16, 17, and 18 using an initial temperature estimate about 50°C above ambient. Then calculate the power
dissipation for each switch, using the formula:
P
D
+ rDS(on) @ I2
ǒS
Ǔ
Next, sum the power dissipation and calculate the junction temperature:
T
J
+
P
D
@ RqJA ) TA,
R
qJA + 108 °CńW
Compare the calculated junction temperature with the initial temperature estimate. If they are not within a few
degrees of each other, reiterate using the calculated temperature as the initial estimate.
logic input and outputs
The serial interface consists of DATA, CLOCK, and LATCH leads. The data is clocked in on the positive leading
edge of the clock (see Figure 2). The 9-bit (D0 through D8) serial data word is loaded during the positive edge
of the latch signal. The latch signal should occur before the next positive leading edge of the clock.
The shutdown bit of the data word places all VCC and Vpp outputs in a high-impedance state and reduces chip
quiescent current to 1 µA to conserve battery power.
The TPS2202 serial interface is designed to be compatible with serial-interface PCMCIA controllers and current
PCMCIA and JEIDA standards.
An overcurrent output (OC) is provided to indicate an overcurrent condition in any of the VCC or Vpp outputs,
as previously discussed.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
TPS2202, TPS2202Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103B – DECEMBER 1994 – REVISED JANUARY 2001
APPLICATION INFORMATION
TPS2202
S7
S9
S2
3V
S3
CS
3V
3V
17
12V
12V
10
17
11
51
20
17
21
51
VCC
VCC
Card B
S4
S6
5V
Vpp2
CS
CS
5V
Vpp1
9
16
S5
5V
18
52
S8
S1
15
Card A
8
S10
1
S12
30
CS
VCC
22
S11
2
VCC
18
23
52
Vpp1
Vpp2
7
24
Internal
Current Monitor
Thermal
3
4
5
DATA
CLOCK
LATCH
Serial
Interface
25
VDD
Controller
19
13
18
BPWR_GOOD
APWR_GOOD
GND
OC
12
Figure 24. Internal Switching Matrix
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS2202, TPS2202Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103B – DECEMBER 1994 – REVISED JANUARY 2001
APPLICATION INFORMATION
TPS2202 control logic
AVPP
CONTROL SIGNALS
INTERNAL SWITCH SETTINGS
D8 SHDN
D0 A_VPP_PGM
D1 A_VPP_VCC
S7
1
0
0
1
0
1
1
1
OUTPUT
S8
S9
VAVPP
CLOSED
OPEN
OPEN
0V
OPEN
CLOSED
OPEN
VCC†
0
OPEN
OPEN
CLOSED
VPP(12 V)
1
1
1
OPEN
OPEN
OPEN
Hi-Z
0
X
X
OPEN
OPEN
OPEN
Hi-Z
BVPP
CONTROL SIGNALS
INTERNAL SWITCH SETTINGS
D8 SHDN
D4 B_VPP_PGM
D5 B_VPP_VCC
S10
1
0
0
1
0
1
1
1
OUTPUT
S11
S12
VBVPP
CLOSED
OPEN
OPEN
0V
OPEN
CLOSED
OPEN
VCC‡
0
OPEN
OPEN
CLOSED
VPP(12 V)
1
1
1
OPEN
OPEN
OPEN
Hi-Z
0
X
X
OPEN
OPEN
OPEN
Hi-Z
AVCC
CONTROL SIGNALS
INTERNAL SWITCH SETTINGS
OUTPUT
D8 SHDN
D3 A_VCC3
D2 A_VCC5
S1
S2
S3
VAVCC
1
0
0
CLOSED
OPEN
OPEN
0V
1
0
1
OPEN
CLOSED
OPEN
3V
1
1
0
OPEN
OPEN
CLOSED
5V
1
1
1
CLOSED
OPEN
OPEN
0V
0
X
X
OPEN
OPEN
OPEN
Hi-Z
BVCC
CONTROL SIGNALS
INTERNAL SWITCH SETTINGS
OUTPUT
D8 SHDN
D6 B_VCC3
D7 B_VCC5
S4
S5
S6
VBVCC
1
0
0
CLOSED
OPEN
OPEN
0V
1
0
1
OPEN
CLOSED
OPEN
3V
1
1
0
OPEN
OPEN
CLOSED
5V
1
1
1
CLOSED
OPEN
OPEN
0V
0
X
X
OPEN
OPEN
OPEN
Hi-Z
† Output depends on AVCC
‡ Output depends on BVCC
ESD protection
All TPS2202 inputs and outputs incorporate ESD-protection circuitry designed to withstand a 2-kV
human-body-model discharge as defined in MIL-STD-883C, Method 3015. The VCC and Vpp outputs can be
exposed to potentially higher discharges from the external environment through the PC Card connector.
Bypassing the outputs with 0.1-µF capacitors protects the devices from discharges up to 10 kV.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
TPS2202, TPS2202Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103B – DECEMBER 1994 – REVISED JANUARY 2001
APPLICATION INFORMATION
5V
VDD
AVCC
0.1 µF
AVCC
12 V
12V
AVCC
VCC
VCC
Vpp1
Vpp2
12V
PC Card
Connector A
BVCC
BVCC
BVCC
0.1 µF
TPS2202
Vpp1
Vpp2
AVPP
5V
0.1 µF
AVPP
5V
VCC
VCC
PC Card
Connector B
5V
5V
3V
BVPP
0.1 µF
BVPP
3V
3V
DATA
3V
DATA
CLOCK
CLOCK
LATCH
LATCH
PCMCIA
Controller
APWR_GOOD
AVPPGOOD
BVPPGOOD
BPWR_GOOD
OC
To CPU
GND
CS
Shutdown Signal
From CPU
Figure 25. Detailed Interconnections and Capacitor Recommendations
20
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its products to the specifications applicable at the time of sale in accordance with
TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary
to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except
those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
products or services might be or are used. TI’s publication of information regarding any third party’s products
or services does not constitute TI’s approval, license, warranty or endorsement thereof.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation
or reproduction of this information with alteration voids all warranties provided for an associated TI product or
service, is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use.
Resale of TI’s products or services with statements different from or beyond the parameters stated by TI for
that product or service voids all express and any implied warranties for the associated TI product or service,
is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use.
Also see: Standard Terms and Conditions of Sale for Semiconductor Products. www.ti.com/sc/docs/stdterms.htm
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright  2001, Texas Instruments Incorporated