CHERRY CS5101EN14

CS5101
CS5101
Secondary Side Post Regulator for AC/DC
and DC/DC Multiple Output Converters
Description
The CS5101 is a bipolar monolithic
secondary side post regulator
(SSPR) which provides tight regulation of multiple output voltages in
AC-DC or DC-DC converters.
Leading edge pulse width modulation is used with the CS5101.
Features
The CS5101 features include a totem
pole output with 1.5A peak output
current capability, externally programmable overcurrent protection,
an on chip 2% precision 5V reference, internally compensated error
amplifier, externally synchronized
switching frequency, and a power
switch drain voltage monitor. It is
available in a 14 lead plastic DIP or
a 16 lead wide body SO package.
The CS5101 is designed to operate
over an 8V to 45V supply voltage
(VCC) range and up to a 75V drive
voltage (VC).
Application Diagram
VSY
L1
CR4
1
3
4
Q1
VOUT
R10
TR
■ 1.5A Peak Output
(Grounded Totem Pole)
■ 8V to 75V Gate Drive Voltage
■ 8V to 45V Supply Voltage
■ 300ns Propagation Delay
■ 1% Error Amplifier
Reference Voltage
■ Lossless Turn On and
Turn Off
■ Sleep Mode: < 100µA
■ Overcurrent Protection with
Dedicated Differential Amp
■ Synchronization to External
Clock
■ External Power Switch
Drain Voltage Monitor
5
R8
6
R5
R11
R13
+
CR5
R6
R9
R12
C6
Package Options
14L PDIP
R14
SYNC
Gnd
CR1
VC
VREF
VG
LGnd
PGnd
+
C5
VD
1
VCC
R2
R1
CR3
R7
VD
VSYNC
VCC
R3
VREF
CR2
LGnd
VFB
+
C1
C2
R4
COMP
RAMP
VFB
CS5101
SSPR
COMP
IS-
RAMP
IS+
VC
16L SO Wide
VG
PGnd
C4
SYNC
IS COMP
ISIS+
2
C3
IS COMP
VD
1
VCC
VC
VREF
VG
DGnd
PGnd
PGnd
AGnd
CR
VFB
IS COMP
COMP
IS-
RAMP
IS+
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: [email protected]
Web Site: www.cherry-semi.com
Rev. 3/31/97
1
A
¨
Company
CS5101
Absolute Maximum Ratings
Power Supply Voltage, VCC .....................................................................................................................................-0.3V to 45V
VSYNC and Output Supply Voltages, VC, VG, VSYNC, VD .....................................................................................-0.3V to 75V
VIS+, VIS- (VCC Ð 4V, up to 24V)..................................................................................................................................-0.3 to 24V
VREF, VFB, VCOMP, VRAMP, VISCOMP ............................................................................................................................-0.3 to 10V
Operating Junction Temperature, TJ .......................................................................................................................-40 to 150¡C
Operating Temperature Range ..................................................................................................................................-40 to 85¡C
Storage Temperature Range ....................................................................................................................................-65 to 150¡C
Output Energy (capacitive load per cycle).............................................................................................................................5µJ
ESD Human Body ....................................................................................................................................................................2kV
ESD Machine Model...............................................................................................................................................................200V
Lead Temperature Soldering
Wave Solder (through hole styles only)....................................................................................10 sec. max, 260¡C peak
Reflow (SMD styles only).....................................................................................60 sec. max above 183¡C, 230¡C peak
Electrical Characteristics: -40¡C ² TA ² 85¡C; -40¡C ² TJ ² 150¡C; 10V < VCC < 45V; 8V < VC <75V unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
■ Error Amplifier
Input Voltage Initial Accuracy
VFB = VCOMP; VCC = 15V;
T = 25¡C (Note 1)
1.98
2.00
2.02
V
Input Voltage
VFB = VCOMP, includes line and temp
1.94
2.00
2.06
V
Input Bias Current
VFB = 0V; IVFB flows out of pin
500
nA
Open Loop Gain
1.5V < VCOMP < 3.0V
60
70
dB
Unity Gain Bandwidth
1.5V < VCOMP < 3.0V; (Note 1)
0.7
1.0
MHz
Output Sink Current
VCOMP = 2.0V; VFB = 2.2V
2
8
mA
Output Source Current
VCOMP = 2.0V; VFB = 1.8V
2
6
VCOMP High
VFB = 1.8V
3.3
3.5
3.7
V
VCOMP Low
VFB = 2.2V
0.85
1.0
1.15
V
PSRR
10V < VCC < 45V;
VFB = VCOMP (Note 1)
60
70
VCC = 15V; T = 25¡C (Note 1)
4.9
5.0
5.1
V
4.8
mA
dB
■ Voltage Reference
Output Voltage Initial Accuracy
Output Voltage
0A < IREF < 8mA
5.0
5.2
V
Line Regulation
10V < VCC < 45V; IREF = 0A
10
60
mV
Load Regulation
0A < IREF < 8mA
20
60
mV
Current Limit
VREF = 4.8V
10
50
VREF_OK FAULT V
VSYNC = 5V; VREF = VLOAD
4.10
4.40
4.60
V
VREF_OK V
VSYNC = 5V; VREF = VLOAD
4.30
4.50
4.80
V
40
100
250
mV
VREF_OK Hysteresis
mA
■ Current Sense Amplifier
IS COMP High V
IS+ = 5V; ISÐ = IS COMP
4.7
5.0
5.3
V
IS COMP Low V
IS+
0.5
1.0
1.3
V
Source Current
IS+
Sink Current
Open Loop Gain
= 0V;
ISÐ
= IS COMP
= 5V;
ISÐ
= 0V
2.0
10
mA
IS- = 5V; IS+ = 0V
10
20
mA
1.5V ² VCOMP ² 4.5V; RL = 4k½
60
80
dB
CMRR
(Note 1)
60
80
dB
PSRR
10V < VCC < 45V, (Note 1)
60
80
dB
Unity Gain Bandwidth
1.5V ² VCOMP ² 4.5V; RL = 4k½ (Note 1)
0.5
0.8
MHz
2
PARAMETER
TEST CONDITIONS
MIN
VIS+ = 2.5V; VIS- = VISCOMP
-8
TYP
MAX
UNIT
0
8
mV
20
250
nA
0
250
nA
■ Current Sense Amplifier: continued
Input Offset Voltage
Input Bias Currents
Input Offset Current
VIS+ = VIS- = 0V; IIS flows out of pins
(IS+,
IS-)
Input Signal Voltage Range
-250
(Note 1)
-0.3
VCC-4.0
VSYNC = 5V, VRAMP = 2.5V ; T = 25¡C
(Note 1)
0.18
0.20
0.22
mA
Ramp Source Current
VSYNC = 5V; VRAMP = 2.5V
0.16
0.20
0.24
mA
Ramp Sink Current
VSYNC = 0V; VRAMP = 2.5V
1.0
4.0
RAMP Peak Voltage
VSYNC = 5V
3.3
3.5
3.7
V
RAMP Valley Voltage
VSYNC = 0V
1.4
1.5
1.6
V
RAMP Dynamic Range
VRAMPDR = VRAMPPK Ð VRAMPVY
1.7
2.0
2.3
V
V
■ RAMP/SYNC Generator
Ramp Source Current Initial
Accuracy
mA
RAMP Sleep Threshold Voltage
VRAMP @ VREF < 2.0V
0.3
0.6
1.0
V
SYNC Threshold
VSYNC @ VRAMP > 2.5V
2.3
2.5
2.7
V
SYNC Input Bias Current
VSYNC = 0V; ISYNC flows out of pin
1
20
µA
VG, High
VSYNC = 5V; IVG = 200mA, VC Ð VG
1.6
2.5
V
■ Output Stage
VG, Low
VSYNC = 0V; IVG = 200mA
0.9
1.5
V
VG Rise Time
Switch VSYNC High; CG = 1nF;
VCC = 15V; measure 2V to 8V
30
75
ns
VG Fall Time
Switch VSYNC Low; CG = 1nF
VCC = 15V; measure 8V to 2V
40
100
ns
VG Resistance to Gnd
Remove supplies; VG = 10V
50
100
k½
VD Resistance to Gnd
Remove supplies; VD = 10V
500
1500
½
■ General
ICC, Operating
VSYNC = 5V
12
18
mA
ICC in UVL
VCC = 6V
300
500
µA
ICC in Sleep Mode High
VRAMP = 0V; VCC = 45V
80
200
µA
ICC In Sleep Mode Low
VRAMP = 0V; VCC = 10V
20
50
µA
IC, Operating High
VSYNC = 5V; VFB = VISÐ = 0V;
VC = 75V
4
8
mA
IC, Operating Low
VSYNC = 5V; VFB = VISÐ = 0V; VC = 8V
3
6
mA
UVLO Start Voltage
7.4
8.0
9.2
V
UVLO Stop Voltage
6.4
7.0
8.3
V
UVLO Hysteresis
0.8
1.0
1.2
V
Leading Edge, tDELAY
VSYNC = 2.5V to VG = 8V
280
ns
Trailing Edge, tDELAY
VSYNC = 2.5V to VG = 2V
750
ns
Note 1: Guaranteed by design. Not 100% tested in production.
3
CS5101
Electrical Characteristics: continued
CS5101
Package Pin Description
PACKAGE PIN #
14L PDIP
PIN SYMBOL
FUNCTION
16L SO Wide
1
1
SYNC
Synchronization input.
2
2
VCC
Logic supply (10V to 45V).
3
3
VREF
5.0V voltage reference.
LGnd
Logic level ground (Analog and digital ground tied).
4
5
6
VFB
Error amplifier inverting input.
6
7
COMP
Error amplifier output and compensation.
7
8
RAMP
RAMP programmable with the external capacitor.
8
9
IS+
Current sense amplifier non-inverting input.
9
10
IS-
Current sense amplifier inverting input.
10
11
IS COMP
Current sense amplifier compensation and output.
11
12, 13
PGnd
Power ground.
12
14
VG
External power switch gate drive.
13
15
VC
Output power stage supply voltage (8V to 75V).
14
16
VD
External FET DRAIN Voltage Monitor.
5
AGnd
Analog Ground.
4
DGnd
Digital Ground.
Circuit Description
Block Diagram
VCC
VD
VCC
VC
REF
VREF
5V
OK
+
UVL+
Ð
+
LGnd
Q1
+
SLEEP
Ð
8V/7V
Ð
VG
Q2
+
0.7V
PGnd
Ð
IS COMP
VCC
5V
5V
24.6k
Ð
IS-
+
IS+
IS
VFB
Ð
EA
Ð
10k
10k
+
+
+
Ð
VC
BUF
2V
+
5V
COMP
5V
Ð
Ð
+ PWM
+
Q3
2.4V
Ð
Q
I = 200mA
RAMP
+
RAMP
Ð
+
Ð
1.65V
0.7V
R
1.5V
Ð
5V
Q4
5V
G1
+
REF_OK
Ð
+
Ð
SYNC
+
SYNC
Ð
G2
+
Ð
5V
LATCH
Q
+
5V
S
2.5V
4
4.5V/4.4V
+
Ð
Ð
VCC_OK
+
VCC
The logic state of the LATCH can be changed only when
both the voltage level of the trailing edge of the power
pulse at the SYNC pin is less than the threshold voltage of
the SYNC comparator (2.5V) and the RAMP voltage is
less than the threshold voltage of the RAMP comparator
(1.65V). On the negative going transition of the secondary
side pulse VSY, gate G2 output goes high, resetting the
latch at time t3. Capacitor CR is discharged through transistor Q4. CRÕs output goes low disabling the output stage,
and the external power switch (an N-FET) is turned off.
Theory of Operation
The CS5101 is designed to regulate voltages in multiple
output power supplies. Functionally, it is similar to a
magnetic amplifier, operating as a switch with a delayed
turn-on. It can be used with both single ended and dual
ended topologies.
The VFB voltage is monitored by the error amplifier EA. It
is compared to an internal reference voltage and the
amplified differential signal is fed through an inverting
amplifier into the buffer, BUF. The buffered signal is compared at the PWM comparator with the ramp voltage
generated by capacitor CR. When the ramp voltage VR,
exceeds the control voltage VC, the output of the PWM
comparator goes high, latching its state through the
LATCH, the output stage transistor Q1 turns on, and the
external power switch, usually an N-FET, turns on.
RAMP Function
The value of the ramp capacitor CR is based on the
switching frequency of the regulator and the maximum
duty cycle of the secondary pulse VSY.
If the RAMP pin is pulled externally to 0.3V or below, the
SSPR is disabled. Current drawn by the IC is reduced to
less than 100µA, and the IC is in SLEEP mode.
SYNC Function
The SYNC circuit is activated at time t1 (Figure 1) when
the voltage at the SYNC pin exceeds the threshold level
(2.5V) of the SYNC comparator. The external ramp capacitor CR is allowed to charge through the internal current
source I (200µA). At time t2, the ramp voltage intersects
with the control voltage VC and the output of the PWM
comparator goes high, turning on the output stage and
the external power switch. At the same time, the PWM
comparator is latched by the RS latch, LATCH.
VSY
FAULT Function
The voltage at the VCC pin is monitored by the undervoltage lockout comparator with hysteresis. When VCC falls
below the UVL threshold, the 5V reference and all the circuitry running off of it is disabled. Under this condition
the supply current is reduced to less than 500µA.
The VCC supply voltage is further monitored by the
VCC_ OK comparator. When VCC is reduced below
VREF - 0.7V, a fault signal is sent to gate G1. This fault signal, which determines if VCC is absent, works in conjunction with the ramp signal to disable the output, but only
after the current cycle has finished and the RS latch is reset.
Therefore this fault will not cause the output to turn off
during the middle of an on pulse, but rather will utilize
lossless turn-off. This feature protects the FET from overvoltage stress. This is accomplished through gate G1 by
driving transistor Q4 on.
VSY
1 0V
VC
VRAMP
2
VSY + VD
VDS
3 0V
VSY
VD
An additional fault signal is derived from the REF_OK
comparator. VREF is monitored so to disable the output
through gate G1 when the VREF voltage falls below the
OK threshold. As in the VCC_OK fault, the REF_OK fault
disables the output after the current cycle has been completed. The fault logic will operate normally only when
VREF voltage is within the specification limits of REF_OK.
VS
4 0V
VSY Ð VOUT
VL1
5
0V
VOUT + VD
VSY + VC
VD
VG
6 0V
Ground Level
(Gate doesn't go
below Gnd)
t1
t2 t3
t4
t1
DRAIN Function
The drain pin, VD monitors the voltage on the drain of the
power switch and derives energy from it to keep the output stage in an off state when VC or VCC is below the minimum specified voltage.
Figure 1. Waveforms for CS5101. The number to the left of each curve
refers to a node on the Application Diagram.
5
CS5101
Circuit Description: continued
CS5101
Circuit Description: continued
S1
8V – 45V
SW SPST
C1
1mF
R1
100k
R2
100k
V1
100kHz
0V to 5V Square Wave
VSYNC
VCC
VREF
C2
0.1mF
LGnd
R3
5k
R6
10k
VFB
C4
0.1mF
R7
10k
VD
CS5101
14 L PDIP
VC
VG
C3
1nF
PGnd
IS COMP
COMP
IS-
RAMP
IS+
R4
2.2k
C5
680pF
CS5101 bench test
6
R5
10k
CS5101
Package Specification
PACKAGE THERMAL DATA
PACKAGE DIMENSIONS IN mm (INCHES)
D
Lead Count
Metric
Max
Min
19.69
18.67
10.50
10.10
14L PDIP
16L SO Wide
Thermal Data
RQJC
typ
RQJA
typ
English
Max
Min
.775
.735
.413
.398
16L SOIC
23
105
14L PDIP
48
85
ûC/W
ûC/W
Plastic DIP (N); 300 mil wide
7.11 (.280)
6.10 (.240)
8.26 (.325)
7.62 (.300)
1.77 (.070)
1.14 (.045)
2.54 (.100) BSC
3.68 (.145)
2.92 (.115)
.356 (.014)
.203 (.008)
0.39 (.015)
MIN.
.558 (.022)
.356 (.014)
REF: JEDEC MS-001
Some 8 and 16 lead
packages may have
1/2 lead at the end
of the package.
All specs are the same.
D
Surface Mount Wide Body (DW); 300 mil wide
7.60 (.299)
7.40 (.291)
10.65 (.419)
10.00 (.394)
0.51 (.020)
0.33 (.013)
1.27 (.050) BSC
2.49 (.098)
2.24 (.088)
1.27 (.050)
0.40 (.016)
2.65 (.104)
2.35 (.093)
0.32 (.013)
0.23 (.009)
D
REF: JEDEC MS-013
0.30 (.012)
0.10 (.004)
Ordering Information
Part Number
CS5101EN14
CS5101EDW16
CS5101EDWR16
Rev. 3/31/97
Description
14L PDIP
16L SO Wide
16L SO Wide (tape & reel)
Cherry Semiconductor Corporation reserves the
right to make changes to the specifications without
notice. Please contact Cherry Semiconductor
Corporation for the latest available information.
PATENTS PENDING
7
© 1999 Cherry Semiconductor Corporation