CS5381
120 dB, 192 kHz, Multi-Bit Audio A/D Converter
Features
General Description
! Advanced Multi-bit Delta-Sigma Architecture
The CS5381 is a complete analog-to-digital converter
for digital audio systems. It performs sampling, analogto-digital conversion, and anti-alias filtering - generating
24-bit values for both left and right inputs in serial form
at sample rates up to 216 kHz per channel.
! 24-bit Conversion
! 120 dB Dynamic Range
! -110 dB THD+N
The CS5381 uses a 5th-order, multi-bit delta-sigma
modulator followed by digital filtering and decimation,
which removes the need for an external anti-alias filter.
The ADC uses a differential architecture which provides
excellent noise rejection.
! Supports All Audio Sample Rates Including
192 kHz
! 260 mW Power Consumption
! High-Pass Filter or DC Offset Calibration
The CS5381 is available in 24-pin TSSOP and SOIC
packages for Commercial grade (-10° to +70° C). The
CDB5381 Customer Demonstration board is also available for device evaluation and implementation
suggestions. Please refer to the “Ordering Information”
on page 22.
! Supports Logic Levels between 5 and 2.5 V
! Differential Analog Architecture
! Low-Latency Digital Filtering
! Overflow Detection
! Pin-Compatible with the CS5361
Analog Supply
5V
The CS5381 is ideal for audio systems requiring wide
dynamic range, negligible distortion, and low noise such as A/V receivers, DVD-R, CD-R, digital mixing
consoles, and effects processors.
Digital Supply
3.3 V to 5 V
Interface Supply
2.5 V to 5 V
Internal Voltage
Reference
Differential
Inputs
Switch-Cap
ADC
http://www.cirrus.com
Digital
Filters
Digital
Filters
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
Level Translator
Differential
Inputs
Switch-Cap
ADC
Reset
Mode
Configuration
HPF
OVFL
PCM Serial
Audio Output
JULY '05
DS563F2
CS5381
TABLE OF CONTENTS
1. PIN DESCRIPTIONS ............................................................................................................................... 4
2. CHARACTERISTICS AND SPECIFICATIONS....................................................................................... 5
SPECIFIED OPERATING CONDITIONS .................................................................................................... 5
ABSOLUTE MAXIMUM RATINGS............................................................................................................... 5
ANALOG CHARACTERISTICS (CS5381-KSZ/-KZZ).................................................................................. 6
DIGITAL FILTER CHARACTERISTICS....................................................................................................... 7
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT .................................................................... 10
DC ELECTRICAL CHARACTERISTICS.................................................................................................... 13
DIGITAL CHARACTERISTICS .................................................................................................................. 13
THERMAL CHARACTERISTICS .............................................................................................................. 13
TYPICAL CONNECTION DIAGRAM ......................................................................................................... 14
3. APPLICATIONS .................................................................................................................................... 15
3.1 Operational Mode/Sample Rate Range Select.............................................................................. 15
3.2 System Clocking ............................................................................................................................ 15
3.2.1 Master Mode ........................................................................................................................ 15
3.2.2 Slave Mode .......................................................................................................................... 16
3.3 Power-Up Sequence ..................................................................................................................... 16
3.4 Analog Connections ...................................................................................................................... 16
3.5 High-Pass Filter and DC Offset Calibration .................................................................................. 17
3.6 Overflow Detection ........................................................................................................................ 18
3.6.1 OVFL Configuration ............................................................................................................. 18
3.6.2 OVFL Output Timing ............................................................................................................ 18
3.7 Grounding and Power Supply Decoupling..................................................................................... 18
3.8 Synchronization of Multiple Devices .............................................................................................. 18
3.9 Capacitor Size on the Reference Pin (FILT+)................................................................................ 19
4. PACKAGE DIMENSIONS ..................................................................................................................... 20
5. ORDERING INFORMATION ................................................................................................................. 22
7. REVISION HISTORY ............................................................................................................................. 24
2
DS563F2
CS5381
LIST OF FIGURES
Figure 1. Single-Speed Mode Stopband Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2. Single-Speed Mode Transition Band . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. Single-Speed Mode Transition Band (Detail). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Single-Speed Mode Passband Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Double-Speed Mode Stopband Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. Double-Speed Mode Transition Band . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. Double-Speed Mode Transition Band (Detail) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. Double-Speed Mode Passband Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 9. Quad-Speed Mode Stopband Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 10. Quad-Speed Mode Transition Band . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 11. Quad-Speed Mode Transition Band (Detail) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 12. Quad-Speed Mode Passband Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 13. Master Mode, Left-Justified SAI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 14. Slave Mode, Left-Justified SAI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 15. Master Mode, I²S SAI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 16. Slave Mode, I²S SAI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 17. OVFL Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 18. Left-Justified Serial Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 19. I²S Serial Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 20. OVFL Output Timing, I²S Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 21. OVFL Output Timing, Left-Justified Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 22. Typical Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 23. CS5381 Master Mode Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 24. Recommended Analog Input Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 25. CS5381 THD + N versus Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
LIST OF TABLES
Table 1. CS5381 Mode Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 2. CS5381 Common Master Clock Frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 3. CS5381 Slave Mode Clock Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DS563F2
3
CS5381
1. PIN DESCRIPTIONS
RST
M/S
LRCK
SCLK
MCLK
VD
GND
VL
SDOUT
MDIV
HPF
I²S/LJ
Pin Name
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
FILT+
REFGND
VQ
AINR+
AINRVA
GND
AINLAINL+
OVFL
M1
M0
#
Pin Description
RST
1
Reset (Input) - The device enters a low power mode when low.
M/S
2
Master/Slave Mode (Input) - Selects operation as either clock master or slave.
LRCK
3
Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the
serial audio data line.
SCLK
4
Serial Clock (Input/Output) - Serial clock for the serial audio interface.
MCLK
5
Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
VD
6
Digital Power (Input) - Positive power supply for the digital section.
GND
7,18
Ground (Input) - Ground reference. Must be connected to analog ground.
VL
8
Logic Power (Input) - Positive power for the digital input/output.
SDOUT
9
Serial Audio Data Output (Output) - Output for two’s complement serial audio data.
MDIV
10
MCLK Divider (Input) - Enables a master clock divide by two function.
HPF
11
High-Pass Filter Enable (Input) - Enables the Digital High-Pass Filter.
I²S/LJ
12
Serial Audio Interface Format Select (Input) -Selects either the left-justified or I²S format for the SAI.
M0
M1
13,14 Mode Selection (Input) - Determines the operational mode of the device.
OVFL
15
AINL+
AINL-
16, 17
VA
AINRAINR+
19
20, 21
Overflow (Output, open drain) - Detects an overflow condition on both left and right channels.
Differential Left Channel Analog Input (Input) - Signals are presented differentially to the delta-sigma
modulators via the AINL+/- pins.
Analog Power (Input) - Positive power supply for the analog section.
Differential Right Channel Analog Input (Input) -Signals are presented differentially to the deltasigma modulators via the AINR+/- pins.
VQ
22
Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage.
REF_GND
23
Reference Ground (Input) - Ground reference for the internal sampling circuits.
FILT+
24
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
4
DS563F2
CS5381
2. CHARACTERISTICS AND SPECIFICATIONS
All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at VA = 5.0 V, VD = VL = 3.3 V,
and TA = 25°C.
SPECIFIED OPERATING CONDITIONS
(GND = 0 V; all voltages with respect to 0 V.)
Parameters
Symbol
Min
Typ
Max
Units
VA
VD
VL
4.75
3.1
2.37
5.0
-
5.25
5.25
5.25
V
V
V
TA
-10
-
+70
°C
DC Power Supply
DC Power Supplies:
Positive Analog
Positive Digital
Positive Logic
Ambient Operating Temperature (Power Applied)
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V, All voltages with respect to ground.) (Note 1)
Parameter
Symbol
Min
Typ
Max
Units
Analog
Logic
Digital
VA
VL
VD
-0.3
-0.3
-0.3
-
+6.0
+6.0
+6.0
V
V
V
Input Current
(Note 2)
Iin
-10
-
+10
mA
Analog Input Voltage
(Note 3)
VIN
GND-0.7
-
VA+0.7
V
Digital Input Voltage
(Note 3)
VIND
-0.7
-
VL+0.7
V
TA
-50
-
+95
°C
Tstg
-65
-
+150
°C
DC Power Supplies:
Ambient Operating Temperature (Power Applied)
Storage Temperature
Notes:
1. Operation beyond these limits may result in permanent damage to the device. Normal operation is not
guaranteed at these extremes.
2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SRC latch-up.
3. The maximum over/under voltage is limited by the input current.
DS563F2
5
CS5381
ANALOG CHARACTERISTICS (CS5381-KSZ/-KZZ)
Test conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is
10 Hz to 20 kHz.
Parameter
Single-Speed Mode
Symbol
Dynamic Range
A-weighted
unweighted
Total Harmonic Distortion + Noise
Double-Speed Mode
Max
Unit
114
111
120
117
-
dB
dB
THD+N
-
-110
-97
-57
-104
-
dB
dB
dB
114
111
-
120
117
114
-
dB
dB
dB
-
-110
-97
-57
-107
-104
-
dB
dB
dB
dB
114
111
-
120
117
114
-
dB
dB
dB
-
-110
-97
-57
-107
-104
-
dB
dB
dB
dB
-
110
-
dB
-5
-
0.1
±100
0
100
5
-
dB
%
ppm/°C
LSB
LSB
1.07*VA
-
1.13*VA
2.5
100
1.18*VA
-
Vpp
kΩ
dB
Fs = 96 kHz
A-weighted
unweighted
40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise
(Note 4)
-1 dB
-20 dB
-60 dB
-1 dB
40 kHz bandwidth
Quad-Speed Mode
Dynamic Range
Typ
(Note 4)
-1 dB
-20 dB
-60 dB
Dynamic Range
Min
Fs = 48 kHz
THD+N
Fs = 192 kHz
A-weighted
unweighted
40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise
(Note 4)
-1 dB
-20 dB
-60 dB
-1 dB
40 kHz bandwidth
THD+N
Dynamic Performance for All Modes
Interchannel Isolation
DC Accuracy
Interchannel Gain Mismatch
Gain Error
Gain Drift
Offset Error
HPF enabled
HPF disabled
Analog Input Characteristics
Full-scale Input Voltage
Input Impedance (Differential)
(Note 5)
Common Mode Rejection Ratio
CMRR
4. Referred to the typical full-scale input voltage.
5. Measured between AIN+ and AIN-.
6
DS563F2
CS5381
DIGITAL FILTER CHARACTERISTICS
Parameter
Symbol
Min
Typ
Max
Unit
0
-
0.47
Fs
-0.1
-
0.035
dB
0.58
-
-
Fs
-95
-
-
dB
-
12/Fs
-
s
(Note 6)
0
-
0.45
Fs
-0.1
-
0.035
dB
(Note 6)
0.68
-
-
Fs
-92
-
-
dB
-
9/Fs
-
s
0
-
0.24
Fs
-0.1
-
0.035
dB
0.78
-
-
Fs
-97
-
-
dB
-
5/Fs
-
s
-
1
20
-
Hz
Hz
-
10
-
Deg
-
-
0
dB
Single-Speed Mode (2 kHz to 54 kHz sample rates)
Passband
(-0.1 dB)
(Note 6)
Passband Ripple
Stopband
(Note 6)
Stopband Attenuation
tgd
Total Group Delay (Fs = Output Sample Rate)
Double-Speed Mode (50 kHz to 108 kHz sample rates)
Passband
(-0.1 dB)
Passband Ripple
Stopband
Stopband Attenuation
tgd
Total Group Delay (Fs = Output Sample Rate)
Quad-Speed Mode (100 kHz to 216 kHz sample rates)
Passband
(-0.1 dB)
(Note 6)
Passband Ripple
Stopband
(Note 6)
Stopband Attenuation
tgd
Total Group Delay (Fs = Output Sample Rate)
High-Pass Filter Characteristics
Frequency Response
Phase Deviation
-3.0 dB
-0.13 dB
(Note 7)
@ 20 Hz
(Note 7)
Passband Ripple
Filter Setting Time
105/Fs
s
6. The filter frequency response scales precisely with Fs.
7. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs.
DS563F2
7
0
0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
Amplitude (dB)
Amplitude (dB)
CS5381
-60
-70
-80
-60
-70
-80
-90
-90
-100
-100
-110
-110
-120
-120
-130
-130
-140
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Frequency (normalized to Fs)
-140
0.40
0.42
0.44
0.46
0.48
0.50
0.52
0.54
0.56
0.58
0.60
Frequency (normalized to Fs)
Figure 1. Single-Speed Mode Stopband Rejection
Figure 2. Single-Speed Mode Transition Band
0
0.10
-1
0.08
-2
0.05
0.03
-4
Amplitude (dB)
Amplitude (dB)
-3
-5
-6
0.00
-0.03
-7
-0.05
-8
-0.08
-9
-10
0.45
0.46
0.47
0.48
0.49
0.50
0.51
0.52
0.53
0.54
-0.10
0.00
0.55
0.05
0.10
0.15
0.20
Frequency (normalized to Fs)
0.25
0.30
0.35
0.40
0.45
0.50
Frequency (normalized to Fs)
Figure 3. Single-Speed Mode Transition Band (Detail)
Figure 4. Single-Speed Mode Passband Ripple
0
0
-10
-10
-20
-20
-30
-30
-40
-40
-50
Amplitude (dB)
Amplitude (dB)
-50
-60
-70
-80
-60
-70
-80
-90
-90
-100
-100
-110
-110
-120
-120
-130
-130
-140
0.40
-140
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0.43
0.45
0.48
0.50
0.53
0.55
0.58
0.60
0.63
0.65
0.68
0.70
Frequency (normalized to Fs)
Frequency (normalized to Fs)
Figure 5. Double-Speed Mode Stopband Rejection
8
Figure 6. Double-Speed Mode Transition Band
DS563F2
CS5381
0
0.10
-1
0.08
-2
0.05
0.03
-4
Amplitude (dB)
Amplitude (dB)
-3
-5
-6
0.00
-0.03
-7
-0.05
-8
-0.08
-9
-10
0.40
0.43
0.45
0.48
0.50
0.53
0.55
-0.10
0.00
0.05
0.10
0.15
0.20
Frequency (normalized to Fs)
0.25
0.30
0.35
0.40
0.45
0.50
Frequency (normalized to Fs)
Figure 7. Double-Speed Mode Transition Band (Detail)
Figure 8. Double-Speed Mode Passband Ripple
0
0
-10
-10
-20
-20
-30
-30
-40
Amplitude (dB)
Amplitude (dB)
-40
-50
-60
-70
-50
-60
-70
-80
-80
-90
-90
-100
-100
-110
-110
-120
-130
-120
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0.2
1.0
0.25
0.3
0
0.10
-1
0.08
-2
0.06
-3
0.04
-4
0.02
-5
-6
-8
-0.06
-9
-0.08
-10
0.25
0.3
0.35
0.4
0.45
0.5
0.55
0.6
Frequency (normalized to Fs)
Figure 11. Quad-Speed Mode Transition Band (Detail)
DS563F2
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.00
-0.04
0.2
0.45
-0.02
-7
0.15
0.4
Figure 10. Quad-Speed Mode Transition Band
Amplitude (dB)
Amplitude (dB)
Figure 9. Quad-Speed Mode Stopband Rejection
0.1
0.35
Frequency (normalized to Fs)
Frequency (normalized to Fs)
-0.10
0.00
0.05
0.10
0.15
0.20
0.25
Frequency (normalized to Fs)
Figure 12. Quad-Speed Mode Passband Ripple
9
CS5381
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT
(Logic “0” = GND = 0 V; Logic “1” = VL, CL = 20 pF)
Parameter
Symbol
Min
Typ
Max
Unit
Fs
Fs
Fs
2
50
100
-
54
108
216
kHz
kHz
kHz
OVFL to LRCK Edge Setup Time
tsetup
16/fsclk
-
-
s
OVFL to LRCK Edge Hold Time
thold
1/fsclk
-
-
s
-
740
680
-
ms
ms
36
-
1953
ns
40
-
60
%
-
20
ns
Output Sample Rate
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
OVFL time-out on overrange condition
Fs = 44.1, 88.2, 176.4 kHz
Fs = 48, 96, 192 kHz
MCLK Specifications
MCLK Period
tclkw
MCLK Duty Cycle
Master Mode
SCLK falling to LRCK transition
tmslr
-20
SCLK falling to SDOUT valid
tsdo
-
-
32
ns
-
50
-
%
SCLK Duty Cycle
Slave Mode
Single-Speed
Output Sample Rate
Fs
LRCK Duty Cycle
SCLK Period
tsclkw
SCLK Duty Cycle
2
-
54
kHz
40
50
60
%
145
-
-
ns
45
50
55
%
SDOUT valid before SCLK rising
tstp
10
-
-
ns
SDOUT valid after SCLK rising
thld
5
-
-
ns
SCLK falling to LRCK transition
tslrd
-20
-
20
ns
Fs
50
-
108
kHz
40
50
60
%
145
-
-
ns
45
50
55
%
Double-Speed
Output Sample Rate
LRCK Duty Cycle
SCLK Period
tsclkw
SCLK Duty Cycle
SDOUT valid before SCLK rising
tstp
10
-
-
ns
SDOUT valid after SCLK rising
thld
5
-
-
ns
SCLK falling to LRCK transition
tslrd
-20
-
20
ns
Fs
100
-
216
kHz
40
50
60
%
72
-
-
ns
45
50
55
%
Quad-Speed
Output Sample Rate
LRCK Duty Cycle
SCLK Period
tsclkw
SCLK Duty Cycle
SDOUT valid before SCLK rising
tstp
10
-
-
ns
SDOUT valid after SCLK rising
thld
5
-
-
ns
SCLK falling to LRCK transition
tslrd
-8
-
8
ns
10
DS563F2
CS5381
LRCK input
LRCK output
t slrd
tmslr
SCLK input
SCLK output
t sclkh
t sdo
SDOUT
MSB
MSB-1
MSB-2
MSB-3
SDOUT
Figure 13. Master Mode, Left-Justified SAI
MSB
MSB-1
Figure 14. Slave Mode, Left-Justified SAI
LRCK input
LRCK output
t slrd
tmslr
SCLK input
SCLK output
t sclkh
MSB
MSB-1
MSB-2 MSB-3
t sclkl
t stp t hld
t sdo
SDOUT
t sclkl
t stp t hld
SDOUT
Figure 15. Master Mode, I²S SAI
MSB
Figure 16. Slave Mode, I²S SAI
LRCK
t setup
t hold
OVFL
Figure 17. OVFL Output Timing
DS563F2
11
CS5381
LRCK
Left Channel
Right Channel
SCLK
SDATA
23
22
9 8 7 6 5 4 3 2 1 0
23
22
9 8 7 6 5 4 3 2 1 0
23
22
23
22
Figure 18. Left-Justified Serial Audio Interface
LRCK
Left Channel
Right Channel
SCLK
SDATA
23
22
9 8 7 6 5 4 3 2 1 0
23
22
9 8 7 6 5 4 3 2 1 0
Figure 19. I²S Serial Audio Interface
Left Channel Frame
LRCK
Right Channel Frame
SCLK
OVFL
OVFL on Left Chan
OVFL on Right Chan
Figure 20. OVFL Output Timing, I²S Format
LRCK
R ig h t C h a n n e l F r a m e
L e ft C h a n n e l F r a m e
SC LK
OVFL
O V F L o n R ig h t C h a n
O V F L o n L e ft
C han
Figure 21. OVFL Output Timing, Left-Justified Format
12
DS563F2
CS5381
DC ELECTRICAL CHARACTERISTICS
(GND = 0 V, all voltages with respect to ground. MCLK=12.288 MHz; Master Mode)
Parameter
Symbol
Min
Typ
Max
Unit
VA = 5 V
VL,VD = 5 V
VL,VD = 3.3 V
IA
ID
ID
-
36
36
24
43
46
28
mA
mA
mA
VA = 5 V
VL,VD = 5 V
IA
ID
-
100
100
-
uA
uA
VA, VL, VD = 5 V
VA = 5 V; VL, VD = 3.3 V
(Power-Down Mode)
-
-
360
260
1
445
307
-
mW
mW
mW
PSRR
-
65
-
dB
-
2.5
25
0.01
-
V
kΩ
mA
-
5
4.5
0.01
-
V
kΩ
mA
Power Supply Current
(Normal Operation)
Power Supply Current
(Power-Down Mode) (Note 8)
Power Consumption
(Normal Operation)
Power Supply Rejection Ratio (1 kHz)
(Note 9)
VQ Nominal Voltage
Output Impedance
Maximum allowable DC current source/sink
Filt+ Nominal Voltage
Output Impedance
Maximum allowable DC current source/sink
8. Power-Down Mode is defined as RST = Low with all clocks and data lines held static.
9. Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical Connection
Diagram.
DIGITAL CHARACTERISTICS
Parameter
Symbol
Min
Typ
Max
Units
VIH
70%
-
-
V
High-Level Input Voltage
(% of VL)
Low-Level Input Voltage
(% of VL)
VIL
-
-
30%
V
High-Level Output Voltage at Io = 100 µA
(% of VL)
VOH
70%
-
-
V
Low-Level Output Voltage at Io = 100 µA
(% of VL)
VOL
-
-
15%
V
Iovfl
-
-
4.0
mA
Iin
-10
-
10
µA
OVFL Current Sink
Input Leakage Current
THERMAL CHARACTERISTICS
Parameter
Symbol
Allowable Junction Temperature
Junction to Ambient Thermal Impedance
(Multi-layer PCB) TSSOP
(Multi-layer PCB) SOIC
(Single-layer PCB) TSSOP
(Single-layer PCB) SOIC
DS563F2
θJA-TM
θJA-SM
θJA-TS
θJA-SS
Min
Typ
Max
Unit
-
-
135
°C
-
70
60
105
80
-
°C/W
°C/W
°C/W
°C/W
13
CS5381
TYPICAL CONNECTION DIAGRAM
+5 V to 3.3 V
+5V
+
1 µF
0.01 µF
0.01µF
*
+
1 µF
VA
VD
VL
FILT+
**47 µF
+
VL
0.01 µF
10 k
REFGND
+
1 µF
0.01 µF
VQ
Analog
Input
Buffer
(Figure 24)
+5Vto 2.5 V
1 µF
0.01 µF
5.1 Ω
0.01 µF
+
AINL+
CS5381
A/D CONVERTER
OVFL
RST
2
I S/LJ
M/S
HPF
M0
M1
MDIV
Power Down
and Mode
Settings
SDOUT
Audio Data
Processor
AINL-
Analog
Input
Buffer
(Figure 24)
AINR+
LRCK
Timing Logic
and Clock
SCLK
MCLK
AINR-
* Resistor may only
be used if VD is
derived from VA. If
used, do not drive any
other logic from VD.
GND
GND
** Capacitor value
affects low frequency
distortion. See
Section 3.9.
Figure 22. Typical Connection Diagram
14
DS563F2
CS5381
3. APPLICATIONS
3.1
Operational Mode/Sample Rate Range Select
The output sample rate, Fs, can be adjusted from 2 kHz to 216 kHz. The CS5381 must be set to the proper
speed mode via the mode pins, M1 and M0. Refer to Table 1.
M1 (Pin 14)
0
0
1
1
M0 (Pin 13)
0
1
0
1
MODE
Output Sample Rate (Fs)
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Reserved
2 kHz - 54 kHz
50 kHz - 108 kHz
100 kHz - 216 kHz
Table 1. CS5381 Mode Control
3.2
System Clocking
The device supports operation in either Master Mode, where the left/right and serial clocks are synchronously generated on-chip, or Slave Mode, which requires external generation of the left/right and serial clocks.
The device also includes a master clock divider in Master Mode where the master clock will be internally
divided prior to any other internal circuitry when MDIV is enabled, set to logic 1. In Slave Mode, the MDIV
pin needs to be disabled, set to logic 0.
3.2.1
Master Mode
In Master mode, LRCK and SCLK operate as outputs. The left/right and serial clocks are internally derived
from the master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as shown
in Figure 23. Refer to Table 2 for common master clock frequencies.
÷1
÷ 256
Single
Speed
00
÷ 128
Double
Speed
01
÷ 64
Quad
Speed
10
LRCK Output
(Equal to Fs)
0
M1 M0
MCLK
÷2
1
MDIV
÷4
Single
Speed
00
÷2
Double
Speed
01
÷1
Quad
Speed
10
SCLK Output
Figure 23. CS5381 Master Mode Clocking
DS563F2
15
CS5381
SAMPLE RATE (kHz)
MDIV = 0
MCLK (MHz)
MDIV = 1
MCLK (MHz)
32
44.1
48
64
88.2
96
176.4
192
8.192
11.2896
12.288
8.192
11.2896
12.288
11.2896
12.288
16.384
22.5792
24.576
16.384
22.5792
24.576
22.5792
24.576
Table 2. CS5381 Common Master Clock Frequencies
3.2.2
Slave Mode
LRCK and SCLK operate as inputs in Slave mode. It is recommended that the left/right clock be synchronously derived from the master clock and must be equal to Fs. It is also recommended that the serial clock
be synchronously derived from the master clock and be equal to 64x Fs to maximize system performance.
Refer to Table 3 for required clock ratios.
Single-Speed Mode Double-Speed Mode
Quad-Speed Mode
Fs = 2 kHz to 54 kHz Fs = 50 kHz to 108 kHz Fs = 100 kHz to 216 kHz
MCLK/LRCK Ratio
256x, 512x
128x, 256x
64x*, 128x
SCLK/LRCK Ratio
64x, 128x
64x
64x
* Only available in Master mode.
Table 3. CS5381 Slave Mode Clock Ratios
3.3
Power-Up Sequence
Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and
configuration pins are stable. It is also recommended that reset be enabled if the analog or digital supplies
drop below the minimum specified operating voltages to prevent power glitch related issues.
The internal reference voltage must be stable for the device to produce valid data. Therefore, there is a delay between the release of reset and the generation of valid output, due to the finite output impedance of
FILT+ and the presence of the external capacitance. This duration of this delay is less than 2500 LRCK cycles.
3.4
Analog Connections
The analog modulator samples the input at 6.144 MHz. The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which are (n × 6.144 MHz) the digital passband frequency, where n=0,1,2,... Refer to Figure 24, which shows the suggested filter that will attenuate
any noise energy at 6.144 MHz in addition to providing the optimum source impedance for the modulators.
The use of capacitors which have a large voltage coefficient (such as general purpose ceramics) must be
avoided since these can degrade signal linearity. C0G capacitors are recommended for this application.
16
DS563F2
CS5381
634 Ω
470 pF
COG
91 Ω
10 uF
ADC AIN+
+
AIN+
100kΩ
10 k Ω
COG
VQ
2700 pF
10 k Ω
10 uF
AIN-
+
100kΩ
-
91 Ω
ADC AIN-
470 pF
COG
634 Ω
Figure 24. Recommended Analog Input Buffer
3.5
High-Pass Filter and DC Offset Calibration
The operational amplifiers in the input circuitry driving the CS5381 may generate a small DC offset into the
A/D converter. The CS5381 includes a high-pass filter after the decimator to remove any DC offset which
could result in recording a DC level, possibly yielding “clicks” when switching between devices in a multichannel system.
The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation
filter. If the HPF pin is taken high during normal operation, the current value of the DC offset register is frozen
and this DC offset will continue to be subtracted from the conversion result. This feature makes it possible
to perform a system DC offset calibration by:
1. Running the CS5381 with the high-pass filter enabled until the filter settles. See the Digital Filter Characteristics for filter settling time.
2. Disabling the high-pass filter and freezing the stored DC offset.
A system calibration performed in this way will eliminate offsets anywhere in the signal path between the
calibration point and the CS5381.
DS563F2
17
CS5381
3.6
Overflow Detection
The CS5381 includes overflow detection on both the left and right channels. This time multiplexed information is presented as open drain, active low on pin 15, OVFL. The OVFL_L and OVFL_R data will go to a
logical low as soon as an overrange condition in the opposite channel is detected. The data will remain low
as specified in the “Switching Characteristics - Serial Audio Port” section on page 10. This ensures sufficient
time to detect an overrange condition regardless of the speed mode. After the timeout, the OVFL_L and
OVFL_R data will return to a logical high if there has not been any other overrange condition detected.
Please note that an overrange condition on either channel will restart the timeout period for both channels.
3.6.1
OVFL Configuration
If the system does not require overflow detection, the user may leave the OVFL pin disconnected. When
using the overflow detection capability of the CS5381, a 10 kΩ pull-up resistor must be inserted between
the OVFL pin and VL because the OVFL output is open drain, active low. This means that the OVFL pin
is high impedance for the case of no overflow condition, but the pull-up resistor will pull the node to VL.
When an overflow condition occurs, the OVFL pin can drive the node to GND thus indicating the presence
of the overflow condition. In effect, the user can use the OVFL pin to illuminate an LED, or mute the channel with an external circuit or a DSP. Furthermore, because the OVFL output is open-drain, the OVFL pins
of multiple CS5381 devices can be tied together such that an overflow condition on a single device will
drive the line low. When connecting OVFL pins of multiple devices, only a single 10kΩ pull-up resistor is
necessary.
3.6.2
OVFL Output Timing
In left-justified format, the OVFL pin is updated one SCLK period after an LRCK transition. In I²S format,
the OVFL pin is updated two SCLK periods after an LRCK transition. Refer to Figures 20 and 21. In both
cases, the OVFL data can be easily demultiplexed by using the LRCK to latch the data. In left-justified
format, the rising edge of LRCK would latch the right channel overflow status, and the falling edge of
LRCK would latch the left channel overflow status. In I²S format, the falling edge of LRCK would latch the
right channel overflow status and the rising edge of LRCK would latch the left channel overflow status.
3.7
Grounding and Power Supply Decoupling
As with any high resolution converter, the CS5381 requires careful attention to power supply and grounding
arrangements if its potential performance is to be realized. Figure 22 shows the recommended power arrangements, with VA and VL connected to clean supplies. VD, which powers the digital filter, may be run
from the system logic supply or may be powered from the analog supply via a resistor. In this case, no additional devices should be powered from VD. Decoupling capacitors should be as near to the ADC as possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be kept
away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and
VQ decoupling capacitors, particularly the 0.01 µF, must be positioned to minimize the electrical path from
FILT+ and REFGND. The CDB5381 evaluation board demonstrates the optimum layout and power supply
arrangements. To minimize digital noise, connect the ADC digital outputs only to CMOS inputs.
3.8
Synchronization of Multiple Devices
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To
ensure synchronous sampling, the MCLK and LRCK must be the same for all of the CS5381’s in the system.
If only one master clock source is needed, one solution is to place one CS5381 in Master mode, and slave
all of the other CS5381’s to the one master. If multiple master clock sources are needed, a possible solution
would be to supply all clocks from the same external source and time the CS5381 reset with the falling edge
of MCLK. This will ensure that all converters begin sampling on the same clock edge.
18
DS563F2
CS5381
3.9
Capacitor Size on the Reference Pin (FILT+)
The CS5381 requires an external capacitance on the internal reference voltage pin, FILT+. The size of this
decoupling capacitor will affect the low frequency distortion performance as shown in Figure 25, with larger
capacitor values used to optimize low frequency distortion performance. The THD+N curves in Figure 25
were measured with VA=VD=VL=5 V in Single-Speed Master Mode with a full-scale sinewave input.
1 uF
10 uF
22 uF
47 uF
100 uF
220 uF
Figure 25. CS5381 THD + N versus Frequency
DS563F2
19
CS5381
4. PACKAGE DIMENSIONS
24L SOIC (300 MIL BODY) PACKAGE DRAWING
E
H
1
b
c
∝
D
L
SEATING
PLANE
A
e
A1
INCHES
DIM
MIN
MAX
A
A1
B
C
D
E
e
H
L
0.093
0.004
0.013
0.009
0.598
0.291
0.040
0.394
0.016
0°
0.104
0.012
0.020
0.013
0.614
0.299
0.060
0.419
0.050
8°
∝
20
MILLIMETERS
MIN
MAX
2.35
0.10
0.33
0.23
15.20
7.40
1.02
10.00
0.40
0°
2.65
0.30
0.51
0.32
15.60
7.60
1.52
10.65
1.27
8°
DS563F2
CS5381
24L TSSOP (4.4 mm BODY) PACKAGE DRAWING
N
D
E11
A2
E
A
∝
e
b2
SIDE VIEW
A1
L
END VIEW
SEATING
PLANE
1 2 3
TOP VIEW
DIM
MIN
INCHES
NOM
MAX
MIN
MILLIMETERS
NOM
MAX
NOTE
A
A1
A2
b
D
E
E1
e
L
µ
-0.002
0.03346
0.00748
0.303
0.248
0.169
-0.020
0°
-0.004
0.0354
0.0096
0.307
0.2519
0.1732
0.026 BSC
0.024
4°
0.043
0.006
0.037
0.012
0.311
0.256
0.177
-0.028
8°
-0.05
0.85
0.19
7.70
6.30
4.30
-0.50
0°
--0.90
0.245
7.80
6.40
4.40
0.65 BSC
0.60
4°
1.10
0.15
0.95
0.30
7.90
6.50
4.50
-0.70
8°
2,3
1
1
JEDEC #: MO-153
Controlling Dimension is Millimeters.
Notes:
1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.
2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
DS563F2
21
CS5381
5. ORDERING INFORMATION
Product
Description
Package
Pb-Free
Grade
Temp
Range
CS5381
120 dB, 192 kHz, Multi-Bit
24-TSSOP
Audio A/D Converter
Yes
Commercial -10° to +70° C
CS5381
120 dB, 192 kHz, Multi-Bit
Audio A/D Converter
24-SOIC
Yes
Commercial -10° to +70° C
-
-
CDB5381 CS5381 Evaluation Board
22
-
-
Container
Order #
Bulk
CS5381-KZZ
Tape & Reel CS5381-KZZR
Bulk
CS5381-KSZ
Tape & Reel CS5381-KSZR
-
CDB5381
DS563F2
CS5381
6
PARAMETER DEFINITIONS
Dynamic Range
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with
a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This
technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991,
and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.
Total Harmonic Distortion + Noise
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured
at -1 and -20 dBFS as suggested in AES17-1991 Annex A.
Frequency Response
A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at
1 kHz. Units in decibels.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full-scale analog input for a full-scale digital output.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
Offset Error
The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
DS563F2
23
CS5381
7. REVISION HISTORY
Release
A1
A2
Date
December 2002 Initial Release
October 2003
Changes
Changed front page description of digital filter
Improved distortion specification from -105 dB to -110 dB
Modified serial port timing specifications for slave mode operation
Added pull-down resistors to recommended input buffer
Changed full-scale voltage specification to reflect VA supply voltage
Added Applications section about capacitor value on FILT+ pin
Changed input impedance specification from 37 to 2.5 kΩ
Changed impedance specification on FILT+ from 35 to 4.5 kΩ
A3
May 2004
A4
August 2004
F1
July 2005
Replaced diagrams showing OVFL functionality (see Figures 20 and 21)
Replaced Figures 13, 15, 18 and 19 to demonstrate pre-emption of the MSB.
Increased maximum digital current (ID) specification at 5 V from 43 mA to 46 mA. .
F2
July 2005
Updated Ordering Information.
Add Lead free part number
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE
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to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
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IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD
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Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
24
DS563F2