CS4344/5/8 Datasheet

CS4344/5/8
10-Pin, 24-Bit, 192 kHz Stereo D/A Converter
Features
Description
 Multi-bit Delta-Sigma Modulator
The CS4344 family members (CS4344, CS4345, and
CS4348) are complete, stereo digital-to-analog output
systems including interpolation, multibit D/A conversion
and output analog filtering in a 10-pin package. The
CS4344 family supports major audio data interface formats. Individual devices differ only in the supported
interface format.
 24-bit Conversion
 Automatically Detects Sample Rates up to
192 kHz.
 105 dB Dynamic Range
The CS4344 family is based on a fourth-order multibit
delta-sigma modulator with a linear analog low-pass filter. This family also includes autospeed mode detection
using both sample rate and master clock ratio as a
method of auto-selecting sampling rates between 2 kHz
and 200 kHz.
 -90 dB THD+N
 Low Clock-Jitter Sensitivity
 Single +3.3 or +5 V Power Supply
The CS4344 family contains on-chip digital deemphasis, operates from a single +3.3 V or +5 V power supply,
and requires minimal support circuitry. These features
are ideal for DVD players & recorders, digital televisions, home theater and set top box products, and
automotive audio systems.
 Filtered Line-Level Outputs
 On-chip Digital De-emphasis
 Popguard® Technology
The CS4344 family is available in a 10-pin TSSOP
package in both Commercial (-10 to +85 °C) and Automotive grades (-40 to +85 °C). See Section 8. “Ordering
Information” on page 23 for complete details.
 Small 10-pin TSSOP Package
3.3 V or 5 V
De-emphasis
Serial Audio
Input
PCM
Serial
Interface
Interpolation
Filter
Multibit
Modulator
Switched
Capacitor
DAC and
Filter
Left
Output
Interpolation
Filter
Multibit
Modulator
Switched
Capacitor
DAC and
Filter
Right
Output
Internal
Voltage
Reference
http://www.cirrus.com
Copyright  Cirrus Logic, Inc. 2013
(All Rights Reserved)
JUL ‘13
DS613F2
CS4344/5/8
TABLE OF CONTENTS
1. PIN DESCRIPTIONS .............................................................................................................................. 4
2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 5
SPECIFIED OPERATING CONDITIONS ............................................................................................... 5
ABSOLUTE MAXIMUM RATINGS ......................................................................................................... 5
DAC ANALOG CHARACTERISTICS ..................................................................................................... 6
DAC ANALOG CHARACTERISTICS - ALL MODES ............................................................................. 6
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ........................................ 7
DIGITAL INPUT CHARACTERISTICS ................................................................................................... 8
POWER AND THERMAL CHARACTERISTICS ................................................................................... 8
SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE ...................................................... 9
3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 11
4. APPLICATIONS ................................................................................................................................... 12
4.1 Master Clock ................................................................................................................................... 12
4.2 Serial Clock .................................................................................................................................... 12
4.2.1 External Serial Clock Mode ................................................................................................... 12
4.2.2 Internal Serial Clock Mode .................................................................................................... 12
4.3 De-Emphasis .................................................................................................................................. 15
4.4 Initialization and Power-Down ........................................................................................................ 15
4.5 Output Transient Control ................................................................................................................ 15
4.5.1 Power-Up .............................................................................................................................. 15
4.5.2 Power-Down .......................................................................................................................... 15
4.6 Grounding and Power Supply Decoupling ...................................................................................... 17
4.7 Analog Output and Filtering ............................................................................................................ 17
5. FILTER PLOTS ..................................................................................................................................... 18
6. PARAMETER DEFINITIONS ................................................................................................................ 21
7. PACKAGE DIMENSIONS .................................................................................................................... 22
8. ORDERING INFORMATION ................................................................................................................ 23
8.1 Functional Compatibility ................................................................................................................. 23
8.2 Selection Guide .............................................................................................................................. 23
9. REVISION HISTORY ............................................................................................................................ 24
2
CS4344/5/8
LIST OF FIGURES
Figure 1.Output Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 2.Maximum Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 3.External Serial Mode Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 4.Internal Serial Mode Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 5.Internal Serial Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 6.Typical Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 7.CS4344 Data Format (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 8.CS4345 Data Format (Left Justified) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 9.CS4348 Data Format (Right Justified 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 10.De-Emphasis Curve (Fs = 44.1kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 11.CS4344/5/8 Initialization and Power-down Sequence . . . . . . . . . . . . . . . . . . . . . . .16
Figure 12.Single-Speed Stopband Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 13.Single-Speed Transition Band . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 14.Single-Speed Transition Band . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 15.Single-Speed Passband Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 16.Double-Speed Stopband Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 17.Double-Speed Transition Band . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 18.Double-Speed Transition Band . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 19.Double-Speed Passband Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 20.Quad-Speed Stopband Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 21.Quad-Speed Transition Band . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 22.Quad-Speed Transition Band . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 23.Quad-Speed Passband Ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3
CS4344/5/8
1. PIN DESCRIPTIONS
1
10
DEM/SCLK
2
9
VA
LRCK
3
8
GND
MCLK
4
7
AOUTL
VQ
5
6
FILT+
AOUTR
Pin Name
#
SDIN
1
Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
2
De-Emphasis/External Serial Clock Input (Input) - used for deemphasis filter control or external serial
clock input.
3
Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio
data line.
MCLK
4
Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
VQ
5
Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.
6
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling
circuits.
7
Left Channel Analog Output (Output) - The full scale analog output level is specified in the Analog Characteristics specification table.
GND
8
Ground (Input) - ground reference.
VA
9
Analog Power (Input) - Positive power for the analog and digital sections.
DEM/SCLK
LRCK
FILT+
AOUTL
AOUTR
4
SDIN
Pin Description
10 Right Channel Analog Output (Output) - The full scale analog output level is specified in the Analog
Characteristics specification table.
CS4344/5/8
2. CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical
performance characteristics and specifications are derived from measurements taken at nominal supply voltage
and TA = 25C.)
SPECIFIED OPERATING CONDITIONS
(AGND = 0 V; all voltages with respect to ground.)
Parameters
DC Power Supply
Specified Temperature Range
-CZZ
-DZZ
Symbol
Min
Nom
Max
Units
VA
4.75
3.00
-10
-40
5.0
3.3
-
5.25
3.47
+70
+85
V
V
C
C
TA
ABSOLUTE MAXIMUM RATINGS
(AGND = 0 V; all voltages with respect to ground.)
Parameters
DC Power Supply
Input Current, Any Pin Except Supplies
Digital Input Voltage
Ambient Operating Temperature (power applied)
Storage Temperature
Symbol
Min
Max
Units
VA
Iin
VIND
Top
Tstg
-0.3
-0.3
-55
-65
6.0
±10
VA+0.4
125
150
V
mA
V
°C
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation
is not guaranteed at these extremes.
5
CS4344/5/8
DAC ANALOG CHARACTERISTICS
(Full-Scale Output Sine Wave, 997 Hz (Note 1), Fs = 48/96/192 kHz; Test load RL = 3 k, CL = 10 pF (Figure 1).
Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified.)
5 V Nom
Parameter
Min
3.3 V Nom
Typ
Max
Min
Typ
Max
Unit
99
96
90
87
105
102
96
93
-
97
94
90
87
103
100
96
93
-
dB
dB
dB
dB
-
-90
-82
-42
-90
-73
-33
-85
-76
-36
-84
-67
-27
-
-90
-80
-40
-90
-73
-33
-85
-74
-34
-84
-67
-27
dB
dB
dB
dB
dB
dB
95
92
86
83
105
102
96
93
-
93
90
86
83
103
100
96
93
-
dB
dB
dB
dB
-
-90
-82
-42
-90
-73
-33
-82
-72
-32
-82
-63
-23
-
-90
-80
-40
-90
-73
-33
-82
-70
-30
-82
-63
-23
dB
dB
dB
dB
dB
dB
Dynamic Performance for CS4344/5/8-CZZ (-10 to 70°C)
Dynamic Range
18 to 24-Bit
16-Bit
A-weighted
unweighted
A-weighted
unweighted
Total Harmonic Distortion + Noise
18 to 24-Bit
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
16-Bit
Dynamic Performance for CS4344/5-DZZ (-40 to 85°C)
Dynamic Range
18 to 24-Bit
16-Bit
A-weighted
unweighted
A-weighted
unweighted
Total Harmonic Distortion + Noise
18 to 24-Bit
16-Bit
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
Notes:
1. One LSB of triangular PDF dither added to data.
DAC ANALOG CHARACTERISTICS - ALL MODES
Parameter
Interchannel Isolation
Symbol
(1 kHz)
Min
Typ
Max
Unit
-
100
-
dB
DC Accuracy
Interchannel Gain Mismatch
-
0.1
0.25
dB
Gain Drift
-
100
-
ppm/°C
Analog Output
Full Scale Output Voltage
0.60•VA
0.65•VA
0.70•VA
Vpp
VQ
-
0.5•VA
-
VDC
IOUTmax
-
10
-
A
IQmax
-
100
-
A
Max AC-Load Resistance (see Figure 2 on page 8)
RL
-
3
-
k
Max Load Capacitance (see Figure 2 on page 8)
CL
-
100
-
pF
ZOUT
-
100
-

Quiescent Voltage
Max DC Current draw from an AOUT pin
Max Current draw from VQ
Output Impedance
6
CS4344/5/8
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
(The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs.) See (Note 6)
Parameter
Symbol
Min
Typ
Max
Unit
0
0
-
.35
.4992
Fs
Fs
-.175
-
+.01
dB
.5465
-
-
Fs
50
-
-
dB
-
10/Fs
-
s
-
-
+1.5/+0
+.05/-.25
-.2/-.4
dB
dB
dB
0
0
-
.22
.501
Fs
Fs
Combined Digital and On-chip Analog Filter Response—Single-Speed Mode
Passband (Note 2)
to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz
StopBand
StopBand Attenuation
(Note 3)
Group Delay
De-emphasis Error (Note 5)
tgd
Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
Combined Digital and On-chip Analog Filter Response—Double-Speed Mode
Passband (Note 2)
to +0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz
-.15
-
+.15
dB
.5770
-
-
Fs
55
-
-
dB
-
5/Fs
-
s
0
0
-
0.110
0.469
Fs
Fs
Frequency Response 10 Hz to 20 kHz
-.12
-
+0
dB
StopBand
0.7
-
-
Fs
StopBand
StopBand Attenuation
(Note 3)
Group Delay
tgd
Combined Digital and On-chip Analog Filter Response—Quad-Speed Mode
Passband (Note 2)
StopBand Attenuation
to -0.1 dB corner
to -3 dB corner
(Note 3)
Group Delay
tgd
51
-
-
dB
-
2.5/Fs
-
s
Notes:
2. Response is clock dependent and will scale with Fs.
3. For Single-Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs.
For Double-Speed Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs.
For Quad-Speed Mode, the Measurement Bandwidth is 0.7 Fs to 1 Fs.
4. Refer to Figure 2.
5. De-emphasis is available only in Single-Speed Mode.
6. Amplitude vs. Frequency plots of this data are available in “Filter Plots” on page 18.
7
CS4344/5/8
DIGITAL INPUT CHARACTERISTICS
Parameters
High-Level Input Voltage
Low-Level Input Voltage
Input Leakage Current
Input Capacitance
Symbol
Min
Typ
Max
Units
VIH
VIL
Iin
60%
-
8
30%
±10
-
V
V
A
pF
(% of VA)
(% of VA)
(Note 7)
7. Iin for LRCK is ±20 A max.
POWER AND THERMAL CHARACTERISTICS
5 V Nom
Parameters
3.3 V Nom
Symbol
Min
Typ
Max
Min
Typ
Max
Units
IA
IA
-
22
220
110
1.1
95
50
40
30
150
-
-
16
100
53
0.33
95
50
40
21
69
-
mA
A
mW
mW
°C/Watt
dB
dB
Power Supplies
Power Supply Current
(Note 8)
Power Dissipation
normal operation
power-down state (Note 9)
normal operation
power-down state(Note 9)
Package Thermal Resistance
Power Supply Rejection Ratio (Note 8)
(1 kHz)
(60 Hz)
JA
PSRR
8. Current consumption increases with increasing FS and increasing MCLK. Typ and Max values are
based on highest FS and highest MCLK. Variance between speed modes is small.
9. Power down mode is defined when all clock and data lines are held static.
10. Valid with the recommended capacitor values on VQ and FILT+ as shown in the typical connection diagram in Section 3.
3.3 µF
V
o ut
AO U Tx
R
C
L
L
AG N D
Figure 1. Output Test Load
Capacitive Load -- C L (pF)
125
100
75
Safe Operating
Region
50
25
2.5
3
5
10
15
Resistive Load -- RL (k )
Figure 2. Maximum Loading
8
20
CS4344/5/8
SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE
Parameters
Symbol
MCLK Frequency
MCLK Duty Cycle
Input Sample Rate
(Note 11)
All MCLK/LRCK ratios combined
256x, 384x, 1024x
256x, 384x
512x, 768x
1152x
128x, 192x
64x, 96x
128x, 192x
Fs
Min
Typ
Max
Units
0.512
-
50
MHz
45
-
55
%
200
50
134
67
34
100
200
200
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
2
2
84
42
30
50
100
168
External SCLK Mode
LRCK Duty Cycle (External SCLK only)
45
50
55
%
SCLK Pulse Width Low
tsclkl
20
-
-
ns
SCLK Pulse Width High
tsclkh
20
-
-
ns
45
50
55
%
SCLK rising to LRCK edge delay
tslrd
20
-
-
ns
SCLK rising to LRCK edge setup time
tslrs
20
-
-
ns
SDIN valid to SCLK rising setup time
tsdlrs
20
-
-
ns
SCLK rising to SDIN hold time
tsdh
20
-
-
ns
-
50
-
%
tsclkw
10 9
---------------SCLK
-
-
ns
SCLK rising to LRCK edge
tsclkr
-
tsclkw
-----------------2
-
ns
SDIN valid to SCLK rising setup time
tsdlrs
10 9
---------------------- + 10
 512 Fs
-
-
ns
SCLK rising to SDIN hold time
MCLK / LRCK =1152, 1024, 512, 256, 128, or 64
tsdh
10 9
---------------------- + 15
 512 Fs
-
-
ns
SCLK rising to SDIN hold time
MCLK / LRCK = 768, 384, 192, or 96
tsdh
10 9
---------------------- + 15
 384 Fs
-
-
ns
SCLK Duty Cycle
Internal SCLK Mode
LRCK Duty Cycle (Internal SCLK only)
(Note 12)
SCLK Period
(Note 13)
11. Not all sample rates are supported for all clock ratios. See Table 1, “Common Clock Frequencies,” on
page 12 for supported ratio’s and frequencies.
12. In Internal SCLK Mode, the Duty Cycle must be 50% 1/2 MCLK Period.
13. The SCLK / LRCK ratio may be either 32, 48, 64, or 72. This ratio depends on part type and MCLK/LRCK ratio. (See Figures 7-9)
9
CS4344/5/8
LRCK
t sclkh
t slrs
t slrd
t sclkl
SCLK
t sdh
t sdlrs
SDATA
Figure 3. External Serial Mode Input Timing
LRCK
t sclkr
SDATA
t sclkw
t sdlrs
t sdh
*INTERNAL SCLK
The SCLK pulses shown are internal to the CS4344/5/8.
Figure 4. Internal Serial Mode Input Timing
LRCK
MCLK
1
N
2
N
*INTERNAL SCLK
SDATA
* The SCLK pulses shown are internal to the CS4344/5/8.
N equals MCLK divided by SCLK
Figure 5. Internal Serial Clock Generation
10
CS4344/5/8
3. TYPICAL CONNECTION DIAGRAM
Note* = This circuitry is intended for applications where the
CS4344/5/8 connects directly to an unbalanced output of
the design. For internal routing applications please see the
DAC analog output characteristics for loading limitations.
+3.3 V to +5 V
+
9
0.1 µF
1 µF
VA
Note*
1
Audio
Data
Processor
2
3
SDIN
3.3 µF
DEM/SCLK
AOUTL
Left Audio
Output
470
7
+
LRCK
C
10 k
CS4344
CS4345 AOUTR 10
CS4348
3.3 µF
Right Audio
Output
470
+
C
10 k
FILT+
MCLK
8
C=
10 µF
Rext + 470
4Fs(Rext
For best 20 kHz response
470)
5
0.1 µF
+
AGND
VQ
Rext
6
+
External Clock
4
Rext
*3.3 µF
or
*10 µF
*Popguard ramp can be adjusted by
selecting this capacitor value to be
3.3 µF to give 250 ms ramp time
or 10 µF to give a 420 ms ramp
time.
Figure 6. Typical Connection Diagram
11
CS4344/5/8
4. APPLICATIONS
The CS4344 family accepts data at standard audio sample rates including 48, 44.1 and 32 kHz in SSM, 96, 88.2
and 64 kHz in DSM, and 192, 176.4 and 128 kHz in QSM. Audio data is input via the serial data input pin (SDIN).
The Left/Right Clock (LRCK) determines which channel is currently being input on SDIN, and the optional Serial
Clock (SCLK) clocks audio data into the input data buffer. The CS4344/5/8 differ in serial data formats as shown in
Figures 7–9.
4.1
Master Clock
MCLK/LRCK must be an integer ratio, as shown in Table 1. The LRCK frequency is equal to Fs, the frequency at which words for each channel are input to the device. The MCLK-to-LRCK frequency ratio and
speed mode is detected automatically during the initialization sequence by counting the number of MCLK
transitions during a single LRCK period and by detecting the absolute speed of MCLK. Internal dividers are
set to generate the proper clocks. Table 1 illustrates several standard audio sample rates and the required
MCLK and LRCK frequencies. Please note there is no required phase relationship, but MCLK, LRCK and
SCLK must be synchronous.
LRCK
64x
96x
128x
(kHz)
32
44.1
48
8.1920
64
11.2896
88.2
12.2880
96
8.1920 12.2880
128
176.4 11.2896 16.9344 22.5792
12.2880 18.4320 24.5760
192
Mode
QSM
192x
12.2880
16.9344
18.4320
33.8680
36.8640
MCLK (MHz)
256x
384x
8.1920 12.2880
11.2896 16.9344
12.2880 18.4320
22.5792 33.8680
24.5760 36.8640
32.7680 49.1520
DSM
512x
22.5792
24.5760
32.7680
-
768x
1024x
32.7680
33.8680 45.1580
36.8640 49.1520
49.1520
SSM
1152x
36.8640
-
Table 1. Common Clock Frequencies
4.2
Serial Clock
The serial clock controls the shifting of data into the input data buffers. The CS4344 family supports both
external and internal serial clock generation modes. Refer to Figures 7–9 for data formats.
4.2.1
External Serial Clock Mode
The CS4344 family will enter the External Serial Clock Mode when 16 low to high transitions are detected
on the DEM/SCLK pin during any phase of the LRCK period. When this mode is enabled, the Internal Serial Clock Mode and deemphasis filter cannot be accessed. The CS4344 family will switch to Internal Serial Clock Mode if no low to high transitions are detected on the DEM/SCLK pin for 2 consecutive frames
of LRCK. Refer to Figure 11.
4.2.2
Internal Serial Clock Mode
In the Internal Serial Clock Mode, the serial clock is internally derived and synchronous with MCLK and
LRCK. The SCLK/LRCK frequency ratio is either 32, 48, 64, or 72 depending upon data format. Operation
in this mode is identical to operation with an external serial clock synchronized with LRCK. This mode allows access to the digital deemphasis function. Refer to Figures 7–11 for details.
12
CS4344/5/8
Left Channel
LRCK
Right Channel
SCLK
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
Internal SCLK Mode
+5 +4 +3 +2 +1 LSB
External SCLK Mode
I²S, 16-Bit data and INT SCLK = 32 Fs if
MCLK/LRCK = 1024, 512, 256, 128, or 64
I²S, Up to 24-Bit data and INT SCLK = 48 Fs if
MCLK/LRCK = 768, 384, 192, or 96
I²S, Up to 24-Bit data and INT SCLK = 72 Fs if
MCLK/LRCK = 1152
I²S, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
Figure 7. CS4344 Data Format (I2S)
Left Channel
LRCK
Right Channel
SCLK
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
Internal SCLK Mode
Left-Justified, up to 24-Bit Data
INT SCLK = 64 Fs if
MCLK/LRCK = 1024, 512, 256, 128, or 64
INT SCLK = 48 Fs if
MCLK/LRCK = 768, 384, 192, or 96
INT SCLK = 72 Fs if
MCLK/LRCK = 1152
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
External SCLK Mode
Left-Justified, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
Figure 8. CS4345 Data Format (Left Justified)
13
CS4344/5/8
LRCK
Right Channel
Left Channel
SCLK
SDATA
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Internal32SCLK
clocks Mode
Right Justified, 16-Bit Data
INT SCLK = 32 Fs if
MCLK/LRCK = 1024, 512, 256, 128, or 64
INT SCLK = 48 Fs if
MCLK/LRCK = 768, 384, 192, or 96
INT SCLK = 72 Fs if
MCLK/LRCK = 1152
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
External SCLK Mode
Right Justified, 16-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 32 Cycles per LRCK Period
Figure 9. CS4348 Data Format (Right Justified 16)
14
CS4344/5/8
4.3
De-Emphasis
The CS4344 family includes on-chip digital deemphasis. Figure 10 shows the deemphasis curve for Fs
equal to 44.1 kHz. The frequency response of the deemphasis curve will scale proportionally with changes
in sample rate, Fs.
The deemphasis filter is active (inactive) if the DEM/SCLK pin is low (high) for 5 consecutive falling edges
of LRCK. This function is available only in the internal serial clock mode
.
Gain
dB
T1=50 µs
0dB
T2 = 15 µs
-10dB
F1
3.183 kHz
F2
Frequency
10.61 kHz
Figure 10. De-Emphasis Curve (Fs = 44.1kHz)
4.4
Initialization and Power-Down
The Initialization and Power-down sequence flow chart is shown in Figure 11. The CS4344 family enters the
Power-Down State upon initial power-up. The interpolation filters and delta-sigma modulators are reset, and the
internal voltage reference, multi-bit digital-to-analog converters and switched-capacitor low-pass filters are powered down. The device will remain in the Power-down mode until MCLK and LRCK are present. Once MCLK and
LRCK are detected, MCLK occurrences are counted over one LRCK period to determine the MCLK/LRCK frequency ratio. Power is then applied to the internal voltage reference. Finally, power is applied to the D/A converters
and switched-capacitor filters, and the analog outputs will ramp to the quiescent voltage, VQ.
4.5
Output Transient Control
The CS4344 family uses Popguard ® technology to minimize the effects of output transients during powerup and power-down. This technique eliminates the audio transients commonly produced by single-ended
single-supply converters when it is implemented with external DC-blocking capacitors connected in series
with the audio outputs. To make best use of this feature, it is necessary to understand its operation.
4.5.1
Power-Up
When the device is initially powered-up, the audio outputs, AOUTL and AOUTR, are clamped to VQ which
is initially low. After MCLK is applied, the outputs begin to ramp with VQ towards the nominal quiescent
voltage. This ramp takes approximately 250 ms with a 3.3 µF cap connected to VQ (420 ms with a 10 µF
connected to VQ) to complete. The gradual voltage ramping allows time for the external DC-blocking capacitors to charge to VQ, effectively blocking the quiescent DC voltage. Once valid LRCK and SDIN are
supplied (and SCLK if used) approximately 2000 sample periods later audio output begins.
4.5.2
Power-Down
To prevent audio transients at power-down, the DC-blocking capacitors must fully discharge before turning off the power. To accomplish this, MCLK should be stopped for a period of about 250 ms for a 3.3 µF
cap connected to VQ (420 ms for a 10 µF cap connected to VQ) before removing power. During this time
voltage on VQ and the audio outputs discharge gradually to GND. If power is removed before this time
period has passed a transient will occur when the VA supply drops below that of VQ. There is no minimum
time for a power cycle; power may be re-applied at any time.
15
CS4344/5/8
When changing clock ratio or sample rate, it is recommended that zero data (or near zero data) be present on
SDIN for at least 10 LRCK samples before the change is made. During the clocking change, the DAC outputs will
always be in a zero data state. If no zero audio is present at the time of switching, a slight click or pop may be
heard as the DAC output automatically goes to its zero data state.
USER: Apply Power
VQ and outputs
ram p down
Power-Down State
VQ and outputs
ram p down
VQ and outputs low
USER: Apply MCLK
USER: Rem ove
MCLK
USER: Rem ove
MCLK
VQ and outputs ram p up
USER: Rem ove
LRCK
USER: Rem ove
LRCK
W ait State
USER: Apply LRCK
USER: change
MCLK/LRCK ratio
MCLK/LRCK Ratio Detection
USER: change
MCLK/LRCK ratio
USER: No SCLK
USER: Applied SCLK
SCLK m ode = internal
SCLK m ode = external
Norm al Operation
De-em phasis
available
Norm al Operation
De-em phasis
not available
Analog Output
is Generated
Analog Output
is Generated
Figure 11. CS4344/5/8 Initialization and Power-down Sequence
16
CS4344/5/8
4.6
Grounding and Power Supply Decoupling
As with any high resolution converter, the CS4344 family requires careful attention to power supply and
grounding arrangements to optimize performance. Figure 6 shows the recommended power arrangement
with VA connected to a clean +3.3 V or +5 V supply. For best performance, decoupling and filter capacitors
should be located as close to the device package as possible with the smallest capacitors closest.
4.7
Analog Output and Filtering
The analog filter present in the CS4344 family is a switched-capacitor filter followed by a continuous time
low pass filter. Its response, combined with that of the digital interpolator, is given in Figures 12 - 19. The
recommended external analog circuitry is shown in the “Typical Connection Diagram” on page 11.
17
CS4344/5/8
5. FILTER PLOTS
Figure 12. Single-Speed Stopband Rejection
Figure 13. Single-Speed Transition Band
0
-1
0.05
-2
0
-3
-0.05
Amplitude dB
Amplitude dB
-4
-5
-6
-0. 1
-0.15
-7
-0. 2
-8
-0.25
-9
-10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
Frequency (normalized to Fs)
0.52
0.53
0.54
Figure 14. Single-Speed Transition Band
18
0.5 5
0
0.05
0.1
0.15
0.2
0.25
0.3
Frequency (normalized to Fs)
0.35
0.4
0.45
Figure 15. Single-Speed Passband Ripple
0.5
CS4344/5/8
Figure 16. Double-Speed Stopband Rejection
Figure 17. Double-Speed Transition Band
1
0.8
0
0.7
-1
0.6
-2
0.5
Amplitude dB
Amplitude dB
-3
-4
-5
0.4
0.3
0.2
-6
0.1
-7
-8
0
-9
-0. 1
- 10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
Frequency (normalized to Fs)
0.52
0.53
0.54
Figure 18. Double-Speed Transition Band
0.55
-0. 2
0
0.05
0.1
0.15
0.2
0.25
0.3
Frequency (normalized to Fs)
0.35
0.4
0.45
0.5
Figure 19. Double-Speed Passband Ripple
19
CS4344/5/8
0
0
-10
-10
-20
-30
-20
Amplitude (dB)
Amplitude (dB)
-40
-50
-60
-30
-40
-70
-50
-80
-60
-90
-100
0
0.1
0.2
0.3
0.4
0.5
0.6
Frequency(normalized to Fs)
0.7
0.8
0.9
1
0.35
0.4
Figure 20. Quad-Speed Stopband Rejection
0.45
0.5
0.55
0.6
Frequency(normalized to Fs)
0.65
0.7
0.75
Figure 21. Quad-Speed Transition Band
0
0
-5
-10
-0. 5
-20
Amplitude dB
Amplitude (dB)
-15
-25
-30
-1
-35
-40
-45
-50
-1. 5
0.4
0.45
0.5
0.55
0.6
Frequency(normalized to Fs)
0.65
Figure 22. Quad-Speed Transition Band
20
0.7
0
0.05
0.1
0.15
0.2
0.25
0.3
Frequency (normalized to Fs)
0.35
0.4
0.45
Figure 23. Quad-Speed Passband Ripple
0.5
CS4344/5/8
6. PARAMETER DEFINITIONS
Dynamic Range
The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth
made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and
do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
Gain Error
The deviation from the nominal full scale analog output for a full scale digital input.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in
decibels.
Total Harmonic Distortion + Noise (THD+N)
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.
21
CS4344/5/8
7. PACKAGE DIMENSIONS
10LD TSSOP (3 mm BODY) PACKAGE DRAWING
N
D
E11
c
E
A2
A

e
b
SIDE VIEW
1 2 3
A1
L
SEATING
PLANE
END VIEW
L1
TOP VIEW
DIM
A
A1
A2
b
c
D
E
E1
e
L
L1

MIN
-0
0.0295
0.0059
0.0031
----0.0157
-0°
INCHES
NOM
-----0.1181 BSC
0.1929 BSC
0.1181 BSC
0.0197 BSC
0.0236
0.0374 REF
--
MAX
0.0433
0.0059
0.0374
0.0118
0.0091
----0.0315
-8°
MIN
-0
0.75
0.15
0.08
----0.40
-0°
MILLIMETERS
NOM
-----3.00 BSC
4.90 BSC
3.00 BSC
0.50 BSC
0.60
0.95 REF
--
Controlling Dimension is Millimeters
Notes:
1. Reference document: JEDEC MO-187
2. D does not include mold flash or protrusions which is 0.15 mm max. per side.
3. E1 does not include inter-lead flash or protrusions which is 0.15 mm max per side.
4. Dimension b does not include a total allowable dambar protrusion of 0.08 mm max.
5. Exceptions to JEDEC dimension.
22
NOTE
MAX
1.10
0.15
0.95
0.30
0.23
----0.80
-8°
4, 5
2
3
CS4344/5/8
8. ORDERING INFORMATION
Product
CS4344
CS4345
Description
24-Bit, 192 kHz
Stereo D/A
Converter
Package Pb-Free
10-TSSOP
Yes
CS4348
8.1
Grade
Temp Range
Commercial
Automotive
Commercial
Automotive
Commercial
-10 to +70 °C
-40 to +85 °C
-10 to +70 °C
-40 to +85 °C
-10 to +70 °C
Container
Order #
Tube
or
Tape and Reel
CS4344-CZZ
CS4344-DZZ
CS4345-CZZ
CS4345-DZZ
CS4348-CZZ
Functional Compatibility
CS4334-KS  CS4344-CZZ
CS4335-KS  CS4345-CZZ
CS4338-KS  CS4348-CZZ
CS4334-BS  CS4344-DZZ
CS4334-DS  CS4344-DZZ
8.2
Selection Guide
The CS4344 family differs by Serial Audio format as follows:
•
CS4344 — 16- to 24-bit, I²S
•
CS4345 — 16- to 24-bit, Left-Justified
•
CS4348 — 16-bit, Right-Justified
23
CS4344/5/8
9. REVISION HISTORY
Release
F1
F2
Changes
-Updated passband and frequency response specifications in “Combined Interpolation & On-chip Analog Filter
Response” on page 7
-Updated PSRR specification
-Updated VIH specification
-Updated figures in “Filter Plots” on page 18
-Removed references to CS4346 throughout.
-Updated Footnote 1 about dither in “DAC Analog Characteristics” on page 6.
-Updated the “SCLK rising to LRCK edge” unit froms to ns in “Switching Characteristics - Serial Audio Interface”
on page 9.
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com/corporate/contacts/sales.cfm
IMPORTANT NOTICE
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to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
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copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD
TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED
IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER
AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH
THESE USES.
Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be
trademarks or service marks of their respective owners.
24