CIRRUS CS4362A-EQZ

CS4362A
114 dB, 192 kHz 6-channel D/A Converter
Features
Description
 Advanced Multi-bit Delta Sigma Architecture
The CS4362A is a complete 6-channel digital-to-analog
system. This D/A system includes digital de-emphasis,
one-dB step size volume control, ATAPI channel mixing, selectable fast and slow digital interpolation filters
followed by an oversampled, multi-bit delta sigma modulator which includes mismatch shaping technology that
eliminates distortion due to capacitor mismatch. Following this stage is a multi-element switched capacitor
stage and low-pass filter with differential analog
outputs.
 24-bit Conversion
 Up to 192 kHz Sample Rates
 114 dB Dynamic Range
 -100 dB THD+N
 Direct Stream Digital Mode
–
–
On-chip 50 kHz filter
Matched PCM and DSD analog output
levels
The CS4362A also has a proprietary DSD processor
which allows for 50 kHz on-chip filtering without an intermediate decimation stage.
 Selectable Digital Filters
 Volume Control with 1-dB Step Size and Soft
Ramp
 Low Clock Jitter Sensitivity
 +5 V Analog Supply, +2.5 V Digital Supply
 Separate 1.8 to 5 V Logic Supplies for the
Control & Serial Ports
The CS4362A accepts PCM data at sample rates from
4 kHz to 216 kHz, DSD audio data, and delivers excellent sound quality. These features are ideal for multichannel audio systems including SACD players, A/V receivers, digital TV’s, mixing consoles, effects
processors, sound cards and automotive audio
systems.
ORDERING INFORMATION
See page 41.
Hardware Mode or
I2C/SPI Software Mode
Control Data
Reset
Level Translator
Control Port Supply = 1.8 V to 5 V
Digital Supply = 2.5 V
Analog Supply = 5 V
Internal Voltage
Reference
Register/Hardware
Configuration
Serial Audio Port
Supply = 1.8 V to 5 V
http://www.cirrus.com
Serial Interface
DSD Audio
Input
6
Level Translator
PCM Serial
Audio Input
Volume
Controls
Digital
Filters
Multi-bit ∆Σ
Modulators
Switch-Cap
DAC and
Analog Filters
DSD Processor
-50 kHz filter
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
External Mute
Control
6
6
6
Six Channels of
Differential
Outputs
Mute Signals
APR '05
DS617PP1
CS4362A
TABLE OF CONTENTS
1. PIN DESCRIPTION..................................................................................................................... 6
2. CHARACTERISTICS AND SPECIFICATIONS.......................................................................... 8
3. APPLICATIONS ....................................................................................................................... 20
3.1 Master Clock..................................................................................................................... 20
3.2 Mode Select...................................................................................................................... 20
3.3 Digital Interface Formats .................................................................................................. 22
3.4 Oversampling Modes........................................................................................................ 23
3.5 Interpolation Filter ............................................................................................................. 23
3.6 De-Emphasis .................................................................................................................... 23
3.7 ATAPI Specification .......................................................................................................... 24
3.8 Direct Stream Digital (DSD) Mode.................................................................................... 25
3.9 Grounding and Power Supply Arrangements ................................................................... 25
3.9.1 Capacitor Placement............................................................................................ 25
3.10 Analog Output and Filtering ............................................................................................ 25
3.11 Mute Control ................................................................................................................... 26
3.12 Recommended Power-Up Sequence ............................................................................. 27
3.12.1 Hardware Mode ................................................................................................. 27
3.12.2 Software Mode................................................................................................... 27
3.13 Recommended Procedure for Switching Operational Modes......................................... 27
3.14 Control Port Interface ..................................................................................................... 28
3.14.1 MAP Auto Increment.......................................................................................... 28
3.14.2 I2C Mode............................................................................................................ 28
3.14.2.1 I2C Write ............................................................................................ 28
3.14.2.2 I2C Read ............................................................................................ 29
3.14.3 SPI™ Mode........................................................................................................ 30
3.14.3.1 SPI Write............................................................................................ 30
3.15 Memory Address Pointer (MAP)
............................................................................... 30
4. REGISTER QUICK REFERENCE ............................................................................................ 31
5. REGISTER DESCRIPTION ...................................................................................................... 32
5.1 Mode Control 1 (address 01h) .......................................................................................... 32
5.1.1 Control Port Enable (CPEN) ................................................................................ 32
5.1.2 Freeze Controls (Freeze)..................................................................................... 32
5.1.3 Master Clock DIVIDE ENABLE (mclkdiv) ............................................................ 32
5.1.4 DAC Pair Disable (DACx_DIS) ............................................................................ 32
5.1.5 Power Down (PDN).............................................................................................. 33
5.2 Mode Control 2 (address 02h) ......................................................................................... 33
5.2.1 Digital Interface Format (dif) ................................................................................ 33
5.2.2 Mode Control 3 (address 03h) ............................................................................ 34
5.2.3 Soft Ramp AND Zero Cross CONTROL (SZC) ................................................... 34
5.2.4 Single Volume Control (Snglvol) .......................................................................... 34
5.2.5 Soft Volume Ramp-Up after Error (RMP_UP) ..................................................... 35
5.2.6 MUTEC Polarity (MUTEC+/-)............................................................................... 35
5.2.7 Auto-Mute (AMUTE) ........................................................................................... 35
5.2.8 Mute Pin Control (MUTEC1, MUTEC0) ............................................................... 35
5.3 Filter Control (address 04h) ............................................................................................. 36
5.3.1 Interpolation Filter Select (FILT_SEL).................................................................. 36
5.3.2 De-Emphasis Control (DEM) ............................................................................... 36
5.3.3 Soft Ramp-Down before Filter Mode Change (RMP_DN) ................................... 36
5.4 Invert Control (address 05h) ............................................................................................ 37
5.4.1 Invert Signal Polarity (Inv_Xx).............................................................................. 37
5.5 Mixing Control Pair 1 (Channels A1 & B1)(address 06h)
Mixing Control Pair 2 (Channels A2 & B2)(address 09h)
2
DS617PP1
CS4362A
Mixing Control Pair 3 (Channels A3 & B3)(address 0Ch) ............................................. 37
5.5.1 Channel A Volume = Channel B Volume (A=B)................................................... 37
5.5.2 ATAPI Channel Mixing and Muting (ATAPI) ........................................................ 37
5.5.3 Functional Mode (FM).......................................................................................... 38
5.6 Volume Control (addresses 07h, 08h, 0Ah, 0Bh, 0Dh, 0Eh) .......................................... 39
5.6.1 Mute (MUTE) ....................................................................................................... 39
5.6.2 Volume Control (xx_VOL) .................................................................................... 39
5.7 Chip Revision (address 12h) ........................................................................................... 40
5.7.1 Part Number ID (part) [Read Only] ...................................................................... 40
6. PARAMETER DEFINITIONS.................................................................................................... 41
7. REFERENCES.......................................................................................................................... 41
8. ORDERING INFORMATION .................................................................................................... 41
9. PACKAGE DIMENSIONS ........................................................................................................ 42
10. APPENDIX ............................................................................................................................. 43
DS617PP1
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CS4362A
LIST OF FIGURES
Figure 1. Serial Audio Interface Timing.....................................................................................................
Figure 2. Direct Stream Digital - Serial Audio Input Timing.......................................................................
Figure 3. Control Port Timing - I2C Format ...............................................................................................
Figure 4. Control Port Timing - SPI Format...............................................................................................
Figure 5. Typical Connection Diagram, Software Mode............................................................................
Figure 6. Typical Connection Diagram, Hardware Mode ..........................................................................
Figure 7. Format 0 - Left-Justified up to 24-bit Data .................................................................................
Figure 8. Format 1 - I2S up to 24-bit Data.................................................................................................
Figure 9. Format 2 - Right-Justified 16-bit Data ........................................................................................
Figure 10. Format 3 - Right-Justified 24-bit Data ......................................................................................
Figure 11. Format 4 - Right-Justified 20-bit Data ......................................................................................
Figure 12. Format 5 - Right-Justified 18-bit Data ......................................................................................
Figure 13. De-Emphasis Curve.................................................................................................................
Figure 14. ATAPI Block Diagram (x = channel pair 1, 2, or 3) ..................................................................
Figure 15. Full-Scale Output .....................................................................................................................
Figure 16. Recommended Output Filter....................................................................................................
Figure 17. Control Port Timing, I2C Mode.................................................................................................
Figure 18. Control Port Timing, SPI mode ................................................................................................
Figure 19. Single-Speed (fast) Stopband Rejection..................................................................................
Figure 20. Single-Speed (fast) Transition Band ........................................................................................
Figure 21. Single-Speed (fast) Transition Band (detail) ............................................................................
Figure 22. Single-Speed (fast) Passband Ripple ......................................................................................
Figure 23. Single-Speed (slow) Stopband Rejection ................................................................................
Figure 24. Single-Speed (slow) Transition Band.......................................................................................
Figure 25. Single-Speed (slow) Transition Band (detail)...........................................................................
Figure 26. Single-Speed (slow) Passband Ripple.....................................................................................
Figure 27. Double-Speed (fast) Stopband Rejection ................................................................................
Figure 28. Double-Speed (fast) Transition Band.......................................................................................
Figure 29. Double-Speed (fast) Transition Band (detail)...........................................................................
Figure 30. Double-Speed (fast) Passband Ripple.....................................................................................
Figure 31. Double-Speed (slow) Stopband Rejection ...............................................................................
Figure 32. Double-Speed (slow) Transition Band .....................................................................................
Figure 33. Double-Speed (slow) Transition Band (detail) .........................................................................
Figure 34. Double-Speed (slow) Passband Ripple ...................................................................................
Figure 35. Quad-Speed (fast) Stopband Rejection ...................................................................................
Figure 36. Quad-Speed (fast) Transition Band .........................................................................................
Figure 37. Quad-Speed (fast) Transition Band (detail) .............................................................................
Figure 38. Quad-Speed (fast) Passband Ripple .......................................................................................
Figure 39. Quad-Speed (slow) Stopband Rejection..................................................................................
Figure 40. Quad-Speed (slow) Transition Band........................................................................................
Figure 41. Quad-Speed (slow) Transition Band (detail)............................................................................
Figure 42. Quad-Speed (slow) Passband Ripple......................................................................................
4
14
15
16
17
18
19
22
22
22
22
23
23
24
24
26
26
29
30
43
43
43
43
43
43
44
44
44
44
44
44
45
45
45
45
45
45
46
46
46
46
46
46
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CS4362A
LIST OF TABLES
Table 1. Common Clock Frequencies........................................................................................... 20
Table 2. Digital Interface Format, Stand-Alone Mode Options...................................................... 21
Table 3. Mode Selection, Stand-Alone Mode Options .................................................................. 21
Table 4. Direct Stream Digital (DSD), Stand-Alone Mode Options ............................................... 21
Table 5. Digital Interface Formats - PCM Mode............................................................................ 33
Table 6. Digital Interface Formats - DSD Mode ............................................................................ 33
Table 7. ATAPI Decode ................................................................................................................ 38
Table 8. Example Digital Volume Settings .................................................................................... 39
Table 9. Revision History ............................................................................................................. 47
DS617PP1
5
CS4362A
AOUTB1+
AOUTB1-
AOUTA1+
AOUTA1-
MUTEC1
VLS
M3(DSD_SCLK)
TST
TST
DSDB3
DSDA3
DSDB2
1. PIN DESCRIPTION
48 47 46 45 44 43 42 41 40 39 38 37
DSDA2
1
36
DSDB1
2
35
AOUTA2+
DSDA1
3
34
33
AOUTB2+
AOUTB2-
32
VA
GND
VD
4
GND
5
MCLK
6
LRCK(DSD_EN)
7
SDIN1
8
29
SCLK
31
CS4362A
30
AOUTA2-
AOUTA3AOUTA3+
9
28
AOUTB3+
TST
10
27
AOUTB3-
SDIN2
TST
11
26
MUTEC2
12
25
MUTEC3
Pin Name
VD
GND
MUTEC4
MUTEC5
MUTEC6
VQ
FILT+
RST
VLC
M0(AD0/CS)
M1(SDA/CDIN)
M2(SCL/CCLK)
TST
SDIN3
13 14 15 16 17 18 19 20 21 22 23 24
#
Pin Description
4
Digital Power (Input) - Positive power supply for the digital section. Refer to the Recommended Operating Conditions for appropriate voltages.
5,31 Ground (Input) - Ground reference. Should be connected to analog ground.
MCLK
6
Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
Table 5 illustrates several standard audio sample rates and the required master clock
frequencies.
LRCK
7
Left Right Clock (Input) - Determines which channel, Left or Right, is currently active
on the serial audio data line. The frequency of the left/right clock must be at the audio
sample rate, Fs.
SDIN1
SDIN2
SDIN3
8
11
13
Serial Data Input (Input) - Input for two’s complement serial audio data.
SCLK
9
Serial Clock (Input) - Serial clocks for the serial audio interface.
TST
10,12 Test - These pins need to be tied to analog ground.
14,44
45
RST
19
Reset (Input) - The device enters a low power mode and all internal registers are
reset to their default settings when low.
VA
32
Analog Power (Input) - Positive power supply for the analog section. Refer to the
Recommended Operating Conditions for appropriate voltages.
VLS
43
Serial Audio Interface Power (Input) - Determines the required signal level for the
serial audio interface. Refer to the Recommended Operating Conditions for appropriate voltages.
VLC
18
Control Port Power (Input) - Determines the required signal level for the control port
and hardware mode configuration pins. Refer to the Recommended Operating Conditions for appropriate voltages.
6
DS617PP1
CS4362A
#
Pin Description
VQ
Pin Name
21
Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. VQ
must be capacitively coupled to analog ground, as shown in the Typical Connection
Diagram. The nominal voltage level is specified in the Analog Characteristics and
Specifications section. VQ presents an appreciable source impedance and any current drawn from this pin will alter device performance. However, VQ can be used to
bias the analog circuitry assuming there is no AC signal component and the DC current is less then the maximum specified in the Analog Characteristics and Specifications section.
FILT+
20
Positive Voltage Reference (Output) - Positive reference voltage for the internal
sampling circuits. Requires the capacitive decoupling to analog ground as shown in
the Typical Connection Diagram.
AOUTA1 +,AOUTB1 +,AOUTA2 +,AOUTB2 +,AOUTA3 +,AOUTB3 +,MUTEC1
MUTEC2
MUTEC3
MUTEC4
MUTEC5
MUTEC6
39,40 Differential Analog Output (Output) - The full scale differential analog output level is
38,37 specified in the Analog Characteristics specification table.
35,36
34,33
29,30
28,27
41
26
25
24
23
22
Mute Control (Output) - The Mute Control pins go high during power-up initialization,
reset, muting, power-down or if the master clock to left/right clock frequency ratio is
incorrect. These pins are intended to be used as a control for external mute circuits on
the line outputs to prevent the clicks and pops that can occur in any single supply system. Use of Mute Control is not mandatory but recommended for designs requiring
the absolute minimum in extraneous clicks and pops.
Hardware Mode Definitions
M0M1
M2
M3
17
16
15
42
Mode Selection (Input) - Determines the operational mode of the device as detailed in Tables
6 and 7.
Software Mode Definitions
SCL/CCLK
15
Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an
external pull-up resistor to the logic interface voltage in I2C mode as shown in the
Typical Connection Diagram.
SDA/CDIN
16
Serial Control Port Data (Input/Output) - SDA is a data I/O line in I2C mode and is
open drain, requiring an external pull-up resistor to the logic interface voltage, as
shown in the Typical Connection Diagram; CDIN is the input data line for the control
port interface in SPI mode.
AD0/CS
17
Address Bit 0 (I2C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address
pin in I2C mode; CS is the chip select signal for SPI mode.
DSDA1
DSDB1
DSDA2
DSDB2
DSDA3
DSDB3
3
2
1
48
47
46
Direct Stream Digital Input (Input) - Input for Direct Stream Digital serial audio data.
DSD_SCLK
42
DSD Serial Clock (Input) - Serial clock for the Direct Stream Digital serial audio interface.
DSD_EN
7
DSD Definitions
DS617PP1
DSD Enable (Input) - When held at logic ‘1’ the device will enter DSD mode (Stand-Alone mode
only).
7
CS4362A
2. CHARACTERISTICS AND SPECIFICATIONS
All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical
performance characteristics and specifications are derived from measurements taken at nominal supply voltage
and TA = 25°C.
SPECIFIED OPERATING CONDITIONS
(GND = 0 V; all voltages with respect to ground.)
Parameters
DC Power Supply
Analog power
Digital internal power
Serial data port interface power
Control port interface power
Specified Temperature Range
-CQZ
-EQZ
Symbol
VA
VD
VLS
VLC
TA
Min
4.75
2.37
1.71
1.71
-10
-40
Typ
5.0
2.5
5.0
5.0
-
Max
5.25
2.63
5.25
5.25
+70
+105
Units
V
V
V
V
°C
°C
Absolute Maximum Ratings
(GND = 0 V; all voltages with respect to ground.)
Parameters
DC Power Supply
Analog power
Digital internal power
Serial data port interface power
Control port interface power
Input Current
Any Pin Except Supplies
Digital Input Voltage
Serial data port interface
Control port interface
Ambient Operating Temperature (power applied)
Storage Temperature
Symbol
VA
VD
VLS
VLC
Iin
VIND-S
VIND-C
Top
Tstg
Min
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-55
-65
Max
6.0
3.2
6.0
6.0
±10
VLS+ 0.4
VLC+ 0.4
125
150
Units
V
V
V
V
mA
V
V
°C
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation
is not guaranteed at these extremes.
8
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CS4362A
DAC ANALOG CHARACTERISTICS
Full-Scale Output Sine Wave, 997 Hz (Note 1); Fs = 48/96/192 kHz; Test load RL = 3 kΩ, CL = 100 pF; Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified.
Parameters
Symbol
Min
Typ
Max
Unit
-10
-
70
°C
108
105
-
114
111
97
94
-
dB
dB
dB
dB
-
-100
-91
-51
-94
-74
-34
-94
-45
-
dB
dB
dB
dB
dB
dB
-
114
-
dB
-40
-
105
°C
105
102
-
114
111
97
94
-
dB
dB
dB
dB
-
-100
-91
-51
-94
-74
-34
-91
-42
-
dB
dB
dB
dB
dB
dB
-
114
-
dB
CS4362A-CQZ Dynamic Performance - All PCM modes and DSD
Specified Temperature Range
Dynamic Range
TA
24-bit
A-weighted
unweighted
16-bit A-weighted
(Note 2) unweighted
THD+N
Total Harmonic Distortion + Noise
24-bit
(Note 2) 16-bit
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
Idle Channel Noise / Signal-to-noise ratio
CS4362A-EQZ Dynamic Performance - All PCM modes and DSD
Specified Temperature Range
Dynamic Range (Note 1)
TA
24-bit
A-weighted
unweighted
16-bit A-weighted
(Note 2) unweighted
Total Harmonic Distortion + Noise
24-bit
(Note 2) 16-bit
(Note 1) THD+N
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
Idle Channel Noise / Signal-to-noise ratio
Notes:
1. One-half LSB of triangular PDF dither is added to data.
2.
Performance limited by 16-bit quantization noise.
DS617PP1
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CS4362A
DAC ANALOG CHARACTERISTICS - ALL MODES (CONTINUED)
Parameters
Symbol
Min
-
Interchannel Isolation
(1 kHz)
DC Accuracy
Interchannel Gain Mismatch
Gain Drift
Analog Output
Full Scale DifferentialPCM, DSD processor VFS
132%•VA
Output Voltage
Direct DSD mode
94%•VA
Output Impedance
(Note 3) ZOUT
Max DC Current draw from an AOUT pin
IOUTmax
Min AC-Load Resistance
RL
Max Load Capacitance
CL
Quiescent Voltage
VQ
Max Current draw from VQ
IQMAX
-
Typ
110
Max
-
Units
dB
0.1
100
-
dB
ppm/°C
134%•VA
96%•VA
130
1.0
3
100
50% VA
10
136%•VA
98%•VA
-
Vpp
Vpp
Ω
mA
kΩ
pF
VDC
µA
POWER AND THERMAL CHARACTERISTICS
Parameters
Symbol
Min
Typ
Max
Units
normal operation, VA= 5 V
VD= 2.5 V
(Note 5) Interface current, VLC=5 V
VLS=5 V
(Note 6) power-down state (all supplies)
Power Dissipation (Note 4)
VA = 5 V, VD = 2.5 V
normal operation
(Note 6) power-down
Package Thermal Resistance
IA
ID
ILC
ILS
Ipd
-
56
20
2
84
200
61
26
-
mA
mA
µA
µA
µA
-
332
1
48
15
60
40
372
-
mW
mW
°C/Watt
°C/Watt
dB
dB
Power Supplies
Power Supply Current
(Note 4)
Power Supply Rejection Ratio (Note 7)
(1 kHz)
(60 Hz)
θJA
θJC
PSRR
Notes:
10
3.
VFS is tested under load RL and includes attenuation due to ZOUT
4.
Current consumption increases with increasing FS within a given speed mode and is signal dependant.
Max values are based on highest FS and highest MCLK.
5.
ILC measured with no external loading on the SDA pin.
6.
Power down mode is defined as RST pin = Low with all clock and data lines held static.
7.
Valid with the recommended capacitor values on FILT+ and VQ as shown in Figures 5 and 6.
DS617PP1
CS4362A
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs.
(See note 12.)
Fast Roll-Off
Parameter
Min
Typ
Combined Digital and On-chip Analog Filter Response - Single-Speed Mode - 48 kHz
Passband (Note 9)
to -0.01 dB corner
0
to -3 dB corner
0
Frequency Response
10 Hz to 20 kHz
-0.01
StopBand
0.547
StopBand Attenuation
(Note 10)
102
Group Delay
10.4/Fs
De-emphasis Error (Note 11)
Fs = 32 kHz
(Relative to 1 kHz)
Fs = 44.1 kHz
Fs = 48 kHz
Combined Digital and On-chip Analog Filter Response - Double-Speed Mode - 96 kHz
Passband (Note 9)
to -0.01 dB corner
0
to -3 dB corner
0
Frequency Response
10 Hz to 20 kHz
-0.01
StopBand
.583
StopBand Attenuation
(Note 10)
80
Group Delay
6.15/Fs
Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode - 192 kHz
Passband (Note 9)
to -0.01 dB corner
0
to -3 dB corner
0
Frequency Response
10 Hz to 20 kHz
-0.01
StopBand
.635
StopBand Attenuation
(Note 10)
90
Group Delay
7.1/Fs
Max
Unit
.454
.499
+0.01
±0.23
±0.14
±0.09
Fs
Fs
dB
Fs
dB
s
dB
dB
dB
.430
.499
+0.01
-
Fs
Fs
dB
Fs
dB
s
.105
.490
+0.01
-
Fs
Fs
dB
Fs
dB
s
Notes:
8.
Slow Roll-off interpolation filter is only available in software mode.
9. Response is clock dependent and will scale with Fs.
10. For Single-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs.
For Double-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs.
For Quad-Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs.
11. De-emphasis is available only in Single-Speed Mode; Only 44.1 kHz De-emphasis is available in hardware mode.
12. Amplitude vs. Frequency plots of this data are available starting on page 43.
DS617PP1
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CS4362A
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
(CONTINED)
Parameter
Single-Speed Mode - 48 kHz
Passband (Note 9)
Frequency Response
StopBand
StopBand Attenuation
Group Delay
De-emphasis Error (Note 11)
(Relative to 1 kHz)
Double-Speed Mode - 96 kHz
Passband (Note 9)
Frequency Response
StopBand
StopBand Attenuation
Group Delay
Quad-Speed Mode - 192 kHz
Passband (Note 9)
Frequency Response
StopBand
StopBand Attenuation
Group Delay
Slow Roll-Off (Note 8)
Min
Typ
Max
to -0.01 dB corner
to -3 dB corner
10 Hz to 20 kHz
(Note 10)
Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
to -0.01 dB corner
to -3 dB corner
10 Hz to 20 kHz
(Note 10)
to -0.01 dB corner
to -3 dB corner
10 Hz to 20 kHz
(Note 10)
Unit
0
0
-0.01
.583
64
-
7.8/Fs
-
0.417
0.499
+0.01
±0.36
±0.21
±0.14
Fs
Fs
dB
Fs
dB
s
dB
dB
dB
0
0
-0.01
.792
70
-
5.4/Fs
.296
.499
+0.01
-
Fs
Fs
dB
Fs
dB
s
0
0
-0.01
.868
75
-
6.6/Fs
.104
.481
+0.01
-
Fs
Fs
dB
Fs
dB
s
DSD COMBINED DIGITAL & ON-CHIP ANALOG FILTER RESPONSE
Parameter
DSD Processor mode
Passband (Note 9)
Frequency Response
Roll-off
12
to -3 dB corner
10 Hz to 20 kHz
Min
Typ
Max
Unit
0
-0.05
27
-
50
+0.05
-
kHz
dB
dB/Oct
DS617PP1
CS4362A
DIGITAL CHARACTERISTICS
Parameters
High-Level Output Voltage (IOH = -1.2 mA)
Serial I/O
Control I/O
Serial I/O
Control I/O
Control I/O
VIH
VIH
VIL
VIL
VOH
Min
70%
70%
80%
Low-Level Output Voltage (IOL = 1.2 mA)
Control I/O
VOL
-
-
20%
VLC
Imax
VOH
VOL
-
3
VA
0
-
mA
V
V
Input Leakage Current
Input Capacitance
High-Level Input Voltage
Low-Level Input Voltage
Maximum MUTEC Drive Current
MUTEC High-Level Output Voltage
MUTEC Low-Level Output Voltage
Symbol
(Note 13)
Iin
Typ
8
-
Max
±10
30%
30%
-
Units
µA
pF
VLS
VLC
VLS
VLC
VLC
13. Any pin except supplies. Transient currents of up to ±100 mA on the input pins will not cause SCR latchup
DS617PP1
13
CS4362A
SWITCHING CHARACTERISTICS - PCM
(Inputs: Logic 0 = GND, Logic 1 = VLS, CL = 30 pF)
Parameters
Symbol
Min
Max
Units
1
-
ms
1.024
55.2
MHz
45
55
%
4
50
100
54
108
216
kHz
kHz
kHz
LRCK Duty Cycle
45
55
%
SCLK Duty Cycle
45
55
%
RST pin Low Pulse Width
(Note 14)
MCLK Frequency
MCLK Duty Cycle
(Note 15)
Input Sample Rate - LRCK
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Fs
Fs
Fs
SCLK High Time
tsckh
8
-
ns
SCLK Low Time
tsckl
8
-
ns
LRCK Edge to SCLK Rising Edge
tlcks
5
-
ns
SDIN Setup Time Before SCLK Rising Edge
tds
3
-
ns
SDIN Hold Time After SCLK Rising Edge
tdh
5
-
ns
Notes:
14.
After powering up, RST should be held low until after the power supplies and clocks are settled.
15.
See Table 1 on page 20 for suggested MCLK frequencies.
LRCK
tlcks
tsckh
tsckl
SCLK
tds
SDINx
tdh
MSB
MSB-1
Figure 1. Serial Audio Interface Timing
14
DS617PP1
CS4362A
SWITCHING CHARACTERISTICS - DSD
(Logic 0 = AGND = DGND; Logic 1 = VLS; CL = 20 pF)
Parameter
MCLK Duty Cycle
DSD_SCLK Pulse Width Low
DSD_SCLK Pulse Width High
DSD_SCLK Frequency
Symbol
tsclkl
tsclkh
(64x Oversampled)
(128x Oversampled)
DSD_A / _B valid to DSD_SCLK rising setup time
DSD_SCLK rising to DSD_A or DSD_B hold time
tsdlrs
tsdh
Min
40
160
160
1.024
2.048
20
20
Typ
-
Max
60
3.2
6.4
-
Unit
%
ns
ns
MHz
MHz
ns
ns
t sclkh
t sclkl
DSD_SCLK
t sdlrs
t sdh
DSDxx
Figure 2. Direct Stream Digital - Serial Audio Input Timing
DS617PP1
15
CS4362A
SWITCHING CHARACTERISTICS - CONTROL PORT - I2C FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 30 pF)
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
fscl
-
100
kHz
RST Rising Edge to Start
tirs
500
-
ns
Bus Free Time Between Transmissions
tbuf
4.7
-
µs
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
-
µs
Clock Low time
tlow
4.7
-
µs
Clock High Time
thigh
4.0
-
µs
Setup Time for Repeated Start Condition
tsust
4.7
-
µs
SDA Hold Time from SCL Falling
(Note 16)
thdd
0
-
µs
SDA Setup time to SCL Rising
tsud
250
-
ns
Rise Time of SCL and SDA
trc, trc
-
1
µs
Fall Time SCL and SDA
tfc, tfc
-
300
ns
Setup Time for Stop Condition
tsusp
4.7
-
µs
Acknowledge Delay from SCL Falling
tack
300
1000
ns
Notes:
16.
Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
RST
t irs
Stop
Repeated
Start
Start
Stop
SDA
t buf
t
t high
t hdst
tf
hdst
t susp
SCL
t
low
t
hdd
t sud
t sust
tr
Figure 3. Control Port Timing - I2C Format
16
DS617PP1
CS4362A
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 30 pF)
Parameter
Symbol
Min
Max
Unit
CCLK Clock Frequency
fsclk
-
6
MHz
RST Rising Edge to CS Falling
tsrs
500
-
ns
CCLK Edge to CS Falling
(Note 17)
tspi
500
-
ns
CS High Time Between Transmissions
tcsh
1.0
-
µs
CS Falling to CCLK Edge
tcss
20
-
ns
CCLK Low Time
tscl
66
-
ns
CCLK High Time
tsch
66
-
ns
CDIN to CCLK Rising Setup Time
tdsu
40
-
ns
CCLK Rising to DATA Hold Time
(Note 18)
tdh
15
-
ns
Rise Time of CCLK and CDIN
(Note 19)
tr2
-
100
ns
Fall Time of CCLK and CDIN
(Note 19)
tf2
-
100
ns
Notes:
17. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
18. Data must be held for sufficient time to bridge the transition time of CCLK.
19. For FSCK < 1 MHz.
RST
t srs
CS
t spi t css
t scl
t sch
t csh
CCLK
t r2
t f2
CDIN
t dsu t
dh
Figure 4. Control Port Timing - SPI Format
DS617PP1
17
CS4362A
+2.5 V
+5 V
1 µF
+
+
0.1 µF
0.1 µF
4
VD
1 µF
32
VA
220 Ω
6
7
PCM
Digital
Audio
Source
9
8
11
13
MCLK
AOUTA1+
LRCK
AOUTA1-
SCLK
SDIN1
AOUTB1+
SDIN2
AOUTB1AOUTA2+
+1.8 V to +5 V
AOUTA2VLS
CS4362A
AOUTB2+
0.1 µF
AOUTB2470 Ω
3
2
1
DSD
Audio
Source
48
47
46
42
19
15
MicroController
16
DSDA1
AOUTA3+
DSDB1
AOUTA3-
37
Analog Conditioning
and Muting
35
36
34
33
29
30
Analog Conditioning
and Muting
Analog Conditioning
and Muting
Analog Conditioning
and Muting
DSDA2
DSDB2
AOUTB3+
DSDA3
AOUTB3-
28
27
Analog Conditioning
and Muting
DSDB3
DSD_SCLK
MUTEC1
41
MUTEC2 26
25
MUTEC3
24
MUTEC4
23
MUTEC5
MUTEC6 22
RST
SCL/CCLK
Mute
Drive
SDA/CDIN
ADO/CS
Note*
+1.8 V to +5 V
38
Analog Conditioning
and Muting
2 KΩ
2 KΩ
17
40
SDIN3
470 Ω
43
39
18
FILT+ 20
VLC
CMOUT
0.1 µF
Note*: Necessary for I 2C
control port operation
+
21
0.1 µ F + 1 µF
GND
5
GND
31
0.1 µ F
47 µF
TST
10, 12,
14, 44, 45
Figure 5. Typical Connection Diagram, Software Mode
18
DS617PP1
CS4362A
+2.5 V
+5 V
1 µF
+
0.1 µF
0.1 µF
4
VD
VLS
NoteDSD
6
7
PCM
Digital
Audio
Source
9
8
11
13
MCLK
AOUTA1+
LRCK
AOUTA1-
SCLK
MUTEC1
SDIN1
AOUTB1+
SDIN3
AOUTB143
+1.8 V to +5 V
MUTEC2
VLS
AOUTA2+
AOUTA23
2
1
DSD
Audio
Source
48
47
46
40
41
MUTEC3
DSDA1
38
37
26
36
25
34
AOUTB2+
DSDB2
AOUTB2- 33
24
MUTEC4
DSDA3
16
17
19
AOUTA3-
M3(DSD_SCLK)
M2
AOUTB3+
AOUTB3-
M1
29
30
MUTEC6
Analog Conditioning
and Muting
28
27
22
Analog Conditioning
and Muting
M0
RST
FILT+ 20
CMOUT
18
Analog Conditioning
and Muting
DSDB3
MUTEC5 23
42
Analog Conditioning
and Muting
DSDB1
AOUTA3+
15
Analog Conditioning
and Muting
35
DSDA2
NoteDSD
Optional
47 KΩ
Analog Conditioning
and Muting
CS4362A
0.1 µF
470 Ω
39
SDIN2
470 Ω
+1.8 V to +5 V
1 µF
32
VA
47 KΩ
220 Ω
Stand-Alone
Mode
Configuration
+
+
21
0.1 µ F + 1 µF
VLC
0.1 µ F
47 µF
0.1 µF
GND
5
GND
31
TST
10, 12,
14, 44, 45
NoteDSD: For DSD operation:
1) LRCK must be tied to VLS and
remain static high.
2) M3 PCM stand-alone configuration
pin becomes DSD_SCLK
Figure 6. Typical Connection Diagram, Hardware Mode
DS617PP1
19
CS4362A
3. APPLICATIONS
The CS4362A serially accepts twos complement formatted PCM data at standard audio sample rates including 48,
44.1 and 32 kHz in SSM, 96, 88.2 and 64 kHz in DSM, and 192, 176.4 and 128 kHz in QSM. Audio data is input via
the serial data input pins (SDINx). The Left/Right Clock (LRCK) determines which channel is currently being input
on SDINx, and the Serial Clock (SCLK) clocks audio data into the input data buffer.
The CS4362A can be configured in hardware mode by the M0, M1, M2 , M3 and DSD_EN pins and in software
mode through I2C or SPI.
3.1
Master Clock
MCLK/LRCK must be an integer ratio as shown in Table 1. The LRCK frequency is equal to Fs, the frequency at which words for each channel are input to the device. The MCLK-to-LRCK frequency ratio is detected
automatically during the initialization sequence by counting the number of MCLK transitions during a single
LRCK period. Internal dividers are then set to generate the proper internal clocks. Table 1 illustrates several
standard audio sample rates and the required MCLK and LRCK frequencies. Please note there is no required phase relationship, but MCLK, LRCK and SCLK must be synchronous.
Speed Mode
(sample-rate range)
MCLK Ratio
Single-Speed
(4 to 50 kHz)
MCLK Ratio
Double-Speed
(50 to 100 kHz)
Sample
Rate
(kHz)
32
44.1
48
64
88.2
96
MCLK Ratio
176.4
Quad-Speed
(100 to 200 kHz)
192
Software
mode only
MCLK (MHz)
256x
8.1920
11.2896
12.2880
128x
8.1920
11.2896
12.2880
64x
11.2896
12.2880
384x
12.2880
16.9344
18.4320
192x
12.2880
16.9344
18.4320
96x
16.9344
18.4320
512x
16.3840
22.5792
24.5760
256x
16.3840
22.5792
24.5760
128x
22.5792
24.5760
768x
24.5760
33.8688
36.8640
384x
24.5760
33.8688
36.8640
192x
33.8688
36.8640
1024x*
32.7680
45.1584
49.1520
512x*
32.7680
45.1584
49.1520
256x*
45.1584
49.1520
Note: These modes are only available in software mode by setting the MCLKDIV bit = 1.
Table 1. Common Clock Frequencies
3.2
Mode Select
In hardware mode operation is determined by the Mode Select pins. The state of these pins are continually
scanned for any changes. These pins require connection to supply or ground as outlined in figure 6. For
M0, M1, M2 supply is VLC and for M3 and DSD_EN supply is VLS. Tables 2 - 4 show the decode of these
pins.
In software mode the operational mode and data format are set in the FM and DIF registers.
Definitions” on page 41.
20
“Parameter
DS617PP1
CS4362A
M1
(DIF1)
0
0
M0
(DIF0)
0
1
1
1
0
1
DESCRIPTION
FORMAT
FIGURE
0
1
33
34
2
3
35
36
Left Justified, up to 24-bit data
I2S, up to 24-bit data
Right Justified, 16-bit Data
Right Justified, 24-bit Data
Table 2. Digital Interface Format, Stand-Alone Mode Options
M3
0
0
1
1
M2
(DEM)
0
1
0
1
DESCRIPTION
Single-Speed without De-Emphasis (4 to 50 kHz sample rates)
Single-Speed with 44.1 kHz De-Emphasis; see Figure 13
Double-Speed (50 to 100 kHz sample rates)
Quad-Speed (100 to 200 kHz sample rates)
Table 3. Mode Selection, Stand-Alone Mode Options
DSD_EN
(LRCK)
1
1
1
1
1
1
1
1
M2
M1
M0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DESCRIPTION
64x oversampled DSD data with a 4x MCLK to DSD data rate
64x oversampled DSD data with a 6x MCLK to DSD data rate
64x oversampled DSD data with a 8x MCLK to DSD data rate
64x oversampled DSD data with a 12x MCLK to DSD data rate
128x oversampled DSD data with a 2x MCLK to DSD data rate
128x oversampled DSD data with a 3x MCLK to DSD data rate
128x oversampled DSD data with a 4x MCLK to DSD data rate
128x oversampled DSD data with a 6x MCLK to DSD data rate
Table 4. Direct Stream Digital (DSD), Stand-Alone Mode Options
DS617PP1
21
CS4362A
3.3
Digital Interface Formats
The serial port operates as a slave and supports the I²S, Left-Justified, and Right-Justified digital interface
formats with varying bit depths from 16 to 24 as shown in Figures 7-12. Data is clocked into the DAC on the
rising edge.
Left Channel
LRCK
Right Channel
SCLK
SDINx
MSB
-1 -2 -3 -4 -5
+5 +4 +3 +2 +1
LSB
MSB
-1 -2 -3 -4
+5 +4 +3 +2 +1
LSB
Figure 7. Format 0 - Left-Justified up to 24-bit Data
Left Channel
LRCK
Right Channel
SCLK
SDINx
MSB
-1 -2 -3 -4 -5
+5 +4 +3 +2 +1
LSB
MSB
-1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Figure 8. Format 1 - I2S up to 24-bit Data
LRCK
Right Channel
Left Channel
SCLK
SDINx
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
Figure 9. Format 2 - Right-Justified 16-bit Data
LRCK
Right Channel
Left Channel
SCLK
SDINx
0
23 22 21 20 19 18
7 6 5 4 3 2 1 0
23 22 21 20 19 18
7 6 5 4 3 2 1 0
32 clocks
Figure 10. Format 3 - Right-Justified 24-bit Data
22
DS617PP1
CS4362A
LRCK
Right Channel
Left Channel
SCLK
SDINx
1 0
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
Figure 11. Format 4 - Right-Justified 20-bit Data
LRCK
Right Channel
Left Channel
SCLK
SDINx
1 0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
Figure 12. Format 5 - Right-Justified 18-bit Data
3.4
Oversampling Modes
The CS4362A operates in one of three oversampling modes based on the input sample rate. Mode selection
is determined by the DSD_EN, M3 and M2 pins in hardware mode or the FM bits in software mode. SingleSpeed mode supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-Speed
mode supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-speed mode
supports input sample rates up to 200 kHz and uses an oversampling ratio of 32x.
3.5
Interpolation Filter
To accommodate the increasingly complex requirements of digital audio systems, the CS4362A incorporates selectable interpolation filters for each mode of operation. A “fast” and a “slow” roll-off filter is available
in each of Single, Double, and Quad-Speed modes. These filters have been designed to accommodate a
variety of musical tastes and styles. The FILT_SEL bit is used to select which filter is used (see the “Parameter Definitions” on page 41 for more details).
When in hardware mode, only the “fast” roll-off filter is available.
Filter specifications can be found in Section 2, and filter response plots can be found in Figures 19 to 42.
3.6
De-Emphasis
The CS4362A includes on-chip digital de-emphasis filters. The de-emphasis feature is included to accommodate older audio recordings that utilize pre-emphasis equalization as a means of noise reduction. Figure
13 shows the de-emphasis curve. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs if the input sample rate does not match the coefficient which has been
selected.
DS617PP1
23
CS4362A
In software mode the required de-emphasis filter coefficients for 32 kHz, 44.1 kHz, or 48 kHz are selected
via the de-emphasis control bits.
In hardware mode only the 44.1 kHz coefficient is available (enabled through the M2 pin). If the input sample rate is not 44.1 kHz and de-emphasis has been selected then the corner frequencies of the de-emphasis
filter will be scaled by a factor of the actual Fs over 44,100.
Gain
dB
T1=50 µs
0dB
T2 = 15 µs
-10dB
F1
3.183 kHz
F2
Frequency
10.61 kHz
Figure 13. De-Emphasis Curve
3.7
ATAPI Specification
The CS4362A implements the channel mixing functions of the ATAPI CD-ROM specification. The
ATAPI functions are applied per A-B pair. Refer to Table 7 on page 38 and Figure 14 for additional information.
A Channel
Volume
Control
Left Channel
Audio Data
Σ
SDINx
Right Channel
Audio Data
MUTE
Aout Ax
MUTE
AoutBx
Σ
B Channel
Volume
Control
Figure 14. ATAPI Block Diagram (x = channel pair 1, 2, or 3)
24
DS617PP1
CS4362A
3.8
Direct Stream Digital (DSD) Mode
In stand-alone mode, DSD operation is selected by holding DSD_EN(LRCK) high and applying the DSD
data and clocks to the appropriate pins. The M[2:0] pins set the expected DSD rate and MCLK ratio.
In control-port mode the FM bits set the device into DSD mode (DSD_EN pin is not required to be held high).
The DIF register then controls the expected DSD rate and MCLK ratio.
During DSD operation, the PCM related pins should either be tied low or remain active with clocks (except
LRCK in Stand-alone mode). When the DSD related pins are not being used they should either be tied static
low, or remain active with clocks (except M3 in Stand-alone mode).
3.9
Grounding and Power Supply Arrangements
As with any high resolution converter, the CS4362A requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. The Typical Connection Diagram shows the
recommended power arrangements, with VA, VD, VLC, and VLS connected to clean supplies. If the ground
planes are split between digital ground and analog ground, the GND pins of the CS4362A should be connected to the analog ground plane.
All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted
coupling into the DAC.
3.9.1 Capacitor Placement
Decoupling capacitors should be placed as close to the DAC as possible, with the low value ceramic capacitor being the closest. To further minimize impedance, these capacitors should be located on the same
layer as the DAC. If desired, all supply pins with similar voltage ratings may be connected to the same supply, but a decoupling capacitor should still be placed on each supply pin.
Notes:
All decoupling capacitors should be referenced to analog ground.
The CDB4362A evaluation board demonstrates the optimum layout and power supply arrangements.
3.10
Analog Output and Filtering
The application note “Design Notes for a 2-Pole Filter with Differential Input” discusses the second-order
Butterworth filter and differential to single-ended converter which was implemented on the CS4362A evaluation board, CDB4362A, as seen in Figure 16. The CS4362A does not include phase or amplitude compensation for an external filter. Therefore, the DAC system phase and amplitude response will be dependent
on the external analog circuitry. The off-chip filter has been designed to attenuate the typical full-scale output level to below 2 Vrms.
Figure 15 shows how the full-scale differential analog output level specification is derived.
DS617PP1
25
CS4362A
3.85 V
2.5 V
AOUT+
1.15 V
3.85 V
AOUT-
2.5 V
1.15 V
Full-Scale Output Level= (AOUT+) - (AOUT-)= 6.7 Vpp
Figure 15. Full-Scale Output
Figure 16. Recommended Output Filter
3.11
Mute Control
The Mute Control pins go active during power-up initialization, reset, muting, or if the MCLK to LRCK ratio
is incorrect. These pins are intended to be used as control for external mute circuits to prevent the clicks
and pops that can occur in any single-ended single supply system.
Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer
to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit.
Please see the CDB4362A data sheet for a suggested mute circuit.
26
DS617PP1
CS4362A
3.12
Recommended Power-Up Sequence
3.12.1 Hardware Mode
1.
Hold RST low until the power supplies and configuration pins are stable, and the master and left/right
clocks are locked to the appropriate frequencies, as discussed in section 3.1. In this state, the registers
are reset to the default settings, FILT+ will remain low, and VQ will be connected to VA/2.
If RST can not be held low long enough the SDINx pins should remain static low until all other clocks
are stable, and if possible the RST should be toggled low again once the system is stable.
2.
Bring RST high. The device will remain in a low power state with FILT+ low and will initiate the
Hardware power-up sequence after approximately 512 LRCK cycles in Single-Speed Mode (1024
LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode).
3.12.2 Software Mode
1.
Hold RST low until the power supply is stable, and the master and left/right clocks are locked to the
appropriate frequencies, as discussed in section 3.1. In this state, the registers are reset to the default
settings, FILT+ will remain low, and VQ will be connected to VA/2.
2.
Bring RST high. The device will remain in a low power state with FILT+ low for 512 LRCK cycles in
Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in QuadSpeed Mode).
3.
In order to reduce the chances of clicks and pops, perform a write to the CP_EN bit prior to the
completion of approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in DoubleSpeed Mode, and 2048 LRCK cycles in Quad-Speed Mode). The desired register settings can be
loaded while keeping the PDN bit set to 1. Set the RMP_UP and RMP_DN bits to 1, then set the format
and mode control bits to the desired settings.
If more than the stated number of LRCK cycles passes before CPEN bit is written then the chip will
enter Hardware mode and begin to operate with the M0-M3 as the mode settings. CPEN bit may be
written at anytime, even after the Hardware sequence has begun. It is advised that if the CPEN bit can
not be set in time then the SDINx pins should remain static low (this way no audio data can be
converted incorrectly by the hardware mode settings).
4.
3.13
Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 µs.
Recommended Procedure for Switching Operational Modes
For systems where the absolute minimum in clicks and pops is required, it is recommended that the MUTE
bits are set prior to changing significant DAC functions (such as changing sample rates or clock sources).
The mute bits may then be released after clocks have settled and the proper modes have been set.
It is required to have the device held in reset if the minimum high/low time specs of MCLK can not be met
during clock source changes.
DS617PP1
27
CS4362A
3.14
Control Port Interface
The control port is used to load all the internal register settings in order to operate in software mode (see
the “Parameter Definitions” on page 41). The operation of the control port may be completely asynchronous
with the audio sample rate. However, to avoid potential interference problems, the control port pins should
remain static if no operation is required.
The control port operates in one of two modes: I2C or SPI.
3.14.1 MAP Auto Increment
The device has MAP (memory address pointer) auto increment capability enabled by the INCR bit (also the
MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I2C writes or reads and SPI
writes. If INCR is set to 1, MAP will auto increment after each byte is written, allowing block reads or writes
of successive registers.
3.14.2 I2C Mode
In the I2C mode, data is clocked into and out of the bi-directional serial control data line, SDA, by the serial
control port clock, SCL (see Figure 17 for the clock to data relationship). There is no CS pin. Pin AD0 enables the user to alter the chip address (001100[AD0][R/W]) and should be tied to VLC or GND as required,
before powering up the device. If the device ever detects a high to low transition on the AD0/CS pin after
power-up, SPI mode will be selected.
3.14.2.1
I2C Write
To write to the device, follow the procedure below while adhering to the control port Switching Specifications in section 2.
1. Initiate a START condition to the I2C bus followed by the address byte. The upper 6 bits must be
001100. The seventh bit must match the setting of the AD0 pin, and the eighth must be 0. The eighth
bit of the address byte is the R/W bit.
2. Wait for an acknowledge (ACK) from the part, then write to the memory address pointer, MAP. This
byte points to the register to be written.
3. Wait for an acknowledge (ACK) from the part, then write the desired data to the register pointed to
by the MAP.
4. If the INCR bit (see section 3.14.1) is set to 1, repeat the previous step until all the desired registers
are written, then initiate a STOP condition to the bus.
5. If the INCR bit is set to 0 and further I2C writes to other registers are desired, it is necessary to initiate a repeated START condition and follow the procedure detailed from step 1. If no further writes to
other registers are desired, initiate a STOP condition to the bus.
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CS4362A
3.14.2.2 I2C Read
To read from the device, follow the procedure below while adhering to the control port Switching Specifications.
1. Initiate a START condition to the I2C bus followed by the address byte. The upper 6 bits must be
001100. The seventh bit must match the setting of the AD0 pin, and the eighth must be 1. The eighth
bit of the address byte is the R/W bit.
2. After transmitting an acknowledge (ACK), the device will then transmit the contents of the register
pointed to by the MAP. The MAP register will contain the address of the last register written to the MAP,
or the default address (see section 3.14.1) if an I2C read is the first operation performed on the device.
3.
Once the device has transmitted the contents of the register pointed to by the MAP, issue an ACK.
4. If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers.
Continue providing a clock and issue an ACK after each byte until all the desired registers are read, then
initiate a STOP condition to the bus.
5. If the INCR bit is set to 0 and further I2C reads from other registers are desired, it is necessary to
initiate a repeated START condition and follow the procedure detailed from steps 1 and 2 from the I2C
Write instructions followed by step 1 of the I2C Read section. If no further reads from other registers are
desired, initiate a STOP condition to the bus.
N ote 1
SDA
001100
ADDR
AD 0
R/W
ACK
DATA
1-8
ACK
DATA
1-8
ACK
SCL
Start
Stop
N ote: If operation is a w rite, th is byte contain s the M em o ry A ddress P ointer, M A P.
Figure 17. Control Port Timing, I2C Mode
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CS4362A
3.14.3 SPI™ Mode
In SPI mode, data is clocked into the serial control data line, CDIN, by the serial control port clock, CCLK
(see Figure 18 for the clock to data relationship). There is no AD0 pin. Pin CS is the chip select signal and
is used to control SPI writes to the control port. When the device detects a high to low transition on the
AD0/CS pin after power-up, SPI mode will be selected. All signals are inputs and data is clocked in on the
rising edge of CCLK.
3.14.3.1
SPI Write
To write to the device, follow the procedure below while adhering to the control port Switching Specifications in Section 2.
1.
Bring CS low.
2.
The address byte on the CDIN pin must then be 00110000.
3.
Write to the memory address pointer, MAP. This byte points to the register to be written.
4.
Write the desired data to the register pointed to by the MAP.
5. If the INCR bit (see section 3.14.1) is set to 1, repeat the previous step until all the desired registers
are written, then bring CS high.
6. If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is necessary to bring
CS high, and follow the procedure detailed from step 1. If no further writes to other registers are desired,
bring CS high.
CS
CCLK
CHIP
ADDRESS
C DIN
0011000
MAP
R/W
DATA
LSB
MSB
byte 1
byte n
M AP = M em ory Address Pointer
Figure 18. Control Port Timing, SPI mode
3.15
Memory Address Pointer (MAP)
7
INCR
0
6
Reserved
0
5
Reserved
0
4
MAP4
0
3
MAP3
0
2
MAP2
0
1
MAP1
0
0
MAP0
0
3.15.1 INCR (AUTO MAP INCREMENT ENABLE)
Default = ‘0’
0 - Disabled
1 - Enabled
3.15.2 MAP4-0 (MEMORY ADDRESS POINTER)
Default = ‘00000’
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4. REGISTER QUICK REFERENCE
Addr
Function
7
01h
Mode Control 1
default
Mode Control 2
default
Mode Control 3
default
Filter Control
default
Invert Control
default
Mixing Control
Pair 1 (AOUTx1)
default
Vol. Control A1
default
Vol. Control B1
default
Mixing Control
Pair 2 (AOUTx2)
default
Vol. Control A2
default
Vol. Control B2
default
Mixing Control
Pair 3 (AOUTx3)
default
Vol. Control A3
default
Vol. Control B3
default
Chip Revision
default
CPEN
0
Reserved
0
SZC1
1
Reserved
0
Reserved
0
P1_A=B
FREEZE MCLKDIV
0
0
DIF2
DIF1
0
0
SZC0
SNGLVOL
0
0
Reserved Reserved
0
0
Reserved
INV_B3
0
0
P1ATAPI4 P1ATAPI3
Reserved DAC3_DIS DAC2_DIS DAC1_DIS
0
0
0
0
DIF0
Reserved Reserved Reserved
0
0
0
0
RMP_UP MUTEC+/AMUTE
MUTEC1
0
0
1
0
FILT_SEL Reserved
DEM1
DEM0
0
0
0
0
INV_A3
INV_B2
INV_A2
INV_B1
0
0
0
0
P1ATAPI2 P1ATAPI1 P1ATAPI0
FM1
PDN
1
Reserved
0
MUTEC0
0
RMP_DN
0
INV_A1
0
FM0
0
A1_MUTE
0
B1_MUTE
0
P2_A=B
0
A1_VOL6
0
B1_VOL6
0
P2ATAPI4
1
A1_VOL5
0
B1_VOL5
0
P2ATAPI3
0
A1_VOL4
0
B1_VOL4
0
P2ATAPI2
0
A1_VOL3
0
B1_VOL3
0
P2ATAPI1
1
A1_VOL2
0
B1_VOL2
0
P2ATAPI0
0
A1_VOL1
0
B1_VOL1
0
Reserved
0
A1_VOL0
0
B1_VOL0
0
Reserved
0
A2_MUTE
0
B2_MUTE
0
P3_A=B
0
A2_VOL6
0
B2_VOL6
0
P3ATAPI4
1
A2_VOL5
0
B2_VOL5
0
P3ATAPI3
0
A2_VOL4
0
B2_VOL4
0
P3ATAPI2
0
A2_VOL3
0
B2_VOL3
0
P3ATAPI1
1
A2_VOL2
0
B2_VOL2
0
P3ATAPI0
0
A2_VOL1
0
B2_VOL1
0
Reserved
0
A2_VOL0
0
B2_VOL0
0
Reserved
0
A3_MUTE
0
B3_MUTE
0
PART4
0
0
A3_VOL6
0
B3_VOL6
0
PART3
1
1
A3_VOL5
0
B3_VOL5
0
PART2
0
0
A3_VOL4
0
B3_VOL4
0
PART1
1
0
A3_VOL3
0
B3_VOL3
0
PART0
0
1
A3_VOL2
0
B3_VOL2
0
REV
x
0
A3_VOL1
0
B3_VOL1
0
REV
x
0
A3_VOL0
0
B3_VOL0
0
REV
x
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
12h
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5
4
3
2
1
0
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CS4362A
5. REGISTER DESCRIPTION
Note: All registers are read/write in I2C mode and write only in SPI, unless otherwise noted.
5.1
Mode Control 1 (address 01h)
7
6
5
4
3
2
1
0
CPEN
0
FREEZE
0
MCLKDIV
0
Reserved
0
DAC3_DIS
0
DAC2_DIS
0
DAC1_DIS
0
PDN
1
5.1.1 Control Port Enable (CPEN)
Default = 0
0 - Disabled
1 - Enabled
Function:
This bit defaults to 0, allowing the device to power-up in Stand-Alone mode. The Control port mode can be
accessed by setting this bit to 1. This will allow the operation of the device to be controlled by the registers
and the pin definitions will conform to Control Port Mode. To accomplish a clean power-up, the user should
write this bit within 10 ms following the release of Reset.
5.1.2 Freeze Controls (Freeze)
Default = 0
0 - Disabled
1 - Enabled
Function:
This function allows modifications to be made to the registers without the changes taking effect until the
FREEZE is disabled. To make multiple changes in the Control port registers take effect simultaneously, enable the FREEZE Bit, make all register changes, then Disable the FREEZE bit.
5.1.3 Master Clock DIVIDE ENABLE (mclkdiv)
Default = 0
0 - Disabled
1 - Enabled
Function:
The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other
internal circuitry.
5.1.4 DAC Pair Disable (DACx_DIS)
Default = 0
0 - Enabled
1 - Disabled
Function:
When enabled the respective DAC channel pairx (AOUTAx and AOUTBx) will remain in a reset state. It is
advised that changes to these bits be made while the power down bit is enabled to eliminate the possibility
of audible artifacts.
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5.1.5 Power Down (PDN)
Default = 1
0 - Disabled
1 - Enabled
Function:
The entire device will enter a low-power state when this function is enabled, and the contents of the control
registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and must be disabled before normal operation in Control Port mode can occur.
5.2
Mode Control 2 (address 02h)
7
6
5
4
3
2
1
0
Reserved
0
DIF2
0
DIF1
0
DIF0
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
5.2.1 Digital Interface Format (dif)
Default = 000 - Format 0 (Left Justified, up to 24-bit data)
Function:
These bits select the interface format for the serial audio input. The Functional Mode bits determine whether PCM or DSD mode is selected.
PCM Mode: The required relationship between the Left/Right clock, serial clock and serial data is defined
by the Digital Interface Format and the options are detailed in Figures 7-12.
DIF2
DIF1
DIF0
DESCRIPTION
Format
FIGURE
0
0
0
0
7
Left Justified, up to 24-bit data
1
8
0
0
1
I2S, up to 24-bit data
0
1
0
2
9
Right Justified, 16-bit data
3
10
0
1
1
Right Justified, 24-bit data
4
11
1
0
0
Right Justified, 20-bit data
1
0
1
5
12
Right Justified, 18-bit data
1
1
0
Reserved
1
1
1
Reserved
Table 5. Digital Interface Formats - PCM Mode
DSD Mode: The relationship between the oversampling ratio of the DSD audio data and the required Master clock to DSD data rate is defined by the Digital Interface Format pins.
DIF2
DIF1
DIFO
DESCRIPTION
0
0
0
64x oversampled DSD data with a 4x MCLK to DSD data rate
0
0
1
64x oversampled DSD data with a 6x MCLK to DSD data rate
0
1
0
64x oversampled DSD data with a 8x MCLK to DSD data rate
0
1
1
64x oversampled DSD data with a 12x MCLK to DSD data rate
1
0
0
128x oversampled DSD data with a 2x MCLK to DSD data rate
1
0
1
128x oversampled DSD data with a 3x MCLK to DSD data rate
1
1
0
128x oversampled DSD data with a 4x MCLK to DSD data rate
1
1
1
128x oversampled DSD data with a 6x MCLK to DSD data rate
Table 6. Digital Interface Formats - DSD Mode
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CS4362A
5.2.2 Mode Control 3 (address 03h)
7
6
5
4
3
2
1
0
SZC1
1
SZC0
0
SNGLVOL
0
RMP_UP
0
MUTEC+/0
AMUTE
1
MUTEC1
0
MUTEC0
0
5.2.3 Soft Ramp AND Zero Cross CONTROL (SZC)
Default = 10
00 - Immediate Change
01 - Zero Cross
10 - Soft Ramp
11 - Soft Ramp on Zero Crossings
Function:
Immediate Change
When Immediate Change is selected all level changes will take effect immediately in one step.
Zero Cross
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout
period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does
not encounter a zero crossing. The zero cross function is independently monitored and implemented for
each channel.
Soft Ramp
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping,
in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
Soft Ramp on Zero Crossing
Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will
occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample
rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored
and implemented for each channel.
5.2.4 Single Volume Control (Snglvol)
Default = 0
0 - Disabled
1 - Enabled
Function:
The individual channel volume levels are independently controlled by their respective Volume Control Bytes
when this function is disabled. The volume on all channels is determined by the A1 Channel Volume Control Byte, and the other Volume Control Bytes are ignored when this function is enabled.
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CS4362A
5.2.5 Soft Volume Ramp-Up after Error (RMP_UP)
Default = 0
0 - Disabled
1 - Enabled
Function:
An un-mute will be performed after a LRCK/MCLK ratio change or error, and after changing the Functional
Mode. When this feature is enabled, this un-mute is affected, similarly to attenuation changes, by the Soft
and Zero Cross bits in the Mode Control 3 register. When disabled, an immediate un-mute is performed in
these instances.
Notes:
For best results, it is recommended that this feature be used in conjunction with the RMP_DN bit.
5.2.6 MUTEC Polarity (MUTEC+/-)
Default = 0
0 - Active High
1 - Active Low
Function:
The active polarity of the MUTEC pin(s) is determined by this register. When set to 0 (default) the MUTEC
pins are high when active. When set to 1 the MUTEC pin(s) are low when active.
Notes:
When the on board mute circuitry is designed for active low, the MUTEC outputs will be high (un-muted)
for the period of time during reset and before this bit is enabled to 1.
5.2.7
Auto-Mute (AMUTE)
Default = 1
0 - Disabled
1 - Enabled
Function:
The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio samples
of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done
independently for each channel. The quiescent voltage on the output will be retained and the Mute Control
pin will go active during the mute period. The muting function is affected, similar to volume control changes,
by the Soft and Zero Cross bits in the Mode Control 3 register.
5.2.8 Mute Pin Control (MUTEC1, MUTEC0)
Default = 00
00 - Six mute control signals
01, 10 - One mute control signal
11 - Three mute control signals
Function:
Selects how the internal mute control signals are routed to the MUTEC1 through MUTEC6 pins. When set
to ‘00’, there is one mute control signal for each channel: AOUT1A on MUTEC1, AOUT1B on MUTEC2,
etc. When set to ‘01’ or ‘10’, there is a single mute control signal on the MUTEC1 pin. When set to ‘11’,
there are three mute control signals, one for each stereo pair: AOUT1A and AOUT1B on MUTEC1,
AOUT2A and AOUT2B on MUTEC2, and AOUT3A and AOUT3B on MUTEC3.
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CS4362A
5.3
Filter Control (address 04h)
7
6
5
4
3
2
1
0
Reserved
0
Reserved
0
Reserved
0
FILT_SEL
0
Reserved
0
DEM1
0
DEM0
0
RMP_DN
0
5.3.1 Interpolation Filter Select (FILT_SEL)
Default = 0
0 - Fast roll-off
1 - Slow roll-off
Function:
This function allows the user to select whether the interpolation filter has a fast or slow roll off. For filter
characteristics please see Section 2.
5.3.2 De-Emphasis Control (DEM)
Default = 00
00 - Disabled
01 - 44.1 kHz
10 - 48 kHz
11 - 32 kHz
Function:
Selects the appropriate digital filter to maintain the standard 15 µs/50 µs digital de-emphasis filter response
at 32, 44.1 or 48 kHz sample rates. (see Figure 13)
De-emphasis is only available in Single Speed Mode.
5.3.3 Soft Ramp-Down before Filter Mode Change (RMP_DN)
Default = 0
0 - Disabled
1 - Enabled
Function:
If either the FILT_SEL or DEM bits are changed the DAC will stop conversion for a period of time to change
filter values. This bit selects how the data is effected prior to and after the change of the filter values. When
this bit is enabled the DAC will ramp down the volume prior to a filter mode change and ramp from mute to
the original volume value after a filter mode change according to the settings of the Soft and Zero Cross
bits in the Mode Control 3 register. When disabled, an immediate mute and unmute is performed.
Loss of clocks or a change in the FM bits will always cause an immediate mute; Unmute in these conditions
is affected by the RMP_UP bit.
Notes:
36
For best results, it is recommended that this feature be used in conjunction with the RMP_UP bit.
DS617PP1
CS4362A
5.4
Invert Control (address 05h)
7
6
5
4
3
2
1
0
Reserved
0
Reserved
0
INV_B3
0
INV_A3
0
INV_B2
0
INV_A2
0
INV_B1
0
INV_A1
0
5.4.1 Invert Signal Polarity (Inv_Xx)
Default = 0
0 - Disabled
1 - Enabled
Function:
When enabled, these bits will invert the signal polarity of their respective channels.
5.5
Mixing Control Pair 1 (Channels A1 & B1)(address 06h)
Mixing Control Pair 2 (Channels A2 & B2)(address 09h)
Mixing Control Pair 3 (Channels A3 & B3)(address 0Ch)
7
6
5
4
3
2
1
0
Px_A=B
0
PxATAPI4
0
PxATAPI3
1
PxATAPI2
0
PxATAPI1
0
PxATAPI0
1
PxFM1
0
PxFM0
0
5.5.1 Channel A Volume = Channel B Volume (A=B)
Default = 0
0 - Disabled
1 - Enabled
Function:
The AOUTAx and AOUTBx volume levels are independently controlled by the A and the B Channel Volume
Control Bytes when this function is disabled. The volume on both AOUTAx and AOUTBx are determined
by the A Channel Attenuation and Volume Control Bytes (per A-B pair), and the B Channel Bytes are ignored when this function is enabled.
5.5.2 ATAPI Channel Mixing and Muting (ATAPI)
Default = 01001 - AOUTAx=aL, AOUTBx=bR (Stereo)
Function:
The CS4362A implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI
functions are applied per A-B pair. Refer to Table 7 and Figure 14 for additional information.
DS617PP1
37
CS4362A
ATAPI4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ATAPI3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
ATAPI2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
ATAPI1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
ATAPI0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AOUTAx
MUTE
MUTE
MUTE
MUTE
aR
aR
aR
aR
aL
aL
aL
aL
a[(L+R)/2]
a[(L+R)/2]
a[(L+R)/2]
a[(L+R)/2]
MUTE
MUTE
MUTE
MUTE
aR
aR
aR
aR
aL
aL
aL
aL
[(aL+bR)/2]
[(aL+bR)/2]
[(bL+aR)/2]
[(aL+bR)/2]
AOUTBx
MUTE
bR
bL
b[(L+R)/2]
MUTE
bR
bL
b[(L+R)/2]
MUTE
bR
bL
b[(L+R)/2]
MUTE
bR
bL
b[(L+R)/2]
MUTE
bR
bL
[(aL+bR)/2]
MUTE
bR
bL
[(bL+aR)/2]
MUTE
bR
bL
[(aL+bR)/2]
MUTE
bR
bL
[(aL+bR)/2]
Table 7. ATAPI Decode
5.5.3 Functional Mode (FM)
Default = 00
00 - Single-Speed Mode (4 to 50 kHz sample rates)
01 - Double-Speed Mode (50 to 100 kHz sample rates)
10 - Quad-Speed Mode (100 to 200 kHz sample rates)
11 - Direct Stream Digital Mode
Function:
Selects the required range of input sample rates or DSD Mode. All DAC pairs are required to be set to the
same functional mode setting before a speed mode change is accepted. When DSD mode is selected for
any channel pair then all pairs will switch to DSD mode.
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5.6
Volume Control (addresses 07h, 08h, 0Ah, 0Bh, 0Dh, 0Eh)
7
6
5
4
3
2
1
0
xx_MUTE
0
xx_VOL6
0
xx_VOL5
0
xx_VOL4
0
xx_VOL3
0
xx_VOL2
0
xx_VOL1
0
xx_VOL0
0
Note: These six registers provide individual volume and mute control for each of the six channels.
The values for “xx” in the bit fields above are as follows:
Register address 07h - xx = A1
Register address 08h - xx = B1
Register address 0Ah - xx = A2
Register address 0Bh - xx = B2
Register address 0Dh - xx = A3
Register address 0Eh - xx = B3
5.6.1 Mute (MUTE)
Default = 0
0 - Disabled
1 - Enabled
Function:
The Digital-to-Analog converter output will mute when enabled. The quiescent voltage on the output will be
retained. The muting function is affected, similarly to attenuation changes, by the Soft and Zero Cross bits.
The MUTE pins will go active during the mute period according to the MUTEC bits.
5.6.2 Volume Control (xx_VOL)
Default = 0 (No attenuation)
Function:
The Digital Volume Control registers allow independent control of the signal levels in 1 dB increments from
0 to -127 dB. Volume settings are decoded as shown in Table 8. The volume changes are implemented
as dictated by the Soft and Zero Cross bits. All volume settings less than -127 dB are equivalent to enabling
the MUTE bit.
Binary Code
0000000
0010100
0101000
0111100
1011010
Decimal Value
0
20
40
60
90
Volume Setting
0 dB
-20 dB
-40 dB
-60 dB
-90 dB
Table 8. Example Digital Volume Settings
DS617PP1
39
CS4362A
5.7
Chip Revision (address 12h)
7
6
5
4
3
2
1
0
PART4
0
PART3
1
PART2
0
PART1
1
PART0
0
Reserved
0
Reserved
0
Reserved
0
5.7.1 Part Number ID (part) [Read Only]
01010 - CS4362A
000 - Revision A
Function:
This read-only register can be used to identify the model and revision number of the device.
40
DS617PP1
CS4362A
6. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.
Dynamic Range
The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth
made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and
do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in
decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full scale analog output for a full scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
7. REFERENCES
Note: "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris. Paper
presented at the 93rd Convention of the Audio Engineering Society, October 1992.
Note: CDB4362A Datasheet
Note: “Design Notes for a 2-Pole Filter with Differential Input” by Steven Green. Cirrus Logic Application Note AN48
Note: “The I2C-Bus Specification: Version 2.0” Philips Semiconductors, December 1998.
http://www.semiconductors.philips.com
8. ORDERING INFORMATION
Product
CS4362A
Description
114 dB, 192 kHz 6channel D/A Converter
Package
Pb-Free
48-pin
LQFP
YES
CDB4362A CS4362A Evaluation Board
DS617PP1
-
Grade
Temp Range
Container
Tray
Commercial -10° to +70° C
Tape & Reel
Tray
Automotive -40° to +105° C
Tape & Reel
-
Order #
CS4362A-CQZ
CS4362A-CQZR
CS4362A-EQZ
CS4362A-EQZR
CDB4362A
41
CS4362A
9. PACKAGE DIMENSIONS
48L LQFP PACKAGE DRAWING
E
E1
D D1
1
e
B
∝
A
A1
L
DIM
A
A1
B
D
D1
E
E1
e*
L
MIN
--0.002
0.007
0.343
0.272
0.343
0.272
0.016
0.018
0.000°
∝
* Nominal pin pitch is 0.50 mm
INCHES
NOM
0.055
0.004
0.009
0.354
0.28
0.354
0.28
0.020
0.24
4°
MAX
0.063
0.006
0.011
0.366
0.280
0.366
0.280
0.024
0.030
7.000°
MIN
--0.05
0.17
8.70
6.90
8.70
6.90
0.40
0.45
0.00°
MILLIMETERS
NOM
1.40
0.10
0.22
9.0 BSC
7.0 BSC
9.0 BSC
7.0 BSC
0.50 BSC
0.60
4°
MAX
1.60
0.15
0.27
9.30
7.10
9.30
7.10
0.60
0.75
7.00°
Controlling dimension is mm.
JEDEC Designation: MS022
42
DS617PP1
CS4362A
0
0
−20
−20
−40
−40
Amplitude (dB)
Amplitude (dB)
10.APPENDIX
−60
−60
−80
−80
−100
−100
−120
0.4
0.5
0.6
0.7
0.8
Frequency(normalized to Fs)
0.9
−120
0.4
1
Figure 19. Single-Speed (fast) Stopband Rejection
0.42
0.44
0.46
0.48
0.5
0.52
Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 20. Single-Speed (fast) Transition Band
0.02
0
−1
0.015
−2
0.01
0.005
−4
Amplitude (dB)
Amplitude (dB)
−3
−5
−6
0
−0.005
−7
−0.01
−8
−0.015
−9
−10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
Frequency(normalized to Fs)
0.52
0.53
0.54
−0.02
0.55
0
0
−20
−20
−40
−40
−60
−80
−100
−100
0.5
0.6
0.7
0.8
Frequency(normalized to Fs)
0.9
1
Figure 23. Single-Speed (slow) Stopband Rejection
DS617PP1
0.1
0.15
0.2
0.25
0.3
Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
−60
−80
−120
0.4
0.05
Figure 22. Single-Speed (fast) Passband Ripple
Amplitude (dB)
Amplitude (dB)
Figure 21. Single-Speed (fast) Transition Band (detail)
0
−120
0.4
0.42
0.44
0.46
0.48
0.5
0.52
Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 24. Single-Speed (slow) Transition Band
43
CS4362A
0.02
0
−1
0.015
−2
0.01
0.005
−4
Amplitude (dB)
Amplitude (dB)
−3
−5
−6
0
−0.005
−7
−0.01
−8
−0.015
−9
−10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
Frequency(normalized to Fs)
0.52
0.53
0.54
−0.02
0.55
Figure 25. Single-Speed (slow) Transition Band (detail)
0.1
0.15
0.2
0.25
0.3
Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
0
20
20
40
40
Amplitude (dB)
Amplitude (dB)
0.05
Figure 26. Single-Speed (slow) Passband Ripple
0
60
60
80
80
100
100
120
0
120
0.4
0.5
0.6
0.7
0.8
Frequency(normalized to Fs)
0.9
1
Figure 27. Double-Speed (fast) Stopband Rejection
0.4
0.42
0.44
0.46
0.48
0.5
0.52
Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 28. Double-Speed (fast) Transition Band
0
0.02
1
0.015
2
0.01
0.005
4
Amplitude (dB)
Amplitude (dB)
3
5
6
0
0.005
7
0.01
8
0.015
9
10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
Figure 29. Double-Speed (fast) Transition Band (detail)
44
0.02
0
0.05
0.1
0.15
0.2
0.25
0.3
Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
Figure 30. Double-Speed (fast) Passband Ripple
DS617PP1
CS4362A
0
20
20
40
40
Amplitude (dB)
Amplitude (dB)
0
60
60
80
80
100
100
120
120
0.2
0.3
0.4
0.5
0.6
0.7
Frequency(normalized to Fs)
0.8
0.9
1
Figure 31. Double-Speed (slow) Stopband Rejection
0.2
0.3
0.4
0.5
0.6
Frequency(normalized to Fs)
0.7
0.8
Figure 32. Double-Speed (slow) Transition Band
0
0.02
1
0.015
2
0.01
0.005
4
Amplitude (dB)
Amplitude (dB)
3
5
6
0
0.005
7
0.01
8
0.015
9
10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
Frequency(normalized to Fs)
0.52
0.53
0.54
0.02
0.55
Figure 33. Double-Speed (slow) Transition Band (detail)
40
40
Amplitude (dB)
Amplitude (dB)
20
60
0.15
0.2
Frequency(normalized to Fs)
0.25
0.3
0.35
60
80
80
100
100
120
0.3
0.4
0.5
0.6
0.7
Frequency(normalized to Fs)
0.8
0.9
1
Figure 35. Quad-Speed (fast) Stopband Rejection
DS617PP1
0.1
0
20
0.2
0.05
Figure 34. Double-Speed (slow) Passband Ripple
0
120
0
0.2
0.3
0.4
0.5
0.6
Frequency(normalized to Fs)
0.7
0.8
Figure 36. Quad-Speed (fast) Transition Band
45
CS4362A
0.2
0
1
0.15
2
0.1
3
Amplitude (dB)
Amplitude (dB)
0.05
4
5
6
0
0.05
7
0.1
8
0.15
9
10
0.45
0.2
0.46
0.47
0.48
0.49
0.5
0.51
Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
Figure 37. Quad-Speed (fast) Transition Band (detail)
0
0.05
0.1
0.15
Frequency(normalized to Fs)
0.2
0.25
Figure 38. Quad-Speed (fast) Passband Ripple
0
0
20
40
40
Amplitude (dB)
Amplitude (dB)
20
60
60
80
80
100
100
120
120
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Frequency(normalized to Fs)
0.8
0.9
1
Figure 39. Quad-Speed (slow) Stopband Rejection
0.1
0.2
0.3
0.4
0.5
0.6
Frequency(normalized to Fs)
0.7
0.8
0.9
Figure 40. Quad-Speed (slow) Transition Band
0.02
0
1
0.015
2
0.01
0.005
4
Amplitude (dB)
Amplitude (dB)
3
5
6
0
0.005
7
0.01
8
0.015
9
10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
Figure 41. Quad-Speed (slow) Transition Band (detail)
46
0.02
0
0.02
0.04
0.06
0.08
Frequency(normalized to Fs)
0.1
0.12
Figure 42. Quad-Speed (slow) Passband Ripple
DS617PP1
CS4362A
Table 9. Revision History
Release
A1
PP1
Date
NOV 2004
APR 2005
Changes
Initial Release
Updated output impedance spec on page 10
Improved interchannel isolation spec on page 10
Updated Legal text
Re-formatted ordering information
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its
subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice
and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before
placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order
acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document
is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks,
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other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
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or service marks of their respective owners.
SPI is a trademark of Motorola, Inc.
DS617PP1
47