CS4341
24-Bit, 96 kHz Stereo DAC with Volume Control
Features
Description
! 101
The CS4341 is a complete stereo digital-to-analog system including digital interpolation, fourth-order DeltaSigma digital-to-analog conversion, digital de-emphasis
and switched capacitor analog filtering. The advantages
of this architecture include: ideal differential linearity, no
distortion mechanisms due to resistor matching errors,
no linearity drift over time and temperature and a high
tolerance to clock jitter.
dB Dynamic Range
! -91 dB THD+N
! +3.0 V or +5.0 V Power Supply
! Low Clock-Jitter Sensitivity
! Filtered Line-Level Outputs
! On-Chip Digital De-Emphasis for 32, 44.1
and 48 kHz
! ATAPI Mixing
! Digital Volume Control with Soft Ramp
The CS4341 accepts data at audio sample rates from
4 kHz to 100 kHz, consumes very little power, and operates over a wide power supply range. The features of
the CS4341 are ideal for DVD players, CD players, settop box and automotive systems.
– 94 dB Attenuation
– 1 dB Step Size
– Zero Crossing Click-Free Transitions
! Popguard®
ORDERING INFORMATION
CS4341-KS
16-pin SOIC, -10 to 70 °C
CS4341-CZZ, Lead Free 16-pin TSSOP, -10 to 70 °C
CDB4341
Evaluation Board
Technology for Control of Clicks
and Pops
! 33 mW with 3.0 V Supply
I
SCL/CCLK
SDA/CDIN
Control Port
RST
SCLK
LRCK
SDATA
Serial Port
Interpolation Filter
AD0/CS
MUTEC
External
Mute Control
Volume Control
∆Σ DAC
Analog Filter
AOUTA
∆Σ DAC
Analog Filter
AOUTB
Mixer
Interpolation Filter
Volume Control
÷2
MCLK
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
DECEMBER '05
DS298F5
1
CS4341
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 4
SPECIFIED OPERATING CONDITIONS .............................................................................................. 4
ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 4
ANALOG CHARACTERISTICS (CS4341-KS/CZZ)............................................................................... 5
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE........................................ 7
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE........................................................ 10
SWITCHING CHARACTERISTICS - INTERNAL SERIAL CLOCK ..................................................... 11
SWITCHING CHARACTERISTICS - CONTROL PORT INTERFACE (I²C®) ..................................... 12
SWITCHING CHARACTERISTICS - CONTROL PORT INTERFACE (SPI™) ................................... 13
DC ELECTRICAL CHARACTERISTICS.............................................................................................. 14
DIGITAL INPUT CHARACTERISTICS ................................................................................................ 14
DIGITAL INTERFACE SPECIFICATIONS........................................................................................... 14
2. PIN DESCRIPTION ............................................................................................................................. 15
3. TYPICAL CONNECTION DIAGRAM ................................................................................................. 16
4. APPLICATIONS ................................................................................................................................... 17
4.1 Sample Rate Range/Operational Mode ........................................................................................ 17
4.2 System Clocking ........................................................................................................................... 17
4.2.1 Internal Serial Clock Mode ............................................................................................... 17
4.2.2 External Serial Clock Mode .............................................................................................. 18
4.3 Digital Interface Format ................................................................................................................. 18
4.4 De-Emphasis ................................................................................................................................ 19
4.5 Power-Up Sequence .................................................................................................................... 19
4.6 Popguard® Transient Control ........................................................................................................ 19
4.6.1 Power-Up ......................................................................................................................... 19
4.6.2 Power-Down ..................................................................................................................... 20
4.6.3 Discharge Time ................................................................................................................ 20
4.7 Mute Control ................................................................................................................................. 20
4.8 Grounding and Power Supply Arrangements ............................................................................... 20
4.9 Control Port Interface .................................................................................................................... 20
4.9.1 Rise Time for Control Port Clock ...................................................................................... 21
4.9.2 Memory Address Pointer (MAP) ...................................................................................... 21
4.9.2a INCR (Auto Map Increment) .............................................................................. 21
4.9.2b MAP0-3 (Memory Address Pointer) .................................................................. 21
4.9.3 I²C Mode .......................................................................................................................... 21
4.9.3a I²C Write ............................................................................................................ 22
4.9.3b I²C Read ............................................................................................................ 22
4.9.4 SPI Mode ......................................................................................................................... 23
4.9.4a SPI Write ........................................................................................................... 23
5. REGISTER QUICK REFERENCE ....................................................................................................... 24
6. REGISTER DESCRIPTION ................................................................................................................. 25
6.1 MCLK Control (address 00h) ......................................................................................................... 25
6.2 Mode Control (address 01h) .......................................................................................................... 25
6.3 Transition and Mixing Control (address 02h) ................................................................................. 27
6.4 Channel A Volume Control (address 03h) ..................................................................................... 29
6.5 Channel B Volume Control (address 04h) ..................................................................................... 29
7. PARAMETER DEFINITIONS ............................................................................................................... 31
8. PACKAGE DIMENSIONS .................................................................................................................... 32
2
DS298F5
CS4341
8.1 SOIC ..............................................................................................................................................32
8.2 TSSOP ..........................................................................................................................................33
9. PACKAGE THERMAL RESISTANCE .................................................................................................33
10. REFERENCES ....................................................................................................................................34
11. REVISION HISTORY ..........................................................................................................................34
LIST OF FIGURES
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Output Test Load .........................................................................................................................6
Maximum Loading ........................................................................................................................6
Single-Speed Stopband Rejection ...............................................................................................8
Single-Speed Transition Band .....................................................................................................8
Single-Speed Transition Band (Detail) .........................................................................................8
Single-Speed Passband Ripple ...................................................................................................8
Double-Speed Stopband Rejection ..............................................................................................8
Double-Speed Transition Band ....................................................................................................8
Double-Speed Transition Band (Detail) .......................................................................................9
Double-Speed Passband Ripple ..................................................................................................9
Serial Input Timing (External SCLK) ..........................................................................................10
Internal Serial Mode Input Timing ..............................................................................................11
Internal Serial Clock Generation ................................................................................................11
Control Port Timing - I²C Mode ..................................................................................................12
Control Port Timing - SPI Mode .................................................................................................13
Typical Connection Diagram ......................................................................................................16
CS4341 Formats 0-1 - I²S up to 24-Bit Data ..............................................................................18
CS4341 Format 2 - Left Justified up to 24-Bit Data ...................................................................18
CS4341 Formats 3-6 - Right Justified ........................................................................................18
De-Emphasis Curve ...................................................................................................................19
I²C Buffer Example .....................................................................................................................21
I²C Write .....................................................................................................................................22
I²C Read .....................................................................................................................................23
Control Port Timing, SPI Mode ..................................................................................................23
ATAPI Block Diagram ................................................................................................................29
LIST OF TABLES
Table 1. CS4341 Speed Modes .....................................................................................................................17
Table 2. Single-Speed Mode Standard Frequencies .....................................................................................17
Table 3. Double-Speed Mode Standard Frequencies ....................................................................................17
Table 4. Internal SCLK/LRCK Ratio ...............................................................................................................18
Table 5. Digital Interface Format ....................................................................................................................26
Table 6. ATAPI Decode..................................................................................................................................28
Table 7. Example Digital Volume Settings .....................................................................................................30
DS298F5
3
CS4341
1.
CHARACTERISTICS AND SPECIFICATIONS
(Min/Max performance characteristics and specifications are guaranteed over the Specified Operating Conditions.
Typical performance characteristics are derived from measurements taken at TA = 25°C.)
SPECIFIED OPERATING CONDITIONS (All voltages with respect to AGND = 0 V.)
Parameters
Symbol
Min
Nom
Max
Units
Nominal 3.3 V
Nominal 5.0 V
VA
VA
2.7
4.75
3.3
5.0
3.6
5.5
V
V
-KS/CZZ
TA
-10
-
+70
°C
DC Power Supply
Specified Operating Temperature
(Power Applied)
ABSOLUTE MAXIMUM RATINGS (AGND = 0 V; all voltages with respect to AGND. Operation beyond
these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.)
Parameters
DC Power Supply
Input Current
Digital Input Voltage
(Note 1)
Symbol
Min
Max
Units
VA
-0.3
6.0
V
Iin
-
±10
mA
VIND
-0.3
VA+0.4
V
Ambient Operating Temperature (power applied)
TA
-55
125
°C
Storage Temperature
Tstg
-65
150
°C
Notes: 1. Any pin except supplies.
4
DS298F5
CS4341
ANALOG CHARACTERISTICS (CS4341-KS/CZZ) (Test conditions (unless otherwise specified): Input
test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth is 10 Hz to 20 kHz; test load R L = 10 kΩ, CL
= 10 pF (see Figure 1).)
VA = 5.0 V
Parameter
Single-Speed Mode
Dynamic Range
18 to 24-Bit
16-Bit
Total Harmonic Distortion + Noise
18 to 24-Bit
16-Bit
Double-Speed Mode
Dynamic Range
18 to 24-Bit
16-Bit
Total Harmonic Distortion + Noise
18 to 24-Bit
16-Bit
DS298F5
VA = 3.0 V
Min
Typ
Max
Min
Typ
Max
Unit
93
96
-
98
101
92
95
-
89
92
-
94
97
92
95
-
dB
dB
dB
dB
-
-91
-78
-38
-90
-72
-32
-86
-
-
-94
-74
-34
-91
-72
-32
-89
-
dB
dB
dB
dB
dB
dB
93
96
-
98
101
92
95
-
89
92
-
94
97
92
95
-
dB
dB
dB
dB
-
-91
-78
-38
-90
-72
-32
-86
-
-
-94
-74
-34
-91
-72
-32
-89
-
dB
dB
dB
dB
dB
dB
Fs = 48 kHz
(Note 2)
unweighted
A-Weighted
unweighted
A-Weighted
(Note 2)
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
Fs = 96 kHz
(Note 2)
unweighted
A-Weighted
unweighted
A-Weighted
(Note 2)
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
5
CS4341
ANALOG CHARACTERISTICS (CS4341-KS/CZZ)
Parameters
Symbol
(Continued)
Min
Typ
Max
Units
-
100
-
dB
Interchannel Gain Mismatch
-
0.1
-
dB
Gain Drift
-
±100
-
ppm/°C
0.6•VA
0.7•VA
0.8•VA
Vpp
-
100
-
Ω
Dynamic Performance for All Modes
Interchannel Isolation (1 kHz)
DC Accuracy
Analog Output Characteristics and Specifications
Full-Scale Output Voltage
Output Impedance
Minimum AC-Load Resistance
(Note 3)
RL
-
3
-
kΩ
Maximum Load Capacitance
(Note 3)
CL
-
100
-
pF
Notes: 2. One-half LSB of triangular PDF dither is added to data.
3. Refer to Figure 2.
.
3.3 µF
AOUTx
+
V
out
R
L
C
L
AGND
Figure 1. Output Test Load
Capacitive Load -- C L (pF)
125
100
75
Safe Operating
Region
50
25
2.5
3
5
10
15
20
Resistive Load -- RL (kΩ )
Figure 2. Maximum Loading
6
DS298F5
CS4341
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (The filter characteristics and the X-axis of the response plots have been normalized to the sample rate (Fs) and can be referenced to the
desired sample rate by multiplying the given characteristic by Fs.)
Parameter
Min
Typ
Max
Unit
0
0
-
0.4535
0.4998
Fs
Fs
-0.02
-
+0.08
dB
0.5465
-
-
Fs
50
-
-
dB
Single-Speed Mode - (4 kHz to 50 kHz sample rates)
Passband
to -0.05 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz
StopBand
StopBand Attenuation
(Note 4)
Group Delay
-
9/Fs
-
s
0 - 20 kHz
-
±0.36/Fs
-
s
Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
-
-
+0.2/-0.1
+0.05/-0.14
+0/-0.22
dB
dB
dB
0
0
-
0.4621
0.4982
Fs
Fs
Frequency Response 10 Hz to 20 kHz
-0.06
-
+0.2
dB
StopBand
0.577
-
-
Fs
55
-
-
dB
Passband Group Delay Deviation
De-emphasis Error (Relative to 1 kHz)
(Note 5)
Double-Speed Mode - (50 kHz to 100 kHz sample rates)
Passband
to -0.1 dB corner
to -3 dB corner
StopBand Attenuation
(Note 4)
Group Delay
Passband Group Delay Deviation
0 - 40 kHz
0 - 20 kHz
-
4/Fs
-
s
-
±1.39/Fs
±0.23/Fs
-
s
s
Notes: 4. For Single-Speed Mode, the measurement bandwidth is 0.5465 Fs to 3 Fs.
For Double-Speed Mode, the measurement bandwidth is 0.577 Fs to 1.4 Fs.
5. De-emphasis is only available in Single-Speed Mode.
DS298F5
7
CS4341
Figure 3. Single-Speed Stopband Rejection
Figure 5. Single-Speed Transition Band (Detail)
Figure 7. Double-Speed Stopband Rejection
8
Figure 4. Single-Speed Transition Band
Figure 6. Single-Speed Passband Ripple
Figure 8. Double-Speed Transition Band
DS298F5
CS4341
Figure 9. Double-Speed Transition Band (Detail)
DS298F5
Figure 10. Double-Speed Passband Ripple
9
CS4341
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE
Parameters
Min
Max
Units
MCLK Frequency
1.024
51.2
MHz
MCLK Duty Cycle
45
55
%
4
50
50
100
kHz
kHz
40
60
%
Input Sample Rate
Symbol
Single-Speed Mode
Double-Speed Mode
Fs
Fs
LRCK Duty Cycle
SCLK Pulse Width Low
tsclkl
20
-
ns
SCLK Pulse Width High
tsclkh
20
-
ns
-
128xFs
64xFs
Hz
Hz
SCLK Frequency
Single-Speed Mode
Double-Speed Mode
SCLK rising to LRCK edge delay
tslrd
20
-
ns
SCLK rising to LRCK edge setup time
tslrs
20
-
ns
SDIN valid to SCLK rising setup time
tsdlrs
20
-
ns
SCLK rising to SDIN hold time
tsdh
20
-
ns
LRCK
t sclkh
t slrs
t slrd
t sclkl
SCLK
t sdlrs
t sdh
SDATA
Figure 11. Serial Input Timing (External SCLK)
10
DS298F5
CS4341
SWITCHING CHARACTERISTICS - INTERNAL SERIAL CLOCK
Parameters
Min
Typ
Max
Units
MCLK Frequency
1.024
-
51.2
MHz
MCLK Duty Cycle
45
-
55
%
4
50
-
50
100
kHz
kHz
Input Sample Rate
Symbol
Single-Speed Mode
Double-Speed Mode
Fs
Fs
LRCK Duty Cycle
%
(Note 6)
SCLK Period
tsclkw
1
---------------SCLK
-
-
s
tsclkr
-
t sclkw
------------2
-
s
SDATA valid to SCLK rising setup time
tsdlrs
1
---------------------- + 10
( 512 )Fs
-
-
ns
SCLK rising to SDATA hold time
MCLK / LRCK = 512, 256 or 128
tsdh
1
---------------------- + 15
( 512 )Fs
-
-
ns
SCLK rising to SDATA hold time
MCLK / LRCK = 384 or 192
tsdh
1
---------------------- + 15
( 384 )Fs
-
-
ns
(Note 7)
SCLK rising to LRCK edge
Notes: 6. The Duty Cycle must be 50% +/− 1/2 MCLK Period.
7. See section 4.2.1 for derived internal frequencies.
LRCK
t sclkr
SDATA
t sclkw
t sdlrs
t sdh
*INTERNAL SCLK
Figure 12. Internal Serial Mode Input Timing
*The SCLK pulses shown are internal to the CS4341.
LRCK
MCLK
1
N
2
N
*INTERNAL SCLK
SDATA
Figure 13. Internal Serial Clock Generation
* The SCLK pulses shown are internal to the CS4341. N equals MCLK divided by SCLK
DS298F5
11
CS4341
SWITCHING CHARACTERISTICS - CONTROL PORT INTERFACE (I²C®)
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
fscl
-
100
kHz
RST Rising Edge to Start
tirs
500
-
ns
Bus Free Time Between Transmissions
tbuf
4.7
-
µs
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
-
µs
Clock Low time
tlow
4.7
-
µs
Clock High Time
thigh
4.0
-
µs
Setup Time for Repeated Start Condition
tsust
4.7
-
µs
thdd
0
-
µs
tsud
250
-
ns
trc
-
25
ns
Fall Time of SCL
tfc
-
25
ns
Rise Time SDA
trd
-
1
µs
Fall Time of SDA
tfd
-
300
ns
tsusp
4.7
-
µs
I²C Mode
SDA Hold Time from SCL Falling
(Note 8)
SDA Setup time to SCL Rising
Rise Time of SCL
(Note 9)
Setup Time for Stop Condition
Notes: 8. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
9. See “Rise Time for Control Port Clock” on page 21 for a recommended circuit to meet rise time
specification.
RST
t irs
Stop
Repeated
Start
Start
Stop
SDA
t buf
t
t high
t hdst
tf
hdst
t susp
SCL
t
low
t
hdd
t sud
t sust
tr
Figure 14. Control Port Timing - I²C Mode
12
DS298F5
CS4341
SWITCHING CHARACTERISTICS - CONTROL PORT INTERFACE (SPI™)
Parameter
Symbol
Min
Max
Unit
CCLK Clock Frequency
fsclk
-
6
MHz
RST Rising Edge to CS Falling
tsrs
500
-
ns
tspi
500
-
ns
CS High Time Between Transmissions
tcsh
1.0
-
µs
CS Falling to CCLK Edge
tcss
20
-
ns
CCLK Low Time
tscl
1
----------------MCLK
-
ns
CCLK High Time
tsch
1
----------------MCLK
-
ns
CDIN to CCLK Rising Setup Time
tdsu
40
-
ns
SPI Mode
CCLK Edge to CS Falling
(Note 10)
CCLK Rising to DATA Hold Time
(Note 11)
tdh
15
-
ns
Rise Time of CCLK and CDIN
(Note 12)
tr2
-
100
ns
Fall Time of CCLK and CDIN
(Note 12)
tf2
-
100
ns
Notes: 10. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
11. Data must be held for sufficient time to bridge the transition time of CCLK.
12. For fsclk < 1 MHz.
RST
t srs
CS
t spi t css
t scl
t sch
t csh
CCLK
t r2
t f2
CDIN
t dsu t
dh
Figure 15. Control Port Timing - SPI Mode
DS298F5
13
CS4341
DC ELECTRICAL CHARACTERISTICS (AGND = 0 V; all voltages with respect to AGND.)
Parameters
Symbol
Min
Typ
Max
Units
IA
IA
-
15
11
18
14
mA
mA
-
75
33
90
42
mW
mW
-
60
30
-
µA
µA
-
0.3
0.09
-
mW
mW
-
60
40
-
dB
dB
VQ Nominal Voltage
Output Impedance
Maximum allowable DC current source/sink
-
0.45•VA
250
0.01
-
kΩ
Filt+ Nominal Voltage
Output Impedance
Maximum allowable DC current source/sink
-
VA
250
0.01
-
mA
MUTEC Low-Level Output Voltage
-
0
-
V
MUTEC High-Level Output Voltage
-
VA
-
V
Maximum MUTEC Drive Current
-
3
-
mA
Normal Operation (Note 13)
Power Supply Current
VA = 5.0 V
VA = 3.0 V
Power Dissipation
VA = 5.0 V
VA = 3.0 V
Power-down Mode (Note 14)
Power Supply Current
VA = 5.0 V
VA = 3.0 V
Power Dissipation
VA = 5.0 V
VA = 3.0 V
IA
All Modes of Operation
Power Supply Rejection Ratio (Note 15)
1 kHz
60 Hz
PSRR
V
mA
V
kΩ
Notes: 13. Normal operation is defined as RST = HI with a 997 Hz, 0 dBFS input sampled at the highest Fs for
each speed mode, and open outputs, unless otherwise specified.
14. Power Down Mode is defined as RST = LO with all clocks and data lines held static.
15. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figure 16. Increasing the
capacitance will also increase the PSRR.
DIGITAL INPUT CHARACTERISTICS (AGND = 0 V; all voltages with respect to AGND.)
Parameters
Input Leakage Current
Symbol
Min
Typ
Max
Units
Iin
-
-
±10
µA
-
8
-
pF
Input Capacitance
DIGITAL INTERFACE SPECIFICATIONS (AGND = 0 V; all voltages with respect to AGND.)
Parameters
Symbol
Min
Max
Units
High-Level Input Voltage
VIH
2.0
-
V
Low-Level Input Voltage
VIL
-
0.8
V
High-Level Input Voltage
VIH
2.0
-
V
Low-Level Input Voltage
VIL
-
0.8
V
3.3 V Logic (3.0 V to 3.6 V DC Supply)
5.0 V Logic (4.75 V to 5.25 V DC Supply)
14
DS298F5
CS4341
2.
PIN DESCRIPTION
RST
1
16
MUTEC
SDATA
2
15
AOUTA
SCLK
3
14
VA
LRCK
4
13
AGND
MCLK
5
12
AOUTB
SCL/CCLK
6
11
REF_GND
SDA/CDIN
7
10
VQ
AD0/CS
8
9
FILT+
Pin Name
#
Pin Description
RST
1
Reset (Input) - Powers down device and resets registers to their default settings.
SDATA
2
Serial Audio Data (Input) - Input for two’s complement serial audio data.
SCLK
3
Serial Clock (Input) -Serial clock for the serial audio interface.
LRCK
4
Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the
serial audio data line.
MCLK
5
Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
SCL/CCLK
6
Serial Control Port Clock (Input) - Serial clock for the control port interface.
SDA/CDIN
7
Serial Control Data I/O (Input/Output) - Input/Output for I²C data. Input for SPI data.
AD0/CS
8
Address Bit / Chip Select (Input) - Chip address bit in I²C Mode. Control signal used to select
the chip in SPI mode.
FILT+
9
Positive Voltage Reference (Output) - Positive voltage reference for the internal
sampling circuits.
VQ
10
Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage.
REF_GND
11
Reference Ground (Input) - Ground reference for the internal sampling circuits.
AOUTB
AOUTA
12
15
Analog Outputs (Output) - The full-scale analog output level is specified in the
Analog Characteristics table.
AGND
13
Analog Ground (Input)
VA
14
Power (Input) - Positive power for the analog, digital, and serial audio interface sections.
MUTEC
16
Mute Control (Output) - Control signal for an optional mute circuit.
DS298F5
15
CS4341
3.
TYPICAL CONNECTION DIAGRAM
+3.0 V or +5.0 V
+
0.1 µF
14
1 µF
VA
2
Serial Audio
Data
Processor
3
4
SDATA
3.3 µF
SCLK
AOUT A
560 Ω
Audio
O utput A
15
+
LR CK
C
10 k Ω
RL
CS4341
M UTEC 16
External Clock
5
M CLK
FILT+
VQ
6
7
Micro-Controlled
Configuration
O PTIO NAL
MUTE
CIRCUIT
9
+
10
.1 µF + 1 µF
0.1 µF
1 µF
11
SCL/CCLK
REF_GND
3.3 µF
SDA/CDIN
560 Ω
12
8
AO UTB
AD0/CS
1
10 k Ω
RST
Audio
O utput B
+
C
RL
AG ND
13
R L + 560
C=
4 π Fs(R L 560)
Figure 16. Typical Connection Diagram
16
DS298F5
CS4341
4.
APPLICATIONS
4.1
Sample Rate Range/Operational Mode
The device operates in one of two operational modes determined by the Master Clock to Left/Right Clock
ratio (see section 4.2). Sample rates outside the specified range for each mode are not supported.
Input Sample Rate (Fs)
4 kHz - 50 kHz
50 kHz - 100 kHz
MODE
Single-Speed Mode
Double-Speed Mode
Table 1. CS4341 Speed Modes
4.2
System Clocking
The device requires external generation of the master (MCLK) and left/right (LRCK) clocks. The device
also requires external generation of the serial clock (SCLK) if the internal serial clock is not used. The
LRCK, defined also as the input sample rate Fs, must be synchronously derived from MCLK according to
specified ratios. The specified ratios of MCLK to LRCK, along with several standard audio sample rates
and the required MCLK frequency, are illustrated in Tables 2 and 3.
Sample Rate
(kHz)
32
44.1
48
256x
8.1920
11.2896
12.2880
384x
12.2880
16.9344
18.4320
MCLK (MHz)
512x
16.3840
22.5792
24.5760
768x*
24.5760
33.8688
36.8640
1024x*
32.768
45.1584
49.1520
Table 2. Single-Speed Mode Standard Frequencies
Sample Rate
(kHz)
64
88.2
96
MCLK (MHz)
128x
8.1920
11.2896
12.2880
192x
12.2880
16.9344
18.4320
256x*
16.3840
22.5792
24.5760
384x*
24.5760
33.8688
36.8640
Table 3. Double-Speed Mode Standard Frequencies
*Requires MCLKDIV bit = 1 in the MCLK Control (address 00h) register.
4.2.1
Internal Serial Clock Mode
The device will enter the Internal Serial Clock Mode if no low to high transitions are detected on
the SCLK pin for 2 consecutive periods of LRCK. In this mode, the SCLK is internally derived and
synchronous with MCLK and LRCK. The SCLK/LRCK ratio is either 32, 48, or 64 depending upon
the MCLK/LRCK ratio and the Digital Interface Format selection (see Table 4).
Operation in the Internal Serial Clock mode is identical to operation with an external SCLK synchronized with LRCK; however, External SCLK mode is recommended for system clocking applications.
DS298F5
17
CS4341
Input
MCLK/LRCK
Ratio
512, 256, 128
384, 192
512, 256, 128
Digital Interface Format Selection
Right Justified
I S up to 16 or Left Justified 24 Right Justified
Bits
18, 20 or 24 Bits
16 Bits
24 Bits
(Format 1)
X
2
Internal
SCLK/LRCK
Ratio
32
X
X
X
X
48
(Format 0)
X
X
-
64
Table 4. Internal SCLK/LRCK Ratio
4.2.2
External Serial Clock Mode
The device will enter the External Serial Clock Mode whenever 16 low to high transitions are detected on the SCLK pin during any phase of the LRCK period. The device will revert to Internal
Serial Clock Mode if no low to high transitions are detected on the SCLK pin for 2 consecutive periods of LRCK.
4.3
Digital Interface Format
The device will accept audio samples in several digital interface formats. The desired format is selected
via the DIF0, DIF1 and DIF2 bits in the Mode Control register (see section 6.2.2). For an illustration of the
required relationship between LRCK, SCLK and SDATA, see Figures 17 through 19.
Left C ha nnel
LR C K
R ig ht C ha nnel
SCLK
SDATA
MSB
-1 -2 -3 -4 -5
+5 +4 +3 +2 +1
LSB
MSB
-1 -2 -3 -4
+5 +4 +3 +2 +1
LSB
Figure 17. CS4341 Formats 0-1 - I²S up to 24-Bit Data
Left C ha nnel
LR C K
R ig ht C ha nnel
SCLK
SDATA
MSB -1
-2 -3 -4 -5
+5 +4 +3 +2 +1
MSB -1
LSB
-2 -3 -4
+5 +4 +3 +2 +1
LSB
Figure 18. CS4341 Format 2 - Left Justified up to 24-Bit Data
LRCK
R ight Cha nnel
Left Channel
SCLK
SDATA
LSB
MSB
-1 -2 -3 -4 -5
+7 +6 +5 +4 +3 +2 +1
LSB
MSB
-1 -2 -3 -4 -5
+7 +6 +5 +4 +3 +2 +1
LSB
Figure 19. CS4341 Formats 3-6 - Right Justified
18
DS298F5
CS4341
4.4
De-Emphasis
The device includes on-chip digital de-emphasis. The Mode Control (address 01h) bits select either the
32, 44.1 or 48 kHz de-emphasis filter. Figure 20 shows the de-emphasis curve for Fs equal to 44.1 kHz.
The frequency response of the de-emphasis curve will scale proportionally with changes in sample
rate, Fs. Please see section 6.2.3 for the desired de-emphasis control.
De-emphasis is only available in Single-Speed Mode.
Gain
dB
T1=50 µs
0dB
T2 = 15 µs
-10dB
F1
3.183 kHz
F2
Frequency
10.61 kHz
Figure 20. De-Emphasis Curve
4.5
Power-Up Sequence
1) Hold RST low until the power supply is stable, and the master and left/right clocks are locked to the
appropriate frequencies, as discussed in section 4.2. In this state, the control port is reset to its default
settings and VQ will remain low.
2) Bring RST high. The device will remain in a low power state with VQ low.
3) Load the desired register settings while keeping the PDN bit set to 1.
4) Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 µS when
the POR bit is set to 0. If the POR bit is set to 1, see section 4.6 for a complete description of powerup timing.
4.6
Popguard® Transient Control
The CS4341 uses Popguard® technology to minimize the effects of output transients during power-up and
power-down. This technology, when used with external DC-blocking capacitors in series with the audio
outputs, minimizes the audio transients commonly produced by single-ended single-supply converters. It
is activated inside the DAC when RST is enabled/disabled and requires no other external control, aside
from choosing the appropriate DC-blocking capacitors.
4.6.1
Power-Up
When the device is initially powered-up, the audio outputs, AOUTL and AOUTR, are clamped to
AGND. Following a delay of approximately 1000 sample periods, each output begins to ramp toward the quiescent voltage. Approximately 10,000 LRCK cycles later, the outputs reach VQ and
audio output begins. This gradual voltage ramping allows time for the external DC-blocking capacitors to charge to the quiescent voltage, minimizing the power-up transient.
DS298F5
19
CS4341
4.6.2
Power-Down
To prevent transients at power-down, the device must first enter its power-down state by enabling
RST or setting the PDN bit. When this occurs, audio output ceases and the internal output buffers
are disconnected from AOUTL and AOUTR. In their place, a soft-start current sink is substituted
which allows the DC-blocking capacitors to slowly discharge. Once this charge is dissipated, the
power to the device may be turned off and the system is ready for the next power-on.
4.6.3
Discharge Time
To prevent an audio transient at the next power-on, it is necessary to ensure that the DC-blocking
capacitors have fully discharged before turning on the power or exiting the power-down state. If
not, a transient will occur when the audio outputs are initially clamped to AGND. The time that the
device must remain in the power-down state is related to the value of the DC-blocking capacitance.
For example, with a 3.3 µF capacitor, the minimum power-down time will be approximately
0.4 seconds.
4.7
Mute Control
The Mute Control pin goes high during power-up initialization, reset, muting (see section 6.2.1 and 6.5.1)
or if the MCLK to LRCK ratio is incorrect. This pin is intended to be used as a control for an external mute
circuit to prevent the clicks and pops that can occur in any single-ended single supply system.
Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute
minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system
designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute
circuit. See the CDB4341 data sheet for a suggested mute circuit.
4.8
Grounding and Power Supply Arrangements
As with any high resolution converter, the CS4341 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 16 shows the recommended power
arrangements, with VA connected to a clean supply. If the ground planes are split between digital ground
and analog ground, REF_GND & AGND should be connected to the analog ground plane.
Decoupling capacitors should be as close to the DAC as possible, with the low value ceramic capacitor
being the closest. To further minimize impedance, these capacitors should be located on the same layer
as the DAC.
All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted
coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be
positioned to minimize the electrical path from FILT+ and REF_GND (as well as VQ and REF_GND), and
should also be located on the same layer as the DAC. The CDB4341 evaluation board demonstrates the
optimum layout and power supply arrangements.
4.9
Control Port Interface
The control port is used to load all the internal register settings (see section 6). The operation of the control
port may be completely asynchronous with the audio sample rate. However, to avoid potential interference problems, the control port pins should remain static if no operation is required.
The control port operates in one of two modes: I²C or SPI.
Notes: MCLK must be applied during all I²C communication.
20
DS298F5
CS4341
4.9.1
Rise Time for Control Port Clock
When excess capacitive loading is present on the I²C clock line, pin 6 (SCL/CCLK) may not have
sufficient hysteresis to meet the standard I²C rise time specification. This prevents the use of common I²C configurations with a resistor pull-up. A workaround is achieved by placing a Schmitt Trigger buffer, a 74HC14 for example, on the SCL line just prior to the CS4341. This will not affect the
operation of the I²C bus as pin 6 is an input only.
VA
P in 6
SCL
Figure 21. I²C Buffer Example
4.9.2
Memory Address Pointer (MAP)
The MAP byte precedes the control port register byte during a write operation and is not available
again until after a start condition is initiated. During a read operation the byte transmitted after the
ACK will contain the data of the register pointed to by the MAP (see section 4.9.3 for write/read
details).
7
INCR
0
4.9.2a
6
Reserved
0
5
Reserved
0
4
Reserved
0
3
MAP3
0
2
MAP2
0
1
MAP1
0
0
MAP0
0
INCR (Auto Map Increment)
The device has a MAP auto increment capability enabled by the INCR bit (the MSB) of the MAP.
If INCR is set to 0, MAP will stay constant for successive I²C writes or reads and SPI writes. If INCR
is set to 1, MAP will auto increment after each byte is written, allowing block reads or writes of successive registers.
Default = ‘0’
0 - Disabled
1 - Enabled
4.9.2b
MAP0-3 (Memory Address Pointer)
Default = ‘0000’
4.9.3
I²C Mode
In the I²C Mode, data is clocked into and out of the bi-directional serial control data line, SDA, by
the serial control port clock, SCL. There is no CS pin. Pin AD0 enables the user to alter the chip
address (001000[AD0][R/W]) and should be tied to VA or AGND as required, before powering up
the device. If the device ever detects a high to low transition on the AD0/CS pin after power-up,
SPI mode will be selected.
DS298F5
21
CS4341
SDA
001000
AD0
W
ACK
MAP
1-8
ACK
DATA
1-8
ACK
SCL
Stop
S tart
Figure 22. I²C Write
4.9.3a
I²C Write
To write to the device, follow the procedure below while adhering to the control port Switching
Specifications in section 6.
1) Initiate a START condition to the I²C bus followed by the address byte. The upper 6 bits must
be 001000. The seventh bit must match the setting of the AD0 pin, and the eighth must be 0.
The eighth bit of the address byte is the R/W bit.
2) Wait for an acknowledge (ACK) from the part, then write to the memory address pointer, MAP.
This byte points to the register to be written.
3) Wait for an acknowledge (ACK) from the part, then write the desired data to the register pointed to by the MAP.
4) If the INCR bit (see section 4.9.2a) is set to 1, repeat the previous step until all the desired
registers are written, then initiate a STOP condition to the bus.
5) If the INCR bit is set to 0 and further I²C writes to other registers are desired, it is necessary to
repeat the procedure detailed from step 1. If no further writes to other registers are desired,
initiate a STOP condition to the bus.
4.9.3b
I²C Read
To read from the device, follow the procedure below while adhering to the control port Switching
Specifications. During this operation it is first necessary to write to the device, specifying the appropriate register through the MAP.
1) After writing to the MAP (see section 4.9.3a), initiate a repeated START condition to the I²C
bus followed by the address byte. The upper 6 bits must be 001000. The seventh bit must
match the setting of the AD0 pin, and the eighth must be 1. The eighth bit of the address byte
is the R/W bit.
2) Signal the end of the address byte by not issuing an acknowledge. The device will then transmit the contents of the register pointed to by the MAP. The MAP will contain the address of the
last register written to the MAP.
3) If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers. Continue providing a clock but do not issue an ACK on the bytes clocked out of the device. After all the desired registers are read, initiate a STOP condition to the bus.
4) If the INCR bit is set to 0 and further I²C reads from other registers are desired, it is necessary
to repeat the procedure detailed from step 1. If no further reads from other registers are desired, initiate a STOP condition to the bus.
22
DS298F5
CS4341
SD A
001000
AD0
W
M AP
1-8
ACK
ACK
001000
AD0
R
ACK
Data 1-8
(pointed to by MAP)
ACK
Data 1-8
(pointed to by MAP)
SCL
Repeated START
or
Aborted W RITE
S tart
Stop
Figure 23. I²C Read
4.9.4
SPI Mode
In SPI mode, data is clocked into the serial control data line, CDIN, by the serial control port clock,
CCLK (see Figure 24 for the clock to data relationship). There is no AD0 pin. Pin CS is the chip
select signal and is used to control SPI writes to the control port. When the device detects a high
to low transition on the AD0/CS pin after power-up, SPI mode will be selected. All signals are inputs
and data is clocked in on the rising edge of CCLK.
4.9.4a
SPI Write
To write to the device, follow the procedure below while adhering to the control port Switching
Specifications in section 1.
1) Bring CS low.
2) The address byte on the CDIN pin must then be 00100000.
3) Write to the memory address pointer, MAP. This byte points to the register to be written.
4) Write the desired data to the register pointed to by the MAP.
5) If the INCR bit (see section 4.9.2a) is set to 1, repeat the previous step until all the desired
registers are written, then bring CS high.
6) If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is necessary
to bring CS high, and repeat the procedure detailed from step 1. If no further writes to other
registers are desired, bring CS high.
CS
CCLK
CHIP
ADDRESS
CDIN
0010000
MAP
R/W
DATA
MSB
byte 1
LSB
byte n
MAP = Memory Address Pointer
Figure 24. Control Port Timing, SPI Mode
DS298F5
23
CS4341
5. REGISTER QUICK REFERENCE
Addr
0h
Function
MCLK Control
DEFAULT
1h
Mode Control 2
DEFAULT
2h
Transition and Mixing
Control
DEFAULT
3h
Channel A Volume
Control
4h
Channel B Volume
Control
DEFAULT
DEFAULT
24
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
0
AMUTE
DIF2
DIF1
DIF0
DEM1
DEM1
POR
PDN
1
0
0
0
0
0
1
1
A=B
SCZ1
SCZ0
ATAPI4
ATAPI3
ATAPI2
ATAPI1
ATAPI0
0
0
0
0
0
0
0
0
MUTEA
VOLA6
VOLA5
VOLA4
VOLA3
VOLA2
VOLA1
VOLA0
Reserved MCLKDIV Reserved
0
0
0
0
0
0
0
0
MUTEB
VOLB6
VOLB5
VOLB4
VOLB3
VOLB2
VOLB1
VOLB0
0
0
0
0
0
0
0
0
DS298F5
CS4341
6. REGISTER DESCRIPTION
NOTE: All registers are read/write in I²C Mode and write only in SPI mode, unless otherwise stated.
6.1
MCLK CONTROL (ADDRESS 00H)
7
Reserved
0
6
Reserved
0
5
Reserved
0
4
Reserved
0
3
Reserved
0
2
Reserved
0
1
MCLKDIV
0
0
Reserved
0
6.1.1 MCLK DIVIDE-BY-2 (MCLKDIV) BIT 1
Default = 0
0 - Disabled
1 - Enabled
Function:
The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2.
6.2
MODE CONTROL (ADDRESS 01H)
7
AMUTE
1
6
DIF2
0
5
DIF1
0
4
DIF0
0
3
DEM1
0
2
DEM0
0
1
POR
1
0
PDN
1
6.2.1 AUTO-MUTE (AMUTE) BIT 7
Default = 1
0 - Disabled
1 - Enabled
Function:
The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio
samples of static 0 or -1. A single sample of non-zero data will release the mute. Detection and muting
is done independently for each channel. The quiescent voltage on the output will be retained and the
Mute Control pin will go active during the mute period. The muting function is affected, similar to volume control changes, by the Soft and Zero Cross bits in the Transition and Mixing Control (address
02h) register.
DS298F5
25
CS4341
6.2.2 DIGITAL INTERFACE FORMAT (DIF)
BIT 4-6
Default = 000 - Format 0 (I²S, up to 24-bit data, 64 x Fs Internal SCLK)
Function:
The required relationship between the Left/Right clock, serial clock and serial data is defined by the
Digital Interface Format and the options are detailed in Figures 17 through 19.
DIF2
0
0
0
0
1
1
1
1
DIF1
0
0
1
1
0
0
1
1
DIF0
0
1
0
1
0
1
0
1
DESCRIPTION
I²S, up to 24-bit data, 64Fs Internal SCLK
I²S, up to 16-bit data, 32Fs Internal SCLK
Left Justified, up to 24-bit data,
Right Justified, 24-bit data
Right Justified, 20-bit data
Right Justified, 16-bit data
Right Justified, 18-bit data
Identical to Format 1
Format
0
1
2
3
4
5
6
1
FIGURE
17
17
18
19
19
19
19
17
Table 5. Digital Interface Format
6.2.3 DE-EMPHASIS CONTROL (DEM) BIT 2-3
Default = 00
00 - Disabled
01 - 44.1 kHz
10 - 48 kHz
11 - 32 kHz
Function:
Implementation of the standard 15µs/50µs digital de-emphasis filter response, Figure 20, requires reconfiguration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 kHz sample
rates.
NOTE: De-emphasis is only available in Single-Speed Mode.
6.2.4 POPGUARD® TRANSIENT CONTROL (POR) BIT 1
Default = 1
0 - Disabled
1 - Enabled
Function:
The Popguard® Transient Control allows the quiescent voltage to slowly ramp to and from 0 volts to
the quiescent voltage during power-on or power-down. Please refer to section 4.6 for implementation
details.
6.2.5 POWER DOWN (PDN)
BIT 0
Default = 1
0 - Disabled
1 - Enabled
Function:
The device will enter a low-power state when this function is enabled. The power-down bit defaults to
‘enabled’ on power-up and must be disabled before normal operation can occur. The contents of the
control registers are retained in this mode.
26
DS298F5
CS4341
6.3
TRANSITION AND MIXING CONTROL (ADDRESS 02H)
7
A=B
0
6
SZC1
1
5
SZC0
0
4
ATAPI4
0
3
ATAPI3
1
2
ATAPI2
0
1
ATAPI1
0
0
ATAPI0
1
6.3.1 CHANNEL A VOLUME = CHANNEL B VOLUME (A = B) BIT 7
Default = 0
0 - Disabled
1 - Enabled
Function:
The AOUTA and AOUTB volume levels are independently controlled by the A and the B Channel Volume Control Bytes when this function is disabled. The volume on both AOUTA and AOUTB are determined by the A Channel Volume Control Byte and the B Channel Byte is ignored when this function
is enabled.
6.3.2 SOFT RAMP AND ZERO CROSS CONTROL (SZCX) BIT 5-6
Default = 10
00 - Immediate Changes
01 - Changes On Zero Crossings
10 - Soft Ramped Changes
11 - Soft Ramped Changes On Zero Crossings
Function:
Immediate Changes
When Immediate Changes is selected all level changes will take effect immediately in one step.
Changes On Zero Crossings
Changes on Zero Crossings dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will
occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz
sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel.
Soft Ramped Changes
Soft Ramped Changes allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1dB per 8
left/right clock periods.
Soft Ramped Changes on Zero Crossings
Soft Ramped Changes On Zero Crossings dictates that signal level changes, either by attenuation
changes or muting, will occur in 1/8 dB steps implemented on a signal zero crossing. The 1/8 dB level
change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms
at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is
independently monitored and implemented for each channel.
DS298F5
27
CS4341
6.3.3 ATAPI CHANNEL MIXING AND MUTING (ATAPI) BIT 0-4
Default = 01001 - AOUTA = Left Channel, AOUTB = Right Channel (Stereo)
Function:
The CS4341 implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to
Table 6 and Figure 25 for additional information.
ATAPI4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ATAPI3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
ATAPI2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
ATAPI1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
ATAPI0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AOUTA
MUTE
MUTE
MUTE
MUTE
aR
aR
aR
aR
aL
aL
aL
aL
a[(L+R)/2]
a[(L+R)/2]
a[(L+R)/2]
a[(L+R)/2]
MUTE
MUTE
MUTE
MUTE
aR
aR
aR
aR
aL
aL
aL
aL
aL/2
[(aL+bR)/2]
[(bL+aR)/2]
[(aL+bR)/2]
AOUTB
MUTE
bR
bL
b[(L+R)/2]
MUTE
bR
bL
b[(L+R)/2]
MUTE
bR
bL
b[(L+R)/2]
MUTE
bR
bL
b[(L+R)/2]
MUTE
bR
bL
bL/2
MUTE
bR
bL
[(aR+bL)/2]
MUTE
bR
bL
[(aL+bR)/2]
MUTE
bR
bL
[(aL+bR)/2]
Table 6. ATAPI Decode
28
DS298F5
CS4341
A Channel
Volume
Control
Left Channel
Audio Data
Σ
MUTE
AoutA
MUTE
AoutB
Σ
B Channel
Volume
Control
Right Channel
Audio Data
Figure 25. ATAPI Block Diagram
6.4
CHANNEL A VOLUME CONTROL (ADDRESS 03H)
Same as CHANNEL B Volume Control.
6.5
CHANNEL B VOLUME CONTROL (ADDRESS 04H)
7
MUTEx
0
6
VOLx6
0
6.5.1 MUTE (MUTE)
5
VOLx5
0
4
VOLx4
0
3
VOLx3
0
2
VOLx2
0
1
VOLx1
0
0
VOLx0
0
BIT 7
Default = 0
0 - Disabled
1 - Enabled
Function:
The Digital-to-Analog converter output will mute when enabled. The quiescent voltage on the output
will be retained. The muting function is affected, similar to attenuation changes, by the Soft and Zero
Cross bits in the Transition and Mixing Control (address 02h) register. The MUTEC will go active during the mute period if the Mute function is enabled for both channels.
DS298F5
29
CS4341
6.5.2 VOLUME (VOLx)
BIT 0-6
Default = 0 dB (No Attenuation)
Function:
The digital volume control allows the user to attenuate the signal in 1 dB increments from 0 to -90 dB.
Volume settings are decoded as shown in Table 7. The volume changes are implemented as dictated
by the Soft and Zero Cross bits in the Transition and Mixing Control (address 02h) register. All volume
settings less than - 94 dB are equivalent to enabling the Mute bit.
Binary Code
0000000
0010100
0101000
0111100
1011010
Decimal Value
0
20
40
60
90
Volume Setting
0 dB
-20 dB
-40 dB
-60 dB
-90 dB
Table 7. Example Digital Volume Settings
30
DS298F5
CS4341
7. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.
Dynamic Range
The ratio of the full-scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth
made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement
to full scale. This technique ensures that the distortion components are below the noise level and do not
affect the measurement. This measurement technique has been accepted by the Audio Engineering
Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter’s
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in
decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full-scale analog output for a full-scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
DS298F5
31
CS4341
8. PACKAGE DIMENSIONS
8.1
SOIC
16L SOIC (150 MIL BODY) PACKAGE DRAWING
E
H
1
b
c
D
SEATING
PLANE
∝
A
L
e
DIM
A
A1
b
C
D
E
e
H
L
∝
MIN
0.053
0.004
0.013
0.0075
0.386
0.150
0.040
0.228
0.016
0°
A1
INCHES
NOM
0.064
0.006
0.016
0.008
0.390
0.154
0.050
0.236
0.025
4°
MAX
0.069
0.010
0.020
0.010
0.394
0.157
0.060
0.244
0.050
8°
MIN
1.35
0.10
0.33
0.19
9.80
3.80
1.02
5.80
0.40
0°
MILLIMETERS
NOM
1.63
0.15
0.41
0.20
9.91
3.90
1.27
6.0
0.64
4°
MAX
1.75
0.25
0.51
0.25
10.00
4.00
1.52
6.20
1.27
8°
JEDEC #: MS-012
Controling Dimension is Millimeters
32
DS298F5
CS4341
8.2
TSSOP
16L TSSOP (4.4 mm BODY) PACKAGE DRAWING
N
D
E11
A2
E
A
∝
e
b2
A1
SIDE VIEW
L
END VIEW
SEATING
PLANE
1 2 3
TOP VIEW
DIM
A
A1
A2
b
D
E
E1
e
L
∝
MIN
-0.002
0.03346
0.00748
0.193
0.248
0.169
-0.020
0°
INCHES
NOM
-0.004
0.0354
0.0096
0.1969
0.2519
0.1732
0.026 BSC
0.024
4°
MAX
0.043
0.006
0.037
0.012
0.201
0.256
0.177
-0.028
8°
MIN
-0.05
0.85
0.19
4.90
6.30
4.30
-0.50
0°
MILLIMETERS
NOM
--0.90
0.245
5.00
6.40
4.40
0.65 BSC
0.60
4°
NOTE
MAX
1.10
0.15
0.95
0.30
5.10
6.50
4.50
-0.70
8°
2,3
1
1
JEDEC #: MO-153
Controlling Dimension is Millimeters
Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.
2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not
reduce dimension “b” by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
9. PACKAGE THERMAL RESISTANCE
Package
SOIC
TSSOP
DS298F5
(for multi-layer boards)
(for multi-layer boards)
Symbol
Min
Typ
Max
Units
θJA
θJA
-
74
89
-
°C/Watt
°C/Watt
33
CS4341
10.REFERENCES
CDB4341 Evaluation Board Datasheet
11.REVISION HISTORY
Revision
Changes
F4
Added lead-free packaging information
F5
Corrected Dimension e in TSSOP Package Drawing value for NOM Millimeters from 0.065 to 0.65
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative.
To find the one nearest to you, go to www.cirrus.com/corporate/contacts/sales.cfm
IMPORTANT NOTICE
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to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
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does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
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IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED,
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Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
I²C is a registered trademark of Philips Semiconductor.
SPI is a trademark of Motorola, Inc.
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DS298F5