CML Semiconductor Products PRODUCT INFORMATION FX621 Low-Power Subscriber Private Metering (SPM) Detector Publication D/621/2 June 1991 Provisional Issue Features/Applications Meets 12kHz and 16kHz SPM Specifications Adjustable Input Gain PABX, Payphone and Telephone Applications Low-Power CMOS [ 3.5 – 5 Volt Operation ] General-Purpose Tone Detection Tone Follower and SPM Packet Detection Modes XTAL Crystal Oscillator Stability XTAL/CLOCK V DD 4.433619 MHz OSCILLATOR V SS 4.433619 MHz V BIAS 1 SYSTEM SELECT 12/16 kHz 3 or 4 AMP INPUT ( – ) – AMP INPUT (+) "SYSTEM GAIN SET" AMPLIFIER FREQUENCY DIVIDERS + 1 AMP OUTPUT (GAIN SET) DETECTOR INPUT MODE SELECT 2 554.203 kHz or 738.937 kHz LEVEL DETECTOR FREQUENCY WINDOW DETECTOR FX621 OUTPUT RESET COUNTERS AND OUTPUT LOGIC OUTPUT PULSE LENGTH TIME SPACE LENGTH TIME Fig.1 Internal Block Diagram Brief Description The FX621 is a single-chip, low-power CMOS tone detector designed for use in both PABX and general payphone applications for Subscriber Private Metering. The Decode and Not-Decode band edges are accurately defined by the use of an external 4.433619MHz crystal. Operation to either of the 12kHz or 16kHz SPM systems is pin programmable, with system amplitude sensitivities and pulse-length timing being provided by the use of external components. The FX621 has 2 pin-selectable modes of operation: 1) Tone Follower Mode. A logic “0” is output whenever a tone of the correct frequency and length is detected. 2) SPM Packet Mode. An output is obtained only when both the mark and space timing criteria of an input SPM tone have been fulfilled. The FX621, which is available in plastic DIL and SMD packages, requires only a single 3.5-volt (min.) power supply, a 4.433619MHz crystal with external gain and timing components to meet most SPM specifications. Pin Number Function DIL FX621P Quad FX621LG/LS 1 1 Xtal/Clock: Input to the clock oscillator inverter. A single 4.433619MHz Xtal or external clock pulse input is required (see Figure 2). 2 2 VDD: The positive supply rail. A single, stable supply in the range 3.5V to 5V is required. 3 5 Detector Input: “Schmitt Trigger” level detector circuitry whose input thresholds are set internally and dependent on the applied VDD. For use with low signal-level systems this input should be preceded by the “System Gain Set” amplifier. To use this input without the “System Gain Set” amplifier, the components indicated in Figure 2 (inset) should be used with the protection diodes (D1 - D4). 4 6 Amplifier Input (+): 5 7 Amplifier Input (–): 6 8 Amplifier Output: The output of the “System Gain Set” Amplifier, is used with gain setting components. See Figures 1 and 2. 8 12 VSS: The negative supply rail, (GND). 9 13 VBIAS: The internal analogue bias pin, this point is at VDD/2 and requires to be externally decoupled to VSS via capacitor C3. 10 14 Space Length Time: Active only in the ‘SPM Packet’ mode, this input, with an external RC network, sets the minimum valid No-Tone (Space) period for the incoming packet using the formula: tS = 0.7 (R6 x C5). If the ‘SPM Packet’ mode is not required these timing components may be omitted. See Page 4. 11 17 Pulse Length Time: Active only in the ‘SPM Packet’ mode, this input, with an external RC network, sets the minimum valid Tone period for the incoming packet using the formula: tM = 0.7 (R5 x C4). If the ‘SPM Packet’ mode is not required these timing components may be omitted. See Page 4. 12 18 Output Reset: This input is used only in the ‘SPM Packet’ mode. Once an SPM packet has been detected and an output generated (logic “0”) from this device the output remains as set until this input is strobed to a logic “0.” See Figure 3. This input has an internal 1MΩ pullup resistor. 13 19 Mode Select: A control pin to select either the ‘Tone Follower’ mode or the ‘SPM Packet’ mode. A logic “1” selects ‘Tone Follower’, a logic “0” selects ‘SPM Packet.’ This input has an internal 1MΩ pullup resistor (Tone Follower). 14 20 Output: The digital output of the SPM Detector. In the ‘Tone Follower’ mode a valid tone gives a logic “0” and no-tone gives a logic “1.” Tonebursts and tone dropouts of less than 16 cycles are ignored. In the ‘SPM Packet’ mode the output is set to a logic “0” when a valid ‘packet’ is measured. The output remains as set until reset by a logic “0” at the Output Reset function, see Figure 3. 15 23 System Select: A control pin to set the device to work on either a 12kHz (logic “1”) or 16kHz (logic “0”) SPM system. This input has an internal 1MΩ pullup resistor (12kHz). 16 24 Xtal: The output of the clock oscillator inverter, see Figure 2. 7 3, 4, 9, 10, 11, 15, 16, 21, 22. The positive and negative inputs to the “System Gain Set” Amplifier. With single or differential inputs this amplifier and its external circuitry can be used to provide the extra gain required to set the device to the user’s National Level Specification. External diodes are used at both inputs (if in use) to provide protection when the line input level exceeds the supply rails (above the Absolute Maximum Rating). If this device is used without this amplifier, the protection diodes should be employed at the Detector Input. See Figure 2. No internal connection – leave open circuit. 2 Application Information The notes on these pages are intended to assist in calculating the external components required to operate the FX621 as an SPM Detector. DETECTOR INPUT VDD FX621P PIN No. X1 3 C9 XTAL XTAL/CLOCK R7 V BIAS VBIAS V DD INSET D2 D1 C1 DETECTOR INPUT R1 AMP INPUT (+) R2 R3 AMP OUTPUT C7 V SS D4 2 15 3 14 13 FX621P 5 x D3 16 4 AMP INPUT (-) C2 1 12 6 11 7 10 8 9 R5 SYSTEM SELECT OUTPUT MODE SELECT OUTPUT RESET C6 PULSE LENGTH SPACE LENGTH V BIAS R4 V BIAS R6 C4 C3 C5 C8 (a) Differential Input Configuration V SS Component References Component Reference Component R1 Note 4 C1 R2 Note 4 C2 R3 390kΩ ± 1.0% C3 R4 390kΩ ± 1.0% C4 R5 Note 5 C5 R6 Note 5 C6 R7 1.0MΩ C7 D1 to D4 1N4148 or equivalent C8 (small signal type) C9 X1 4.433619MHz V BIAS Reference Note 4 Note 4 1.0µF ± 20% Note 5 Note 5 1.0µF ± 20% 12.0pF ± 10.0% 12.0pF ± 10.0% 0.1µF ± 10.0% C7 D1 R3 "SYSTEM GAIN SET" AMPLIFIER 5 C2 6 R2 D3 + 4 V BIAS 3 AMP DETECTOR OUTPUT INPUT C3 V SS (b) Single Input Configuration Fig.2 Recommended External Components Gain Component Calculations (1) Calculate the FX621 sensitivity. (4) Calculate the gain/attenuation components for the chosen gain. Device Sensitivity – at the Detector Input (Figure 1) is dependent upon the VDD value and is calculated as: Device Sensitivity ≈ 0.2 x VDD Gain Components – for a differential input: R1 = R2 R3 = R4 (Vrms) 2 x √2 Gain = (2) Ascertain the required National {Minimum WillDecode} and [Maximum Will-Not Decode] Levels. C8 = C7 C1 = C2 ZFeedback (R4 //X(C8)) ZInput (R1 + X(C1)) This calculation approximates as: R1 ≈ (3) Calculate the acceptable range of required Gain/ Attenuation for the levels in Note 2, using the “System Gain Set” amplifier. 1.2 x (selected gain) and The gain requirement is calculated as : R4 C1 ≈ 1 2π x R1 x 6.0kHz [Max] / {Min} Gain [or] = Device Sensitivity – using the nearest preferred value components. The values of R1 and C1 have been calculated to give a highpass cut-off between the audio and SPM tone frequencies, approximately 6kHz. C7 and C8 are anti-alias components and are calculated for an approximate cut-off frequency of 32kHz. { Minimum Will-Decode Level } [ Maximum Will-Not Decode Level ] Choose a gain figure that meets both level requirements. 3 Application Information ...... (5) (6) Timing Components In the ‘SPM Packet’ mode R5 and C4 set the minimum 'Tone' period (tM), R6 and C5 set the minimum 'Space' period (tS), and are calculated as follows: tM = 0.7(R5 x C4). Protection Diodes As most telephone systems operate at voltages in excess of the Absolute Maximum Limits for damage, diodes D1 – D4 are essential for device protection. tS = 0.7(R6 x C5). When calculating Tone and Space time settings the following points should be taken into consideration: (7) (1) (2) (3) Response and De-response times tR and tD. Component tolerances can alter the calculation. The MINIMUM expected pulse/space length must be catered for. Component Tolerances The tolerances of external components used with this device are dependent upon the required accuracy of the gain and pulse period timings. Timing Figure 3 shows the FX621 output timing – Timing value limits are given on the “Specification” page. Note – There is no reaction to pulses or drop-outs of less than the valid Response or De-response time. TONE FOLLOWER MODE TONE INPUT NOTE tD tR NOTE tR tD OUTPUT SPM PACKET MODE TONE INPUT tR tD tM tR tS OUTPUT OUTPUT RESET t RESET Fig.3 Output Timing Example Values – for the FX621 to operate with the West German (16kHz) 'FTZ' Specification. (a) Min. 'Will Decode' Level = 71.3 mV rms (b) Max. 'Will Decode' Level = 10.0 V rms (c) Max. 'Will-Not Decode' Level = 34.6 mVrms (d) Device Sensitivity @ 3.5V VDD ≈ 248.0 mVrms Min. Gain Required (d÷a) ≈ 3.47 Max. Gain Allowed (d÷c) ≈ 7.17 = 4.7 Chosen Gain Figure For a chosen gain figure of 4.7, a minimum Tone length of 80ms, a minimum Space length of 135ms and a VDD of 3.5V, the required component values are : R1 R2 R3 R4 R5 R6 68kΩ 68kΩ 390kΩ 390kΩ 100kΩ 120kΩ X1 4.433619MHz Tolerances: 4 C1 C2 C3 C4 C5 C6 C7 C8 330pF 330pF 1.0µF 820nF 1.0µF 1.0µF 12pF 12pF Resistors = ±1%. Capacitors = ±10%. Specification Absolute Maximum Ratings Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits is not implied. Supply Voltage Input Voltage at any pin (ref VSS = 0V) Sink/source current (supply pins) (other pins) Total device dissipation @ TAMB 25°C Derating -0.3 to 7.0V -0.3 to (VDD + 0.3V) ± 30mA ± 20mA 800mW Max. 10mW/°C Operating temperature range: FX621P/LG/LS -30°C to + 70°C Storage temperature range: FX621P/LG/LS -40°C to + 85°C Operating Limits All device characteristics are measured under the following conditions unless otherwise specified : VDD = 3.5V TAMB = 25°C Xtal/Clock fC = 4.433619MHz Audio level 0dB ref = 775mV rms Characteristics Static Values Supply Voltage (VDD) Supply Current (IDD) Input Logic “1” Input Logic “0” Output Logic “1” Output Logic “0” Impedances "Gain Set" Amplifier Input "Gain Set" Amplifier Output Analogue Detector Input Digital Inputs Digital Output Dynamic Values Sensitivity Required Signal to Noise Ratio Upper Detector Threshold Lower Detector Threshold Amplifier Input Offset Xtal Oscillator Frequency Frequency Discrimination 'Will-Decode' Frequency Limits 'Will-Not Decode' Frequency Limits Timing Information – Fig.3 Valid Tone Burst Length (tM) Valid Space Length (tS) Tone Response Time (tR) De-response Time (tD) SPM Output Reset Time (tRESET) Notes System See Note 12kHz/16kHz 1, 2 7 2 2 12kHz 16kHz 12kHz 12kHz 16kHz 16kHz 12/16kHz 12/16kHz 12kHz 16kHz 12kHz 16kHz 12/16kHz 3, 4 4 5, 7 5, 7 6, 7 6, 7 4 1. 2. 3. 4. Min. Typ. Max. Unit 3.5 – 70.0 0 80.0 – – 1.0 – – – – 5.0 1.4 100 30.0 – 20.0 V mA % VDD % VDD % VDD % VDD 1.0 – 1.0 0.5 – – – – 1.0 – – 10.0 – – 10.0 MΩ kΩ MΩ MΩ kΩ – – 2.06 1.36 – 248 45.0 2.1 1.4 15.0 4.433619 – – 2.14 1.44 – mVrms dB V V mV MHz 11.82 15.76 0 12.48 0 16.64 – – – – – – 12.18 16.24 11.52 – 15.36 – kHz kHz kHz kHz kHz kHz 16.0 5.0 – – – – 150.0 – – 1.7 1.2 1.7 1.2 – – – 3.0 2.0 3.0 2.0 – cycles ms ms ms ms ms ns Device sensitivity at the Detector Input pin, or using the 'Gain Set' Amplifier at unity. These values are quoted at 3.5 volt VDD, any supply variation will alter levels accordingly. Tone Follower mode. SPM Packet mode, in this mode the minimum valid Pulse (Space) length is programmable by means of an RC network on the Pulse (Space) Length Time pin. If no RC network is used, the minimum valid tone length reverts to 16 cycles. 5. The time for the circuit to recognize a valid 'Tone' in the Tone Follower mode. 6. The time for the circuit to recognize a valid 'No Tone' in the Tone Follower mode. 7. The FX621 is a low-power zero crossing detector without on-chip filtering, for use with a good Signal-to-Noise ratio. The FX611 is recommended for high noise environments. If the supply current requirement of the FX611 is unacceptable, separate external filters should be employed with the FX621. 5 Package Outlines Handling Precautions The FX621 is available in the package styles outlined below. Mechanical package diagrams and specifications are detailed in Section 10 of this document. Pin 1 identification marking is shown on the relevant diagram and pins on all package styles number anti-clockwise when viewed from the top. The FX621 is a CMOS LSI circuit which includes input protection. However precautions should be taken to prevent static discharges which may cause damage. FX621P 16-pin DIL Package FX621LG 24-pin Package NOT TO SCALE NOT TO SCALE Max. Body Length Max. Body Width Max. Body Length Max. Body Width 10.49mm 7.59mm 10.25mm 10.25mm FX621LS 24-lead Package Ordering Information FX621P FX621LG FX621LS 16-pin plastic DIL 24-pin quad plastic encapsulated bent and cropped 24-lead plastic leaded chip carrier NOT TO SCALE Max. Body Length Max. Body Width CML does not assume any responsibility for the use of any circuitry described. No circuit patent licences are implied and CML reserves the right at any time without notice to change the said circuitry. 10.40mm 10.40mm CML Microcircuits COMMUNICATION SEMICONDUCTORS CML Product Data In the process of creating a more global image, the three standard product semiconductor companies of CML Microsystems Plc (Consumer Microcircuits Limited (UK), MX-COM, Inc (USA) and CML Microcircuits (Singapore) Pte Ltd) have undergone name changes and, whilst maintaining their separate new names (CML Microcircuits (UK) Ltd, CML Microcircuits (USA) Inc and CML Microcircuits (Singapore) Pte Ltd), now operate under the single title CML Microcircuits. These companies are all 100% owned operating companies of the CML Microsystems Plc Group and these changes are purely changes of name and do not change any underlying legal entities and hence will have no effect on any agreements or contacts currently in force. CML Microcircuits Product Prefix Codes Until the latter part of 1996, the differentiator between products manufactured and sold from MXCOM, Inc. and Consumer Microcircuits Limited were denoted by the prefixes MX and FX respectively. These products use the same silicon etc. and today still carry the same prefixes. In the latter part of 1996, both companies adopted the common prefix: CMX. This notification is relevant product information to which it is attached. Company contact information is as below: CML Microcircuits (UK)Ltd CML Microcircuits (USA) Inc. CML Microcircuits (Singapore)PteLtd COMMUNICATION SEMICONDUCTORS COMMUNICATION SEMICONDUCTORS COMMUNICATION SEMICONDUCTORS Oval Park, Langford, Maldon, Essex, CM9 6WG, England Tel: +44 (0)1621 875500 Fax: +44 (0)1621 875600 [email protected] www.cmlmicro.com 4800 Bethania Station Road, Winston-Salem, NC 27105, USA Tel: +1 336 744 5050, 0800 638 5577 Fax: +1 336 744 5054 [email protected] www.cmlmicro.com No 2 Kallang Pudding Road, 09-05/ 06 Mactech Industrial Building, Singapore 349307 Tel: +65 7450426 Fax: +65 7452917 [email protected] www.cmlmicro.com D/CML (D)/1 February 2002