TI ADS61B23

ADS61B23
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SLAS582 – FEBRUARY 2008
12-BIT, 80-MSPS ADC WITH BUFFERED ANALOG INPUTS
FEATURES
1
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Maximum Sample Rate: 80 MSPS
12-bit Resolution with No Missing Codes
Buffered Analog Inputs with
– Very Low Input Capacitance (< 2 pF)
– High DC Resistance (5 kΩ)
82 dBc SFDR and 70 dBFS SNR
(-1 dBFS or 1.8 Vpp input)
85 dBc SFDR (-6 dBFS or 1 Vpp input)
3.5 dB Coarse Gain and up to 6 dB
Programmable Fine Gain for SNR and SFDR
Trade-Off
Parallel CMOS and Double Data Rate (DDR)
LVDS Output Options
Supports Sine, LVCMOS, LVPECL, LVDS Clock
Inputs and Clock Amplitude Down to 400 mVPP
Clock Duty Cycle Stabilizer
Internal Reference with Support for External
Reference
External Decoupling Eliminated for References
Programmable Output Clock Position and
Drive Strength to Ease Data Capture
3.3 V Analog and 1.8 V to 3.3 V Digital Supply
32-pin QFN Package (5 mm × 5 mm)
Pin Compatible 12-Bit Family (ADS612X)
Temperature range –40°C to 85°C
DESCRIPTION
ADS61B23 is a 12-bit A/D converter (ADC) with a
maximum sampling frequency of 80 MSPS. It
combines high performance and low power
consumption in a compact 32-QFN package. The
analog inputs use buffers to isolate the switching
transients of the internal sample & hold from the
external driving circuit. The buffered inputs present
very low input capacitance (< 2pF) & wide bandwidth.
This makes it easy to drive them at high input
frequencies, compared to an ADC without the input
buffers.
ADS61B23 has coarse and fine gain options that are
used to improve SFDR performance at lower
full-scale analog input ranges.
The digital data outputs are parallel CMOS or DDR
LVDS (Double Data Rate). Several features exist to
ease data capture—controls for output clock position
and output buffer drive strength, plus LVDS current
and internal termination programmability.
The output interface type, gain, and other functions
are programmed using a 3-wire serial interface.
Alternatively, some of these functions are configured
using dedicated parallel pins so the device starts in
the desired state after power-up.
ADS61B23 includes internal references, while
eliminating the traditional reference pins and
associated external decoupling. External reference
mode is also supported.
APPLICATIONS
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Wireless Communications Infrastructure
Software Defined Radio
Power Amplifier Linearization
802.16d/e
Test and Measurement Instrumentation
High Definition Video
Medical Imaging
Radar Systems
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
ADS61B23
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SLAS582 – FEBRUARY 2008
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
CLKP
DRGND
DRVDD
AGND
AVDD
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
CLOCKGEN
CLKM
CLKOUT
D0
D1
Analog
Buffer
D2
D3
INP
SHA
D4
Digital
Encoder
and
Serializer
12-Bit
ADC
INM
CMOS
Output
Buffer
D5
D6
D7
D8
D9
D10
D11
VCM
Reference
Control
Interface
RESET
SEN
SDATA
SCLK
ADS61B23
CMOS Mode
B0290-01
2
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PACKAGE/ORDERING INFORMATION (1)
PRODUCT
PACKAGELEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ADS61B23
QFN-32 (2)
RHB
–40°C to 85°C
AZ61B23
(1)
(2)
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
ADS61B23IRHBT
Tape and Reel, 250
ADS61B23IRHBR
Tape and Reel, 3000
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
For thermal pad size on the package, see the mechanical drawings at the end of this data sheet. θJA = 34 °C/W (0 LFM air flow),
θJC = 30 °C/W when used with 2 oz. copper trace and pad soldered directly to a JEDEC standard four layer 3 in × 3 in (7.62 cm ×
7.62 cm) PCB.
ABSOLUTE MAXIMUM RATINGS (1)
VI
VALUE
UNIT
Supply voltage range, AVDD
–0.3 to 3.9
V
Supply voltage range, DRVDD
–0.3 to 3.9
V
Voltage between AGND and DRGND
–0.3 to 0.3
V
Voltage between AVDD to DRVDD
–0.3 to 3.3
V
Voltage applied to VCM pin (in external reference mode)
Voltage applied to analog input pins, INP and INM
Voltage applied to analog input pins, CLKP and CLKM
–0.3 to 2
V
–0.3 to minimum ( 3.6, AVDD + 0.3)
V
–0.3 to (AVDD + 0.3)
V
TA
Operating free-air temperature range
–40 to 85
°C
TJ
Operating junction temperature range
125
°C
Tstg
Storage temperature range
–65 to 150
°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
3
3.3
3.6
V
1.65
1.8 to 3.3
3.6
V
3
3.3
3.6
V
1.45
1.5
SUPPLIES
AVDD
Analog supply voltage
CMOS Interface
DRVDD Output buffer supply voltage
LVDS Interface
ANALOG INPUTS
Differential input voltage range
2
Voltage applied on VCM in external reference mode
Vpp
1.55
V
CLOCK INPUT
FS
Input clock sample rate
1
Sine wave, ac-coupled
0.4
LVPECL, ac-coupled
Input clock amplitude differential
(VCLKP – VCLKM)
± 0.8
LVDS, ac-coupled
MSPS
Vpp
± 0.35
LVCMOS, ac-coupled
Input Clock duty cycle
80
1.5
3.3
35%
50%
65%
DIGITAL OUTPUTS
Output buffer drive strength
(1)
For CLOAD ≤ 5 pF and DRVDD ≥ 2.2
V
DEFAULT
strength
For CLOAD > 5 pF and DRVDD ≥ 2.2
V
MAXIMUM
strength
For DRVDD < 2.2 V
MAXIMUM
strength
CMOS Interface, maximum buffer
strength
CLOAD
Maximum external load capacitance from each
output pin to DRGND
10
LVDS Interface, without internal
termination
5
LVDS Interface, with internal
termination
RLOAD
Differential load resistance (external) between the LVDS output pairs
TA
Operating free-air temperature
(1)
4
pF
10
Ω
100
-40
85
°C
See Output Buffer Strength Programmability in application section
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ELECTRICAL CHARACTERISTICS
Typical values are specified at 25°C, AVDD= 3.3 V, DRVDD=1.8 to 3.3 V, sampling frequency = 80 MSPS, –1 dBFS
differential analog input (1.8Vpp) , internal reference mode & apply to CMOS and LVDS interfaces, unless otherwise noted.
Min and max values are specified across the full temperature range TMIN = –40°C to TMAX = 85°C at AVDD = 3.3 V, DRVDD =
3.3 V.
ADS61B23
FS = 80 MSPS
PARAMETER
MIN
RESOLUTION
TYP
UNIT
MAX
12
Bits
Differential input voltage range
2
VPP
Input resistance from each input pin to ground (at dc)
see Figure 32
5
kΩ
<2
pF
ANALOG INPUT
Input capacitance from each input pin to ground
see Figure 33
Analog input bandwidth
> 800
MHz
REFERENCE VOLTAGES
VREFB
Internal reference bottom voltage
1
VREFT
Internal reference top voltage
2
ΔVREF
Internal reference error (VREFT–VREFB)
–20
V
V
±5
20
mV
DC ACCURACY
No missing codes
EO
Specified
Offset error
–10
Offset error temperature coefficient
±2
10
0.05
mV
mV/°C
There are two sources of gain error – internal reference inaccuracy and channel gain error
EGREF
Gain error due to internal reference inaccuracy alone, (ΔVREF) %
–2
0.25
2
EGCHAN
Gain error of channel alone (1)
–1
± 0.3
1
Channel gain error temperature coefficient
DNL
Differential non-linearity
INL
Integral non-linearity
% FS
% FS
Δ%/°C
0.005
–0.75
± 0.5
2
LSB
–3
±1
3
LSB
POWER SUPPLY
IAVDD
Analog supply current
104
mA
IDRVDD
Digital supply current, CMOS interface
DRVDD = 1.8V
No load capacitance, FIN= 2 MHZ (2)
4.5
mA
IDRVDD
Digital supply current, LVDS interface
DRVDD = 3.3V
With 100 Ω external termination
42
mA
(1)
(2)
Total power, CMOS
351
475
mW
Global power down
30
60
mW
This is specified by design and characterization; it is not tested in production.
In CMOS mode, the DRVDD current scales with the sampling frequency and the load capacitance on output pins (see Figure 26).
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ELECTRICAL CHARACTERISTICS
Typical values are specified at 25°C, AVDD= 3.3 V, DRVDD=1.8 to 3.3 V, sampling frequency = 80 MSPS, 50% clock duty
cycle, –1 dBFS differential analog input (1.8Vpp) , internal reference mode & apply to CMOS and LVDS interfaces, unless
otherwise noted.
Min and max values are specified across the full temperature range TMIN = –40°C to TMAX = 85°C at AVDD = 3.3 V & DRVDD
= 3.3 V.
PARAMETER
TEST CONDITIONS
ADS61B23
FS = 80 MSPS
MIN
TYP
UNIT
MAX
DYNAMIC AC CHARACTERISTICS
Fin = 10 MHz
70.2
Fin = 50 MHz
68.5
Fin = 70 MHz
SNR
Signal to noise ratio
Fin = 100 MHz
Fin = 130 MHz
0 dB Gain
69.7
3.5 dB Coarse gain
68.7
0 dB Gain
69.5
3.5 dB Coarse gain
68.4
Fin = 10 MHz
68
Fin = 70 MHz
Fin = 100 MHz
Fin = 130 MHz
ENOB
Effective number of bits
69.3
69.2
3.5 dB Coarse gain
68.4
0 dB Gain
67
3.5 dB Coarse gain
68
Fin = 50 MHz
11
78
Fin = 70 MHz
Fin = 130 MHz
SFDR
Spurious free dynamic range
(-6 dBFS or 1Vpp input)
78
82
3.5 dB Coarse gain
87
0 dB Gain
71
3.5 dB Coarse gain
77
Fin = 10 MHz
87
Fin = 50 MHz
85
Fin = 70 MHz
85
Fin = 100 MHz
85
Fin = 130 MHz
78
75
Fin = 70 MHz
Fin = 130 MHz
THD
Total harmonic distortion
(-6 dBFS or 1Vpp input)
6
dBc
dBc
80
Fin = 50 MHz
Fin = 100 MHz
Bits
82
0 dB Gain
Fin = 10 MHz
THD
Total harmonic distortion
11.3
dBFS
82
Fin = 50 MHz
Fin = 100 MHz
69.7
0 dB Gain
Fin = 10 MHz
SFDR
Spurious free dynamic range
dBFS
69.8
Fin = 50 MHz
SINAD
Signal to noise and distortion ratio
70
69.9
80
75
0 dB Gain
79
3.5 dB Coarse gain
83
0 dB Gain
69
3.5 dB Coarse gain
75
Fin = 10 MHz
85
Fin = 50 MHz
82
Fin = 70 MHz
83
Fin = 100 MHz
82
Fin = 130 MHz
76
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dBc
dBc
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ELECTRICAL CHARACTERISTICS (continued)
Typical values are specified at 25°C, AVDD= 3.3 V, DRVDD=1.8 to 3.3 V, sampling frequency = 80 MSPS, 50% clock duty
cycle, –1 dBFS differential analog input (1.8Vpp) , internal reference mode & apply to CMOS and LVDS interfaces, unless
otherwise noted.
Min and max values are specified across the full temperature range TMIN = –40°C to TMAX = 85°C at AVDD = 3.3 V & DRVDD
= 3.3 V.
PARAMETER
ADS61B23
FS = 80 MSPS
TEST CONDITIONS
MIN
Fin = 10 MHz
78
Fin = 70 MHz
Fin = 100 MHz
0 dB Gain
86
3.5 dB Coarse gain
88
0 dB Gain
86
3.5 dB Coarse gain
88
Fin = 10 MHz
dBc
82
Fin = 50 MHz
78
Fin = 70 MHz
82
78
Fin = 100 MHz
Fin = 130 MHz
Worst spur (Other than HD2, HD3)
88
86
Fin = 130 MHz
HD3
Third harmonic distortion
UNIT
MAX
90
Fin = 50 MHz
HD2
Second harmonic distortion
TYP
0 dB Gain
82
3.5 dB Coarse gain
87
0 dB Gain
71
3.5 dB Coarse gain
77
Fin = 10 MHz
95
Fin = 50 MHz
94
Fin = 70 MHz
94
Fin = 100 MHz
92
dBc
dBc
Fin = 130 MHz
92
IMD
2-Tone intermodulation distortion
F1 = 46 MHz, F2 = 50 MHz
Each tone at -7 dBFS
85
dBFS
Input overload recovery
Recovery to within 1% (of final value) for 6-dB overload with sine wave input
1
clock cycles
PSRR
AC Power supply rejection ratio
For 100 mVpp signal on AVDD supply
35
dBc
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DIGITAL CHARACTERISTICS (1)
The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1 with AVDD = 3.0 to 3.6 V.
PARAMETER
TEST CONDITIONS
ADS61B23
MIN
TYP MAX
UNIT
DIGITAL INPUTS
High-level input voltage
2.4
V
Low-level input voltage
0.8
V
High-level input current
33
µA
Low-level input current
–33
µA
4
pF
DRV
DD
V
0
V
2
pF
High-level output voltage
1375
mV
Low-level output voltage
1025
mV
Input capacitance
DIGITAL OUTPUTS – CMOS INTERFACE, DRVDD = 1.65 to 3.6 V
High-level output voltage
Low-level output voltage
Output capacitance
Output capacitance inside the device, from each output to
ground
DIGITAL OUTPUTS – LVDS INTERFACE, DRVDD = 3.0 V to 3.6 V, IO = 3.5 mA, RL = 100 Ω
(2)
Output differential voltage, |VOD|
225
VOS Output offset voltage, single-ended
Common-mode voltage of OUTP, OUTM
Output capacitance
Output capacitance inside the device, from either output to
ground
(1)
(2)
8
350
mV
1200
mV
2
pF
All LVDS and CMOS specifications are characterized, but not tested at production.
IO Refers to the LVDS buffer current setting, RL is the differential load resistance between the LVDS output pair.
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TIMING CHARACTERISTICS – LVDS AND CMOS MODES (1)
Typical values are specified at 25°C, AVDD= 3.3 V, sampling frequency = 80 MSPS, 50% clock duty cycle, sine wave input
clock, 1.5 VPP clock amplitude, CL = 5 pF (2), IO = 3.5 mA, RL = 100 Ω (3), no internal termination & apply to CMOS and LVDS
interfaces, unless otherwise noted.
Min and max values are specified across the full temperature range TMIN = –40°C to TMAX = 85°C for AVDD = 3.0 to 3.6 V,
unless otherwise noted.
For timings at lower sampling frequencies, see the APPLICATION INFORMATION section of this data sheet.
PARAMETER
ADS61B23
FS = 80 MSPS
TEST CONDITIONS
MIN
ta
Aperture delay
tj
Aperture jitter
0.7
UNIT
TYP
MAX
1.5
2.5
150
Wake-up time
(to valid data)
ns
fs rms
From global power down
15
50
µs
From standby
15
50
µs
CMOS
100
200
ns
LVDS
200
500
From output buffer
disable
Latency
9
ns
clock cycles
DDR LVDS MODE (4), DRVDD = 3.0 to 3.6 V
tsu
Data setup time (5)
Data valid
3.9
4.5
ns
th
Data hold time (5)
Zero-cross of CLKOUTP to data becoming invalid (6)
(6)
0.7
1.7
ns
tPDI
Clock propagation delay
Input clock rising edge zero-cross to output clock rising edge
zero-cross
4.3
5.8
7.3
LVDS bit clock duty cycle
Duty cycle of differential clock, (CLKOUTP-CLKOUTM)
10 ≤ Fs ≤ 125 MSPS
40%
47%
55%
tr
tf
Data rise time,
Data fall time
Rise time measured from –50 mV to 50 mV
Fall time measured from 50 mV to –50 mV
1 ≤ Fs ≤ 125 MSPS
70
100
170
ps
tCLKRISE
tCLKFALL
Output clock rise time,
Output clock fall time
Rise time measured from –50 mV to 50 mV
Fall time measured from 50 mV to –50 mV
1 ≤ Fs ≤ 125 MSPS
70
100
170
ps
to zero-cross of CLKOUTP
PARALLEL CMOS MODE, DRVDD = 2.5 V to 3.6 V, default output buffer drive strength
(5)
(7)
tsu
Data setup time
to 50% of CLKOUT rising edge
4.3
5.8
th
Data hold time (5)
50% of CLKOUT Rising edge to data becoming invalid (8)
3.0
4.2
tPDI
Clock propagation delay
Input clock rising edge zero-cross to 50% of CLKOUT rising edge
5
6.5
7.9
Output clock duty cycle
Duty cycle of output clock (CLKOUT)
10 ≤ Fs ≤ 125 MSPS
45%
50%
55%
tr
tf
Data rise time,
Data fall time
Rise time measured from 20% to 80% of DRVDD
Fall time measured from 80% to 20% of DRVDD
1 ≤ Fs ≤ 125 MSPS
0.8
1.5
2.4
ns
tCLKRISE
tCLKFALL
Output clock rise time,
Output clock fall time
Rise time measured from 20% to 80% of DRVDD
Fall time measured from 80% to 20% of DRVDD
1 ≤ Fs ≤ 125 MSPS
0.8
1.5
2.4
ns
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Data valid
(8)
ns
ns
ns
ns
Timing parameters are specified by design and characterization and not tested in production.
CL is the Effective external single-ended load capacitance between each output pin and ground.
IO Refers to the LVDS buffer current setting; RL is the differential load resistance between the LVDS output pair.
Measurements are done with a transmission line of 100 Ω characteristic impedance between the device and the load.
Setup and hold time specifications take into account the effect of jitter on the output data and clock.
Data valid refers to logic high of +100 mV and logic low of –100 mV.
For DRVDD < 2.2V, it is recommended to use external clock for data capture and NOT the device output clock signal (CLKOUT). See
Parallel CMOS interface in the APPLICATION INFORMATION section
Data valid refers to logic high of 2V (1.7V) and logic low of 0.8 V (0.7V) for DRVDD = 3.3V (2.5V).
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Table 1. Timing Characteristics at Lower Sampling Frequencies
Fs, MSPS
tsu DATA SETUP TIME, ns
MIN
TYP
MAX
th DATA HOLD TIME, ns
MIN
TYP
(1) (2)
tPDI CLOCK PROPAGATION DELAY, ns
MAX
MIN
TYP
MAX
5
6.5
7.9
CMOS INTERFACE, DRVDD = 2.5 V to 3.6 V
65
5.1
6.6
3.8
5
40
6.5
8
5.3
6.5
20
11.3
12.8
10
11.2
10
23
25
21
23
0.7
1.7
DDR LVDS INTERFACE, DRVDD = 3.0 V to 3.6 V
(1)
(2)
10
65
5.4
6
4.3
5.8
7.3
40
10.2
10.8
4.3
5.8
7.3
20
22
23
4.5
6.5
8.5
10
47
48
4.5
6.5
8.5
Timing parameters are specified by design and characterization and not tested in production.
Timings are specified with default output buffer drive strength and CL= 5 pF.
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N+4
N+3
N+2
N+12
N+11
N+10
N+1
Sample
N
N+9
Input
Signal
ta
CLKP
Input
Clock
CLKM
CLKOUTM
CLKOUTP
tsu
DDR
LVDS
Output Data
DXP, DXM
E
E
O
E – Even Bits D0,D2,D4,D6,D8,D10
O – Odd Bits D1,D3,D5,D7,D9,D11
O
N–9
E
E
O
N–8
O
E
N–7
tPDI
th
9 Clock Cycles
O
E
N–6
O
N–5
E
O
E
E
O
N
N–1
E
O
O
N+2
N+1
tPDI
CLKOUT
tsu
Parallel
CMOS
9 Clock Cycles
Output Data
D0–D11
N–8
N–9
N–7
th
N–6
N–5
N–1
N
N+1
N+2
Figure 1. Latency
Input
Clock
CLKM
CLKM
Input
Clock
CLKP
CLKP
tPDI
Output
Clock
tPDI
CLKOUTM
Output
Clock
CLKOUTP
CLKOUT
tsu
th
tsu
th
th
tsu
Output
Data Pair
(1)
(2)
Dn
Dn_Dn+1_P,
Dn_Dn+1_M
Dn
(1)
Dn+1
(2)
Output
Data
Dn
Dn
(1)
– Bits D0, D2, D4, D6, D8, D10
Dn+1 – Bits D1, D3, D5, D7, D9, D11
(1)
Dn – Bits D0–D11
Figure 3. CMOS Mode Timing
Figure 2. LVDS Mode Timing
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DEVICE PROGRAMMING MODES
ADS61B23 has several features that can be easily configured using a parallel interface control or serial interface
programming.
USING SERIAL INTERFACE PROGRAMMING ONLY
To program using the serial interface, the internal registers must first be reset to their default values, and the
RESET pin must be kept low. In this mode, SEN, SDATA, and SCLK function as serial interface pins and are
used to access the internal registers of ADC. The registers are reset either by applying a pulse on the RESET
pin, or by a high setting on the <RST> bit (D4 in register 0x00). The Serial Interface section describes register
programming and register reset in more detail.
USING PARALLEL INTERFACE CONTROL ONLY
To control the device using parallel interface, keep RESET tied to high (AVDD). Now, SEN, SCLK, SDATA and
PDN function as parallel interface control pins. These pins can be used to directly control certain modes of the
ADC by connecting them to the correct voltage levels (as described in Table 2 to Table 4). There is no need to
apply a reset pulse.
Frequently used functions are controlled in this mode—standby, selection between LVDS/CMOS output format,
internal/external reference, and 2s complement/straight binary output format. Table 2(SCLK Control Pin),
Table 3(SEN Control Pin), and Table 4(SDATA, PDN Control Pin) describe the modes controlled by the parallel
pins.
AVDD
(5/8) AVDD
3R
(5/8) AVDD
GND
2R
AVDD
(3/8) AVDD
(3/8) AVDD
3R
To Parallel Pin
(SCLK, SDATA, SEN)
GND
Figure 4. Simple Scheme to Configure Parallel Pins
DESCRIPTION OF PARALLEL PINS
Table 2. SCLK Control Pin
SCLK
DESCRIPTION
0
Internal reference and 0 dB gain (Full-scale = 2 VPP)
(3/8) AVDD
External reference and 0 dB gain (Full-scale = 2 VPP)
(5/8) AVDD
External reference and 3.5 dB coarse gain (Full-scale = 1.34 VPP)
AVDD
Internal reference and 3.5 dB coarse gain (Full-scale = 1.34 VPP)
Table 3. SEN Control Pin
SEN
2s Complement format and DDR LVDS interface
(3/8) AVDD
Straight binary format and DDR LVDS interface
(5/8) AVDD
Straight binary and parallel CMOS interface
AVDD
12
DESCRIPTION
0
2s Complement format and parallel CMOS interface
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Table 4. SDATA, PDN Control Pins
SDATA
PDN
DESCRIPTION
Low
Low
Low
High (AVDD)
Normal operation
High (AVDD)
Low
High (AVDD)
High (AVDD)
Standby - only the ADC is powered down
Output buffers are powered down, fast wake-up time
Global power down. ADC, internal reference and output buffers are powered down, slow wake-up time
SERIAL INTERFACE
The ADC has a set of internal registers, which can be accessed through the serial interface formed by pins SEN
(Serial interface Enable), SCLK (Serial Interface Clock), SDATA (Serial Interface Data) and RESET. After device
start, the internal registers must be reset to the default values by applying a high-going pulse on RESET (width
greater than 10 ns).
Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge
of SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edge
when SEN is low. If the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data is loaded in
multiples of 16-bit words within a single active SEN pulse.
The first 5 bits form the register address and the remaining 11 bits form the register data.
The interface can work with SCLK frequency from 20 MHz down to very low speeds (few Hertz) and also with
non-50% SCLK duty cycle.
REGISTER ADDRESS
SDATA
A4
A3
A2
A1
REGISTER DATA
A0
D10
D9
D8
D7
D6
D5
D4
tDSU
tSCLK
D3
D2
D1
D0
tDH
SCLK
tSLOADH
SEN
tSLOADS
RESET
Figure 5. Serial Interface Timing Diagram
REGISTER INITIALIZATION
After power application, internal registers must be reset to the default values. This is done using one of these
methods:
1. Use a hardware reset by applying a high-going pulse on RESET pin (of width greater than 10 ns) as shown
in Figure 5.
or
2. Apply a software reset. Using the serial interface, set the <RST> bit (D4 in register 0x00) to high. This
initializes the internal registers to their default values and then self-resets the <RST> bit to low. In this case
the RESET pin is kept low.
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SERIAL INTERFACE TIMING
Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.0 to
3.6V, DRVDD = 1.65 to 3.6V (unless otherwise noted)
MIN
TYP MAX
UNIT
> DC
20
MHz
fSCLK
SCLK Frequency = 1/tSCLK
tSLOADS
SEN to SCLK Setup time
25
ns
tSLOADH
SCLK to SEN Hold time
25
ns
tDSU
SDATA Setup time
25
ns
tDH
SDATA Hold time
25
ns
RESET TIMING
Typical values at 25°C, min and max values across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.0 to
3.6V, DRVDD = 1.65 to 3.6V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
t1
Power-on delay
Delay from power-up of AVDD and DRVDD to RESET pulse active
t2
Reset pulse width
t3
tPO
TYP
MAX
UNIT
5
ms
Pulse width of active RESET signal
10
ns
Register write delay
Delay from RESET disable to SEN active
25
Power-up time
Delay from power-up of AVDD and DRVDD to output stable
ns
6.5
ms
Power Supply
AVDD, DRVDD
t1
RESET
t2
t3
SEN
NOTE: A high-going pulse on RESET pin is required in serial interface mode in case of initialization through hardware reset.
For parallel interface operation, RESET has to be tied permanently HIGH.
Figure 6. Reset Timing Diagram
14
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SERIAL REGISTER MAP
Table 5 provides a summary of all the modes that can be programmed through the serial interface.
Table 5. Summary of Functions Supported by Serial Interface (1) (2)
REGISTER
ADDRESS
IN HEX
REGISTER FUNCTIONS
A4 - A0
D10
00
<PDN
OBUF>
Output
buffers
powered
down
D9
D8
D6
D5
D4
D3
D2
D1
D0
0
<STBY>
ADC Power
down
<LVDS
<COARSE
CMOS>
GAIN>
LVDS or
Coarse gain CMOS output
interface
0
0
<REF>
Internal or
external
Reference
<RST>
Software
Reset
0
<PDN
CLKOUT>
Output
clock buffer
powered
down
04
<DATAOUT
POSN>
Output data
position
control
<CLKOUT
EDGE>
Output
Clock edge
control
<CLKOUT
POSN>
Output Clock
position
control
0
0
0
0
0
0
0
0
09
Bit-wise or
Byte-wise
control
0
0
0
0
0
0
0
0
0
0
0A
<DATA
FORMAT>
2s
complement
or straight
binary
0
0
0
0
0
0
0
0
0
0
0
<TEST PATTERNS>
<CUSTOM LOW>
Custom Pattern lower 7bits
0B
<FINE GAIN>
Fine Gain 0 to 6dB
0C
(1)
(2)
D7
0E
0
0F
0
0
0
0
LVDS Termination
LVDS Internal Termination control for output data and clock
0
0
<DRIVE STRENGTH>
CMOS output buffer drive strength control
<CUSTOM HIGH>
Custom Pattern upper 5 bits
<LVDS CURRENT>
LVDS Current control
0
0
<CURRENT
DOUBLE>
LVDS current double
0
0
The unused bits in each register (shown by blank cells in above table) must be programmed as ‘0’.
Multiple functions in a register can be programmed in a single write operation.
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DESCRIPTION OF SERIAL REGISTERS
Each register function is explained in detail using Table 6 through Table 13.
Table 6.
A4–A0
(hex)
00
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
<PDN OBUF>
Output buffers
powered down
<COARSE
GAIN>
Coarse gain
<LVDS CMOS>
LVDS or CMOS
output interface
0
0
<REF>
Internal or
external
reference
<RST>
Software
Reset
0
<PDN CLKOUT>
Output clock
buffer powered
down
0
<STBY>
ADC Power
down
D0
0
Normal operation
1
Device enters standby mode where only ADC is powered down.
D2
<PDN CLKOUT>
0
Output clock is active (on CLKOUT) pin
1
Output clock buffer is powered down and becomes tri-stated. Data outputs are unaffected.
D4
1
<RST>
Software reset applied - resets all internal registers and the bit self-clears to 0.
D5
<REF> Reference selection
0
Internal reference enabled
1
External reference enabled
D8
<LVDS CMOS> Output Interface selection
0
Parallel CMOS interface
1
DDR LVDS interface
D9
<COARSE GAIN> Gain programming
0
0 dB Coarse gain
1
3.5 dB Coarse gain
D10
16
<STBY> Power down modes
<PDN OBUF> Power down modes
0
Output data and clock buffers enabled
1
Output data and clock buffers disabled
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Table 7.
A4–A0
(hex)
04
D8
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
<DATAOUT POSN>
Output data position
control
<CLKOUT EDGE>
Output Clock edge
control
<CLKOUT POSN>
Output Clock
position control
0
0
0
0
0
0
0
0
<CLKOUT POSN> Output clock position control
0
Default output clock position after reset. The setup/hold timings for this clock position are specified
in the timing specifications table.
1
Output clock shifted (delayed) by 400 ps
D9
<CLKOUT EDGE>
0
Use rising edge to capture data
1
Use falling edge to capture data
D10
<DATAOUT_POSN>
0
Default position (after reset)
1
Data transition delayed by half clock cycle with respect to default position
Table 8.
A4–A0
(hex)
09
D10
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Bit-wise or
Byte-wise control
0
0
0
0
0
0
0
0
0
0
Bit-wise or byte-wise selection (DDR LVDS mode only)
0
Bit-wise sequence - Even data bits (D0, D2, D4..D12) are output at rising edge of CLKOUTP and
odd data bits (D1, D3, D5..D13) at falling edge of CLKOUTP
1
Byte-wise sequence - Lower 7 data bits (D0-D7) are output at rising edge of CLKOUTP and upper
7 data bits (D8-D13) at falling edge of CLKOUTP
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Table 9.
A4–A0
(hex)
0A
D7-D5
D10
D9
D8
<DF>
2s complement or straight binary
0
0
D7
D6
D5
<TEST PATTERNS>
D4
D3
D2
D1
D0
0
0
0
0
0
Test Patterns
000
Normal operation - <D11:D0> = ADC output
001
All zeros - <D11:D0> = 0x000
010
All ones - <D11:D0> = 0xFFF
011
Toggle pattern - <D11:D0> toggles between 0xAAA and 0x555
100
Digital ramp - <D11:D0> increments from 0x000 to 0xFFF by one code every cycle
101
Custom pattern - <D11:D0> = contents of CUSTOM PATTERN registers
110
Unused
111
Unused
D10
<DATA FORMAT>
0
2s Complement
1
Straight binary
Table 10.
A4–A0
(hex)
D10
D9
0B
D8
D7
D6
D5
D4
<CUSTOM LOW>
Lower 7bits of custom pattern
D3
D2
D1
D0
0
0
0
0
D3
D2
D1
D0
Table 11.
A4–A0
(hex)
D10
0C
18
D9
D8
<FINE GAIN>
Fine Gain 0 to 6dB
D7
D6
D5
0
0
0
Reg 0B
D10-D4
<CUSTOM LOW> - Specifies lower 7 bits of custom pattern
Reg 0C
D4-D0
<CUSTOM HIGH> - Specifies upper 5 bits of custom pattern
D10-D8
<FINE GAIN> Gain programming
000
0 dB Gain
001
1 dB Gain
010
2 dB Gain
011
3 dB Gain
100
4 dB Gain
101
5 dB Gain
110
6 dB Gain
111
Unused
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D4
<CUSTOM HIGH>
Upper 5 bits of custom pattern
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Table 12.
A4–A0
(hex)
D10
0E
0
D1-D0
D0
D9
D8
D7
D4
D2
<LVDS
CURRENT>
LVDS Current
control
D1
D0
<CURRENT
DOUBLE>
LVDS current
double
LVDS Data buffer current control
1
2x LVDS Current set by <LVDS_CURR>
LVDS Clock buffer current control
0
Default current, set by <LVDS_CURR>
1
2x LVDS Current set by <LVDS_CURR>
<LVDS CURRENT> LVDS current programming
00
3.5 mA
01
2.5 mA
10
4.5 mA
11
1.75 mA
D9-D4
LVDS internal termination
D9-D7
<DATA TERM> Internal termination for LVDS output data bits
000
No internal termination
001
300 Ω
010
185 Ω
011
115 Ω
100
150 Ω
101
100 Ω
110
80 Ω
111
65 Ω
D6-D4
D3
<CURRENT DOUBLE> LVDS current programming
Default current, set by <LVDS_CURR>
D3-D2
D5
<LVDS TERMINATION>
LVDS Internal Termination control for output data and clock
0
D1
D6
<CLKOUT TERM> Internal termination for LVDS output clock
000
No internal termination
001
300 Ω
010
185 Ω
011
115 Ω
100
150 Ω
101
100 Ω
110
80 Ω
111
65 Ω
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Table 13.
A4–A0
(hex)
D10
D9
D8
0F
0
0
0
D7-D4
D7
D6
D5
D4
<DRIVE STRENGTH>
CMOS output buffer drive strength control
D3
D2
D1
D0
0
0
0
0
<DRIVE STRENGTH> Output buffer drive strength controls
0101
WEAKER than default drive
0000
DEFAULT drive strength
1111
STRONGER than default drive strength (recommended for load capacitances > 5 pF)
1010
MAXIMUM drive strength (recommended for load capacitances > 5 pF)
Other
Do not use
combinations
20
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PIN CONFIGURATION (CMOS MODE)
DRVDD 1
25 OVR
26 CLKOUT
27 D6
28 D7
29 D8
30 D9
31 D10
32 D11
RHB PACKAGE
(TOP VIEW)
24 D5
Bottom Pad Connected
To DRGND
RESET 2
23 D4
CLKP 7
18 NC
CLKM 8
17 NC
PDN 16
19 D0
AVDD 15
AGND 6
CM 14
20 D1
AVDD 13
SEN 5
AGND 12
21 D2
INM 11
SDATA 4
INP 10
22 D3
AGND 9
SCLK 3
Figure 7. CMOS Mode Pinout
Table 14. Pin Assignments – CMOS Mode
PIN NAME
PIN
TYPE
DESCRIPTION
PIN
NUMBER
NUMBER
OF PINS
AVDD
Analog power supply
I
13, 15
2
AGND
Analog ground
I
6, 9, 12
3
CLKP, CLKM
Differential clock input
I
7, 8
2
INP, INM
Differential analog input. On each pin, a 2.3 V common-mode voltage is set
internally.
I
10, 11
2
I/O
14
1
VCM
Internal reference mode – 1.5 V voltage output. Do NOT use this pin to set the
common-mode on the analog input pins.
External reference mode – reference input. The voltage forced on this pin sets the
internal references.
RESET
Serial interface RESET input.
When using the serial interface mode, the user MUST initialize internal registers
through hardware RESET by applying a high-going pulse on this pin, or by using
the software reset option. See the SERIAL INTERFACE section.
In parallel interface mode, the user has to tie the RESET pin permanently HIGH.
(SCLK, SDATA and SEN are used as parallel pin controls in this mode)
The pin has an internal 100-kΩ pull-down resistor.
I
2
1
SCLK
This pin functions as serial interface clock input when RESET is low.
When RESET is tied high, it controls the coarse gain and internal/external reference
selection. Tie SCLK to low for internal reference and 0 dB gain and high for
internal reference and 3.5 dB gain. See Table 2.
The pin has an internal 100 kΩ pull-down resistor.
I
3
1
I
4
1
I
5
1
This pin functions as serial interface data input when RESET is low. It controls
various power down modes along with PDN pin when RESET is tied high.
SDATA
See Table 4 for detailed information.
The pin has an internal 100 kΩ pull-down resistor.
SEN
This pin functions as serial interface enable input when RESET is low. When
RESET is high, it controls output interface type and data formats. See Table 3 for
detailed information.
The pin has an internal 100 kΩ pull-up resistor to DRVDD.
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Table 14. Pin Assignments – CMOS Mode (continued)
PIN NAME
DESCRIPTION
PIN
TYPE
PIN
NUMBER
NUMBER
OF PINS
PDN
Global power down control pin
I
16
1
CLKOUT
CMOS Output clock
O
26
1
D0
CMOS Output data D0
O
19
1
D1
CMOS Output data D1
O
20
1
D2
CMOS Output data D2
O
21
1
D3
CMOS Output data D3
O
22
1
D4
CMOS Output data D4
O
23
1
D5
CMOS Output data D5
O
24
1
D6
CMOS Output data D6
O
27
1
D7
CMOS Output data D7
O
28
1
D8
CMOS Output data D8
O
29
1
D9
CMOS Output data D9
O
30
1
D10
CMOS Output data D10
O
31
1
D11
CMOS Output data D11
O
32
1
OVR
Indicates over-voltage on analog inputs (for differential input greater than full-scale),
CMOS level
O
25
1
DRVDD
Digital supply
I
1
1
I
PAD
1
DRGND
Digital ground.
Connect the pad to the ground plane. See Board Design Considerations in
application information section.
22
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PIN CONFIGURATION (LVDS MODE)
DRVDD 1
25 CLKOUTM
26 CLKOUTP
27 D6_D7_M
28 D6_D7_P
29 D8_D9_M
30 D8_D9_P
31 D10_D11_M
32 D10_D11_P
RHB PACKAGE
(TOP VIEW)
24 D4_D5_P
Bottom Pad Connected
To DRGND
RESET 2
23 D4_D5_M
CLKP 7
18 NC
CLKM 8
17 NC
PDN 16
19 D0_D1_M
AVDD 15
AGND 6
CM 14
20 D0_D1_P
AVDD 13
SEN 5
AGND 12
21 D2_D3_M
INM 11
SDATA 4
INP 10
22 D2_D3_P
AGND 9
SCLK 3
Figure 8. LVDS Mode Pinout
Table 15. Pin Assignments – LVDS Mode
PIN NAME
DESCRIPTION
PIN
TYPE
PIN
NUMBER
NUMBER
OF PINS
AVDD
Analog power supply
I
13, 15
2
AGND
Analog ground
I
6, 12
3
CLKP, CLKM
Differential clock input
I
7, 8
2
INP, INM
Differential analog input
I
10, 11
2
VCM
Internal reference mode – 1.5V voltage output. Do NOT use this pin to set the
common-mode on the analog input pins.
External reference mode – reference input. The voltage forced on this pin sets the
internal references.
I/O
14
1
RESET
Serial interface RESET input.
When using the serial interface mode, the user MUST initialize internal registers
through hardware RESET by applying a high-going pulse on this pin, or by using the
software reset option. See the SERIAL INTERFACE section.
In parallel interface mode, the user has to tie the RESET pin permanently HIGH.
(SCLK, SDATA and SEN are used as parallel pin controls in this mode)
The pin has an internal 100-kΩ pull-down resistor.
I
2
1
SCLK
This pin functions as serial interface clock input when RESET is low.
When RESET is tied high, it controls the coarse gain and internal/external reference
selection. Tie SCLK to low for internal reference and 0 dB gain and high for internal
reference and 3.5 dB gain. See Table 2.
The pin has an internal 100-kΩ pull-down resistor.
I
3
1
I
4
1
I
5
1
This pin functions as serial interface data input when RESET is low. It controls
various power down modes along with PDN pin when RESET is tied high.
SDATA
See Table 4 for detailed information.
The pin has an internal 100 kΩ pull-down resistor.
SEN
This pin functions as serial interface enable input when RESET is low. When RESET
is high, it controls output interface type and data formats. See Table 3 for detailed
information. The pin has an internal 100-kΩ pull-up resistor to DRVDD.
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Table 15. Pin Assignments – LVDS Mode (continued)
PIN NAME
DESCRIPTION
PIN
TYPE
PIN
NUMBER
NUMBER
OF PINS
PDN
Global power down control pin
I
16
1
CLKOUTP
Differential output clock, true
O
26
1
CLKOUTM
Differential output clock, complement
O
25
1
D0_D1_P
Differential output data D0 and D1 multiplexed, true
O
20
1
D0_D1_M
Differential output data D0 and D1 multiplexed, complement.
O
19
1
D2_D3_P
Differential output data D2 and D3 multiplexed, true
O
22
1
D2_D3_M
Differential output data D2 and D3 multiplexed, complement
O
21
1
D4_D5_P
Differential output data D4 and D5 multiplexed, true
O
24
1
D4_D5_M
Differential output data D4 and D5 multiplexed, complement
O
23
1
D6_D7_P
Differential output data D6 and D7 multiplexed, true
O
28
1
D6_D7_M
Differential output data D6 and D7 multiplexed, complement
O
27
1
D8_D9_P
Differential output data D8 and D9 multiplexed, true
O
30
1
D8_D9_M
Differential output data D8 and D9 multiplexed, complement
O
29
1
D10_D11_P
Differential output data D10 and D11 multiplexed, true
O
32
1
D10_D11_M
Differential output data D10 and D11 multiplexed, complement
O
31
1
DRVDD
Digital supply
I
1
1
I
PAD
1
DRGND
Digital ground.
Connect the pad to the ground plane. See Board Design Considerations in application
information section.
24
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TYPICAL CHARACTERISTICS
All plots are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = 80 MSPS, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input (1.8 Vpp) , internal reference mode, 0 dB gain,
unless otherwise noted.
FFT for 20 MHz INPUT SIGNAL
FFT for 100 MHz INPUT SIGNAL
0
0
SFDR = 81 dBc
SINAD = 69.7 dBFS
SNR = 70 dBFS
THD = 80 dBc
−20
−40
Amplitude − dB
Amplitude − dB
−40
−60
−80
−100
−60
−80
−100
−120
−120
−140
−140
−160
−160
0
10
20
30
40
f − Frequency − MHz
0
10
20
30
f − Frequency − MHz
G001
40
G002
Figure 9.
Figure 10.
INTERMODULATION DISTORTION
SFDR vs. INPUT FREQUENCY
FOR 1.8Vpp and 1Vpp INPUT SIGNAL (AT 0 dB GAIN)
0
92
fIN1 = 50.1 MHz, –7 dBFS
fIN2 = 46.1 MHz, –7 dBFS
2-Tone IMD = –85.31 dBFS
SFDR = –90.8 dBFS
−20
88
84
SFDR − dBc
−40
Amplitude − dB
SFDR = 81.3 dBc
SINAD = 69.3 dBFS
SNR = 69.6 dBFS
THD = 78.9 dBc
−20
−60
−80
−100
1 VPP
80
76
72
−120
68
−140
64
−160
1.8 VPP
60
0
10
20
30
f − Frequency − MHz
40
0
20
40
60
80
100 120 140 160 180 200 220
fIN − Input Frequency − MHz
G003
Figure 11.
Figure 12.
SNR vs. INPUT FREQUENCY
FOR 1.8Vpp and 1Vpp INPUT SIGNAL (AT 0 dB GAIN)
SFDR ACROSS COARSE GAIN
FOR 1.8Vpp and 1Vpp INPUT SIGNAL
72
G004
100
95
71
1 VPP, 3.5 dB
90
1 VPP
SFDR − dBc
SNR − dBFS
70
69
68
1.8 VPP
1 VPP, 0 dB
85
80
75
70
1.8 VPP, 3.5 dB
65
67
60
66
55
65
1.8 VPP, 0 dB
50
0
20
40
60
80
100 120 140 160 180 200 220
fIN − Input Frequency − MHz
0
20
G005
Figure 13.
40
60
80
100 120 140 160 180 200 220
fIN − Input Frequency − MHz
G006
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = 80 MSPS, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input (1.8 Vpp) , internal reference mode, 0 dB gain,
unless otherwise noted.
SNR ACROSS COARSE GAIN
FOR 1.8Vpp and 1Vpp INPUT SIGNAL
SFDR ACROSS FINE GAIN
72
100
1 VPP, 0 dB
71
90
1.8 VPP, 0 dB
69
68
6 dB
85
SFDR − dBc
5 dB
80
4 dB
75
70
1 dB
65
1 VPP, 3.5 dB
2 dB
60
1.8 VPP, 3.5 dB
66
0 dB
3 dB
55
65
50
0
20
40
60
80
100 120 140 160 180 200 220
fIN − Input Frequency − MHz
0
20
40
60
G007
Figure 15.
SINAD ACROSS FINE GAIN
G008
PERFORMANCE vs AVDD
96
Input adjusted to get −1dBFS input
85
94
80
76
fIN = 10.1 MHz
DRVDD = 1.8 V
75
92
3 dB
75
SFDR − dBc
SINAD − dBFS
100 120 140 160 180 200 220
Figure 16.
90
2 dB
70
65
60
4 dB
6 dB
0 dB
50
0
20
40
60
80
90
73
88
72
86
71
SNR
84
70
82
69
80
3.0
100 120 140 160 180 200 220
fIN − Input Frequency − MHz
3.1
3.2
3.3
3.4
3.5
68
3.6
AVDD − Supply Voltage − V
G009
Figure 17.
G010
Figure 18.
PERFORMANCE vs DRVDD
PERFORMANCE vs TEMPERATURE
94
fIN = 10.1 MHz
AVDD = 3.3 V
74
SFDR
1 dB
5 dB
55
92
80
fIN − Input Frequency − MHz
SNR − dBFS
SNR − dBFS
70
67
Input adjusted to get −1dBFS input
95
SFDR
74
84
73
82
74
73
88
71
SNR
86
70
80
72
78
71
SNR
76
SNR − dBFS
72
SFDR − dBc
90
SNR − dBFS
SFDR − dBc
SFDR
70
fIN = 10.1 MHz
84
1.8
2.0
2.2
2.4
2.6
2.8
3.0
DRVDD − Supply Voltage − V
3.2
3.4
69
3.6
74
−40
69
−20
G011
Figure 19.
26
0
20
40
T − Temperature − °C
60
80
G012
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = 80 MSPS, sine wave input clock, 1.5 VPP differential
clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input (1.8 Vpp) , internal reference mode, 0 dB gain,
unless otherwise noted.
PERFORMANCE vs ANALOG INPUT AMPLITUDE
110
PERFORMANCE vs CLOCK AMPLITUDE
90
100
92
77
fIN = 20.1 MHz
SFDR
85
90
76
80
88
75
86
74
84
73
82
72
75
SNR (dBFS)
70
70
SFDR (dBc)
60
65
50
40
fIN = 20.1 MHz
30
−50
−40
−30
−20
−10
60
80
55
78
50
76
0.5
0
Input Amplitude − dBFS
70
1.0
1.5
2.0
69
3.0
2.5
Input Clock Amplitude − VPP
G013
G014
Figure 22.
PERFORMANCE vs CLOCK DUTY CYCLE
82
OUTPUT NOISE HISTOGRAM
80
74
70
73
SFDR
72
79
71
SNR
78
70
77
69
Occurence − %
60
80
SNR − dBFS
SFDR − dBc
71
SNR
Figure 21.
81
SNR − dBFS
80
SFDR − dBc
90
SNR − dBFS
SFDR − dBc, dBFS
SFDR (dBFS)
50
40
30
20
10
fIN = 20.1 MHz
76
0
68
30
35
40
45
50
55
60
65
Input Clock Duty Cycle − %
Output Code
G015
G016
Figure 23.
Figure 24.
POWER DISSIPATION vs. SAMPLING FREQUENCY
DRVDD CURRENT vs. SAMPLING FREQUENCY (ACROSS
LOAD CAPACITOR)
0.8
30
fIN = 2.5 MHz
CL = 5 pF
0.7
1.8 V, No Load
25
DRVDD Current − mA
PD − Power Dissipation − W
2038 2039 2040 2041 2042 2043 2044 2045 2046 2047
70
0.6
0.5
LVDS
0.4
0.3
0.2
1.8 V, 5 pF
20
3.3 V, No Load
15
3.3 V, 5 pF
3.3 V, 10 pF
10
CMOS
5
0.1
0.0
0
0
10
20
30
40
50
60
fS − Sampling Frequency − MSPS
70
80
0
10
G017
Figure 25.
20
30
40
50
60
70
fS − Sampling Frequency − MSPS
80
G018
Figure 26.
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TYPICAL CHARACTERISTICS - AT LOWER SAMPLING FREQUENCIES
All plots are at 25°C, AVDD = DRVDD = 3.3 V, sine wave input clock, 1.5 VPP differential clock amplitude, 50% clock duty
cycle, –1 dBFS differential analog input (1.8Vpp) , internal reference mode, 0 dB gain, unless otherwise noted.
FS = 65 MSPS
SFDR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY
100
72
95
1 VPP, 3.5 dB
1 VPP, 0 dB
71
1 VPP, 0 dB
85
80
75
70
1.8 VPP, 0 dB
70
SNR − dBFS
SFDR − dBc
90
1.8 VPP, 0 dB
65
69
68
1 VPP, 3.5 dB
67
60
1.8 VPP, 3.5 dB
1.8 VPP, 3.5 dB
66
55
50
65
0
20
40
60
80
100 120 140 160 180 200 220
fIN − Input Frequency − MHz
0
20
40
60
80
100 120 140 160 180 200 220
fIN − Input Frequency − MHz
G019
Figure 27.
G020
Figure 28.
FS = 40 MSPS
SFDR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY
100
72
1 VPP, 3.5 dB
95
1 VPP, 0 dB
71
1.8 VPP, 0 dB
1 VPP, 0 dB
85
70
SNR − dBFS
SFDR − dBc
90
80
75
1.8 VPP, 0 dB
70
65
68
1 VPP, 3.5 dB
67
1.8 VPP, 3.5 dB
60
69
1.8 VPP, 3.5 dB
66
55
50
65
0
20
40
60
80
100 120 140 160 180 200 220
fIN − Input Frequency − MHz
0
20
G021
Figure 29.
28
40
60
80
100 120 140 160 180 200 220
fIN − Input Frequency − MHz
G022
Figure 30.
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APPLICATION INFORMATION
THEORY OF OPERATION
ADS61B23 is a low-power, 12-bit pipeline ADC (CMOS process) with a maximum 80 MSPS sampling frequency.
It is based on switched capacitor technology and runs off a single 3.3-V supply. The conversion process is
initiated by a rising edge of the external input clock. Once the signal is captured by the input sample and hold,
the input sample is sequentially converted by a series of lower resolution stages, with the outputs combined in a
digital correction logic block. At every clock edge, the sample propagates through the pipeline resulting in a data
latency of 9 clock cycles. The output is available as 12-bit data, in DDR LVDS or CMOS and coded in straight
offset binary or binary 2s complement format.
ANALOG INPUT
The analog input consists of an internal analog buffer followed by the sample and hold circuit, shown in
Figure 31.
The buffer isolates the external drive circuit from the switching transients of the sample and hold. The buffered
inputs present very low input capacitance (< 2pF) & wide bandwidth. This makes it easy to drive them even at
high input frequencies, compared to an ADC without the input buffers. The input common-mode is set internally
by a 5 kΩ resistor from each input pin to an internally generated common-mode voltage (2.3 V). This results in a
differential resistance of kΩ.
For a full-scale differential input, each input pin INP, INM swings symmetrically between (2.3 + 0.5 V) and (2.3 –
0.5 V), resulting in a 2 VPP differential input swing. The maximum swing is determined by the internal reference
voltages REFP (2.0 V, nominal) and REFM (1.0 V, nominal).
Lpkg
»1 nH
INP
Cbond
»1 pF
Ceq
0.8 pF
15 W
To Sampling
Circuit
5 kW
Resr
200 W
2.3 V
Lpkg
»1 nH
5 kW
15 W
INM
Cbond
»1 pF
Ceq
0.8 pF
To Sampling
Circuit
Resr
200 W
S0323-01
Figure 31. Input Stage
As shown by Figure 31, the equivalent input capacitance from each input pin to ground is very low (< 2pF),
resulting in high analog input bandwidth (> 800 MHz).
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Drive Circuit Requirements
For optimum performance, the analog inputs must be driven differentially. This improves the common-mode
noise immunity and even order harmonic rejection. A 5 Ω resistor in series with each input pin is recommended
to damp out ringing caused by the package parasitic effects. Since the common-mode of each input pin is set
internally by the device, it is recommended to ac-couple the analog input signal.
The input impedance of each pin can be approximated by a 5 kΩ resistor in parallel with 1.8 pF capacitor and
presents high impedance over wide frequency range. The low input capacitance and wide input bandwidth
makes it easy to design the external drive circuit with low insertion loss.
7
R − Resistance − kΩ
6
5
4
3
2
1
0
1
10
100
f − Frequency − MHz
1k
G023
Figure 32. ADC Input Resistance, Rin
C − Capacitance − pF
3
2
1
0
1
10
100
f − Frequency − MHz
1k
G024
Figure 33. ADC Input Capacitance, Cin
30
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Using RF-Transformer Based Drive Circuits
Figure 34 shows a drive circuit using a single 1:1 turns ratio transformer (for example, Coilcraft WBC1-1) that can
be used for low input frequencies (≈ 100 MHz).
The single-ended signal is fed to the primary winding of the RF transformer with 50-Ω termination on the
secondary side.
ADS61B23
Rs
50 W
0.1 mF
0.1 mF
5W
INP
0.1 mF
25 W
25 W
INM
5W
0.1 mF
1:1
S0256-02
Figure 34. Single Transformer Drive Circuit
At high input frequencies, the mismatch in the transformer parasitic capacitance (between the windings) results
in degraded even-order harmonic performance. Connecting two identical RF transformers back-to-back helps
minimize this mismatch, and good performance is obtained for high frequency input signals. Figure 35 shows an
example using two transformers (Coilcraft WBC1-1). An additional termination resistor pair (enclosed within the
shaded box in Figure 35) may be required between the two transformers to improve the balance between the P
and M sides. The center point of this termination must be connected to ground.
ADS61B23
Rs
50 W
0.1 mF
0.1 mF
5W
INP
50 W
0.1 mF
50 W
50 W
50 W
INM
1:1
1:1
0.1 mF
5W
S0164-06
Figure 35. Two Transformer Drive Circuit
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Using Differential Amplifier Drive Circuits
Figure 36 shows a drive circuit using a differential amplifier (TI's THS4509) to convert a single-ended input to
differential output that can be interface to the ADC analog input pins. In addition to the single-ended to differential
conversion, the amplifier also provides gain. RFIL & CFIL form a low-pass filter that band-limits the noise (and
signal) at the ADC input.
Note that as the device sets the input common-mode voltage internally, the amplifier outputs can be ac-coupled
to the analog input pins.
RF
+VS
500 W
0.1 mF
RS
0.1 mF 10 mF
RFIL
0.1 mF
ADS61B23
5W
INP
RG
CFIL
0.1 mF
RT
CM THS4509
RG
RFIL
CFIL
INM
0.1 mF
500 W
RS || RT
0.1 mF
–VS
5W
0.1 mF 10 mF
RF
S0259-03
Figure 36. Drive Circuit Using the THS4509
See the ADS61xx EVM User's Guide (SLAU206) for more information.
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REFERENCE
ADS61B23 has built-in internal references REFP and REFM, requiring no external components. Design schemes
are used to linearize the converter load seen by the references; this and the integration of the requisite reference
capacitors on-chip eliminates the need for external decoupling. The full-scale input range of the converter is
controlled in the external reference mode as explained below. The internal or external reference modes can be
selected by programming the serial interface register bit <REF> (seeTable 6).
INTREF
Internal
Reference
VCM
1 kW
INTREF
4 kW
EXTREF
REFM
REFP
ADS61B23
S0165-06
Figure 37. Reference Section
Internal Reference
When the device is in internal reference mode, the REFP and REFM voltages are generated internally. In this
mode, a 1.5 V dc voltage is output on the VCM pin. However, do not use this to set the common-mode of the
analog input pins, as the common-mode on these pins is set internally to 2.3V.
External Reference
When the device is in external reference mode, the VCM acts as a reference input pin. The voltage forced on the
VCM pin is buffered and gained by 1.33 internally, generating the REFP and REFM voltages. The differential
input voltage corresponding to full-scale is given by Equation 1.
Full−scale differential input pp + (Voltage forced on VCM)
1.33
(1)
In this mode, the 1.5 V common-mode voltage to bias the input pins has to be generated externally. There is no
change in performance compared to internal reference mode.
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COARSE GAIN and PROGRAMMABLE FINE GAIN
ADS61B23 includes gain settings that can be used to get improved SFDR performance (compared to 0 dB gain
mode). The gain settings are 3.5 dB coarse gain and programmable fine gain from 0 dB to 6 dB. For each gain
setting, the analog input full-scale range scales proportionally, as shown in Table 16.
The coarse gain is a fixed setting of 3.5 dB and is designed to improve SFDR with little degradation in SNR (as
seen in Figure 14 and Figure 15). The fine gain is programmable in 1 dB steps from 0 to 6 dB. With fine gain
also, SFDR improvement is achieved, but at the expense of SNR (there is about 1 dB SNR degradation for every
1 dB of fine gain).
So, the fine gain can be used to trade-off between SFDR and SNR. The coarse gain makes it possible to get
best SFDR, without losing significant SNR. At high input frequencies, the gains are especially useful as the
SFDR improvement is significant with marginal degradation in SINAD. The gains can be programmed using the
register bits <COARSE GAIN> (see Table 6) and <FINE GAIN> (see Table 11).
Note that the default gain after reset is 0 dB.
Table 16. Full-Scale Range Across Gains
GAIN, dB
TYPE
FULL-SCALE RANGE, VPP
0
Default after reset
2.00
3.5
Coarse setting (fixed)
1.34
1
1.78
2
1.59
3
4
34
Fine gain (programmable)
1.42
1.26
5
1.12
6
1.00
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CLOCK INPUT
The clock inputs of ADS61B23 can be driven differentially (SINE, LVPECL or LVDS) or single-ended (LVCMOS),
with little or no difference in performance between configurations. The common-mode voltage of the clock inputs
is set to VCM using internal 5-kΩ resistors as shown in Figure 38. This allows the use of transformer-coupled
drive circuits for sine wave clock, or ac-coupling for LVPECL, LVDS clock sources (Figure 40 and Figure 41).
For best performance, it is recommended to drive the clock inputs differentially, reducing susceptibility to
common-mode noise. In this case, it is best to connect both clock inputs to the differential input clock signal with
0.1-µF capacitors, as shown in Figure 40. A single-ended CMOS clock can be ac-coupled to the CLKP input,
with CLKM connected to ground with a 0.1-µF capacitor, as shown in Figure 41.
For high input frequency sampling, the use a clock source with very low jitter is recommended. Bandpass filtering
of the clock source can help reduce the effect of jitter. There is no change in performance with a non-50% duty
cycle clock input. Figure 23 shows the performance of the ADC versus clock duty cycle.
Clock Buffer
Lpkg
» 1 nH
10 W
CLKP
Cbond
» 1 pF
Ceq
Ceq
5 kW
Resr
» 100 W
VCM
6 pF
5 kW
Lpkg
» 1 nH
10 W
CLKM
Cbond
» 1 pF
Resr
» 100 W
Ceq » 1 to 3 pF, equivalent input capacitance of clock buffer
S0275-03
Figure 38. Internal Clock Buffer
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1000
Impedance (Magnitude) − Ω
900
800
700
600
500
400
300
200
100
0
0
25
50
75
100
125
Clock Frequency − MHz
G082
Figure 39. Clock Buffer Input Impedance
0.1 mF
CLKP
Differential Sine-Wave
or PECL or LVDS
Clock Input
0.1 mF
CLKM
ADS61B23
Figure 40. Differential Clock Driving Circuit
0.1 mF
CMOS Clock Input
CLKP
0.1 mF
CLKM
ADS61B23
Figure 41. Single-Ended Clock Driving Circuit
36
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POWER DOWN MODES
ADS61B23 has four power-down modes—global power down, standby, output buffer disable, and input clock
stopped (normal operation). These modes can be set using the serial interface or the parallel interface (pins
SDATA and PDN).
Table 17. Power Down Modes
POWER-DOWN
MODES
PARALLEL INTERFACE
SERIAL INTERFACE
REGISTER BIT
(Table 6)
TOTAL POWER,
mW
(DRVDD=3.3V)
WAKE-UP TIME
(to valid data)
SDATA
PDN
Normal operation
Low
Low
<PDN OBUF>=0 and
<STBY>=0
372
-
Standby
Low
High
<PDN OBUF>=0 and
<STBY>=1
168
Slow (50 µs)
Output buffer disable
High
Low
<PDN OBUF>=1 and
<STBY>=0
349
Fast (200 ns)
Global power down
High
High
<PDN OBUF>=1 and
<STBY>=1
40
Slow (50 µs)
Global Powerdown
In this mode, the A/D converter, internal references and the output buffers are powered down and the total power
dissipation reduces to about 40 mW. The output buffers are in high impedance state. The wake-up time from the
global power down to output data becoming valid in the normal mode is maximum 50 µs. Note that after coming
out of global power down, optimum performance will be achieved after the internal reference voltages have
stabilized (about 1 ms).
Standby
Here, only the A/D converter is powered down and the total power dissipation is about 168 mW. The wake-up
time from standby to output data becoming valid is maximum 50 µs.
Output Buffer Disable
The data output buffers can be disabled, reducing the total power to about 350 mW. With the buffers disabled,
the outputs are in high impedance state. The wake-up time from this mode to data becoming valid in normal
mode is maximum 500 ns in LVDS mode and 200 ns in CMOS mode.
Input Clock Stop (Normal operation)
The converter enters this mode when the input clock frequency falls below 1 MSPS. The power dissipation is
about 115 mW, and the wake-up time from this mode to data becoming valid in normal mode is maximum 50 µs.
Power Supply Sequence
During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are
separated inside the device. Externally, they can be driven from separate supplies or from a single supply.
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DIGITAL OUTPUT INTERFACE
ADS61B23 outputs 12 data bits together with an output clock. The output interface are either parallel CMOS or
DDR LVDS voltage levels and can be selected using serial register bit <LVDS CMOS> or parallel pin SEN.
Parallel CMOS Interface
In the CMOS mode, the output buffer supply (DRVDD) can be operated over a wide range from 1.8 V to 3.3 V
(typical). Each data bit is output on separate pin as CMOS voltage level, every clock cycle.
For DRVDD ≥ 2.2 V, it is recommended to use the CMOS output clock (CLKOUT) to latch data in the receiving
chip. The rising edge of CLKOUT can be used to latch data in the receiver, even at the highest sampling speed
(125 MSPS). It is recommended to minimize the load capacitance seen by data and clock output pins by using
short traces to the receiver. Also, match the output data and clock traces to minimize the skew between them.
For DRVDD < 2.2 V, it is recommended to use external clock (for example, input clock delayed to get desired
setup/hold times).
Output Clock Position Programmability
There exists an option to shift (delay) the output clock position so that the setup time increases by 400 ps
(typical, with respect to the default timings specified). This may be useful if the receiver needs more setup time,
especially at high sampling frequencies. This can be programmed using the serial interface register bit
<CLKOUT_POSN> (see Table 7).
Output Buffer Strength Programmability
Switching noise (caused by CMOS output data transitions) can couple into the analog inputs during the instant of
sampling and degrade the SNR. The coupling and SNR degradation increases as the output buffer drive is made
stronger. To minimize this, the ADS61B23 CMOS output buffers are designed with controlled drive strength to
get best SNR. The default drive strength also ensures wide data stable window for load capacitances up to 5 pF
and DRVDD supply voltage ≥ 2.2 V.
To ensure wide data stable window for load capacitance > 5 pF, there is an option to increase the drive strength
using the serial interface (<DRIVE STRENGTH>, see Table 13). Note that for DRVDD supply voltage < 2.2 V, it
is recommended to use maximum drive strength (for any value of load capacitance).
CMOS Mode Power Dissipation
With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every
output pin. The maximum DRVDD current occurs when each output bit toggles between 0 and 1 every clock
cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determined
by the average number of output bits switching, which is a function of the sampling frequency and the nature of
the analog input signal.
Digital current due to CMOS output switching = CL × DRVDD x (N x FAVG)
where CL = load capacitance, N × FAVG = average number of output bits switching
Figure 33 shows the current with various load capacitances across sampling frequencies at 2 MHz analog input
frequency.
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Pins
OVR
CLKOUT
D0
D1
CMOS
Output Buffers
D2
D3
D4
D5
D6
12 bit ADC data
D7
D8
D9
D10
D11
ADS61B23
Figure 42. CMOS Output buffers
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DDR LVDS Interface
The LVDS interface works only with 3.3 V DRVDD supply. In this mode, the 12 data bits and the output clock are
available as LVDS (Low Voltage Differential Signal) levels. Two successive data bits are multiplexed and output
on each LVDS differential pair every clock cycle (DDR - Double Data Rate, see Figure 43 ). So, there are 7
LVDS output pairs for the 12 data bits and 1 LVDS output pair for the output clock.
LVDS Buffer Current Programmability
The default LVDS buffer output current is 3.5 mA. When terminated by 100 Ω, this results in a 350-mV
single-ended voltage swing (700-mVPP differential swing). The LVDS buffer currents can also be programmed to
2.5 mA, 4.5 mA, and 1.75 mA (register bits <LVDS CURRENT>, see Table 12). In addition, there is a current
double mode, where this current is doubled for the data and output clock buffers (register bits <CURRENT
DOUBLE>, see Table 12).
Pins
CLKOUTP
Output Clock
CLKOUTM
D0_D1_P
Data bits D0, D1
LVDS Buffers
D0_D1_M
D2_D3_P
Data bits D2, D3
D2_D3_M
D4_D5_P
Data bits D4, D5
D4_D5_M
12-Bit ADC Data
D6_D7_P
Data bits D6, D7
D6_D7_M
D8_D9_P
Data bits D8, D9
D8_D9_M
D10_D11_P
Data bits D10, D11
D10_D11_M
ADS61B23
Figure 43. DDR LVDS Outputs
Even data bits D0, D2, D4, D6, D8, D10, and D12 are output at the rising edge of CLKOUTP and the odd data
bits D1, D3, D5, D7, D9, D11, and D13 are output at the falling edge of CLKOUTP. Both the rising and falling
edges of CLKOUTP must be used to capture all the 12 data bits (see Figure 44).
40
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CLKOUTM
CLKOUTP
D0_D1_P,
D0_D1_M
D0
D1
D0
D1
D2_D3_P,
D2_D3_M
D2
D3
D2
D3
D4_D5_P,
D4_D5_M
D4
D5
D4
D5
D6_D7_P,
D6_D7_M
D6
D7
D6
D7
D8_D9_P,
D8_D9_M
D8
D9
D8
D9
D10_D11_P,
D10_D11_M
D10
D11
D10
D11
Sample N
Sample N+1
Figure 44. DDR LVDS Interface
LVDS Buffer Internal Termination
An internal termination option is available (using the serial interface), by which the LVDS buffers are differentially
terminated inside the device. The termination resistors available are – 300 Ω, 185 Ω, and 150 Ω (nominal with
±20% variation). Any combination of these three terminations can be programmed; the effective termination is
the parallel combination of the selected resistance. This results in eight effective terminations from open (no
termination) to 65 Ω.
The internal termination helps to absorb any reflections coming from the receiver end, improving the signal
integrity. With 100 Ω internal and 100 Ω external termination, the voltage swing at the receiver end is halved
(compared to no internal termination). The voltage swing can be restored by using the LVDS current double
mode. Figure 45 and Figure 46 compare the LVDS eye diagrams without and with internal termination (100 Ω).
With internal termination, the eye looks clean even with 10 pF load capacitance (from each output pin to ground).
The terminations is programmed using register bits <DATA TERM> and <CLKOUT TERM> (see Table 12).
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Figure 45. LVDS Eye Diagram - No Internal Termination
5-pF Load Capacitance
Blue Trace - Output Clock (CLKOUT)
Pink Trace - Output Data
Figure 46. LVDS Eye Diagram with 100-Ω Internal
Termination
10-pF Load Capacitance
Blue Trace - Output Clock (CLKOUT)
Pink Trace - Output Data
Output Data Format
Two output data formats are supported – 2s complement and offset binary. They can be selected using the
parallel control pin SEN or the serial interface register bit <DATA FORMAT> (see Table 9).
BOARD DESIGN CONSIDERATIONS
Grounding
A single ground plane is sufficient to give good performance, provided the analog, digital and clock sections of
the board are cleanly partitioned. See the ADS61xx EVM User's Guide (SLAU206) for details on layout and
grounding.
Supply Decoupling
As the ADS61B23 already includes internal decoupling, minimal external decoupling can be used without loss in
performance. Note that decoupling capacitors can help to filter external power supply noise, so the optimum
number of capacitors would depend on the actual application. The decoupling capacitors should be placed very
close to the converter supply pins.
It is recommended to use separate supplies for the analog and digital supply pins to isolate digital switching
noise from sensitive analog circuitry. In case only a single 3.3-V supply is available, it should be routed first to
AVDD. It can then be tapped and isolated with a ferrite bead (or inductor) with decoupling capacitor, before being
routed to DRVDD.
Exposed Thermal Pad
It is necessary to solder the exposed pad at the bottom of the package to a ground plane for best thermal
performance. For detailed information, see the QFN Layout Guidelines (SLOA122) and QFN/SON PCB
Attachment Application Report (SLUA271) documents.
42
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SPECIFICATION DEFINITIONS
Analog Bandwidth
Analog input frequency at which the power of the fundamental is reduced by 3 dB with respect to the low
frequency value.
Aperture Delay
Time delay between the rising edge of the input sampling clock and the actual time at which the sampling occurs.
Aperture Uncertainty (Jitter)
Sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle
Ratio of the time the clock signal remains at a logic high (clock pulse width) to the period of the clock signal. Duty
cycle is typically expressed as a percentage. A perfect differential sine-wave clock results in a 50% duty cycle.
Maximum Conversion Rate
Maximum sampling rate at which certified operation is expressed. All parametric testing is performed at this
sampling rate unless otherwise noted.
Minimum Conversion Rate
Minimum sampling rate at which the ADC functions.
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions at analog input values spaced exactly 1 LSB apart. The DNL is the
deviation of any single step from this ideal value, measured in units of LSBs.
Integral Nonlinearity (INL)
Deviation of the ADC’s transfer function from a best fit line determined by a least squares curve fit of that transfer
function, measured in units of least-significant bits (LSBs).
Gain Error
Deviation of the ADC’s actual input full-scale range from its ideal value. The gain error is expressed as a
percentage of the ideal input full-scale range.
Offset Error
Difference between the ADC’s actual average idle channel output code and the ideal average idle channel output
code. This quantity is often expressed in number of LSBs and converted to mV.
Temperature Drift
Coefficient (with respect to gain error and offset error) the specifies the change per degree Celsius of the
parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation of the parameter across the TMIN
to TMAX range by the difference TMAX–TMIN.
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Signal-to-Noise Ratio
Ratio of the power of the fundamental (PS) to the noise floor power (PN), excluding the power at dc and the first
nine harmonics.
P
SNR + 10Log 10 s
PN
(3)
SNR is expressed in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or in dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s
full-scale range.
Signal-to-Noise and Distortion (SINAD)
Ratio of the power of the fundamental (PS) to the power of all the other spectral components including noise (PN)
and distortion (PD), but excluding dc.
Ps
SINAD + 10Log 10
PN ) PD
(4)
SINAD is expressed in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or in dBFS (dB to full scale) when the power of the fundamental is extrapolated to the converter’s
full-scale range.
Effective Number of Bits (ENOB)
A measure of a converter’s performance as compared to the theoretical limit based on quantization noise.
ENOB + SINAD * 1.76
6.02
(5)
Total Harmonic Distortion (THD)
Ratio of the power of the fundamental (PS) to the power of the first nine harmonics (PD).
P
THD + 10Log 10 s
PN
(6)
THD is typically expressed in units of dBc (dB to carrier).
Spurious-Free Dynamic Range (SFDR)
Ratio of the power of the fundamental to the highest other spectral component (either spur or harmonic). SFDR
is typically expressed in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion (IMD3)
Ratio of the power of the fundamental (at frequencies f1 and f2) to the power of the worst spectral component at
either frequency 2f1–f2 or 2f2–f1. IMD3 is expressed in units of dBc (dB to carrier) when the absolute power of the
fundamental is used as the reference, or in dBFS (dB to full scale) when the power of the fundamental is
extrapolated to the converter’s full-scale range.
DC Power Supply Rejection Ratio (DC PSRR)
Ratio of the change in offset error to a change in analog supply voltage. The DC PSRR is typically expressed in
units of mV/V.
44
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AC Power Supply Rejection Ratio (AC PSRR)
Measure of rejection of variations in the supply voltage of the ADC. If ΔVSUP is the change in the supply voltage
and ΔVOUT is the resultant change in the ADC output code (referred to the input), then
DVOUT
(Expressed in dBc)
PSRR = 20Log 10
DVSUP
(7)
Common Mode Rejection Ratio (CMRR)
Measure of rejection of variations in the input common-mode voltage of the ADC. If ΔVcm is the change in the
input common-mode voltage and ΔVOUT is the resultant change in the ADC output code (referred to the input),
then
DVOUT
(Expressed in dBc)
CMRR = 20Log10
DVCM
(8)
Voltage Overload Recovery
Number of clock cycles taken to recover to less than 1% error for a 6-dB overload on the analog inputs. A
6-dBFS sine wave at Nyquist frequency is used as the test stimulus.
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PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ADS61B23IRHBR
QFN
RHB
32
3000
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
ADS61B23IRHBT
QFN
RHB
32
250
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS61B23IRHBR
QFN
RHB
32
3000
333.2
345.9
28.6
ADS61B23IRHBT
QFN
RHB
32
250
333.2
345.9
28.6
Pack Materials-Page 2
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