CONEXANT RP336LD

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Introduction
The CONEXANT RP56LD, RP336LD, and RP144LD
Modem Data Pump (MDP) families support data/fax
modem, voice coding/decoding, optional full-duplex
speakerphone, and optional AudioSpan (Table 1). Low
voltage and low power consumption support portable
applications. Downloadable architecture allows upgrading
of MDP code from the host/DTE.
In V.90/K56flex mode (RP56), the MDP can receive data
at speeds up to 56 kbps from a digitally connected V.90or K56flex-compatible central site modem. These MDPs
take advantage of the PSTN which is primarily digital
except for the client modem to central office local loop and
are ideal for applications such as remote access to an
Internet service provider (ISP), on-line service, or
corporate site. The MDP can send upstream data at
speeds up to V.34 rates.
In V.34 data mode (RP56 and RP336), the MDP can
connect at the highest data rate the channel can support
from 33.6 kbps to 2400 bps with auto-fallback to V.32bis.
In V.32 bis mode, the MDP can connect at the highest
data rate the channel can support from 14.4 kbps to 4800
bps with optional auto-fallback to lower rate modulations.
Internal HDLC support eliminates the need for an external
serial input/output (SIO) device in the DTE for products
incorporating error correction and T.30 protocols.
Voice mode includes an Adaptive Differential Pulse Code
Modulation (ADPCM) voice coder and decoder (codec).
The codec compresses and decompresses voice signals
for efficient digital storage of voice messages. The codec
operates at 28.8k, 21.6k, or 14.4k bps (4-bit, 3-bit, or 2-bit
quantization, respectively) with a 7.2 kHz or 8.0 kHz
sample rate.
A voice pass-through mode allows the host to transmit
and receive uncompressed voice samples in 16-bit linear
form at 7.2 kHz, 8.0 kHz, or 11.025 kHz sample rate, or in
8-bit A-Law/µ-Law PCM form at 8.0 kHz sample rate.
SP models support position-independent full-duplex
speakerphone (FDSP) operation using a dual internal
integrated analog circuit to interface with the telephone
line and the audio input/out (i.e., a headset, handset, or a
microphone with external speaker).
SP models in 144-pin TQFP also support a 4-line voice
serial interface used to transfer 16-bit linear or 8-bit ALaw/µ-Law PCM FDSP voice samples with acoustic echo
cancellation to and from the host.
SP models also support AudioSpan (analog simultaneous
audio/voice and data) operation at a data rate of 4.8 kbps.
The MDP operates over the public switched telephone
network (PSTN) through the appropriate line termination.
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Features
• Downloadable MDP code from the host/DTE
• 2-wire full-duplex
− V.90 and K56flex (RP56 models)
− V.34 (33.6 kbps) (RP56 and RP336 models)
− V.32 bis, V.32, V.22 bis, V.22, V.23, and V.21
− Bell 212 and 103
• 2-wire half-duplex
− V.34 fax, V.17, V.33, V.29, V.27 ter, and V.21 ch 2
− Bell 208
− Short train option in V.17 and V.27 ter
• Serial synchronous and asynchronous data
• Parallel synchronous and asynchronous data
• Parallel synchronous SDLC/HDLC support
• In-band secondary channel (V.34 and V.32 bis)
• Automatic mode selection (AMS)
• Automatic rate adaption (ARA)
• Digital near-end and far-end echo cancellation
• Bulk delay for satellite transmission
• ADPCM voice mode (7.2 kHz or 8.0 kHz)
• Voice pass-through mode (7.2 kHz, 8.0 kHz, or 11.025 kHz)
• Full-duplex speakerphone (SP models)
− Acoustic and line echo cancellation
− Programmable microphone AGC
− Microphone volume selection and muting
− Speaker volume control and muting; room monitor
• Voice serial data interface (144-pin TQFP, SP models)
− 16-bit linear or 8-bit A-Law/µ-Law PCM voice
samples
− FDSP support with acoustic echo cancellation
• AudioSpan (SP models)
− ITU-T V.61 modulation (4.8 kbps data plus audio)
− Handset, headset, or half-duplex speakerphone
• TTL and CMOS compatible DTE interface
− ITU-T V.24 (EIA/TIA-232-E) (data/control)
− Microprocessor bus (data/configuration/control)
• Dynamic range: -9 dBm to -43 dBm
• Adjustable speaker output to monitor received signal
• DMA support interrupt lines
• Transmit and receive (16+128)-byte FIFO data buffers
• NRZI encoding/decoding
• 511 pattern generation/detection
• V.8 and V.8 bis signaling
• V.13 signaling
• Diagnostic capability
− V.54 inter-DCE signaling
− V.54 local analog and remote digital loopback
• +3.3V operation with +5V tolerant inputs
− +5V or +3.3V analog signal interface
• Low power consumption:
− Normal Mode = 260 mW; Sleep Mode = 40 mW
• Low profile, small footprint package
− 100-pin PQFP or 144-pin TQFP
− Meets PC Card Type II envelope requirements
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Information provided by CONEXANT SYSTEMS, INC. is believed to be accurate and reliable. However, no responsibility is assumed by CONEXANT for its use, nor
any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of
CONEXANT other than for circuitry embodied in CONEXANT products. CONEXANT reserves the right to change circuitry at any time without notice. This document
is subject to change without notice.
K56flex is a trademark of CONEXANT SYSTEMS, INC. and Lucent Technologies.
CONEXANT and “What's Next in Communications Technologies” are trademarks of CONEXANT SYSTEMS, INC.
©1998, CONEXANT SYSTEMS, INC.
Printed in U.S.A.
All Rights Reserved
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Technical Description
The MDP functional interface is illustrated in Figure 1.
Configurations and Rates
The selectable MDP configurations, signaling rates, and
data rates are listed in Table 2.
~RDCLK
CLKIN**
TDCLK
CLOCK
CIRCUIT
XTCLK
TXD
V.24
SERIAL
DTE
INTERFACE
XTLI**
XTLO**
RXD
~RTS
CRYSTAL
CIRCUIT
~CTS
~RLYA
~DTR
~DSR
~RLYB
~RLSD
RINGD
~RI
~READ
~WRITE
DATA BUS (8) D0-D7
ADDRESS BUS (5) A0-A4
HOST
PROCESSOR
MODEM DATA PUMP
(MDP)
[R6785: 144-PIN TQFP
R6764: 100-PIN PQFP]
RXA
RIN
TXA
TXA1
TXA2
MICM
SPK
TELEPHONE LINE/
TELIN
TELEPHONE/
TELEPHONE
AUDIO INTERFACE TELOUT
LINE
INTERFACE
SPKMD
RS0-RS4
MIC
MICV/NC*
SPKR
TELIN/NC*
DECODER
~CS
TELEPHONE
LINE
MIC/
SPEAKER
TELOUT/NC*
IRQ
~RESET
VGG (+5V OR 3.3V)
VCC (+3.3V)
VAA (+3.3V)
SR8OUT***
HOST
PROCESSOR
AGND
SR8IN***
POWER
SUPPLY
DGND
SR4CLK***
SA4CLK***
*
PINS ARE INTERNAL NO CONNECT (NC) ON NON-SP MODELS.
** SEPARATE PINS FOR CLOCK AND CRYSTAL INPUT ON R6785 144-PIN TQFP WITH USE DETERMINED BY INPUT CONTROL SIGNAL;
R6764 100-PIN PQFP SUPPORTS CLOCK INPUT ONLY.
*** VOICE SERIAL INTERFACE SUPPORTED FOR R6785 144-PIN SP MODEL.
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V.90/K56flex PCM*
PCM
–
V.34 33600 TCM**
V.34 31200 TCM**
V.34 28800 TCM**
V.34 26400 TCM**
V.34 24000 TCM**
V.34 21600 TCM**
V.34 19200 TCM**
V.34 16800 TCM**
V.34 14400 TCM**
V.34 12000 TCM**
V.34 9600 TCM**
V.34 7200 TCM**
V.34 4800 TCM**
V.34 2400 TCM**
V.32 bis 14400 TCM
V.32 bis 12000 TCM
V.32 bis 9600 TCM
V.32 bis 7200 TCM
V.32 bis 4800
V.32 9600 TCM
V.32 9600
V.32 4800
V.22 bis 2400
V.22 bis 1200
V.22 1200
V.22 600
V.23 1200/75
V.21
Bell 208 4800
Bell 212A
Bell 103
V.23 1200/75
V.21
TCM
TCM
TCM
TCM
TCM
TCM
TCM
TCM
TCM
TCM
TCM
TCM
TCM
TCM
TCM
TCM
TCM
TCM
QAM
TCM
QAM
QAM
QAM
DPSK
DPSK
DPSK
FSK
FSK
DPSK
DPSK
FSK
FSK
FSK
TCM
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
1800
1800
1800
1800
1800
1800
1800
1800
1200/2400
1200/2400
1200/2400
1200/2400
1700/420
1080/1750
1800
1200/2400
1170/2125
1700/420
1080/1750
1800
56000R/V.34ratesT4
33600
31200
28800
26400
24000
21600
19200
16800
14400
12000
9600
7200
4800
2400
14400
12000
9600
7200
4800
9600
9600
4800
2400
1200
1200
600
1200/75
0–300
4800
1200
0–300
1200/75
0–300
14400
V.17 14400 TCM/V.333
V.17 12000 TCM/V.333
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Dynamic
–
–
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
2400
2400
2400
2400
2400
2400
2400
2400
600
600
600
600
1200
300
1600
600
300
1200
300
2400
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
6
5
4
3
2
4
4
2
4
2
2
1
1
1
3
2
1
1
1
6
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
128
64
32
16
4
32
16
4
16
4
4
4
–
–
8
4
–
–
–
128
TCM
1800
12000
2400
5
1
64
V.17 9600 TCM3
V.17 7200 TCM3
TCM
1800
9600
2400
4
1
32
TCM
1800
7200
2400
3
1
16
V.29 96003
V.29 72003
QAM
1700
9600
2400
4
0
16
QAM
1700
7200
2400
3
0
8
V.29 48003
V.27 48003
QAM
1700
4800
2400
2
0
4
DPSK
1800
4800
1600
3
0
8
V.27 24003
DPSK
1800
2400
1200
2
0
4
FSK
1750
300
300
1
0
–
–
–
–
–
–
–
V.21 Channel 23
Tone Transmit
–
Notes:
1. Modulation legend:
TCM: Trellis-Coded Modulation
FSK: Frequency Shift Keying
2. Adaptive; established during handshake:
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QAM: Quadrature Amplitude Modulation
DPSK: Differential Phase Shift Keying
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3. Models with fax support only.
4. Maximum data rate.
* RP56 models only.
** RP56 and RP336 models only.
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Automatic Mode Selection
When automatic mode selection (AMS) is enabled, the
MDP configures itself to the highest compatible data rate
supported by the remote modem (AUTO bit). Automode
operation is supported in V.90, K56flex, V.34, V.32 bis,
V.32 V.22 bis, V.22, V.21, V.23, Bell 212A, and Bell 103
modes.
Automatic Rate Adaption (ARA)
In V.90, K56flex, V.34, and V.32 bis modes, automatic
rate adaption (ARA) can be enabled to select the highest
data rate possible based on the measured eye quality
monitor (EQM) (EARC bit). This selection occurs during
handshake/retrain and rate renegotiation.
Tone Generation
The MDP can generate single or dual voice-band tones
from 0 Hz to 3600 Hz with a resolution of 0.15 Hz and an
accuracy of ± 0.01%. Tones over 3000 Hz are attenuated.
DTMF tone generation allows the MDP to operate as a
programmable DTMF dialer.
Data Encoding
The data encoding conforms to ITU-T recommendations
V.90, V.34, V.32 bis, V.32, V.17, V.33, V.29, V.27 ter,
V.22 bis, V.22, V.23, or V.21, and is compatible with Bell
208, 212A, or 103, depending on the model and selected
configuration.
RTS - CTS Response Time
The response times of CTS relative to a corresponding
transition of RTS are listed in Table 3.
Transmit Level
The transmitter output level is selectable from -4 dBm to
-19 dBm (VAA = +3.3V) or 0 dBm to -15 dBm (VAA = +5V)
in 1 dB steps and is accurate to ±0.5 dB when used with
an external hybrid. The output level can also be fine tuned
by changing a gain constant in MDP DSP RAM. The
maximum V.34/V.32 bis/V.32 transmit level for acceptable
receive performance should not exceed -9 dBm.
Note: In V.34 mode, the transmit level may be
automatically changed during the handshake. This
automatic adjustment of the transmit level may be
disabled via a parameter in DSP RAM.
Transmitter Timing
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RTS-CTS Response1
Constant
Carrier
Controlled
Carrier
Turn-Off
Sequence3
± 2 ms
N/A
N/A
V.33/V.17 Long
N/A
1393 ms2
15 ms4
V.33/V.17 Short
N/A
142 ms2
15 ms4
V.29
N/A
253 ms2
12 ms
V.27 4800 Long
N/A
708 ms2
7 ms4
V.27 4800 Short
N/A
50 ms2
7 ms4
V.27 2400 Long
N/A
943 ms2
10 ms4
V.27 2400 Short
N/A
67 ms2
10 ms4
± 2 ms
270 ms
N/A
Configuration
V.90, K56flex, V.34,
V.32 bis, V.32
V.22 bis, V.22,
Bell 212A
V.21
500 ms
500 ms
N/A
V.23, Bell 103
210 ms
210 ms
N/A
Notes:
1. Times listed are CTS turn-on. The CTS OFF-to-ON
response time is host programmable in DSP RAM. (Fullduplex modes only.)
2. Add echo protector tone duration plus 20 ms when echo
protector tone is used during turn-on.
3. Turn-off sequence consists of transmission of remaining
data and scrambled ones for controlled carrier operation.
CTS turn-off is less than 2 ms for all configurations.
4. Plus 20 ms of no transmitted energy.
5. N/A = not applicable.
Receive Level
The MDP satisfies performance requirements for received
line signal levels from –9 dBm to –43 dBm measured at
the Receiver Analog (RXA) (TIP and RING) input (-15
dBm at RIN).
Note: A 6 dB pad is required between TIP and RING and
the RIN input.
Receiver Timing
Transmitter timing is selectable between internal
(±0.01%), external, or slave.
The timing recovery circuit can track a frequency error in
the associated transmit timing source of ±0.035% (V.22
bis) or ±0.01% (other configurations).
Scrambler/Descrambler
Carrier Recovery
A self-synchronizing scrambler/descrambler is used in
accordance with the selected configuration.
The carrier recovery circuit can track a ±7 Hz frequency
offset in the received carrier.
Answer Tone
Clamping
When the NV25 bit is a zero, the MDP generates a 2100
Hz answer tone at the beginning of the answer handshake
for 5.0 seconds (V.8) or 3.6 seconds (V.32 bis, V.32, V.22
bis, V.22, V.23, and V.21). The answer tone has 180°
phase reversals every 0.45 second to disable network
echo cancellers (V.8, V.32 bis, V.32).
Received Data (RXD) is clamped to a constant mark
whenever the Received Line Signal Detector (~RLSD) is
off. ~RLSD can be clamped off (RLSDE bit).
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Echo Canceller
A data echo canceller with near-end and far-end echo
cancellation is included for 2-wire full-duplex
V.34/V.32 bis/V.32 operation. The combined echo span of
near and far cancellers can be up to 40 ms. The
proportion allotted to each end is automatically
determined by the MDP. The delay between near-end and
far-end echoes can be up to 1.2 seconds.
V.90 and K56flex echo cancellation is also provided.
ADPCM Voice Mode
The Adaptive Differential Pulse Code Modulation
(ADPCM) voice coder and decoder (codec) compresses
and decompresses voice signals for efficient digital
storage of voice messages. The codec operates at 28.8k,
21.6k, or 14.4k bps (4-bit, 3-bit, or 2-bit quantization,
respectively) with a 7.2 kHz or 8.0 kHz sample rate.
Transmit Voice. 16-bit compressed transmit voice can be
sent to the MDP ADPCM codec for decompression then to
the digital-to-analog converter (DAC) by the host.
Receive Voice. 16-bit received voice samples from the
MDP analog-to-digital converter (ADC) can be sent to the
ADPCM codec for compression, and then be read by the
host.
Voice Pass-Through Mode
Voice pass-through mode allows the host to transmit and
receive uncompressed voice samples in 16-bit linear form
at 7.2 kHz, 8.0 kHz, or 11.025 kHz sample rate, or in 8-bit
A-Law/µ-Law PCM form at 8.0 kHz sample rate.
Voice Serial Interface (SP models in 144-Pin TQFP)
A 4-pin serial interface supports the transfer of 16-bit
linear or 8-bit A-Law/µ-Law PCM voice samples in fullduplex speakerphone form with acoustic echo
cancellation to and from the host. These signals can be
used in concurrent voice and data applications such as
host-controlled DSVD by the host. Signals supported are
Serial Data Output (S8OUT), Serial Data In (SR8IN),
Serial Shift Clock (SR4CLK), and Sample Shift Clock
(SA4CLK).
Analog voice on the MICV input pin is converted to 16-bit
linear or 8-bit A-Law/µ-Law PCM digital voice samples
and output on the SR8OUT pin to the host. Digital voice in
16-bit linear or 8-bit A-Law/µ-Law PCM form is received
from the host on the SR8IN pin, converted to analog form
and routed to the SPK output pin. SA4CLK provides the
bit clock used to shift data bits in on the SR8IN pin and
out on the SR8OUT pin. SR8CLK provides the frame
clock used to synchronize words shifted in on the SR8IN
pin and shifted out on the SR8OUT pin.
AudioSpan Mode (SP Models)
AudioSpan provides full-duplex analog simultaneous
audio/voice and data over a single telephone line at a
data rate with audio of 4800 bps using V.61 modulation.
AudioSpan can send any type of audio waveform,
including music. Data can be sent with or without error
correction. The audio/voice interface can be in the form of
a headset, handset, or a microphone and speaker (halfduplex speakerphone). Handset echo cancellation is
provided.
Transmit Voice. Transmit voice samples can be sent to
the MDP DAC from the host.
Data Formats
Receive Voice. Received voice samples from the MDP
ADC can be read by the host.
Data rate:
Serial Synchronous Data
Speakerphone Voice/Audio Paths (SP Models)
The MDP incorporates a dual integrated analog interface.
The voice/audio transmit and receive signals can be
routed through several paths. The voice/audio paths are
available in the speakerphone mode configuration and are
selected through DSP RAM.
Selectable clock: Internal, external, or slave.
Serial Asynchronous Data
Data rate:
The voice/audio input can be taken from one of four
different sources: telephone line input (RIN), handset
(TELIN), microphone (MICM or MICV).
The speaker output (SPK) can originate from one of five
different sources: RIN, TELIN, MICM or MICV or from the
MDP’s internal voice playback mode.
The voice/audio output may be routed to the telephone
line output (TXA1 and TXA2) or handset (TELOUT).
The voice paths can be switched to allow an audio input
to be routed to the telephone line output through a
variable gain for applications such as music-on-hold.
The “room monitor” mode allows the MDP to receive
audio from its surroundings and concurrently transmit the
audio to a remote site.
300-56000 bps (RP56), 300-33600 bps
(RP56 and RP336), or 300-14400 bps,
±0.01%.
300-56000 bps (RP56), 300-33600 bps
(RP56 and RP336), or 300-14400 bps,
+1% (or +2.3%), -2.5%;
0-300 bps (V.21 and Bell 103);
1200/75 bps (V.23).
Bits per character: 7, 8, 9, 10, or 11.
Parallel Synchronous Data
Normal sync: 8-bit data for transmit and receive
Data rate:
300-56000 bps (RP56), 300-33600 bps
(RP56 and RP336), or 300-14400 bps,
±0.01%.
SDLC/HDLC support:
Transmitter: Flag generation, 0 bit stuffing,
CRC-16 or CRC-32 generation.
Receiver:
Flag detection, 0 bit deletion,
CRC-16 or CRC-32 checking.
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Parallel Asynchronous Data
Supervisory Tone Detection
Data rate:
300-56000 bps (RP56), 300-33600 bps
(RP56 and RP336), or 300-14400 bps,
+1% (or 2.3%), -2.5%;
Three parallel tone detectors (A, B, and C) are provided
for supervisory tone detection. The signal path to these
detectors is separate from the main received signal path.
1200, 300, or 75 bps (FSK).
Each tone detector consists of two cascaded second
order IIR biquad filters. The coefficients are host
programmable. Each fourth order filter is followed by a
level detector which has host programmable turn-on and
turn-off thresholds allowing hysteresis. Tone detector C is
preceded by a prefilter and squarer. This circuit is useful
for detecting a tone with frequency equal to the difference
between two tones that may be simultaneously present on
the line. The squarer may be disabled by the SQDIS bit
causing tone detector C to be an eighth order filter. The
tone detectors are disabled in data mode.
Data bits per character: 5, 6, 7, or 8.
Parity generation/checking: Odd, even, or 9th data bit.
Async/Sync and Sync/Async Conversion
An asynchronous-to-synchronous converter is provided in
the transmitter and a synchronous-to-asynchronous
converter is provided in the receiver. The converters
operate in both serial and parallel modes. The
asynchronous character format is 1 start bit, 5 to 8 data
bits, an optional parity bit, and 1 or 2 stop bits. Valid
character size, including all bits, is 7, 8, 9, 10, or 11 bits
per character. Two ranges of signaling rates are provided:
• Basic range: +1% to –2.5%
• Extended overspeed range: +2.3% to –2.5%
When the transmitter's converter is operating at the basic
signaling rate, no more than one stop bit will be deleted
per 8 consecutive characters. When operating at the
extended rate, no more than one stop bit will be deleted
per 4 consecutive characters. Break handling is
performed as described in V.14.
Asynchronous characters are accepted on the TXD serial
input and are issued on the RXD serial output.
V.54 Inter-DCE Signaling
The MDP supports V.54 inter-DCE signaling procedures
in synchronous and asynchronous configurations.
Transmission and detection of the preparatory,
acknowledgment, and termination phases as defined in
V.54 are provided. Three control bits in the transmitter
allow the host to send the appropriate bit patterns (V54T,
V54A, and V54P bits). Three control bits in the receiver
are used to enable one of three bit pattern detectors
(V54TE, V54AE, and V54PE bits). A status bit indicates
when the selected pattern detector has found the
corresponding bit pattern (V54DT bit).
V.13 Remote RTS Signaling
The MDP supports V.13 remote RTS signaling.
Transmission and detection of signaling bit patterns in
response to a change of state in the RTS bit or the ~RTS
input signal are provided. The RRTSE bit enables V.13
signaling. The RTSDE bit enables detection of V.13
patterns. The RTSDT status bit indicates the state of the
remote RTS signal. This feature may be used to
clamp/unclamp the local ~RLSD and RXD signals in
response to a change in the remote RTS signal in order to
simulate controlled carrier operation in a constant carrier
environment. The MDP automatically clamps and
unclamps ~RLSD.
Dialing and Answering
The host can dial and answer using supported
DTMF/pulse dialing and tone detection functions. The
major parameters are host programmable.
0'
The tone detection sample rate is 9600 Hz in V.8 and
V.34 modes and is 7200 Hz in non-V.34 modes. The
default call progress filter coefficients are based on a
7200 Hz sampling rate and apply to non-V.34 modes only.
The maximum detection bandwidth is equal to one-half
the sample rate.
The default bandwidths and thresholds of the tone
detectors are:
Tone Detector
Bandwidth
Turn-On
Threshold
Turn-Off
Threshold
A
245 – 650 Hz
–25 dBm
–31 dBm
B
360 – 440 Hz
–25 dBm
–31 dBm
C Prefilter
0 – 500 Hz
N/A
N/A
C
50 – 110 Hz
*
*
* Tone Detector C will detect a difference tone within its
bandwidth when the two tones present are in the range –1 dBm
to –26 dBm.
511 Pattern Generation/Detection
In synchronous mode, a 511 pattern can be generated
and detected (control bit S511). Use of this bit pattern
during self-test eliminates the need for external test
equipment.
In-Band Secondary Channel
A full-duplex in-band secondary channel is provided in
V.34 (all speeds) and V.32 bis/V.32 (7200 bps and above)
modes. Control bit SECEN enables and disables the
secondary channel operation. The secondary channel
operates in parallel data mode with independent transmit
and receive interrupts and data buffers. The main channel
may operate in parallel or serial mode.
In V.34 modes, the secondary channel rate is 200 bps.
In V.32 bis/V.32 modes, the secondary channel rate is
150 bps. This rate is also host programmable in V.32
bis/V.32 modes.
Transmit and Receive FIFO Data Buffers
Two (16+128)-byte first-in first-out (FIFO) data buffers
allow the DTE/host to rapidly output up to 144 bytes of
transmit data and input up to 144 bytes of accumulated
received data. The receiver FIFO is always enabled. The
transmitter FIFO is enabled by the FIFOEN control bit.
TXHF and RXHF bits operate off the lower 16 bits and
53/'53/'DQG53/'
/RZ9ROWDJH9.IOH[99ELV/RZ3RZHU0RGHP'DWD3XPSV
indicate the corresponding FIFO buffer half full (8 or more
bytes loaded) status. TXFNF and RXFNE bits indicate the
TXFIFO buffer not full and RXFIFO buffer not empty
status, respectively. An interrupt mask register allows an
interrupt request to be generated whenever the TXFNF,
RXFNE, RXHF, or TXHF status bit changes state. The
128-byte FIFO extensions are enabled by default and can
be disabled by clearing a bit in RAM.
external amplifier is recommended if driving non-amplified
speakers.
DMA Support Interrupt Request Lines
Additional information is provided in the RP56LD,
RP336LD, and RP144LD Modem Designer's Guide (Order
No. 1155).
DMA support is available in synchronous, asynchronous,
and HDLC parallel data modes. Control bit DMAE enables
and disables DMA support. When DMA support is
enabled, the MDP ~RI and ~DSR lines are assigned to
Transmitter Request (TXRQ) and Receiver Request
(RXRQ) hardware output interrupt request lines,
respectively. The TXRQ and RXRQ signals follow the
assertion of the TDBE and RDBF interrupt bits thus
allowing the DTE/host to respond immediately to the
interrupt request without masking out status bits to
determine the interrupt source.
A digital speaker output (SPKMD) is provided which
reflects the received analog input signal digitized to TTL
high or low level by an internal comparator to create a PC
Card (PCMCIA)-compatible signal.
Additional Information
Hardware Interface Signals
A functional interconnect diagram showing the typical
MDP connection in a system is illustrated in Figure 2. Any
point that is active low is represented by a small circle at
the signal point.
Edge triggered inputs are denoted by a small triangle
(e.g., TDCLK). An active low signal is indicated by a tilde
preceding the signal name (e.g., ~RESET).
NRZI data encoding/decoding may be selected in
synchronous and HDLC modes instead of the default NRZ
(control bit NRZIEN). In NRZ encoding, a 1 is represented
by a high level and a 0 is represented by a low level. In
NRZI encoding, a 1 is represented by no change in level
and a 0 is represented by a change in level.
A clock intended to activate logic on its rising edge (lowto-high transition) is called active low (e.g., ~RDCLK),
while a clock intended to activate logic on its falling edge
(high-to-low transition) is called active high (e.g., TDCLK).
When a clock input is associated with a small circle, the
input activates on a falling edge. If no circle is shown, the
input activates on a rising edge.
ITU-T CRC-32 Support
The 144-pin TQFP MDP hardware interface signals are
shown Figure 2.
ITU-T CRC-32 generation/checking may be selected
instead of the default ITU-T CRC-16 in HDLC mode using
DSP RAM access.
The 144-pin TQFP MDP signal pin assignments are
shown Figure 3 and are listed in Table 4.
NRZI Encoding/Decoding
Caller ID Demodulation
Caller ID information can be demodulated in V.23 1200
receive configuration and presented to the host/DTE in
serial (RXD) and parallel (RBUFFER) form.
Telephone Line Interface
Line Transformer Interface. V.90/K56flex/V.34/V.32
bis/V.32 places high requirements upon the Data Access
Arrangement (DAA) to the telephone line. Any non-linear
distortion generated by the DAA in the transmit direction
cannot be canceled by the MDP's echo canceller and
interferes with data reception. The designer must,
therefore, ensure that the total harmonic distortion seen at
the RXA input to the MDP be at least 65 dB below the
minimum level of received signal. Due to the wider
bandwidth requirements in V.90, K56flex, and V.34, the
DAA must maintain linearity from 10 Hz to 4000 Hz.
The 100-pin PQFP MDP hardware interface signals are
shown Figure 4.
The 100-pin PQFP MDP signal pin assignments are
shown Figure 5 and are listed in Table 5.
The MDP hardware interface signals are described in
Table 6.
The digital interface characteristics are defined in Table 7.
The analog interface characteristics are defined Table 8.
The power requirements are defined in Table 9.
The absolute maximum ratings are defined in Table 10.
Relay Control. Direct control of the off-hook and talk/data
relays is provided. Internal relay drivers allow direct
connection to the off-hook (RLYA) and talk/data (RLYB)
relays. The talk/data relay output can optionally be used
for pulse dial.
Speaker Interface
An analog speaker output (SPK) is provided with on/off
and volume control logic incorporated in the MDP. An
0'
/RZ9ROWDJH9.IOH[99ELV/RZ3RZHU0RGHP'DWD3XPSV
122
123
7
144
1
3
4
6
8
9
10
11
12
64
65
66
67
68
69
MCU
EXTERNAL
BUS
130
72
86
32
MCU: IRQ
MCU: ~WKRESOUT
MCU: ~RESET
115
NOXTL 140
CLKIN
141
XTLI
56.448 MHz/
28.224 MHz
143
XTLO
YCLK
XCLK
SYCLK
D0
D1
D2
D3
D4
D5
D6
D7
RS0
RS1
RS2
RS3
RS4
~CS
~WRITE
~READ
HOST
VOICE SERIAL
INTERFACE
~RLYA
~RLYB
RINGD
RIN
TXA1
TXA2
TELIN/NC*
TELOUT/NC*
MICV/NC*
MICM
SPK
SPKMD
MICBIAS
IRQ
~WKRES
~RES1
~RES2
134
71
76
108
77
111
129
78
112
125
75
127
GPO0
~RDCLK
TDCLK
XTCLK
TXD
RXD
~RTS
~CTS
~DTR
~DSR
~RLSD
~RI
100
99
98
97
SR8OUT
SR8IN
SR4CLK
SA4CLK
74
NC
+5V/+3.3V
(HIGHEST AVAILABLE)
117
+3.3V
0.1
10
37
50
79
107
137
138
52
60
84
109
121
132
PROVIDE DIRECT CONNECTION OR
FERRITE BEAD BETWEEN GND AND AGND,
WHICHEVER ACHIEVES LOWEST NOISE
FLOOR.
~SET3V
10µH
23
0.022
VGG
AVDD
AVDD
VDD
VDD
VDD
VDD
VC
PLLVDD
* PINS ARE INTERNAL NO CONNECT (NC) ON
NON-SP MODELS.
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
63
80
82
101
102
105
110
114
116
118
119
120
126
131
135
136
15pF (56.448 MHz)/
56pF (28.224 MHz) 5%
40
TELEPHONE LINE/
TELEPHONE/
AUDIO
INTERFACE
AGND (VAA = +3.3V OR NC (VAA = +5V)
27
10
0.1 CER
10
0.1 CER
28
DAA FOR EXTERNAL VC USE
PLLGND
SLEEPO
IASLEEP
GND
GND
GND
GND
GND
GND
MCLKIN
MTXSIN
MRXOUT
MSTROBE
MSCLK
MCNTRLSIN
SR1IO
IA1CLK
SA1CLK
SR4IN
SR4OUT
AVAA
10
13
+3.3V (VDD)
10
NOTE DIFFERENCES IN VC AND PLLVDD,
CIRCUIT GND/AGND CONNECTIONS FOR
144-PIN TQFP AND AND 100-PIN PQFP.
61
NC
NC
NC
NC
NC
NC
NC
NC
* COMPONENT VALUES SHOWN IN THE CRYSTAL CIRCUIT ARE
TYPICAL AND MAY REQUIRE SLIGHTLY DIFFERENT VALUES TO
COMPENSATE FOR STRAY CAPACITANCE AND CRYSTAL
CHARACTERISTIC DIFFERENCES.
IT IS GOOD PRACTICE TO TUNE THE CRYSTAL FREQUENCY
WITHIN +/- 0.002% TOLERANCE AT ROOM TEMPERATURE.
THE TDCLK CLOCK MAY BE MEASURED FOR ACCURACY IN ORDER
NOT TO AFFECT THE OSCILLATOR WITH PROBE CAPACITANCE.
THE DEFAULT TDCLK FREQUENCY IS 14.4 KHZ. ADJUST THE LOAD
CAPACITORS EQUALLY SUCH THAT TDCLK IS WITHIN 14.4 KHZ +/- 0.3 HZ.
113
59
43
44
46
47
45
42
106
94
93
89
87
91
CLKOUT
88
SR3OUT
90
SR3IN
103
SA2CLK
73
SR2CLK
104
SR2IO
AGND
AGND
AGND
AGND
AGNDM
VCNTRLSIN/NC*
21
51
48
35
128
30
25
26
20
22
29
33
24
36
34
RESERVED 139
96
RESERVED
62
RESERVED
RESERVED 124
95
RESERVED
92
RESERVED
38
RESERVED/NC*
39
RESERVED/NC*
10
14
18
19
49
31
10pF (56.448 MHz)/
18pF (28.224 MHz)
5% *
MK4 133
85
MK5
FB
+5V OR +3.3V
(+5V RECOMMENDED)
0.1
TIRO2
4.7µH
10%
10pF (56.448 MHz)/
18pF (28.224 MHz) 5% *
VREF
SERIAL
DTE
INTERFACE
53/'53/'DQG53/'
AGNDV/NC* VSCLK/NC*
VSTROBE/NC*
VSUB
VRXOUT/NC*
VTXSIN/NC*
RESERVED VCLKIN/NC*
RESERVED
RESERVED
RESERVED RESERVED
RESERVED RESERVED
NC
RESERVED
NC
RESERVED
NC
RESERVED
NC
RESERVED
NC
RESERVED
NC
RESERVED
NC
RESERVED
NC
RESERVED
RESERVED
RESERVED
RESERVED
58
55
53
54
56
57
2
5
15
16
17
41
70
81
83
142
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NOTES:
1. TOLERANCES AND RATINGS (UNLESS OTHERWISE
SPECIFIED):
RESISTOR VALUES IN OHMS; 5%, 1/8W
CAPACITOR VALUES IN MICROFARADS; 10%, 20V
2.
DENOTES ANALOG GROUND.
3.
DENOTES DIGITAL GROUND.
MD212F2 HIS
)LJXUH 0'3 +DUGZDUH ,QWHUIDFH 6LJQDOV3LQ 74)3
0'
~DTR
RXD
RESERVED
GND
112
111
110
109
RESERVED
SLEEPO
114
113
RESERVED
NOXTL
116
115
RESERVED
VGG
118
117
RESERVED
RESERVED
120
119
YCLK
GND
122
121
RESERVED
XCLK
124
123
RESERVED
~DSR
126
125
RINGD
~RI
128
127
IRQ
~RTS
130
129
GND
RESERVED
132
131
GP00
MK4
134
133
RESERVED
RESERVED
136
135
VDD
VDD
138
/RZ9ROWDJH9.IOH[99ELV/RZ3RZHU0RGHP'DWD3XPSV
137
CLKIN
RESERVED
140
139
NC
XTLI
142
141
D0
XTLO
144
143
53/'53/'DQG53/'
D1
1
108
XTCLK
RESERVED
2
107
VDD
D2
3
106
SR1IO
D3
4
105
RESERVED
RESERVED
5
104
SR2IO
D4
6
103
SA2CLK
SYCLK
7
102
RESERVED
D5
8
101
RESERVED
D6
9
100
D7
10
99
SR8OUT
SR8IN
RS0
11
98
SR4CLK
RS1
12
97
SA4CLK
PLLVDD
13
96
RESERVED
AGND
14
95
RESERVED
NC
15
94
IA1CLK
NC
16
93
SA1CLK
NC
17
92
RESERVED
AGND
18
91
CLKOUT
AGND
19
90
SR3IN
TELIN/NC*
20
89
SR4IN
AGNDV/NC*
21
88
SR3OUT
TELOUT/NC*
22
87
SR4OUT
AVAA
23
86
~RES1
SPK
24
85
MK5
TXA1
25
84
GND
TXA2
26
83
NC
VREF
27
82
RESERVED
VC
28
81
NC
MICV/NC*
29
80
RESERVED
RIN
30
79
VDD
AGNDM
31
78
~CTS
~RES2
32
77
TXD
MICM
33
76
TDCLK
MICBIAS
34
75
~RLSD
69
70
71
72
~READ
NC
~RDCLK
~WKRES
67
68
~CS
~WRITE
65
66
RS3
RS2
RS4
63
64
RESERVED
61
62
GND
PLLGND
59
60
IASLEEP
RESERVED
57
58
VCLKIN/NC*
VCNTRLSIN/NC*
55
56
VSCLK/NC*
VTXSIN/NC*
53
54
VRXOUT/NC*
GND
VSTROBE/NC*
51
52
VSUB
49
50
AVDD
~RLYA
AGND
47
48
MSTROBE
45
46
MSCLK
MRXOUT
43
44
MCLKIN
MTXSIN
41
42
NC
~SET3V
MCNTRLSIN
39
40
~VRLYB/NC*
37
TIRO2
SR2CLK
38
74
73
AVDD
35
36
~VRLYA/NC*
~RLYB
SPKMD
* NC ON NON-SP MODELS.
MD212F3 PO-R6785-144T
)LJXUH 0'3 3LQ 6LJQDOV 3LQ 74)3
0'
/RZ9ROWDJH9.IOH[99ELV/RZ3RZHU0RGHP'DWD3XPSV
53/'53/'DQG53/'
7DEOH 0'3 3LQ 6LJQDOV 3LQ 74)3
Pin
Signal Label
1
2
3
4
5
6
7
8
9
10
11
12
13
D1
RESERVED
D2
D3
RESERVED
D4
SYCLK
D5
D6
D7
RS0
RS1
PLLVDD
IA/OB
OA
IA/OB
IA/OB
IA/OB
IA
IA
PLL
14
AGND
15
16
17
18
19
NC
NC
NC
AGND
AGND
20
21
22
23
24
25
26
27
28
29
30
31
32
TELIN/NC*
AGNDV/NC*
TELOUT/NC*
AVAA
SPK
TXA1
TXA2
VREF
VC
MICV/NC*
RIN
AGNDM
~RES2
I(DA)
GND
O(DD)
PWR
O(DF)
O(DD)
O(DD)
REF
REF
I(DA)
I(DA)
GND
33
34
35
36
37
38
39
40
MICM
MICBIAS
~RLYB
SPKMD
AVDD
RESERVED/NC*
RESERVED/NC*
~SET3V
I(DA)
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
NC
MCNTRLSIN
MCLKIN
MTXSIN
MSCLK
MRXOUT
MSTROBE
~RLYA
AGND
AVDD
VSUB
GND
VSTROBE/NC*
VRXOUT/NC*
VSCLK/NC*
VTXSIN/NC*
VCLKIN/NC*
VCNTRLSIN/NC*
IASLEEP
GND
0'
Interface3
I/O Type
IA/OB
Pin
Signal Label
73
74
75
76
77
78
79
80
81
82
83
84
85
SR2CLK
TIRO2
~RLSD
TDCLK
TXD
~CTS
VDD
RESERVED
NC
RESERVED
NC
GND
MK5
GND
Host Parallel Interface
NC
Host Parallel Interface
Host Parallel Interface
NC
Host Parallel Interface
Controller
Host Parallel Interface
Host Parallel Interface
Host Parallel Interface
Host Parallel Interface
Host Parallel Interface
To +3.3 (VDD) through 10 Ω
and to AGND though10 µF
AGND
86
~RES1
GND
GND
NC
NC
NC
AGND
AGND
87
88
89
90
91
SR4OUT
SR3OUT
SR4IN
SR3IN
CLKOUT
Line/Audio Interface
AGND
Line/Audio Interface
+3.3VA or +5VA
Line/Audio Interface
Line/Audio Interface
Line/Audio Interface
VC through capacitors
DAA; AGND thru capacitors
Line/Audio Interface
Line/Audio Interface
AGND
PIF: ~RESET
SIF: Reset circuit
Line/Audio Interface
MICBIAS circuit
Line/Audio Interface
Line/Audio Interface
+3.3V
NC
NC
AGND (VAA = +3.3V) or NC
(VAA = +5V)
NC
To SR1IO (106)
To CLKOUT (91)
To SR4OUT (87)
To IA1CLK (94)
To SR4IN (89)
To SA1CLK (93)
Line/Audio Interface
AGND
+3.3V
AGND
DGND
To SA2CLK (103)
To SR3IN (90)
To SR2CLK (73)
To SR3OUT (88)
To CLKOUT (91)
To SR2IO (104)
To SLEEPO (113)
DGND
92
93
94
95
96
97
98
99
100
101
102
103
104
RESERVED
SA1CLK
IA1CLK
RESERVED
RESERVED
SA4CLK
SR4CLK
SR8IN
SR8OUT
RESERVED
RESERVED
SA2CLK
SR2IO
105
106
107
108
109
110
111
112
RESERVED
SR1IO
VDD
XTCLK
GND
RESERVED
RXD
~DTR
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
SLEEPO
RESERVED
NOXTL
RESERVED
VGG
RESERVED
RESERVED
RESERVED
GND
YCLK
XCLK
RESERVED
~DSR
RESERVED
~RI
RINGD
~RTS
IRQ
RESERVED
GND
IA/OB
IA/OB
OD
OA
PWR
IA
DI
DI
DI
DI
DI
DI
OD
GND
PWR
GND
GND
DI
DI
DI
DI
DI
DI
DI
GND
I/O Type
DI
IA
OA
OA
IA
OA
PWR
GND
IA
DI
DI
DI
DI
DI
DI
DI
OA
OA
IA
OA
DI
DI
DI
PWR
IA
GND
OA
IA
DI
IA
REF
GND
OA
OA
OA
OA
IA
IA
IA
GND
Interface
To VSCLK (55)
NC
DTE Serial Interface
DTE Serial Interface
DTE Serial Interface
DTE Serial Interface
+3.3V
NC
NC
NC
NC
DGND
PLL Circuit Select (Note 4)
PIF: ~RESET
SIF: Reset circuit
To MTXSIN (44)
To VTXSIN (56)
To MRXOUT (46)
To VRXOUT (54)
To MCLKIN (43) & VCLKIN
(57)
NC
To MSTROBE (47)
To MSCLK (45)
NC
NC
Host Voice Serial Interface
Host Voice Serial Interface
Host Voice Serial Interface
Host Voice Serial Interface
NC
NC
To VSTROBE (53)
To VCNTRLSIN (58)
NC
To MCNTRLSIN (42)
+3.3V
DTE Serial Interface
DGND
NC
DTE Serial Interface
DTE Serial Interface
To IASLEEP (59)
NC
VCC or GND
NC
+5V or +3.3V
NC
NC
NC
DGND
NC
NC
NC
DTE Serial Interface
NC
DTE Serial Interface
Line/Audio Interface
DTE Serial Interface
Host Parallel Interface
NC
DGND
53/'53/'DQG53/'
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Pin
61
62
63
64
65
66
67
68
69
70
71
72
Signal Label
PLLGND
RESERVED
RESERVED
RS2
RS3
RS4
~CS
~WRITE
~READ
NC
~RDCLK
~WKRES
I/O Type
PLL
IA
IA
IA
IA
IA
IA
OA
IA
Interface3
AGND
NC
NC
Host Parallel Interface
Host Parallel Interface
Host Parallel Interface
Host Parallel Interface
Host Parallel Interface
Host Parallel Interface
NC
DTE Serial Interface
MCU: READY/~WKRESOUT
Pin
133
134
135
136
137
138
139
140
141
142
143
144
Signal Label
MK4
GP00
RESERVED
RESERVED
VDD
VDD
RESERVED
CLKIN
XTLI
NC
XTLO
D0
I/O Type
IA
DI
PWR
PWR
IA
I
O
IA/OB
Interface
PLL Circuit Select (Note 4)
To ~RDCLK (71)
NC
NC
+3.3V
+3.3V
NC
Clock Circuit
Crystal Circuit
NC
Crystal Circuit
Host Parallel Interface
Notes:
1.
I/O types:
IA, IB = Digital input; OA, OB = Digital output.
I(DA) = Analog input; O(DD), O(DF) = Analog output.
DI = Device interconnect.
2.
NC = No internal pin connection; RESERVED = No external connection allowed (may have internal connection).
3.
Interface Legend:
MDP = Modem Data Pump
DTE = Data Terminal Equipment
PIF = Parallel host interface
SIF = Serial DTE interface.
4.
An internal 55 kΩ pullup resistor is connected to this pin.
* NC on non-SP models.
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75
76
88
89
90
91
92
93
94
95
96
97
2
3
4
5
6
7
MCU
EXTERNAL
BUS
80
9
36
17
MCU: IRQ
MCU: ~WKRESOUT
MCU: ~RESET
86
CLKIN
YCLK
XCLK
SERIAL
DTE
INTERFACE
28.224 MHz CLOCK
87
NC
D0
D1
D2
D3
D4
D5
D6
D7
RS0
RS1
RS2
RS3
RS4
~CS
~WRITE
~READ
~RLYA
RINGD
RIN
TXA1
TXA2
TELIN/NC*
TELOUT/NC*
MICV/NC*
MICM
SPK
SPKMD
IRQ
~WKRES
~RES2
~RES1
VREF
NC
47
79
35
30
31
26
27
34
37
29
38
TELEPHONE LINE/
TELEPHONE/
AUDIO
INTERFACE
32
10
VC
82
8
12
64
13
67
11
78
0.1 CER
33
DAA FOR EXTERNAL VC USE
10
0.1 CER
10
98
+3.3V (VDD)
10
PLLGND
RESERVED
RESERVED
RESERVED
58
RESERVED RESERVED
RESERVED
71
RESERVED
VGG
RESERVED
RESERVED
RESERVED
40
RESERVED
AVDD
63
RESERVED
VDD
68
RESERVED
VDD
85
RESERVED
VDD
+5V/+3.3V
(HIGHEST AVAILABLE)
+3.3V
0.1
10
16
65
81
99
49
PROVIDE DIRECT CONNECTION OR
FERRITE BEAD BETWEEN GND AND AGND,
WHICHEVER ACHIEVES LOWEST NOISE
FLOOR.
GND
GND
GND
GND
GND
MCLKIN
MTXSIN
MRXOUT
MSTROBE
MSCLK
MCNTRLSIN
FB
10µH
28
+5V OR +3.3V
(+5V RECOMMENDED)
0.1
SLEEPO
IASLEEP
0.022
AVAA
10
25
39
48
* PINS ARE INTERNAL NO CONNECT (NC)
ON NON-SP MODELS.
AGND
AGND
AGND
SR1IO
IA1CLK
SA1CLK
SR4IN
SR4OUT
CLKOUT
SR3OUT
SR3IN
SA2CLK
SR2CLK
SR2IO
VCNTRLSIN/NC*
VSCLK/NC*
VSTROBE/NC*
VRXOUT/NC*
VTXSIN/NC*
VCLKIN/NC*
FB
FERRITE BEADS (70 OHM @ 100 MHZ TYPE
WITH A MAX DC RESISTANCE OF 0.5 OHM
AND A RATED CURRENT OF 200 mA).
FB
GPO0
~RDCLK
TDCLK
XTCLK
TXD
RXD
~RLSD
~RI
PLLVDD
NC
53/'53/'DQG53/'
100
14
15
1
57
61
66
70
72
73
74
77
83
84
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NOTE DIFFERENCES IN VC AND PLLVDD,
CIRCUIT GND/AGND CONNECTIONS FOR
144-PIN TQFP AND AND 100-PIN PQFP.
*** COMPONENT VALUES SHOWN IN THE CRYSTAL CIRCUIT ARE
TYPICAL AND MAY REQUIRE SLIGHTLY DIFFERENT VALUES TO
COMPENSATE FOR STRAY CAPACITANCE AND CRYSTAL
CHARACTERISTIC DIFFERENCES.
IT IS GOOD PRACTICE TO TUNE THE CRYSTAL FREQUENCY
WITHIN +/- 0.002% TOLERANCE AT ROOM TEMPERATURE.
THE TDCLK CLOCK MAY BE MEASURED FOR ACCURACY IN ORDER
NOT TO AFFECT THE OSCILLATOR WITH PROBE CAPACITANCE.
THE DEFAULT TDCLK FREQUENCY IS 14.4 KHZ. ADJUST THE LOAD
CAPACITORS EQUALLY SUCH THAT TDCLK IS WITHIN 14.4 KHZ +/- 0.3 HZ.
69
56
42
43
45
46
44
41
62
24
23
20
18
22
19
21
59
10
60
55
52
50
51
53
54
NOTES:
1. TOLERANCES AND RATINGS (UNLESS OTHERWISE
SPECIFIED):
RESISTOR VALUES IN OHMS; 5%, 1/8W
CAPACITOR VALUES IN MICROFARADS; 10%, 20V
2.
DENOTES ANALOG GROUND.
3.
DENOTES DIGITAL GROUND.
MD212F4-HIS-100PQFP
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PLLGND
GND
PLLVDD
RS1
RS0
D7
D6
D5
D4
D3
D2
D1
D0
NC
CLKIN
VDD
RESERVED
RESERVED
GP00
GND
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
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99
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RS2
1
80
IRQ
2
RINGD
RS3
3
79
78
RS4
~CS
4
77
RESERVED
5
6
76
XCLK
75
YCLK
7
74
RESERVED
~RDCLK
8
73
~WKRES
SR2CLK
~RLSD
9
72
RESERVED
RESERVED
10
71
VGG
11
RESERVED
~WRITE
~READ
~RI
15
16
66
RESERVED
65
GND
~RES1
17
64
XTCLK
SR4OUT
18
63
SR3OUT
SR4IN
19
62
VDD
SR1IO
20
61
RESERVED
SR3IN
21
SR2IO
CLKOUT
22
60
59
SA1CLK
IA1CLK
AGND
23
58
RESERVED
24
25
57
RESERVED
56
IASLEEP
TELIN/NC*
26
55
VCNTRLSIN/NC*
TELOUT/NC*
AVAA
SPKR
TXA1
27
54
VCLKIN/NC*
28
53
29
52
VTXSIN/NC*
VSCLK/NC*
30
51
VRXOUT/NC*
SA2CLK
50
46
MSTROBE
~RLYA
SLEEPO
GND
VSTROBE/NC*
45
MRXOUT
AGND
44
41
MCNTRLSIN
MCLKIN
43
40
AVDD
MTXSIN
MSCLK
39
MICM
SPKMD
AGND
32
RIN
~RES2
31
TXA2
VREF
VC
MICV/NC*
49
RXD
RESERVED
GND
47
48
67
42
14
37
38
VDD
RESERVED
36
68
35
13
34
12
33
TDCLK
TXD
70
69
MD212F5 PO-R6764-100P
* NC on non-SP models.
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Pin
Signal Label
I/O Type
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
RESERVED
RS2
RS3
RS4
~CS
~WRITE
~READ
~RDCLK
~WKRES
SR2CLK
~RLSD
TDCLK
TXD
RESERVED
RESERVED
GND
~RES1
18
19
20
21
22
SR4OUT
SR3OUT
SR4IN
SR3IN
CLKOUT
DI
DI
DI
DI
DI
23
24
25
26
27
28
29
30
31
32
33
SA1CLK
IA1CLK
AGND
TELIN/NC*
TELOUT/NC*
AVAA
SPK
TXA1
TXA2
VREF
VC
DI
DI
GND
I(DA)
O(DD)
PWR
O(DF)
O(DD)
O(DD)
REF
REF
34
35
36
MICV/NC*
RIN
~RES2
I(DA)
I(DA)
37
38
39
40
41
42
43
44
45
46
47
48
MICM
SPKMD
AGND
AVDD
MCNTRLSIN
MCLKIN
MTXSIN
MSCLK
MRXOUT
MSTROBE
~RLYA
AGND
49
50
GND
VSTROBE/NC*
Interface3
I(DA)
OA
GND
PWR
DI
DI
DI
DI
DI
DI
OD
GND
NC
Host Parallel Interface
Host Parallel Interface
Host Parallel Interface
Host Parallel Interface
Host Parallel Interface
Host Parallel Interface
DTE Serial Interface
MCU: READY/~WKRESOUT
To VSCLK (52)
DTE Serial Interface
DTE Serial Interface
DTE Serial Interface
NC
NC
DGND
PIF: ~RESET
SIF: Reset circuit
To MTXSIN (43)
To VTXSIN (53)
To MRXOUT (45)
To VRXOUT (51)
To MCLKIN (42) & VCLKIN
(54)
To MSTROBE (46)
To MSCLK (44)
Analog Ground
Line/Audio Interface
Line/Audio Interface
+3.3VA or +5VA
Line/Audio Interface
Line/Audio Interface
Line/Audio Interface
VC through capacitors
DAA through FB; GND
through capacitors and FB
Line/Audio Interface
Line/Audio Interface
PIF: ~RESET
SIF: Reset circuit
Line/Audio Interface
Line/Audio Interface
Analog Ground
+3.3V
To SR1IO (62)
To CLKOUT (22)
To SR4OUT (18)
To IA1CLK (24)
To SR4IN (20)
To SA1CLK (23)
NC
AGND
GND
DI
DGND
To SA2CLK (59)
IA
IA
IA
IA
IA
IA
OA
IA
DI
OA
OA
IA
GND
Notes:
1.
I/O types:
IA, IB = Digital input; OA, OB = Digital output.
I(DA) = Analog input; O(DD), O(DF) = Analog output.
DI = Device interconnect.
2.
NC = No internal pin connection;
RESERVED = No external connection allowed (may have
internal connection).
0'
Pin
Signal Label
I/O Type
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
VRXOUT/NC*
VSCLK/NC*
VTXSIN/NC*
VCLKIN/NC*
VCNTRLSIN/NC*
IASLEEP
RESERVED
RESERVED
SA2CLK
SR2IO
RESERVED
SR1IO
VDD
XTCLK
GND
RESERVED
RXD
68
69
70
71
72
VDD
SLEEPO
RESERVED
VGG
RESERVED
73
74
75
76
77
78
79
80
81
82
83
RESERVED
RESERVED
YCLK
XCLK
RESERVED
~RI
RINGD
IRQ
GND
GP00
RESERVED
84
85
86
RESERVED
VDD
CLKIN
PWR
I
87
88
89
90
91
92
93
94
95
96
97
98
NC
D0
D1
D2
D3
D4
D5
D6
D7
RS0
RS1
PLLVDD
IA/OB
IA/OB
IA/OB
IA/OB
IA/OB
IA/OB
IA/OB
IA/OB
IA
IA
PLL
99
100
GND
PLLGND
GND
PLL
3.
DI
DI
DI
DI
DI
DI
DI
DI
DI
PWR
IA
GND
OA
PWR
DI
REF
OA
OA
OA
IA
IA
GND
DI
Interface
To SR3IN (21)
To SR2CLK (10)
To SR3OUT (19)
To CLKOUT (22)
To SR2IO (60)
To SLEEPO (69)
NC
NC
To VSTROBE (50)
To VCNTRLSIN (55)
NC
To MCNTRLSIN (41)
+3.3V
DTE Serial Interface
DGND
NC
DTE Serial Interface
+3.3V
To IASLEEP (56)
NC
+5V or +3.3V
NC
NC
NC
NC
NC
NC
DTE Serial Interface
Line/Audio Interface
Host Parallel Interface
DGND
To ~RDCLK (8)
NC
NC
+3.3V
Clock Circuit
NC
Host Parallel Interface
Host Parallel Interface
Host Parallel Interface
Host Parallel Interface
Host Parallel Interface
Host Parallel Interface
Host Parallel Interface
Host Parallel Interface
Host Parallel Interface
Host Parallel Interface
To +3.3 (VDD) through 10 Ω
and to DGND through 10 µF.
DGND
DGND
Interface Legend:
MDP = Modem Data Pump
DTE = Data Terminal Equipment
PIF = Parallel host interface
SIF = Serial DTE interface.
* NC on non-SP models.
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Label
I/O Type
Signal/Definition
OVERHEAD SIGNALS
CLKIN
IA
Clock In (144-Pin TQFP). If external clock is selected (NOXTL = low), connect to an external 56.448 MHz or
28.224 MHz clock circuit. The clock frequency is selected by the MK4 and MK5 inputs.
XTLI
I
Crystal In (144-Pin TQFP). If external crystal is selected (NOXTL = high), connect to an external 56.448 MHz or
28.224 MHz crystal circuit. The clock frequency is selected by the MK4 and MK5 inputs.
XTLO
O
Crystal Out (144-Pin TQFP). If external crystal is selected (NOXTL = high), connect to the external crystal
circuit return.
NOXTL
IA
No Crystal Circuit (144-Pin TQFP). Selects external crystal (NOXTL = high, i.e., leave open or connect to VDD
through 10kΩ) or clock (NOXTL = low, i.e., connect to GND) circuit. Internal pull-up provided.
XTLI/CLKIN
I
Crystal In/Clock In (100-Pin PQFP). Connect to an external 56.448 MHz/28.224 MHz crystal circuit (crystal
input option) or to an external 56.448 MHz/28.224 MHz clock circuit (clock input option).
XTLO/NC
O
Crystal Out/NC (100-Pin PQFP). Connect to the external crystal circuit return (crystal input option) or leave
open (clock input option).
~RES1,
~RES2
IA
Reset. ~RESET low holds the MDP in the reset state. ~RESET going high releases the MDP from the reset
state and initiates normal operation using power turn-on (default) values. ~RESET must be held low for at least
3 µs. The MDP is ready to use 400 ms after the low-to-high transition of ~RESET. ~RES1 and ~RES2 are
typically connected to the MCU ~RESET input and to the host bus ~RESET (or RESET through an inverter) line
(parallel host) or reset circuit (serial DTE interface) which resets both the MCU and MDP upon power turn-on.
~RES1 and ~RES2 have active internal pull-up resistors.
~WKRES
IA
Wake-up Reset. ~WKRES is connected internally to ~RESET but will not drive the MDP ~RESET pins.
Asserting ~WKRES performs the same reset function as the MDP ~RESET and typically used by the MCU to
wake up the MDP from SLEEP Mode when the MDP ~RESET lines cannot be asserted (because they are also
connected to the MCU ~RESET input). For a serial DTE or parallel host MCU configuration, connect ~WKRES to
the MCU ~WKRESOUT output. ~WKRES has an active internal pull-up resistor.
VDD
PWR
+3.3V Digital Circuit Power Supply. Connect to +3.3V through digital circuit power supply filter.
AVDD
PWR
+3.3V Analog Circuit Digital Power Supply. Connect to +3.3V through digital circuit power supply filter.
AVAA
PWR
Analog Circuit Analog Power Supply. Connect to +3.3V or +5V (preferred) through analog circuit power
supply filter.
Note: When operating the analog circuitry at +3.3V, the transmit level is 4 dB lower and the converted receive
level is 4 dB higher when compared to operating the analog circuitry at +5V. The transmit level must be adjusted
accordingly using TLVL or other means.
VGG
REF
Input Reference Voltage. Reference voltage for +5V tolerant input pins. Connect to the highest of +3.3V or +5V
available on the circuit board. A connection to +5V allows +5V or +3.3V input levels. A connection to +3.3V
allows +3.3V input levels only.
GND
GND
Digital Ground. Connect to digital ground.
AGND
GND
Analog Ground. Connect to analog ground.
XCLK
OA
X Clock. Output clock at 56.448 MHz (PLL disabled) or 63.5045 (PLL enabled), which runs during MDP Normal
Mode and is turned off during Sleep Mode.
YCLK
OA
Y Clock. Output clock at 28.224 MHz, which runs during MDP Normal Mode and is turned off during Sleep
Mode.
SYCLK
OA
System Clock. Output clock at 28.224 MHz, which runs during MDP Normal Mode and during Sleep Mode.
PLLVDD
PLL
PLLVDD Connection. For the 144-pin TQFP, connect to +3.3V (VDD) through 10 Ω and to AGND through 10
(+) µF, For the 100-pin PQFP, connect to +3.3V (VDD) through 10 Ω and to DGND through 10 (+) µF.
PLLGND
PLL
PLLGND Connection. For the 144-pin TQFP, connect to AGND. For the 100-pin PQFP, connect to DGND.
~SET3V
IA
Set Integrated Analog +3.3V Reference. Selects analog circuit voltage reference: High (NC) = +5V, low
(AGND) = +3.3V.
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Label
I/O Type
Signal Name/Description
OVERHEAD SIGNALS (CONTINUED)
MK4
IA
PLL Circuit Enable/Disable (144-Pin TQFP). This pin disables (MK4 = high) or enables (MK4 = low,
recommended setting) the internal PLL circuit. Connect this pin to GND to enable the PLL circuit. Internal pull-up
provided. MK4 must be low if using the 28.224 MHz option. See MK5.
Note: The 100-pin PQFP is internally bonded to enable the internal PLL.
MK5
IA
PLL Circuit Frequency Select (144-Pin TQFP). This pin selects the input frequency (MK5 high = 28.224 MHz,
MK5 low = 56.448 MHz) when the internal PLL circuit is enabled (MK4 = low). If the PLL is disabled (MK4 =
high), leave MK5 high and use 56.448 MHz. Internal pull-up provided. See MK4. If 28.224 MHz input frequency
is used, MK4 must be low and MK5 must be high.
Note: The 100-pin PQFP is internally bonded to select a 28.224 MHz input frequency.
MK4
MK5
PLL Enabled
Crystal/Clock
0
0
1
1
0
1
0
1
Yes
Yes
No
No
56.448 MHz
28.224 MHz (Most common)
Invalid Option
56.448 MHz
PARALLEL HOST INTERFACE
Address, data, control, and interrupt hardware interface signals allow MDP connection to an 8086-compatible microprocessor bus. With the
addition of external logic, the interface can be made compatible with a wide variety of other microprocessors such as the 6502, 8086 or
68000. The microprocessor interface allows a microprocessor to change MDP configuration, read or write channel and diagnostic data, and
supervise MDP operation by writing control bits and reading status bits.
D0–D7
IA/OB
Data Lines. Eight bidirectional data lines (D0–D7) provide parallel transfer of data between the host and the
MDP. The most significant bit is D7. Data direction is controlled by the Read Enable and Write Enable signals.
RS0–RS4
IA
Register Select Lines. The five active high register select lines (RS0–RS4) address internal MDP interface
memory registers and are typically connected to the five least significant lines (A0–A4) of the address bus.
The MDP decodes RS0 through RS4 to address one of 32 internal interface memory registers (00–1F). The
most significant address bit is RS4, while the least significant address bit is RS0. The selected register can be
read from or written into via the 8-bit parallel data bus (D0–D7). The most significant data bit is D7, while the
least significant data bit is D0.
~CS
IA
Chip Select. ~CS selects the MDP for microprocessor bus operation. ~CS is typically generated by decoding
host address bus lines.
~READ
IA
Read Enable. During a read cycle (~READ asserted), data from the selected interface memory register is gated
onto the data bus by means of three-state drivers in the MDP. These drivers force the data lines high for a one
bit, or low for a zero bit. When not being read, the three-state drivers assume their high-impedance (off) state.
~WRITE
IA
Write Enable. During a write cycle (~WRITE asserted), data from the data bus is copied into the selected MDP
interface memory register, with high and low bus levels representing one and zero bit states, respectively.
IRQ
OA
Interrupt Request. The MDP IRQ output may be connected to the host processor interrupt request input in
order to interrupt host program execution for immediate MDP service. The IRQ output can be enabled in the
MDP interface memory to indicate immediate change of conditions. The use of IRQ is optional depending upon
MDP application. The IRQ output is driven by a TTL-compatible CMOS driver.
VOICE SERIAL INTERFACE (144-PIN R6785; SP MODEL)
Timing and data signals provide a voice serial interface which is used to transfer 16-bit linear or 8-bit A-Law/µ-Law PCM voice samples in fullduplex speakerphone form with acoustic echo cancellation to and from the host. These signals can be used in concurrent voice and data
applications by the host.
In non-SP models, voice samples are not supported on these pins and these pins should be left open.
SR8OUT
OA
Serial Data Out. Analog voice on the MICV input pin is converted to 16-bit linear or 8-bit A-Law/µ-Law PCM
digital voice samples and output on this pin in serial form to the host.
SR8IN
IN
Serial Data In. Digital voice in 16-bit linear or 8-bit A-Law/µ-Law PCM form is received from the host on this
serial data input pin, converted to analog form and routed to the SPKR output pin.
SR4CLK
IA
Serial Shift Clock. Serial bit clock used to shift data bits into the MDP on the SR8IN pin and out of the MDP on
the SR8OUT pin. Connect to MDP CLKOUT (PB0) pin.
SA4CLK
IA
Sample Shift Clock. Serial frame clock used to synchronize words shifted in on the SR8IN pin and shifted out
on the SR8OUT pin. SA4CLK clock edges must align with the rising edge of SR4CLK.
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Label
I/O Type
Signal Name/Description
DTE SERIAL INTERFACE
Timing, data, control, and status signals provide a V.24-compatible serial interface. These signals are TTL compatible in order to drive the
short wire lengths and circuits normally found within a printed circuit board, stand-alone modem enclosures, or equipment cabinets. For
driving longer cables, these signals can be easily converted to EIA/RS-232-D voltage levels.
TXD
IA
Transmitted Data. The MDP obtains serial data to be transmitted from the local DTE on the Transmitted Data
(TXD) input.
RXD
OA
Received Data. The MDP presents received serial data to the local DTE on the Received Data (RXD) output.
~RTS
IA
Request to Send. Activating ~RTS causes the MDP to transmit data on TXD when ~CTS becomes active. The
~RTS pin is logically ORed with the RTS bit.
~CTS
OA
Clear To Send. ~CTS active indicates to the local DTE that the MDP will transmit any data present on TXD.
CTS response times from an active condition of RTS are shown in Table 3.
~RLSD
OA
Received Line Signal Detector. ~RLSD active indicates to the local DTE that energy above the receive level
threshold is present on the receiver input, and that the energy is not a training sequence.
One of four ~RLSD receive level threshold options can be selected (RTH bits). A minimum hysteresis action of
2 dB exists between the actual off-to-on and on-to-off transition levels. The threshold level and hysteresis action
are measured with a modulated signal applied to the Receiver Analog (RXA) input. Note that performance may
be degraded when the received signal level is less than -43 dBm. The ~RLSD on and off thresholds are host
programmable in DSP RAM.
~DTR
IA
Data Terminal Ready. In V.8, V.90, K56flex, V.34, V.32 bis, V.32, V.22 bis, V.22, or Bell 212A configuration,
activating ~DTR initiates the handshake sequence. The DATA bit must be set to complete the handshake.
In V.21, V.23, or Bell 103 configuration, activating ~DTR causes the MDP to enter the data state provided that
the DATA bit is a 1. If in answer mode, the MDP immediately sends answer tone. In these modes, if controlled
carrier is enabled, carrier is controlled by RTS.
During the data mode, deactivating ~DTR causes the transmitter and receiver to turn off and return to the idle
state.
The ~DTR input and the DTR control bit are logically ORed.
Data Set Ready. ~DSR ON indicates that the MDP is in the data transfer state. ~DSR OFF indicates that the
DTE is to disregard all signals appearing on the interchange circuits except Ring Indicator (~RI). ~DSR is OFF
when the MDP is in a test mode (i.e., local analog or remote digital loopback).
~DSR
OA
~RI
OA
Ring Indicator. ~RI output follows the ringing signal present on the line with a low level (0 V) during the ON
time, and a high level during the OFF time coincident with the ringing signal. The RI status bit reflects the state
of the ~RI output.
TDCLK
OA
Transmit Data Clock. The MDP outputs a synchronous Transmit Data Clock (TDCLK) for USRT timing. The
TDCLK frequency is the data rate (±0.01%) with a duty cycle of 50±1%. The TDCLK source can be internal,
external (input on XTCLK), or slave (to ~RDCLK) as selected by TXCLK bits in interface memory.
XTCLK
IA
External Transmit Clock. In synchronous communication, an external transmit data clock can be connected to
the MDP XTCLK input. The clock supplied at XTCLK must exhibit the same characteristics as TDCLK. The
XTCLK input is then reflected at the TDCLK output.
~RDCLK
OA
Receive Data Clock. The MDP outputs a synchronous Receive Data Clock (~RDCLK) for USRT timing. The
~RDCLK frequency is the data rate (±0.01%) with a duty cycle of 50±1%. The ~RDCLK low-to-high transitions
coincide with the center of the received data bits.
The DSR status bit reflects the state of the ~DSR output.
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Label
I/O Type
Signal Name/Description
TELEPHONE LINE/TELEPHONE/AUDIO INTERFACE SIGNALS AND REFERENCE VOLTAGE
TXA1, TXA2
O(DF)
Transmit Analog 1 and 2 Output. The TXA1 and TXA2 outputs are differential outputs 180 degrees out of
phase with each other. Each output can drive a 300 Ω load. Typically, TXA1 and TXA2 are connected to the
telephone line interface or an optional external hybrid circuit.
RIN
I(DA)
Receive Analog Input. RIN is a single-ended input with 70K Ω input impedance. Typically, RIN is connected to
telephone line interface or an optional external hybrid circuit. NOTE: If not used, do not tie directly to ground;
this input has a bias voltage of +1.35V (VAA = +3.3V) or +2.5V (VAA = +5V).
RINGD
IA
Ring Detect. The RINGD input is monitored for pulses in the range of 15 Hz to 68 Hz. The frequency detection
range may be changed by the host in DSP RAM. The circuit driving RINGD should be a 4N35 optoisolator or
equivalent. The circuit driving RINGD should not respond to momentary bursts of ringing less than 125 ms in
duration, or less than 40 VRMS (15 Hz to 68 Hz) across TIP and RING. Detected ring signals are reflected on
the ~RI output signal as well as the RI bit.
~RLYA
(~OHRC,
~CALLID)
OD
Relay A Control. The ~RLYA open drain output can directly drive a reed relay coil with a minimum resistance of
360 ohms (9.2 mA max. @ +3.3V). A clamp diode, such as a 1N4148, should be installed across the relay coil.
An external transistor can be used to drive heavier loads (e.g., electro-mechanical relays). ~RLYA is controlled
by host setting/resetting of the RA bit.
In a typical application, ~RLYA is connected to the normally open Off-Hook relay (~OHRC). In this case, ~RLYA
active closes the relay to connect the MDP to the telephone line.
Alternatively, in a typical application, ~RLYA is connected to the normally open Caller ID relay (~CALLID). When
the MDP detects a Calling Number Delivery (CND) message, the ~RLYA output is asserted to close the Caller ID
relay in order to AC couple the CND information to the MDP RIN input (without closing the off-hook relay and
allowing loop current flow which would indicate an off-hook condition).
~RLYB
(~TALK)
OD
Relay B Control. The ~RLYB open drain output can directly drive a reed relay coil with a minimum resistance of
360 ohms (9.2 mA max. @ 3.3V). A clamp diode, such as a 1N4148, should be installed across the relay coil. An
external transistor can be used to drive heavier loads (e.g., electro-mechanical relays). ~RLYB is controlled by
host setting/resetting of the RB bit.
In a typical application, ~RLYB is connected to the normally closed Talk/Data relay (~TALK). In this case,
~RLYB active opens the relay to disconnect the handset from the telephone line.
MICM
I(DA)
Modem Microphone Input. MICM is a single-ended microphone input. The input impedance is > 70k Ω. NOTE:
If not used, do not tie directly to ground; this input has a bias voltage of +1.35V (VAA = +3.3V) or +2.5V
(VAA = +5V).
SPK
O(DF)
Speaker Analog Output. The SPK analog output can originate from one of five different sources: RIN, TELIN,
MICM or MICV or from the MDP’s internal voice playback mode. The SPK on/off and three levels of attenuation
are controlled by bits in DSP RAM. When the speaker is turned off, the SPK output is clamped to the voltage at
the VC pin. The SPK output can drive an impedance as low as 300 ohms. In a typical application, the SPK
output is an input to an external LM386 audio power amplifier.
SPKMD
OA
Modem Speaker Digital Output. The SPKMD digital output reflects the received analog input signal digitized to
TTL high or low level by an internal comparator to create a PC Card (PCMCIA)-compatible signal.
VREF
REF
High Voltage Reference. Connect to VC through 10 µF (polarized, + terminal to VREF) and 0.1 µF (ceramic) in
parallel.
VC
REF
Low Voltage Reference. For the 144-pin TQFP, connect to AGND through 10 µF (polarized, + terminal to VC)
and 0.1 µF (ceramic) in parallel. For the 100-pin PQFP, connect to a ferrite bead and connect the other end of
the ferrite bead to DGND through 10 µF (polarized, + terminal to VC) and 0.1 µF (ceramic) in parallel.
MICV/NC*
I(DA)
Voice Microphone Input. MICV is a single-ended microphone input. Typically, MICV is connected to a
microphone output for recording voice e.g., in a speakerphone application. NOTE: If not used, do not tie
directly to ground; this input has a bias voltage of +1.35V (VAA = +3.3V) or +2.5V (VAA = +5V).
TELIN/NC*
I(DA)
Telephone Analog Input. TELIN is a single-ended input with 70K Ω input impedance. Typically, TELIN is
connected to a telephone handset microphone circuit. NOTE: If not used, do not tie directly to ground; this
input has a bias voltage of +1.35V (VAA = +3.3V) or +2.5V (VAA = +5V).
TELOUT/NC*
O(DF)
Telephone Analog Output. TELOUT is a single-ended output that can drive a 300 Ω load. Typically, TELOUT is
connected to a telephone handset speaker circuit.
MICBIAS
REF
Microphone Bias. Microphone bias reference voltage.
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Label
I/O Type
Signal Name/Description
MISCELLANEOUS
TIRO2
IA
RESERVED
NC
Reserved Function. May be connected to internal circuit. Leave open.
MDP INTERCONNECT
GP00
DI
SLEEPO
DI
To ~RDCLK.
To IASLEEP.
IASLEEP
DI
To SLEEPO.
MSCLK
DI
To IA1CLK.
CLKOUT
DI
To MCLKIN & VCLKIN.
SR1IO
DI
To MCNTRLSIN.
SR3IN
DI
To VRXOUT.
IA1CLK
DI
To MSCLK.
SA1CLK
DI
To MSTROBE.
SR4OUT
DI
To MTXSIN.
MCLKIN
DI
To CLKOUT.
VCLKIN/NC*
DI
To CLKOUT.
MSTROBE
DI
To SA1CLK.
VSTROBE/NC*
DI
To SA2CLK.
MCNTRLSIN
DI
To SR1IO.
VSCLK/NC*
DI
To SR2CLK.
VCNTRLSIN/NC*
DI
To SR2IO.
MRXOUT
DI
To SR4IN.
VTXSIN/NC*
DI
To SR3OUT.
VRXOUT/NC*
DI
To SR3IN.
MTXSIN
DI
To SR4OUT.
SR2IO
DI
To VCNTRLSIN.
SR4IN
DI
To MRXOUT.
SR2CLK
DI
To VSCLK.
SA2CLK
DI
To VSTROBE.
SR3OUT
DI
To VTXSIN.
* NC on non-SP models. External interconnects as described can made for the NC pins on non-SP models in case SP models are ever
substituted in the application design and SP support is required.
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Parameter
Input High Voltage
Symbol
Min.
Typ.
Max.
VIH
Type IA
Units
Vdc
2.0
–
VCC
–
40
µA
0.8
VDC
Input High Current
IIH
–
Input Low Voltage
VIL
0.3
Input Low Current
IIL
–
–
40
µA
Input Leakage Current
IIN
–
–
±100
µADC
–
–
VDC
–
VCC
Output High Voltage
VOH
Type OA
2.4
VIN = 0 to +3.3V, VCC = 3.6V
ILOAD = – 100 µA
Type OD
Output Low Voltage
Test Conditions1
ILOAD = 0 mA
VOL
VDC
Type OA
–
–
0.4
ILOAD = 1.6 mA
Type OD
–
–
0.75
ILOAD = 15 mA
Three-State (Off) Current
ITSI
±10
µADC
VIN = 0.4 to VCC-1
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Signal Name
Type
Characteristic
Value
RIN, TELIN,
MICM, MICV
I (DA)
Input Impedance
AC Input Voltage Range
Reference Voltage
> 70K Ω
1.1 VP-P
+1.35 VDC (VAA = +3.3V) or +2.5 VDC (VAA = +5V)
TXA1, TXA2,
TELOUT
O (DD)
Minimum Load
Maximum Capacitive Load
Output Impedance
AC Output Voltage Range
Reference Voltage
DC Offset Voltage
300 Ω
0 µF
10 Ω
1.4 VP-P (VAA = +3.3V) or 2.2 VP-P (VAA = +5V)
(with reference to ground and a 600 Ω load)
+1.35 VDC (VAA = +3.3V) or +2.5 VDC (VAA = +5V)
± 200 mV
Minimum Load
300 Ω
Maximum Capacitive Load
Output Impedance
AC Output Voltage Range
Reference Voltage
DC Offset Voltage
0.01 µF
10 Ω
1.4 VP-P (VAA = +3.3V) or 2.2 VP-P (VAA = +5V)
+1.35 VDC (VAA = +3.3V) or +2.5 VDC (VAA = +5V)
± 20 mV
SPK
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Notes
Typical
Current
(mA)
Maximum
Current
(mA)
Typical
Power
(mW)
Maximum
Power
(mW)
Normal Mode
75
84
250
300
f = 28.224 MHz
Sleep Mode
10
—
33
—
f = 28.224 MHz
Stop Mode
<0.3
—
<1
—
f = 0 MHz
Mode
Notes:
1.
2.
3.
4.
5.
Operating voltage: VDD = +3.3V ± 0.3V.
Test conditions: VDD = +3.3V for typical values; VDD = +3.6V for maximum values.
Input Ripple ≤ 0.1 Vpeak-peak.
f = Internal frequency.
Stop Mode is the same as Sleep Mode with clocks turned off.
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Symbol
Limits
Units
Supply Voltage
Parameter
VDD
-0.5 to +4.0
V
Input Voltage
VIN
Except XTLI
XTLI
Operating Temperature Range
V
TA
-0.5 to (VGG +0.5)*
-0.5 to 3.9V
-0 to +70
°C
TSTG
-55 to +125
°C
Analog Inputs
VIN
-0.3 to (VAA + 0.5)
V
Voltage Applied to Outputs in High Impedance (Off) State
VHZ
-0.5 to (VGG +0.5)*
V
DC Input Clamp Current
IIK
±20
mA
DC Output Clamp Current
IOK
±20
mA
Static Discharge Voltage (25°C)
VESD
±2500
V
Latch-up Current (25°C)
ITRIG
±400
mA
Storage Temperature Range
* VGG = +5.0V ± 5% or +3.3V ± 0.3V.
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