SN54ABTH245, SN74ABTH245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS663D – APRIL 1996 – REVISED SEPTEMBER 1999 D D D D description These octal bus transceivers are designed for asynchronous communication between data buses. The devices transmit data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are effectively isolated. DIR A1 A2 A3 A4 A5 A6 A7 A8 GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC OE B1 B2 B3 B4 B5 B6 B7 B8 SN54ABTH245 . . . FK PACKAGE (TOP VIEW) A3 A4 A5 A6 A7 3 OE D SN54ABTH245 . . . J OR W PACKAGE SN74ABTH245 . . . DB, DGV, DW, N, OR PW PACKAGE (TOP VIEW) A2 A1 DIR VCC D State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds 500 mA Per JESD 17 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C Ioff and Power-Up 3-State Support Hot Insertion High-Drive Outputs (–32-mA IOH, 64-mA IOL) Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Thin Very Small-Outline (DGV) Packages, Ceramic Chip Carriers (FK), Plastic (N) and Ceramic (J) DIPs, and Ceramic Flat (W) Package 4 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 B1 B2 B3 B4 B5 A8 GND B8 B7 B6 D When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN54ABTH245 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ABTH245 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-ΙΙB is a trademark of Texas Instruments Incorporated. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ABTH245, SN74ABTH245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS663D – APRIL 1996 – REVISED SEPTEMBER 1999 FUNCTION TABLE INPUTS OE DIR OPERATION L L B data to A bus L H A data to B bus H X Isolation logic symbol† 19 OE 1 DIR 2 A1 G3 3 EN1 [BA] 3 EN2 [AB] 18 1 B1 2 A2 A3 A4 A5 A6 A7 A8 3 17 4 16 5 15 6 14 7 13 8 12 9 11 B2 B3 B4 B5 B6 B7 B8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) DIR 1 19 A1 2 18 To Seven Other Channels 2 OE POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 B1 SN54ABTH245, SN74ABTH245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS663D – APRIL 1996 – REVISED SEPTEMBER 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABTH245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABTH245 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 3) SN54ABTH245 SN74ABTH245 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage IOH IOL High-level output current VCC –24 Low-level output current 48 64 mA ∆t/∆v Input transition rise or fall rate 5 5 ns/V ∆t/∆VCC TA Power-up ramp rate High-level input voltage 2 2 0.8 Input voltage 0 V 0.8 0 VCC –32 –55 125 –40 V V mA µs/V 200 Operating free-air temperature V 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ABTH245, SN74ABTH245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS663D – APRIL 1996 – REVISED SEPTEMBER 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = –18 mA IOH = –3 mA VCC = 5 V, VCC = 4 4.5 5V VOL VCC = 4 4.5 5V MIN SN54ABTH245 MIN –1.2 MAX SN74ABTH245 MIN –1.2 2.5 2.5 IOH = –3 mA IOH = –24 mA 3 3 3 2 2 IOH = –32 mA IOL = 48 mA 2* UNIT V V 2 0.55 IOL = 64 mA 0.55 0.55* 0.55 100 V mV Control inputs VCC = 0 to 5.5 V, VI = VCC or GND ±1 ±1 ±1 A or B ports VCC = 2.1 V to 5.5 V, VI = VCC or GND VI = 0.8 V ±20 ±100 ±20 100 100 100 –100 –100 –100 µ µA µA II(hold) I(h ld) VCC = 4 5V 4.5 IOZPU VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X ±50** ±50** ±50 µA IOZPD VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X ±50** ±50** ±50 µA ±100 µA 50 µA –180 mA 250 µA Ioff ICEX IO‡ ICC A or B ports VCC = 0, VCC = 5.5 V, VO = 5.5 V VI or VO ≤ 4.5 V VCC = 5.5 V, VO = 2.5 V Outputs high VCC = 5.5 V, IO = 0, VI = VCC or GND ±100 Outputs high Outputs low Outputs disabled Control inputs Control inputs VI = 2.5 V or 0.5 V ∆ICC§ Ci VI = 2 V VCC = 5.5 V, Outputs enabled One input at 3.4 V,, Other inputs at Outputs disabled VCC or GND VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND ts Data inp inputs 50 –50 –140 –180 5 250 50 –50 –180 –50 250 22 30 30 30 mA 1 250 250 250 µA 1.5 1.5 1.5 mA 1.5 1.5 1.5 mA 1.5 1.5 1.5 mA 4 Cio A or B ports VO = 2.5 V or 0.5 V 8 * On products compliant to MIL-PRF-38535, this parameter does not apply. ** On products compliant to MIL-PRF-38535, this parameter is not production tested. † All typical values are at VCC = 5 V. ‡ Not more than one output should be tested at a time, and the duration of the test should not exceed one second. § This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. 4 MAX –1.2 2.5 Vhys II TA = 25°C TYP† MAX POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 pF pF SN54ABTH245, SN74ABTH245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS663D – APRIL 1996 – REVISED SEPTEMBER 1999 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B B or A tPZH tPZL OE A or B tPHZ tPLZ OE A or B PARAMETER tsk(o) VCC = 5 V, TA = 25°C SN54ABTH245 MIN TYP MAX MIN MAX MIN MAX 1 2 3.2 0.8 3.8 1 3.6 1 2.6 3.5 0.8 4.2 1 3.9 2 3.5 4.5 1.2 6.2 2 5.6 1.9 4 5.3 1.3 7 1.9 6.2 2.2 4.4 5.4 2.2 6.1 2.2 5.9 1.5 3 4 1 4.9 1.5 4.5 0.5 POST OFFICE BOX 655303 SN74ABTH245 • DALLAS, TEXAS 75265 0.5 UNIT ns ns ns ns 5 SN54ABTH245, SN74ABTH245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS663D – APRIL 1996 – REVISED SEPTEMBER 1999 PARAMETER MEASUREMENT INFORMATION 500 Ω From Output Under Test S1 7V Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open 3V LOAD CIRCUIT Timing Input 1.5 V 0V tw tsu 3V th 3V Input 1.5 V 1.5 V 0V 1.5 V Data Input 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V 1.5 V VOL Output tPLZ 3.5 V 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at Open (see Note B) VOL + 0.3 V VOL tPHZ tPZH VOH 1.5 V 1.5 V 0V Output Waveform 1 S1 at 7 V (see Note B) tPLH tPHL 1.5 V tPZL VOH 1.5 V Output 3V Output Control tPHL tPLH 1.5 V 1.5 V VOH – 0.3 V VOH ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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