SN74LVCR162245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES047 - AUGUST 1995 D D D D D D D D D DGG OR DL PACKAGE (TOP VIEW) Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors All Outputs Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required Package Options Include Plastic Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages 1DIR 1B1 1B2 GND 1B3 1B4 VCC 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 VCC 2B5 2B6 GND 2B7 2B8 2DIR description 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1OE 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 VCC 2A5 2A6 GND 2A7 2A8 2OE This 16-bit (dual-octal) noninverting bus transceiver is designed for 2.7-V to 3.6-V VCC operation. The SN74LVCR162245 is designed for asynchronous communication between data buses. The control function implementation minimizes external timing requirements. This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. All outputs, which are designed to sink up to 12 mA, include 26-Ω resistors to reduce overshoot and undershoot. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74LVCR162245 is characterized for operation from – 40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are a trademarks of Texas Instruments Incorporated. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74LVCR162245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES047 - AUGUST 1995 FUNCTION TABLE (each 8-bit section) INPUTS OE DIR L L B data to A bus L H A data to B bus H X Isolation logic symbol† 48 1OE 1DIR 1 OPERATION logic diagram (positive logic) G3 1DIR 1 3 EN1 [BA] 3 EN2 [AB] 25 2OE 2DIR 24 48 G6 6 EN4 [BA] 6 EN5 [AB] 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 47 1A1 2 1 2 46 3 44 5 43 6 41 8 40 9 38 11 37 12 36 13 4 47 1B1 2 1B3 1B4 1B5 To Seven Other Channels 1B6 1B7 1B8 2DIR 24 2B1 25 2A3 2A4 2A5 2A6 2A7 2A8 35 14 33 16 32 17 30 19 29 20 27 22 26 23 2OE 2B2 2B3 2B4 2A1 36 2B5 13 2B6 2B7 2B8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 1B1 1B2 5 2A2 1OE POST OFFICE BOX 655303 To Seven Other Channels • DALLAS, TEXAS 75265 2B1 SN74LVCR162245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES047 - AUGUST 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 4.6 V I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 100 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 3): DGG package . . . . . . . . . . . . . . . 0.85 W DL package . . . . . . . . . . . . . . . . . . 1.2 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B. recommended operating conditions (see Note 4) VCC VIH Supply voltage VIL VI Low-level input voltage VO Output voltage High-level input voltage VCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V Input voltage MIN MAX 2.7 3.6 2 0 0 IOH High level output current High-level VCC = 2.7 V VCC = 3 V IOL Low level output current Low-level VCC = 2.7 V VCC = 3 V ∆t /∆V Input transition rise or fall rate TA Operating free-air temperature NOTE 4: Unused control inputs must be held high or low to prevent them from floating. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT V V 0.8 V VCC VCC V –8 – 12 12 8 V mA mA 0 10 ns / V – 40 85 °C 3 SN74LVCR162245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES047 - AUGUST 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER IOH = – 100 µA IOH = – 4 mA, VOH IOH = – 8 mA, IOH = – 6 mA, IOH = – 12 mA, IOH = – 100 µA VOL Il MAX 2.7 V 2.7 V 2 VIH = 2 V VIH = 2 V 3V 2.4 3V 2 MIN to MAX 0.2 2.7 V 2.7 V 0.6 IOH = – 6 mA, IOH = – 12 mA, VIL = 0.8 V VIL = 0.8 V 3V 0.55 3V 0.8 IOZ§ ICC VO = VCC or GND VI = VCC or GND, 0.4 ±5 3.6 V 75 3V One input at VCC – 0.6 V, IO = 0 Other inputs at VCC or GND V µA µA –75 3.6 V ± 500 µA 3.6 V ± 10 µA 20 µA 500 µA 3.6 V 2.7 V to 3.6 V VI = VCC or GND VO = VCC or GND UNIT V VIL = 0.8 V VIL = 0.8 V VI = 2 V VI = 0 to 3.6 V Control inputs TYP‡ VCC – 0.2 2.2 VIH = 2 V VIH = 2 V VI = VCC or GND VI = 0.8 V nICC MIN IOH = – 4 mA, IOH = – 8 mA, Il(hold) ( ) Ci VCC† MIN to MAX TEST CONDITIONS 3.3 V Cio A or B ports 3.3 V † For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions. ‡ All typical values are at VCC = 3.3 V, TA = 25°C. § For I/O ports, the parameter IOZ includes the input leakage current. 2.5 pF 3.5 pF switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER tpd FROM (INPUT) TO (OUTPUT) VCC = 3.3 V ± 0.3 V VCC = 2.7 V MIN MAX MIN MAX UNIT A or B B or A 1.5 7.5 1.5 8.5 ns ten OE A or B 1.5 9 1.5 10 ns tdis OE A or B 1.5 7.5 1.5 8.5 ns operating characteristics, VCC = 3.3 V, TA = 25_C PARAMETER Cpd d 4 TEST CONDITIONS Power dissipation capacitance per transceiver Outputs enabled Outputs enabled POST OFFICE BOX 655303 CL = 50 pF, pF • DALLAS, TEXAS 75265 f = 10 MHz TYP 20 2 UNIT pF SN74LVCR162245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES047 - AUGUST 1995 PARAMETER MEASUREMENT INFORMATION 6V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND 500 Ω 2.7 V LOAD CIRCUIT FOR OUTPUTS 1.5 V Timing Input 0V tw tsu 2.7 V Input 1.5 V 2.7 V 1.5 V 1.5 V Data Input 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V 0V 1.5 V VOL tPLH tPHL VOH Output 1.5 V 1.5 V 0V 1.5 V VOL tPLZ Output Waveform 1 S1 at 6 V (see Note B) VOH Output 1.5 V tPZL tPHL 1.5 V 2.7 V Output Control 1.5 V tPLH 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION Input th Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V tPZH 3V VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH [0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as tden. G. tPHL and tPLH are the same as tpd. Figure 1. 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