SN74LVCH245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES008 – JULY 1995 D D D D D D D D EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C ESD Protection Exceeds 2000 V Per MIL-STD-833C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17 Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltages With 3.3-VVCC) Bus Hold on Data Inputs Eliminates the Need for External Pullup Resistors Package Options Include Shrink Small-Outline (DB), Plastic Small-Outline (DW), and Thin Shrink Small-Outline (PW) Packages DB, DW, OR PW PACKAGE (TOP VIEW) DIR A1 A2 A3 A4 A5 A6 A7 A8 GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC OE B1 B2 B3 B4 B5 B6 B7 B8 description This octal bus transceiver is designed for 2.7-V to 3.6-V VCC operation; it can interface to a 5-V system environment. The SN74LVCH245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are effectively isolated. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74LVCH245 is characterized for operation from – 40°C to 85°C. FUNCTION TABLE INPUTS OPERATION OE DIR L L B data to A bus L H A data to B bus H X Isolation Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74LVCH245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES008 – JULY 1995 logic symbol† OE DIR A1 A2 A3 A4 A5 A6 A7 A8 19 1 2 3 logic diagram (positive logic) DIR G3 1 3EN1[BA] 3EN2[AB] 19 18 1 2 17 4 16 5 15 6 14 7 13 8 12 9 11 B1 A1 OE 2 B2 18 B3 B1 B4 B5 To Seven Other Channels B6 B7 B8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 100 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 3): DB package . . . . . . . . . . . . . . . . . . 0.6 W DW package . . . . . . . . . . . . . . . . . 1.6 W PW package . . . . . . . . . . . . . . . . . . 0.7 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74LVCH245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES008 – JULY 1995 recommended operating conditions (see Note 4) Operating VCC Supply voltage VIH VIL High-level input voltage VI Input voltage data inputs Data retention only MAX 2 3.6 1.5 VCC = 2.7 V to 3.6 V VCC = 2.7 V to 3.6 V Low-level input voltage MIN 2 UNIT V V 0.8 V 0 5.5 V High or low state 0 3 state 0 VCC 5.5 V VO Output voltage IOH High level output current High-level VCC = 2.7 V VCC = 3 V – 12 IOL Low level output current Low-level VCC = 2.7 V VCC = 3 V 12 ∆t /∆v Input transition rise or fall rate – 24 24 TA Operating free-air temperature NOTE 4: Unused control inputs must be held high or low to prevent them from floating. mA mA 0 10 ns / V – 40 85 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VCC† MIN to MAX TEST CONDITIONS IOH = – 100 µA VOH 2.7 V IOH = – 12 mA IOH = – 24 mA IOL = 100 µA VOL MIN TYP‡ MAX VCC – 0.2 2.2 3V 2.4 3V 2.2 V MIN to MAX 0.2 IOL = 12 mA IOL = 24 mA 2.7 V 0.4 3V 0.55 II VI = 5.5 V or GND VI = 0.8 V 3.6 V ±5 II(hold) ( ) VI = 2 V VI = 0 to 3.6 V IOZ§ ICC nICC VI = VCC or GND, One input at VCC – 0.6 V, Ci Control inputs 3V 75 3V – 75 ± 10 3.6 V 3.3 V Cio A or B ports 3.3 V † For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions. ‡ All typical values are measured at VCC = 3.3 V, TA = 25°C. § For I/O ports, the parameter IOZ includes the input leakage current. POST OFFICE BOX 655303 ± 50 2.7 V to 3.6 V VI = VCC or GND VO = VCC or GND • DALLAS, TEXAS 75265 µA ± 500 MIN to MAX IO = 0 Other inputs at VCC or GND V µA 3.6 V VO = VCC or GND VO = 3.6 V or 5.5 V UNIT µA 10 µA 500 µA 3.3 pF 5.4 pF 3 SN74LVCH245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES008 – JULY 1995 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER tpd ten tdis tsk(o)† FROM (INPUT) TO (OUTPUT) A or B VCC = 3.3 V ± 0.3 V VCC = 2.7 V MIN UNIT MIN MAX MAX B or A 1.5 7 8 ns OE A or B 1.5 8.5 9.5 ns OE A or B 1.5 7.5 8.5 ns 1 ns † Skew between any two outputs of the same package switching in the same direction. This parameter is warranted but not production tested. operating characteristics, VCC = 3.3 V, TA = 25°C PARAMETER Cpd d 4 Power dissipation capacitance per transceiver TEST CONDITIONS Outputs enabled Outputs disabled POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CL = 50 pF, pF f = 10 MHz TYP 36 2 UNIT pF SN74LVCH245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES008 – JULY 1995 PARAMETER MEASUREMENT INFORMATION 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND 2.7 V LOAD CIRCUIT FOR OUTPUTS 1.5 V Timing Input 0V tw tsu 2.7 V 1.5 V Input th 2.7 V 1.5 V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V Input 0V tPLH 1.5 V VOL VOH Output 1.5 V 1.5 V VOL 1.5 V 0V tPLZ Output Waveform 1 S1 at 6 V (see Note B) VOH tPLH tPHL 1.5 V tPZL tPHL 1.5 V Output 2.7 V Output Control 1.5 V Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 3V 1.5 V VOL + 0.3 V VOL tPZH tPHZ 1.5 V VOH – 0.3 V VOH [0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74LVCH245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES008 – JULY 1995 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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