DAEWOO DMC73C168

1
8Bit Single Chip Microcontroller
DMC73C168
Table of Contents
1. INTRODUCTION
3
3
1.1 Key Features
2. DMC73C168 BLOCK DIAGRAM
5
3. PIN ASSIGNMENT AND DESCRIPTION
6
6
8
3.1 DMC73C168 Pin Assignment
3.2 Description
4. ARCHITECTURE
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
11
12
12
12
13
13
14
14
33
Register File (RF)
Peripheral File (PF)
Peripheral RAM File (PRF)
Stack Pointer (SP)
Status Register (ST)
Program Counter (PC)
Peripheral File Map
Interrupt and Reset Priorities
5. DESCRIPTION OF EACH FUNCTION
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
Input / Output Ports
Device Initialization
I/O Control Register
Interrupt Logic and External Interrupt
Programmable Timer / Event Counter
A/D Converter
PLL
IF Counter
Serial Communication I/O Ports : SIO1, SIO2
6. OTP DEVICE SPECIFICATION
6.1 Pin Assignment of OTP and OTP Programming Adapter Board
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
34
34
36
36
38
41
47
51
59
63
66
66
2
8Bit Single Chip Microcontroller
DMC73C168
7. ELECTRICAL SPECIFICATION
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
Absolute Maximum Ratings Over Operating Free-Air Temperature Range
Recommended Operating Conditions
Electrical Characteristics Over Full Range of Operation
AC Characteristics for Input/Output Ports
A/D Converter Characteristics
AC Characteristics for Serial I/O Ports
Schematic of Input/Outputs
80 Pin Quad Flat Package (Mechanical Data)
67
67
68
69
70
71
71
72
73
* APPENDICES
A. DMC73C168 Table
B. Development Support
C. OTP Programming
75
75
79
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
3
DMC73C168
8Bit Single Chip Microcontroller
1. INTRODUCTION
The DMC73C168 is an 8-Bit microcontroller that contains Prescaler, PLL Frequency Synthesizer
and 2 channel A/D converter for Digital Tuning System.
The device is provided with abundant I/O ports and 2 channel serial interface ports (SI/O) controlled
by powerful instruction. The package is 80-pin QFP and hi gh performance CPU and internal peripheral
allow flexible and easy system design in car-stereo, radio tuner and Hi-Fi audio system.
1.1
Key Features
n
CMOS Technology
n
Memory Configuration
n
l
256 Byte On-Chip RAM Register file plus 128 Byte Peripheral Free RAM
l
Memory-Mapped Ports for Easy Addressing
l
16K-Byte On-Chip ROM
On-Chip PLL Frequency Synthesizer with Dual Modules Prescaler
l
Independant Frequency input ports : Max 150MHz at FM, 40MHz at AM
l
Two Types of Frequency Dividing Method : Pulse Swallow and Direct
l
8 Kinds of reference Frequencies : 1, 5, 6.25, 9, 10, 12.5, 25 and 50KHz
n
2 Channel SIO port
n
2 Channel On-Chip Timer
n
n
n
l
16-Bit with 5-Bit Prescaler and 16-Bit capture latch, timer outputs
l
Internal interrupt with Automatic timer Reload
On-Chip A/D Converter
l
2-channels with 8 bit resolution
l
Ratiometric Conversion
l
144 Machine-Cycles Conversion time (64us)
On-Chip IF Counter
l
17-Bit, Gate Time : Program can select from 1ms to 15ms
l
maximum Input Frequency : FM IF = 20MHz, AM IF = 5MHz
Easy Interrupt Handling
l
External Interrupts with Schmitt-Trigger Input
l
Software Calls through Interrupt Vectors
l
Software Monitoring of Interrupt Status
l
Precise Interrupt Timing through Capture Latch
n
Selectable Beep clock : 417Hz, 1KHz, 1.25KHz, 2.5KHz
n
64 I/O Pins
l
n
64 Bidirectional Pins
W ide Operating Range
l
Voltage(VDD) : 5V ¡ 1
¾ 0%
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
4
DMC73C168
8Bit Single Chip Microcontroller
n
l
Clock : 4.5MHz
l
Temperature : -40 deg to 85 deg
l
One Machine Execution Time : 0.44us (with 4.5MHz Crystal Oscillator)
Low operating Current
l
Halt Mode for Power Savings (Typical : 1uA at OSC stop)
l
W arm-up mode for avoid unstable osc operation at the wake time from Halt mode.
The warm-up time can be adjustable by S/W.
n
Package
l
n
80 QFP (Quad Flat Package)
Development Support
l
Evaluation Module : EVM73C00A & ADP73C168
l
Assembler/Linker Cross Support for Popular Hosts
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
5
DMC73C168
8Bit Single Chip Microcontroller
2. DMC73C168 BLOCK DIAGRAM
INT4-0
RESET
Interrupt
Control
CE
(INT1)
INT3
INT4-1
INT2
VDD
¡æ
VSS
¡æ
RAM
384 Byte
8 BIT
CPU
INT6
INT5
INT7
EXT INT4
EXT INT3 PORT A
A/D CON
TIMER1 BEEP GEN
TIMER2
PORT E
SIO 1
SIO 2
Peripheral
/Memory
Control
OSCIN
PORT B
OSC
GEN
¡ê A0/FMIF
¡ê A1/AMIF
¡ê A2/AD1
¡ê A3/AD2
¡ê A4/ECI1
¡ê A5/ECI2
¡ê A6/INT4
¡ê A7/INT3
¡ê E0/SO1
¡ê E1/SI1
¡ê E2/SCLK1
¡ê E3/SO2
¡ê E4/SI2
¡ê E5/SCLK2
¡ê E6
¡ê E7/BEEP
¡ê B0/T1OUT
¡ê B1/T2OUT
OSCOUT
TEST
¡æ
EO1
EO2
¡ç
¡ç
VCOL
VCOH
¡æ
¡æ
VREF
ROM
16 Kbyte
PORT B
¡ê B2-B7
PORT C
¡ê C0-C7
PORT D
¡ê D0-D7
PORT F
¡ê F0-F7
PORT G
¡ê G0-G7
Phase Locked
Loop
¡æ
VASS ¡æ
H0-H7 ¡ê
PORT H
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
6
8Bit Single Chip Microcontroller
DMC73C168
3. PIN ASSIGNMENT AND DESCRIPTION
3.1 DMC73C168 Pin Assignment
B
1
/
T
2
O
C C C D D D D D D D D B B B B B B U
2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 T
C3
C4
C5
C6
C7
NC
EO1
EO2
VSS
VASS
VCOH
VCOL
VREF
NC
CE/INT1
RESET
64
¡ê 65
¡ê
¡ê
¡ê
¡ê
¡ª
¡ç
¡ç
¡ª
¡ª
¡æ
¡æ
¡æ
¡ª
¡æ
¡æ 80
* 1
A
0
/
F
M
I
F
B
0
/
T
1
O
U H H H H H
T 7 6 5 4 3
41
¡ê
¡ê
¡ê
¡ê
¡ê
¡ê
¡ê
¡ê
¡ê
¡ê
¡ê
¡ç
¡ç
¡æ
¡ç
25 ¡ª
80 PIN QFP TOP VIEW
DMC73C168
24
A
1
/
A
M
I
F
A
2
/
A
D
1
A
3
/
A
D
2
A
4
/
E
C
I
1
A
5
/
E
C
I
2
A
6
/
I
N
T
4
A
7
/
I
N
T
3
E
0
/
S
O
1
E
1
/
S
I
1
E
2
/
S
C
L
K
1
E
3
/
S
O
2
E
4
/
S
I
2
E E E F F F F F F F F
5 6 7 0 1 2 3 4 5 6 7
/
/
S
B
C
E
L
E
K
P
2
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
H2
H1
H0
G7
G6
G5
G4
G3
G2
G1
G0
TEST
VDD
OSCOUT
OSCIN
VSS
7
8Bit Single Chip Microcontroller
D
A
T
A
2
D
A
T
A
1
DMC73C168
D
A
T
A
0
A
D
D
R
7
A
D
D
R
6
A
D
D
R
5
A
D
D
R
4
A
D
D
R
3
¡é ¡é ¡é ¡é ¡é ¡é ¡é ¡é ¡é ¡é ¡é ¡é ¡é ¡é ¡é ¡é ¡é ¡é ¡é ¡é ¡é ¡é ¡é ¡é
64
¡ê 65
¡ê
¡ê
¡ê
¡ê
¡ª
¡ç
¡ç
¡ª
VSS ¡ª
¡æ
¡æ
VDD ¡æ
¡ª
¡æ
VSS ¡ª 80
* 1
41
¡ê
¡ê
¡ê
¡ê
¡ê
¡ê
¡ê
¡ê
¡ê
¡ê
¡ê
¡ç
¡ç
¡æ
¡ç
25 ¡ª
DATA3
DATA4
DATA5
DATA6
DATA7
80 PIN QFP TOP VIEW
OTP MODE
24
¡é ¡é ¡é ¡é ¡é ¡é ¡é ¡é ¡é ¡é ¡é ¡é ¡é ¡é ¡é ¡é ¡é ¡é ¡é ¡é ¡é ¡é ¡é ¡é
X X X E E
P C O P P
G E E T T
M
E E
S S
T T
H
V
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
ADDR2
ADDR1
ADDR0
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
VPP
VDD
VSS
VSS
8
8Bit Single Chip Microcontroller
3.2
DMC73C168
Description
NAME
Pin No.
I/O
FUNCTIONAL DESCRIPTION
PORT TYPE
A0/FM IF
A1/AM IF
1
2
I/O
I/O
Port A is a bidirectional data port.
These Ports can be selected as universal Counter
input. A0 and A1 work as the FM IF and AM IF pin,
independently. The maximum input frequency is 5MHz
for AM IF (0.1Vp-p) and 20MHz (0.1Vp-p) for FM IF.
Analog-IN or
Logic-IN/
Push-Pull OUT
A2/AD1
A3/AD2
3
4
I/O
I/O
These Posts can be selected for an A/D Converter Input.
2 Channel/8-Bit Analog-to-Digital Converter are used for
the Sequential Comparison method by program.
Reference Voltage of the A/D Converter is the same
level of VDD (5V ¡ 1
¾0%)
Analog-IN or
Logic-IN/
Push-Pull OUT
A4/ECI1
A5/ECI2
5
6
I/O
I/O
The A4,A5 Port can be used as event counter input 1,2.
A6/INT4
A7/INT3
7
8
I/O
I/O
These Ports can be used as external interrupt pin.
E0/SO1
E1/SI1
E2/SCLK1
9
10
11
I/O
I/O
I/O
Port E is a bidirectional data port.
These Ports can be selected as serial interface (SIO) 1.
E0, E1 and E2 work as the serial output, serial input and
serial clock pin, respectively.
E3/SO2
E4/SI2
E5/SCLK2
12
13
14
I/O
I/O
I/O
These Ports can be selected as serial interface (SIO) 2.
E3, E4 and E5 work as the serial output, serial input and
serial clock pin, respectively.
E6
E7/BEEP
15
16
I/O
I/O
The E7 Port can be used as BEEP output pin.
F0
F1
F2
F3
F4
F5
F6
F7
17
18
19
20
21
22
23
24
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Logic-IN or
SchmittTrigger-IN/
Push-Pull OUT
Logic-IN/
Push-Pull OUT
Logic-IN/
Push-Pull OUT
Port F is a bidirectional data port.
Logic-IN/
Push-Pull OUT
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
9
8Bit Single Chip Microcontroller
DMC73C168
NAME
G0
G1
G2
G3
G4
G5
G6
G7
PIN NO.
30
31
32
33
34
35
36
37
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
FUNCTION DESCRIPTION
Port G is a bidirectional data port.
PORT TYPE
Logic-IN/
Push-Pull OUT
H0
H1
H2
H3
H4
H5
H6
H7
38
39
40
41
42
43
44
45
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port H is a bidirectional data port.
Logic-IN/
Push-Pull OUT
B0/T1OUT
B1/T2OUT
B2
B3
B4
B5
B6
B7
46
47
48
49
50
51
52
53
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port B is a bidirectional data port.
Port B0, B1 can be selected as Timer 1 & 2 output ports.
Logic-IN/
Push-Pull OUT
D0
D1
D2
D3
D4
D5
D6
D7
54
55
56
57
58
59
60
61
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port D is a bidirectional data port.
Logic-IN/
Push-Pull OUT
C0
C1
C2
C3
C4
C5
C6
C7
62
63
64
65
66
67
68
69
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port C is a bidirectional data port.
Logic-IN/
Push-Pull OUT
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
10
8Bit Single Chip Microcontroller
DMC73C168
NAME
Pin No.
I/O
FUNCTION DESCRIPTION
VCOH
75
I
FM VCO input port.
Only Pulse swallow method is used for this port.
The range of local oscillator output is 10MHz to 150MHz
with 0.3Vp-p minimum.
The output is required by capacitor coupling because an
AC amplifier is contained.
Analog-IN
VCOL
76
I
AM VCO input port.
This terminal can be selected by direct-dividing method
or pulse-swallow method.
In direct-dividing method, the range of local oscillator
output is 0.5MHz to 10MHz with 0.3Vp-p minimum, and
in pulse-swallow method, the range of local oscillator
output is 5MHz to 40MHz with 0.3Vp-p minimum.
Input to this port should be coupled by capacitor coupling
because and AC amplifier is contained.
Analog-IN
VDD
VREF
28
77
Power source port.
The terminal suppl ies 5V ¡ 1
¾0% for normal operation.
VDD and VREF must be connected to the same electric
potential. VDD is a power for logic circuit and VREF is a
power for analog circuit in the device.
NC
70
No connection
EO1
EO2
71
72
O
O
Phase comparison error output ports.
3-State-OUT
The divided frequency of VCO output and the reference
frequency are compared in their phase.
If divided frequency is higher than the reference frequency,
output signal is logic high level. If divided frequency is
lower than the reference frequency, output signal is vice
versa. When two frequencies are matched, port become a
floating state.
EO1 and EO2 have the same waveform.
TEST
29
I
Internal Chip Test port.
It should be connected to VSS.
VSS
VASS
73, 25
74
OSCOUT
OSCIN
27
26
Ground reference
VSS is a ground for logic circuit and VASS is a ground for
Analog circuit in the device
O
I
Crystal oscillator input and output ports.
Connect 4.5MHz Crystal.
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
PORT TYPE
11
8Bit Single Chip Microcontroller
NAME
PIN NO.
NC
78
RESET
80
DMC73C168
I/O
FUNCTION DESCRIPTION
PORT TYPE
No connection
I
System reset request input port.
The reset pin must be held low for minimum of 5 internal
clock cycles to guarantee recognition by the device.
The dev ice initialization requires 15 machine cycles.
CE/INT1
79
I
Device selection Signal input port.
Schimitt-
External interrupt input port.
Trigger-IN
This port can be used as a Chip Enable input.
W hen activated, CPU resumes its operation from HALT
mode
4. ARCHITECTURE
The DMC73C168 has a maximum memory address space of 64K bytes and only the Single-Chip mode.
On-Chip memory spaces are configured as shown in Table 4.1.
In the sections that follow, the Register File (RF) and the Peripheral File (PF) are described along
with three important registers in the CPU : the Stack Pointer (SP), the Status Register (ST), and the
Program Counter (PC)
Memory Address
> 0000
Register File (RF)
> 00FF
; 256 byte RAM
> 0100
Peripheral File (PF)
> 0132
> 0133
Reserved
> 013F
> 0140
128 byte PRF
> 01BF
; 128 byte RAM
> 01C0
Not Available
> C005
> C006
16K bytes ROM
> FFFF
Table 4-1. DMC73C168 Memory Map
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
12
8Bit Single Chip Microcontroller
4.1
DMC73C168
Register File (RF)
The 256-byte on chip RAM resides in location >0000 to >00FF (‘>’ means hex) of the DMC73C168’s
address space and is called the Register File (RF). The RAM is treated as registers by much of the
instruction set and numbered R0-R255. The first two registers, R0 and R1, are also called the A and
B registers respectively. Several instructions specify A or B as either the source or destination
register ; e.g., STSP stores the contents of the Stack Pointer (SP) in the B register.
Except where stated otherwise, any register in the Register File can be addressed as an 8-bit source or
destination register. The stack is also located in the Register File. Refer to section 4.3 for information
regarding the initialization of the Stack Pointer (SP) and stack definition in the Register File.
4.2
Peripheral File (PF)
The Peripheral File (PF) resides in location >0100 to >0132 of the DMC73C168’s address space.
Peripheral File locations are numbered P0-P50. The PF registers are used for interrupt control, parallel
I/O, timer control, PLL, IF counter, BEEP, SIO and A/D converter control.
4.3
Peripheral RAM File (PRF)
The Peripheral RAM file (PRF) resides in location >0140 to >01BF of DMC73C168’s address space.
PRF will act a role P64-P191. Useage is for additional RAM, but addressing method is same as
Peripheral File’s.
Memory address
>0100
>0132
>0133
>013F
>0140
>01BF
>01C0
>01FF
P0
:
P50
Peripheral File
P51
:
P63
Not Avail
P64
:
P191
128 bytes PRF
P192
:
P255
Not Avail
Table 4.3 DMC73C168 Peripheral File Map
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
13
8Bit Single Chip Microcontroller
4.4
DMC73C168
Stack Pointer (SP)
The Stack Pointer(SP) is an 8-bit register in the CPU that is typically used to hold a pointer in RAM
(the Register File). However, the SP can also be used as temporary data storage if a stack is not
implemented, or if the SP contents are not needed. When a stack is implemented just before data is
pushed onto the stack and automatically decremented immediately after data is poped from the
stack. Upon assertion if the RESET function (see Section 4.7) >01 is loaded into the SP. The size
of the stack can be changed from the 254-level stack at RESET to a smaller stack by executing
a stack initialization program as illustrated in Figure 4.4. The This feature allows the stack to be
located anywhere in the Register File. The SP is initialized through the B register (R1).
RF
RF
SP
>0001
RF
>01
>0002
ST
>0003
Interrupt
>0004
PCH
SP
PCL
>04
>0005
CALL
>0006
Figure 4.4
PCH
SP
PCL
>06
Example of Stack Initialization in the Register File
4.5 Status Register (ST)
The Status Register (ST) is an 8-bit register in the CPU that contains three conditional status bits ;
Carry (C), Sign (N), Zero (Z), and a global Interrupt Enable bit (I) as shown in Figure 4-5.
Bit
7
6
5
4
C
N
Z
I
C
N
Z
I
:
:
:
:
3
2
1
FUTURE USE
CARRY OUT
SIGN
ZERO
INTERRUPT ENABLE
Figure 4-5. Status Register (ST)
The C, N and Z bits are used mostly for arithmetic operations, bit rotating, and conditional branching.
The Carry(C) bits is used as the carry-in and carry-out for most of lotate and arithmetic instructions.
The Sign(N) bit contains the most significant bit of the destination operand contents after instruction
execution. The Zero(Z) bit contains a one when all bits of the destination operand are equal to zero
after instruction execution. The C, N and Z status bits also have jump-on-condition instructions
associated them. The global Interrupt Enable (I) bit must be set to one by the EINT instruction in
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
0
14
8Bit Single Chip Microcontroller
DMC73C168
order for any of the individual interrupts (INTn) to be recognized by the CPU. The Interrupt Enable
(I) bit can cleared by DINT instruction of by executing a device RESET (see Section 4.7).
4.6
Program Counter (PC)
The DMC73C168’s 16-bit Program Counter (PC) consists of two 8-bit registers in the CPU which
contain the MSB and the LSB respectively of a 16-bit address ; the Program Counter High (PCH) and
Low (PCL). The PC acts as the 16-bit address pointer of the opcodes and operands in memory of the
currently executing instruction. Upon assertion of the RESET function, the MSB and the LSB of the PC
are loaded into the A and B registers of the Register File (see Section 4.7).
4.7
Peripheral File Map
The Peripheral File (PF) resides in locations >0100 to >01BF of the DMC73C168’s address space as
shown in Table 4.7
Table 4.7 Peripheral File Map
REGISTER
ADDRESS
P0
P1
P2
P4
>0100
>0101
>0102
>0104
P5
NAME
NOTE
FUNCTION
IOCTL0
IOCTL1
IOCTL2
T1MSDATA
1
1
1
1
>0105
T1LSDATA
1
P6
>0106
T1CTL0
1
P7
>0117
T1CTL1
1
P8
>0118
T2MSDATA
1
P9
>0109
T2LSDATA
1
P10
>010A
T2CTL0
1
P11
>010B
T2CTL1
1
P13
P14
P15
P16
>010D
>010E
>010F
>0110
APSLCT
ADCTL
ADDATA
PLLCTL0
1
1
Interrupt 1,2 and 3 control register
Ext-INT 1,3 and 4 input edge select
Interrupt 4,5,6,7 control register
Timer 1 MSB reload register
/ MSB readout latch
Timer 1 LSB reload register
/ LSB decrementer value
Timer 1 control register 0
/ MSB readout latch
Timer 1 control register 1
/ LSB capture latch value
Timer 2 MSB reload register
/ MSB readout latch
Timer 2 LSB reload register
/ LSB decrementer value
Timer 2 control register 0
/ MSB readout latch
Timer 2 control register 1
/ LSB capture latch value
A port select control register
A/D converter control register
A/D converter data value
PLL control register 0
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
RESET
VALUE
00000000
0000x000
00000000
xxxxxxxx
xxxxxxxx
x0xxxxxx
0x0xxxxx
xxxxxxxx
xxxxxxxx
00xxxxxx
0x0xxxxx
00000000
00xxxxx0
00000000
00000000
15
8Bit Single Chip Microcontroller
REGISTER
ADDRESS
P17
P18
P19
P22
P23
P24
P25
P27
P28
P29
P30
P32
P33
P34
P35
P36
P37
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P50
P64
:
:
P191
>0111
>0112
>0113
>0116
>0117
>0118
>0119
>011B
>011C
>011D
>011E
>0120
>0121
>0122
>0123
>0124
>0125
>0126
>0127
>0128
>0129
>012A
>012B
>012C
>012D
>012E
>012F
>0132
>0140
:
:
>01BF
Notes
NAME
PLLCTL1
PLLDATAH
PLLDATAL
IFCCTL
IFCLSD
IFCMSD
IFCHSD
SIO1CTL
SIO1BUF
SIO2CTL
SIO2BUF
ADATA
ADDR
BDATA
BDDR
CDATA
CDDR
DDATA
DDDR
EDATA
EDDR
FDATA
FDDR
GDATA
GDDR
HDATA
HDDR
BEEP
DMC73C168
NOTE
FUNCTION
1
PLL control register 1
PLL program counter MSB data register
PLL program counter LSB data register
IF counter data register
IF counter data register (LSB)
IF counter data register
IF counter data register (MSB)
SIO 1 control register
SIO 1 data register
SIO 2 control register
SIO 2 data register
Port A data value
Port A direction register
Port B data value
Port B direction
Port C data value
Port C direction register
Port D data value
Port D direction register
Port E data value
Port E direction register
Port F data value
Port F direction register
Port G data value
Port G direction register
Port H data value
Port H direction register
BEEP control register
Peripheral RAM
128 bytes
1
1
1
1
RESET
VALUE
0xx x0000
00000000
00000000
00000000
00000000
00000000
xxxxxxx0
0000000x
xxxxxxxx
0000000x
xxxxxxxx
xxxxxxxx
00000000
xxxxxxxx
00000000
xxxxxxxx
00000000
xxxxxxxx
00000000
xxxxxxxx
00000000
xxxxxxxx
00000000
xxxxxxxx
00000000
xxxxxxxx
00000000
00000000
xxxxxxxx
xxxxxxxx
1 : Be careful when using logical instructions (e.g., ANDP, ORP, XORP) on these registers
because of different read/write functions.
2 : ‘x’ means indeterminate
3 : P3, P12, P20, P21, P26,P31, P48, P49, P51-63 are not implemented.
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
16
8Bit Single Chip Microcontroller
4.7.1
DMC73C168
Peripheral Files detail Description
I/O CONTROL REGISTERS
1)
PF NAME : IOCTL0
R/W
P0
READ
>0100
WRITE
: I/O CONTROL REGISTER 0
BIT 7
BIT 6
NOT USED
RESET VALUE
X
X
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
INT3F
INT3E
INT2F
INT2E
INT1F
INT1E
INT3C
INT3E
INT2C
INT2E
INT1C
INT1E
O
O
O
O
O
O
X = Indeterminate
Read : INTnF : 0 = INTn inactive
1 = INTn pending
PF NAME :
IOCTL1
R/W
Write : INTnE : 0 = INTn disable
1 = INTn enable
INTnC : 0 = No Effect
1 = Clear INTn flag
: I/O CONTROL REGISTER 1
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
P1
READ
INT41F
INT41E
INT40F
INT40E
NOT
INT40S
INT3S
INT1S
>0101
WRITE
INT41C
INT41E
INT40C
INT40E
USED
INT40S
INT3S
INT1S
O
X
O
O
O
O
O
O
RESET VALUE
X = Indeterminate
INT41 = INT4-1
INT40 = INT4-0
Read : INTnF : 0 = INTn inactive
1 = INTn pending
INTnS : 0 = Falling edge sensing
1 = Rising edgi sensing
PF NAME : IOCTL2
Write : INTnE : 0 = INTn disable
1 = INTn enable
INTnC : 0 = No Effect
1 = Clear INTn flag
: I/O CONTROL REGISTER 2
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
P2
READ
INT7F
INT7E
INT6F
INT6E
INT5F
INT5E
INT4F
INT4E
>0102
WRITE
INT7C
INT7E
INT6C
INT6E
INT5C
INT5E
X
INT4E
RESET VALUE
O
O
O
O
O
O
O
Read : INTnF : 0 = INTn inactive
Write : INTnE : 0 = INTn disable
1 = INTn pending
1 = INTn enable
This bit is automatically cleared
INTnC : 0 = No Effect
When CPU fetch its vector address.
1 = Clear INTn flag
<< INT4F is not automatically cleared
When CPU fetch v ector address>>
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
O
17
8Bit Single Chip Microcontroller
2)
DMC73C168
TIMER 1 & 2 CONTROL REGISTERS
PF NAME : T1MSDATA
R/W
BIT 7
:
BIT 6
TIMER 1 MS BYTE DATA REGISTER
BIT 5
BIT 4
BIT 3
BIT 2
P4
READ
MSB READOUT LATCH
>0104
WRITE
MSB READOUT LATCH
RESET VALUE
X
X
X
PF NAME : T1LSDATA
R/W
BIT 7
X
X
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
LSB DECREMENTER VALUE
>0105
WRITE
LSB RELOAD REGISTER
X
X
PF NAME : T1CTL0
R/W
P6
READ
>0106
WRITE
RESET VALUE
T1OUT :
:
BIT 7
BIT 6
P7
READ
>0107
WRITE
X
BIT 1
BIT 0
X
X
X
X
X
BIT 1
BIT 0
X
X
TIMER 1 CONTROL REGISTER 0
BIT 5
BIT 4
BIT 3
BIT 2
MSB READOUT LATCH
X
T1OUT
X
X
X
X
X
O
X
X
X
X
X
X
Timer 1 toggle output enable bit.
This write bit determines PORT B0 is timer 1 toggle output pin or normal I/O pin.
0 = PORT B0 is normal I/O pin.
1 = PORT B0 is timer 1 toggle output in, and B0 is toggle when Timer 1
decrements through zero value.
PF NAME : T1CTL1
R/W
X
: TIMER 1 LS BYTE DATA REGISTER
READ
X
BIT 0
X
P5
RESET VALUE
BIT 1
BIT 7
:
BIT 6
TIMER 1 CONTROL REGISTER 1
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
LSB CAPTURE LATCH
START1
SOURC1
T1HALT
PRESCALER RELOAD REGISTER (PL)
RESET VALUE
O
X
O
X
X
X
X
X
Write : SOURC1 : 0 = Internal clock source Fosc/4
1 = External clock source from A4/ECI1
START1 : 0 = Timer 1 is stop, hold current count value and clear INT2 flag.
1 = Timer 1 reloads prescaler and decrementer, begins decrementing.
T1HALT : 0 = Timer 1 remains active when execute IDLE instruction. (WAKE-UP)
1 = Timer 1 will halt when execute IDLE instruction. (HALT)
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
18
8Bit Single Chip Microcontroller
DMC73C168
PF NAME : T2MSDATA
R/W
BIT 7
:
BIT 6
TIMER 2 MS BYTE DATA REGISTER
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
X
X
BIT 1
BIT 0
X
X
BIT 2
BIT 1
BIT 0
X
X
X
P8
READ
MSB READOUT LATCH
>0108
WRITE
MSB READOUT REGISTER
RESET VALUE
X
X
X
PF NAME : T2LSDATA
R/W
BIT 7
X
X
X
: TIMER 2 LS BYTE DATA REGISTER
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
P9
READ
LSB DECREMENTER VALUE
>0109
WRITE
LSB RELOAD REGISTER
RESET VALUE
X
X
X
PF NAME : T2CTL0
R/W
P10
READ
>010A
WRITE
BIT 7
:
BIT 6
X
X
X
TIMER 2 CONTROL REGISTER 0
BIT 5
BIT 4
BIT 3
MSB READOUT LATCH
CASCADE
T2OUT
X
X
X
RESET VALUE
T2OUT :
O
O
X
X
X
X
X
X
Timer 2 toggle output enable bit.
This write bit determines PORT B1 is timer 2 toggle output pin or normal I/O pin.
0 = PORT B1 is normal I/O pin.
1 = PORT B1 is timer 1 toggle output pin, and B1 is toggle when Timer 2
decrements through zero value.
CASCADE :
Timer 2 cascade control bit
0 = Timer 2 is not cascaded with Timer 1, Timer 2 clock is determined by
source bit.
1 = Timer 1 and 2 are cascaded, clock source is generated by Timer 1 reload
pulse, overrides source bit.
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
19
8Bit Single Chip Microcontroller
DMC73C168
PF NAME : T2CTL1
R/W
P11
READ
>010B
WRITE
: TIMER 2 CONTROL REGISTER 1
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
LSB CAPTURE LATCH
START2
SOURC2
T2HALT
PRESCALER RELOAD REGISTER (PL)
RESET VALUE
O
X
O
X
X
X
X
X
Write : SOURC2 : 0 = Internal clock source Fosc/4
1 = External clock source from A5/ECI2
START2 : 0 = Timer 2 is stop, hold current count value and clear INT6 flag.
1 = Timer 2 reloads prescaler and decrementer, begins decrementing.
T2HALT : 0 = Timer 2 remains active when execute IDLE instruction. (WAKE-UP)
1 = Timer 2 will halt when execute IDLE instruction. (HALT)
3) A/D CONVERTER REGISTERS
PF NAME : APSLCT
R/W
: PORT A SELECT CONTROL REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
P13
READ
INT3SEL
INT40SEL
NOT USED
AD2SEL
AD1SEL
AMIFSEL
FMIFSEL
>010C
WRITE
INT3SEL
INT40SEL
NOT USED
AD2SEL
AD1SEL
AMIFSEL
FMIFSEL
O
O
O
O
O
O
RESET VALUE
FMIFSEL
AMIFSEL :
AD1SEL
AD2SEL :
INT40SEL
INT3SEL :
O
O
FM and AM IF input enable bits. This read/write bits disable digital inputs
when FM and AM IF inputs are enabled.
0 = PORT A0 and A1 are normal I/O pins.
1 = PORT A0 and A1 are disabled.
A/D converter input enable bits. This read/write bits disable digital inputs
when A/D converter inputs when A/D converter inputs are enabled.
0 = PORT A2 and A3 are normal I/O pins.
1 = PORT A2 and A3 are disabled.
External interrupt 3 and 4-0 input enable bits. This read/write disable Digital
inputs when A/D converter inputs are enabled.
0 = PORT A7 and A6 are normal I/O pins.
1 = PORT A7 and A6 are disabled
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
20
8Bit Single Chip Microcontroller
PF NAME : ADCTL
DMC73C168
: A/D CONTROL REGISTER
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
P14
READ
READY START
NOT USED
ADCHS
>010E
WRITE READYC START
NOT USED
ADCHS
RESET VALUE
O
O
X
X
X
X
X
O
BIT 2
BIT 1
BIT 0
READ :
READY : 0 = No Operation or Incomplete Conversion
1 = Complete Conversion
WRITE
ADCHS : 0 = A/D Converter Input Channel is PORT A2
1 = A/D Converter Input Channel is PORT A3
START
: 0 = Conversion Stop
1 = Conversion Start
READYC : 0 = Ineffect
1 = Clear Ready Flag
PF NAME : ADDATA
: A/D CONVERTER DATA REGISTER
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
P15
READ
CONVERSION DATA REGISTER
>010F
WRITE
NOT USED (INVALID)
RESET VALUE
O
O
O
O
O
O
O
O
BIT 3
BIT 2
BIT 1
BIT 0
4) PLL (PHASE LOCKED LOOP) REGISTER
PF NAME : PLLCTL0
R/W
P16
READ
>0110
WRITE
RESET VALUE
: PLL CONTROL REGISTER 0
BIT 7
BIT 6
BIT 5
BIT 4
NOT USED
INSL1
INSL0
REF2
REF1
REF0
DTM2
DTM1
DTM0
O
O
O
O
O
O
O
O
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
21
8Bit Single Chip Microcontroller
DMC73C168
WRITE :
PHASE DETECT TIME SELECT
DTM2
0
0
0
0
1
1
1
1
DTM1
0
0
1
1
0
0
1
1
DTM0
0
1
0
1
0
1
0
1
DETECT TIME
0.44 us
0.55 us
0.66 us
0.77 us
0.88 us
1.00 us
1.11 us
1.22 us
PHASE DETECT TIME SELECT
REF2
0
0
0
0
1
1
1
1
REF1
0
0
1
1
0
0
1
1
REF0
0
1
0
1
0
1
0
1
REF. FREQ
1.0 KHz
5.0 KHz
6.25 KHz
9.0 KHz
10.0 KHz
12.5 KHz
25.0 KHz
50.0 KHz
INSL0
0
1
0
1
INPUT MODE
NOT USED
AM DIRECT
AM SWALLOW
FM SWALLOW
MODE SELECT
INSL1
0
0
1
1
PF NAME : PLLCTL1
R/W
: PLL START/STOP CONTROL REGISTER 1
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
P17
READ
READY
X
X
X
REFTST PLLTST
>0111
WRITE
PLLEN
X
X
X
REFTST PLLTST
O
X
X
X
RESET VALUE
O
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
O
BIT 1
BIT 0
UL1
UL0
NOT USED
O
O
22
8Bit Single Chip Microcontroller
DMC73C168
READ :
PLL UNLOCK STATUS DETECT :
UL1
0
0
1
1
UL0
0
1
0
1
STATUS
PLL LOCK/STOP/OFF
REF FREQ > VCO FREQ
REF FREQ < VCO FREQ
NOT USED
READY : 0 = NO OPERATION
1 = ACTIVE
WRITE :
PLLTST : PLL TEST BIT (ATTENTION : SHOULD BE SET "0" IN NORMAL OPERATION)
0 = ACTIVE NORMAL
1 = TEST MODE
REFTST : REFERENCE DIVIDER TEST BIT(SHOULD BE SET "0" IN NORMAL OPERATION)
0 = ACTIVE NORMAL OPERATION
1 = REFERENCE TEST MODE
PLLEN
: 0 = PLL OFF, PLL STOP
1 = PLL ON, PLL START
PF NAME : PLLDATAH
R/W
P18
READ
>0112
WRITE
BIT 7
O
PF NAME : PLLDATAL
P19
READ
>0113
WRITE
RESET VALUE
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
O
O
O
O
BIT 2
BIT 1
BIT 0
PLL PC MSB DATA
RESET VALUE
R/W
: PLL PC MSB DATA REGISTER
O
O
O
: PLL PC LSB DATA REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
PLL PC LSB DATA
O
O
O
BIT 3
SWALLOW COUNTER VALUE
O
O
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
O
O
O
23
8Bit Single Chip Microcontroller
DMC73C168
5) IF COUNTER REGISTER
PF NAME : IFCCTL
: IF CONTROL REGISTER
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
P22
READ
READY
FMIF
AMIF
TSTIF
TP3
TP2
TP1
TP0
>0116
WRITE
START
O
O
O
O
O
O
O
RESET VALUE
O
READ :
READY : 0 = INACTIVE OR COMPLETE COUNTER
1 = INCOMPLETE OR ACTIVE COUNTER
WRITE :
IF FREQ. COUNTING PERIOD SELECT (TP0, TP1, TP2, TP3)
TP3
TP2
TP1
TP0
COUNT TIME
0
0
0
0
X
0
0
0
1
1 ms
0
0
1
0
2 ms
0
0
1
1
3 ms
0
1
0
0
4 ms
0
1
0
1
5 ms
0
1
1
0
6 ms
0
1
1
1
7 ms
1
0
0
0
8 ms
1
0
0
1
9 ms
1
0
1
0
10 ms
1
0
1
1
11 ms
1
1
0
0
12 ms
1
1
0
1
13 ms
1
1
1
0
14 ms
1
1
1
1
15 ms
TSTIF
: IF COUNTER TEST BIT
(ATTENTION : SHOULD BE SET TO "0" IN NORMAL OPERATION)
0 = NORMAL ACTIVE MODE
1 = TEST MODE
AMIF, FMIF : IF COUNTER INPUT SELECT
FMIF
AMIF COUNTING INPUT
0
0
NOT INPUT
0
1
AMIF
1
0
FMIF
1
1
X
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
24
8Bit Single Chip Microcontroller
START
: IF COUNTER START/STOP
0 = STOP (DISABLE)
1 = START (ENABLE)
PF NAME : IFCLSD
R/W
P23
DMC73C168
: IF COUNTER LSB VALUE
BIT 7
BIT 6
BIT 5
READ
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
IF COUNTER LSB VALUE
>0117
RESET VALUE
O
O
O
O
O
O
O
O
BIT 3
BIT 2
BIT 1
BIT 0
O
O
O
BIT 2
BIT 1
BIT 0
IF Counter LSB data bits
This read bits are LSB 8 bits of 17 bits IF Counter.
PF NAME : IFCMSD
R/W
P24
: IF COUNTER VALUE
BIT 7
BIT 6
READ
BIT 5
BIT 4
IF COUNTER MSB-1 VALUE
>0118
RESET VALUE
O
O
O
O
O
IF Counter MSB data bits
This read bits are MSB 8 bits (from bit-15 to bit-8) of 17 bits IF Counter.
PF NAME : IFCHSD
R/W
P25
: IF COUNTER MSB VALUE
BIT 7
BIT 6
BIT 5
READ
BIT 4
BIT 3
NOT USED
IFD16
>0119
RESET VALUE
X
X
X
X
X
IF Counter MSB data bits
This read bits are MSB 1 bits (bit-16) of 17 bits IF Counter.
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
X
X
O
25
8Bit Single Chip Microcontroller
DMC73C168
6) SERIAL I/O REGISTERS
PF NAME : SIO1CTL
R/W
: SERIAL I/O 1 CONTROL REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BAU10
P27
READ
SIO1AF CKSRC1 BAU11
>011B
WRITE
SIO1ST CKSRC1
RESET VALUE
O
O
O
O
BIT 3
BIT 2
BIT 1
BIT 0
SIO1EF SCLK1E SO1ENA
X
SIO1EC SCLK1E SO1ENA
X
O
O
O
X
SIO1AF :
SIO1 operation flag bit.
This read bit determines SIO1 is enabled or not.
0 = SIO1 is stop state
1 = SIO1 is processing state
SIO1ST :
SIO1 start enable bit
This write bit determines SIO1 is start or not.
0 = SIO1 is stop
1 = SIO1 is started
* Caution : This bit should be reset to "0" before 8bit transmition for proper SIO
operation.
CKSRC1 :
SIO1 clock source selection bit
This read/write bit determines SIO1 clock source in from external or internal.
0 = SIO1 clock is from internal
1 = SIO1 clock is from external
BAU1n
SIO1 transmission speed select bits.
This read/write bits determine SIO1 transmission speed.
:
BAU11
0
0
1
1
BAU10
0
1
0
1
SCLK FREQ. (Fosc = 4.5MKHz)
Fosc/8
=
563 KHz
Fosc/16
=
281 KHz
Fosc/32
=
141 KHz
Fosc/64
=
70 KHz
SIO1EF :
Transmission error flag bit
This read bit shows overrun error was occured or not
0 = Overrun error is not occured
1 = Overrun error is occured
SIO1EC :
Transmission error flag clear bit
This write bit determines transmission error flag is cleared or not
0 = Transmission error flag is not affected
1 = Transmission error flag is cleared
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
26
8Bit Single Chip Microcontroller
DMC73C168
SCLK1E :
SIO1 clock enable bit
This read/write bit determines PORT E2 bit is SIO1 clock output pin or not
0 = PORT E2 is normal I/O port
1 = PORT E2 is assigned SIO1 clock output pin when "CKSRC1" is set.
(Then, PORT E2 direction should be output)
SO1ENA :
Serial output enable bit
This read/write bit determines PORT E0 is SO1 pin or not
0 = PORT E0 is normal I/O port
1 = PORT E0 is assigned SO1 pin (Then, PORT E0 direction should be output state)
PF NAME : SIO1BUF
R/W
: SERIAL I/O 1 DATA REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
X
X
X
BIT 2
BIT 1
BIT 0
P28
READ
SIO1 RECEIVING DATA
>011C
WRITE
SIO1 TRANSMITTING DATA
RESET VALUE
X
X
X
X
X
X : INDETERMINATOR
PF NAME : SIO2CTL
R/W
: SERIAL I/O 2 CONTROL REGISTER
BIT 7
BIT 6
BIT 5
P29
READ
SIO2AF CKSRC2 BAU21
>011D
WRITE
SIO2ST CKSRC2
RESET VALUE
O
O
O
BIT 4
BIT 3
BAU20 SIO2EF SCLK2E SO2ENA
X
SIO2EC SCLK2E SO2ENA
X
O
O
O
O
X
SIO2AF :
SIO2 Operation flag bit.
This read bit determines SIO2 is enabled or not.
0 = SIO2 is stop state
1 = SIO2 is processing state
SIO2ST :
SIO2 start enable bit.
This write bit determines SIO2 is start or not
0 = SIO2 is stop
1 = SIO2 is start
* Caution : This bit should be reset to "0" before 8bit transmition for proper SIO
operation.
CKSRC2 :
SIO2 clock source selection bit
This read/write bit determines SIO2 clock source in from external or internal
0 = SIO2 clock is from internal
1 = SIO2 clock is from external
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
27
8Bit Single Chip Microcontroller
BAU2n
:
DMC73C168
SIO2 transmission speed select bits.
This read/write bits determine SIO2 transmission speed.
BAU21
0
0
1
1
BAU20
0
1
0
1
SCLK FREQ. (Fosc=4.5KHz)
Fosc/8
=
563 KHz
Fosc/16
=
281 KHz
Fosc/32
=
141 KHz
Fosc/64
=
70 KHz
SIO2EF :
Transmission error flag bit
This read bit shows overrun error was occured or not
0 = Overrun error is not occured
1 = Overrun error is occured
SIO2EC :
Transmission error flag clear bit
This write bit determines transmission error flag is cleared or not.
0 = Transmission error flag is not affected
1 = Transmission error flag is cleared
SCLK2E :
SIO2 clock enable bit
This read/write bit determines PORT E5 bit is SIO2 clock output pin or not
0 = PORT E5 is normal I/O port
1 = PORT E5 is assigned SIO2 clock output pin when "CKSRC2" is set.
(Then, PORT E5 direction should be output)
SO2ENA :
Serial output enable bit
This read/write bit determines PORT E3 is SO2 pin or not
0 = PORT E3 is normal I/O port
1 = PORT E3 is assigned SO2 pin (Then, PORT E3 direction should be output state)
PF NAME : SIO2BUF
R/W
: SERIAL I/O 2 DATA REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
P30
READ
SIO2 RECEIVING DATA
>011E
WRITE
SIO2 TRANSMITTING DATA
RESET VALUE
X
X
X
X
X
X : INDETERMINATOR
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
X
BIT 1
BIT 0
X
X
28
8Bit Single Chip Microcontroller
DMC73C168
7) PORT DATA / DIRECTION REGISTER
PF NAME : ADATA
R/W
P32
READ
>0120
WRITE
RESET VALUE
: PORT A DATA REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
X
X
X
BIT 2
BIT 1
BIT 0
O
O
O
BIT 2
BIT 1
BIT 0
X
X
X
BIT 2
BIT 1
BIT 0
O
O
PORT A DATA VALUE
X
X
X
X
X
X : INDETERMINATOR
PF NAME : ADDR
R/W
: PORT A DIRECTION REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
P33
READ
NOT USED
>0121
WRITE
PORT A DIRECTION REGISTER
RESET VALUE
O
O
0 : PORT A INPUT MODE
PF NAME : BDATA
R/W
P34
READ
>0122
WRITE
RESET VALUE
O
O
O
1 : PORT A OUTPUT MODE
: SERIAL I/O 1 DATA REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
PORT B DATA VALUE
X
X
X
X
X
X : INDETERMINATOR
PF NAME : BDDR
R/W
: PORT B DIRECTION REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
P35
READ
NOT USED
>0123
WRITE
PORT B DIRECTION REGISTER
RESET VALUE
O
0 : PORT B INPUT MODE
O
O
O
O
1 : PORT B OUTPUT MODE
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
O
29
8Bit Single Chip Microcontroller
PF NAME : CDATA
R/W
P36
READ
>0124
WRITE
RESET VALUE
DMC73C168
: PORT C DATA REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
X
X
X
BIT 2
BIT 1
BIT 0
O
O
O
BIT 2
BIT 1
BIT 0
X
X
X
BIT 2
BIT 1
BIT 0
O
O
PORT C DATA VALUE
X
X
X
X
X
X : INDETERMINATOR
PF NAME : CDDR
R/W
P37
READ
>0125
WRITE
RESET VALUE
: PORT C DIRECTION REGISTER
BIT 7
BIT 6
READ
>0126
WRITE
RESET VALUE
BIT 3
PORT C DIRECTION REGISTER
O
PF NAME : DDATA
P38
BIT 4
NOT USED
O
0 : PORT C INPUT MODE
R/W
BIT 5
O
O
O
1 : PORT C OUTPUT MODE
: PORT D DATA REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
PORT D DATA VALUE
X
X
X
X
X
X : INDETERMINATOR
PF NAME : DDDR
R/W
P39
READ
>0127
WRITE
RESET VALUE
: PORT D DIRECTION REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
PORT D DIRECTION REGISTER
O
0 : PORT D INPUT MODE
O
O
O
O
1 : PORT D OUTPUT MODE
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
O
30
8Bit Single Chip Microcontroller
PF NAME : EDATA
R/W
P40
READ
>0128
WRITE
RESET VALUE
DMC73C168
: PORT E DATA REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
X
X
X
BIT 2
BIT 1
BIT 0
O
O
O
BIT 2
BIT 1
BIT 0
X
X
X
BIT 2
BIT 1
BIT 0
O
O
PORT E DATA VALUE
X
X
X
X
X
X : INDETERMINATOR
PF NAME : EDDR
R/W
P41
READ
>0129
WRITE
RESET VALUE
: PORT E DIRECTION REGISTER
BIT 7
BIT 6
O
PF NAME : FDATA
R/W
READ
>012A
WRITE
RESET VALUE
BIT 4
BIT 3
PORT E DIRECTION REGISTER
O
0 : PORT E INPUT MODE
P42
BIT 5
O
O
O
1 : PORT E OUTPUT MODE
: PORT F DATA REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
PORT F DATA VALUE
X
X
X
X
X
X : INDETERMINATOR
PF NAME : FDDR
R/W
P43
READ
>012B
WRITE
RESET VALUE
: PORT F DIRECTION REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
PORT F DIRECTION REGISTER
O
0 : PORT F INPUT MODE
O
O
O
O
1 : PORT F OUTPUT MODE
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
O
31
8Bit Single Chip Microcontroller
PF NAME : GDATA
R/W
P44
READ
>012C
WRITE
RESET VALUE
DMC73C168
: PORT G DATA REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
X
X
X
BIT 2
BIT 1
BIT 0
O
O
O
BIT 2
BIT 1
BIT 0
X
X
X
BIT 2
BIT 1
BIT 0
O
O
PORT G DATA VALUE
X
X
X
X
X
X : INDETERMINATOR
PF NAME : GDDR
R/W
P45
READ
>012D
WRITE
RESET VALUE
: PORT G DIRECTION REGISTER
BIT 7
BIT 6
O
PF NAME : HDATA
P46
READ
>012E
WRITE
RESET VALUE
BIT 4
BIT 3
PORT G DIRECTION REGISTER
O
0 : PORT G INPUT MODE
R/W
BIT 5
O
O
O
1 : PORT G OUTPUT MODE
: PORT H DATA REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
PORT H DATA VALUE
X
X
X
X
X
X : INDETERMINATOR
PF NAME : HDDR
R/W
P47
READ
>012F
WRITE
RESET VALUE
: PORT H DIRECTION REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
PORT H DIRECTION REGISTER
O
0 : PORT H INPUT MODE
O
O
O
O
1 : PORT H OUTPUT MODE
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
O
32
8Bit Single Chip Microcontroller
DMC73C168
8) BEEP REGISTER
PF NAME : BEEP
R/W
P50
READ
>0132
WRITE
RESET VALUE
: BEEP CONTROL REGISTER
BIT 7
BIT 6
BIT 5
T250MS T125MS T100MS
NOT USED
O
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
T5MS
TFEN
BPEN
FSEL1
FSEL0
O
O
O
WTSL1 WTSLO
O
O
TFEN
O
O
** CAUTION 1 "TFEN" bit must be set "1" before HALT mode.
Base clock
(1 KHz)
TFEN
T5MS
5mS
read
read
T250MS, T125MS, T100MS, T5MS : Interval timer flag bits.
This read bits is set by warm-up timer after 250ms, 125ms, 100ms, and 5ms respectively after
"TFEN" bit is set.
These flags are cleared by read operations.
WTSLn
:
Warm-up time select bits
WTSL1 WSTL0 WARM-UP TIME
0
0
25 ms
0
1
50 ms
1
0
100 ms
1
1
NO USE
TFEN
:
Warm-up timer enable bit.
This read/write bit determines warm-up timer is enabled or not
0 = Warm-up timer is disabled.
1 = Warm-up timer is enabled.
BPEN
:
0 = Beep out disable
1 = Beep out enable
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
33
8Bit Single Chip Microcontroller
FSELn
:
DMC73C168
BEEP Frequency select :
FSEL1
0
0
1
1
FSEL0
0
1
0
1
BIT 3
BIT 2
BEEP FREQ.
417Hz
(2/3 Duty)
1KHz
(1/2 Duty)
1.25 KHz (1/2 Duty)
2.5 KHz (1/2 Duty)
9) Peripheral RAM register
PF NAME : PRAM 0-127
P64-P191
R/W
: Peripheral RAM register
BIT 7
BIT 6
BIT 5
BIT 4
>140 ~
READ
Peripheral RAM register
>01BF
WRITE
Peripheral RAM register
RESET VALUE
X
X
X
X
X
BIT 1
BIT 0
X
X
X
These peripheral RAM region is >140 (hex) to >01BF (hex), and size is 128 bytes.
4.8 Interrupt and Reset Priorities
The DMC73C168 has priority servicing of interrupt levels and RESET. These levels are defined as
shown in Table 4-8. The TRAP instruction branch to a two bytes location in a reserved section of
memory called the TRAP Vector Table. As shown in Figure 4-8, each trap location stores a 16-bit
address which references either reset function (TRAP0), one of the seven interrupt service routine
(TRAP1-INT1, TRAP2-INT2, TRAP3-INT3, TRAP4-INT4, TRAP5-INT5, TRAP6-INT6, TRAP7-INT7),
or a subroutine (TRAP8-23).
Once INTn has been acknowledged by the CPU, the corresponding INTn Flag flip flop is cleared.
The CPU then pushes the contents of the Status Register and Program Counter (MSB and LSB)
onto the stack and zeros the Status Register, including the global Interrupt Enable (I) bit. the CPU
reads an interrupt code from the interrupt logic and branches to the address contained in the
corresponding interrupt vector location in memory.
The interrupt service routine can explicitly enable nested interrupt by executing the EINT instruction
to directly set I bit in the Status Register to a one, thus permitting nested interrupt to be recognized.
When the nested interrupt service routine completes, it returns to the previous interrupt service
routine by executing the RETI instruction.
Level
0
1
2
3
4-0
Name
RESET
INT1 External (CE)
INT2 Timer 1
INT3 External
INT4 External
Trigger Factor
Active Low/Level Sensitive
Program Selectable
Timer 1 through '>0000'
Program Selectable
Program Selectable
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
Vector
MSB
LSB
>FFFE >FFFF
>FFFC >FFFD
>FFFA >FFFB
>FFF8 >FFF9
>FFF6 >FFF7
34
8Bit Single Chip Microcontroller
Level
Name
DMC73C168
Trigger Factor
MSB
4-1
INT4 A/D Converter
Vector
LSB
End of A/D Conversion
5
INT5 SI/O 1
End of SI/O 1 Frame
>FFF4
>FFF5
6
INT6 Timer 2
Timer 2 through '>0000"
>FFF2
>FFF3
7
INT7 SI/O 2
End of SI/O 2 Frame
>FFF0
>FFF1
Table 4-8. Interrupt and Reset Priorities
ADDRESS
>FFD0
TRAP23 (A8 - A15)
>FFD1
TRAP23 (A0 - A7)
/
/
/
/
/
/
>FFF0
SI/O2 OR TRAP7 (A8-A15)
>FFF1
SI/O2 OR TRAP7 (A0-A7)
>FFF2
TIMER2 OR TRAP6 (A8-A15)
>FFF3
TIMER2 OR TRAP6 (A0-A7)
>FFF4
SI/O1 OR TRAP5 (A8-A15)
>FFF5
SI/O1 OR TRAP5 (A0-A7)
ADDRESS
>FFF6
>FFF7
>FFF8
>FFF9
>FFFA
>FFFB
>FFFC
>FFFD
>FFFE
>FFFF
INT4, A/D OR TRAP4 (A8-A15)
INT4, A/D OR TRAP4 (A0-A7)
INT3 OR TRAP3 (A8-A15)
INT3 OR TRAP3 (A0-A7)
TIMER1 OR TRAP2 (A8-A15)
TIMER1 OR TRAP2 (A0-A7)
INT1 OR TRAP1 (A8-A15)
INT1 OR TRAP1 (A0-A7)
RESET OR TRAP0 (A8-A15)
RESET OR TRAP0 (A0-A7)
Figure 4-8. The TRAP Vector Table
5. DESCRIPTION OF EACH FUNCTION
5.1 Input / Output Ports
DMC73C168 has 64 I/O pins organized as eight parallel ports labeled Port A,B,C,D,E,F,G,H each Port
is mapped 8 bit data value register in the Peripheral File (PF). The data value registers are usually
called APORT, BPORT, CPORT, DPORT, EPORT, FPORT, GPORT and HPORT in a program.
All Ports are implemented as bidirectional I/O Ports.
Each Bidirecitional ports has a corresponding 8 bit Data Direction Register (DDR) that programs each
ports as input or output. A bit set to one in the DDR will cause the corresponding pin to be an output,
while a zero in the DDR will cause the pin to be a high impedance input.
Upon RESET, the DDR file-flop register are set to zero by the on-chip circuitly, forcing them to become
inputs. And output data register ports (A,B,C,D,E,F,G and H) are indeterminate data set. After RESET,
if '1' s are written to the DDR register sometime before the output data register is changed then the
corresponding I/O pins will output a "1". For this reason, it is good practice that ports A,B,C,D,E,F,G,H
output data register is loaded with the desired value before any bits are configured as outputs.
The logic for each bidirectional I/O line is shown in Figure 5-1.
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
35
8Bit Single Chip Microcontroller
DMC73C168
AND
Read Data
OR
AND
Read
Direction Data
Strobe
Data
Strobe
Direction Register
D
Q
D-Flip Flop
>
Q
Data Register
D
Q
D-Flip Flop
>
Q
Output
Buffer
I/O Pin
Figure 5-1. Bidirectional I/O Logic
Port A : Port A is an 8-bit bidirectional I/O port where any of its eight pins may be individually
programmed as an input or output under software control. Reading port A data register
(P32) returns either the current value at the pin (input mode) or the current value of
port A data register (output mode). And also port A can be used as A/D converter
AM and FM IF input.
Port B : Port B is an 8-bit bidirectional I/O port where any of its eight pins may be individually
programmed as an input or output under software control. Reading port A data register
(P34) returns either the current value at the pin (input mode) or the current value of
port B data register (output mode). And also port B can be used as Timer output ports.
Port C,D,F,G,H : Port C,D,F,G,H is an 8-bit bidirectional I/O port where any of its eight pins
may be individually programmed as an input or output under software control.
Reading port C,D,F,G,H data register (P36, P38, P42, P44, P46) returns either the
current value at the pin (input mode) or the current value of port C,D,F,G,H data
register (output mode).
Port E : Port E is an 8-bit bidirectional I/O port where any of its eight pins may be individually
programmed as an input or output under software control. Reading port E data register
(P40) returns either the current value at the pin (input mode) or the current value of
port E data register (output mode). And also port E can be used as SI/O data and
clock inputs or outputs and BEEP output port.
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
36
8Bit Single Chip Microcontroller
DMC73C168
5.2 Device Initialization
Interrupt level 0 (RESET) cannot be masked and will be recognized immediately even in the middle of
instruction. To execute the level 0 interrupt, the RESET pin must be held low for minimum of 5 internal
clock cycles to guarantee recognition by the device. During assertion of the RESET pin, the following
operations are performed prior to the first instruction acquisition.
1) All zeros are written to the IOCTL0 Register and Status Register. And zero is written to the
IOCTL1, and IOCTL2. This disables all interrupt and clears all interrupt flags.
2) The initialize data are written to the Peripheral Registers. And all zeros are written to the
APSLCT, ADDR, BDDR, CDDR, DDDR, EDDR, FDDR, GDDR and HDDR.
3) The MSB and LSB values of the Program Counter Just before RESET are stored in R0 and
R1 (A and B Register) respectively.
4) The Stack Pointer is initialized to >01.
5) The MSB and LSB of the Reset Vector are fetched location >FFFE and >FFFF respectively
(see Table 4-8) and loaded into the Program Counter.
6) Program execute begins from the address placed in the Program Counter.
5.3 I/O Control Register
The I/O control register are located in the Peripheral File and are responsible for interrupt control.
The DMC73C168 contains the I/O Control 0 (IOCTL0), I/O Control 1 (IOCTL1), I/O Control 2 (IOCTL2).
The I/O control register are mapped into locations P0 (IOCTL0), P1 (IOCTL1), P2 (IOCTL2) of the
Peripheral File as shown in Figure 5-3A, 5-3B and 5-3C. The individual interrupt mask and resets are
controlled through these registers. The interrupt sources may also be individually tested by reading the
interrupt flags. The interrupt flag values are independent of the interrupt enable values. The INTn FLAG
values are independent of the INTn ENABLE values. Writing a '1' to the INTn CLEAR bit will clear the
corresponding INTn FLAG, but writing a '0' to the INTn CLEAR bit has no effect on the bit. If INTn is to
be recognized by the CPU, three conditions must be met as follow.
1) A one must be written to the INTn ENABLE BIT IN THE IOCTL0, IOCTL1 or IOCTL2
Register.
2) The global INTERRUPT ENABLE bit, IE., bit4 in the Status Register, must be set to one
by the EINT instruction.
3) INTn must be the highest priority interrupt asserted within an instruction boundary.
Setting '1' to both INTnFLAG and INTnENABLE bit clears the INTnFLAG first, and then sets '1' to
INTnENABLE bit.
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
37
8Bit Single Chip Microcontroller
IOCTL0
DMC73C168
P0 >0100
0 = INTn Inactive
1 = INTn Pending
Read
INT3
FLAG
O
Bit
O
7
O
O
6
Write
INT3
ENABL
E
O
INT1
FLAG
INT2
ENABL
INT2
FLAG
O
O
5
4
3
2
INT3
CLEAR
INT3
ENABL
E
INT2
CLEAR
INT2
ENABL
E
Set to zero
INT1
ENABL
E
O
1
INT1
CLEAR
0
INT1
ENABL
E
0 = INTn disable
1 = INTn enable
0 = No effect
1 = Clear INTn flag
Figure 5-3A I/O Control Register 0 (IOCTL0)
IOCTL1
P1 >0101
0 = INTn Inactive
1 = INTn Pending
Read
INT4-1
FLAG
O
Bit
Write
INT4-1
ENABL
O
INT4-0
FLAG
INT4-0
ENABL
E
O
O
X
7
6
5
4
INT4-1
CLEAR
INT4-1
ENABL
E
INT4-0
CLEAR
INT4-0
ENABL
E
0 = No effect
1 = Clear INTn flag
NOT
USED
INT4-0
SENSE
O
INT3
SENSE
O
3
2
X
INT4-0
SENSE
0 = INTn disable
1 = INTn enable
Figure 5-3B I/O Control Register 1 (IOCTL1)
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
INT1
ENABL
E
O
1
INT3
SENSE
0
INT1
SENSE
0 = INTn falling edge
sensitive
1 = INTn rising edge
sensitive
38
8Bit Single Chip Microcontroller
IOCTL2
DMC73C168
P1 >0102
0 = INTn Inactive
1 = INTn Pending
Read
INT7
FLAG
O
Bit
Write
INT7
ENABL
O
INT6
FLAG
INT6
ENABL
E
O
O
INT5
FLAG
INT4
FLAG
INT5
ENABL
O
O
O
7
6
5
4
3
2
INT7
CLEAR
INT7
ENABL
E
INT6
CLEAR
INT6
ENABL
E
INT5
CLEAR
INT5
ENABL
E
0 = No effect
1 = Clear INTn flag
INT4
ENABL
E
O
1
X
0
INT4
ENABL
E
0 = INTn disable
1 = INTn enable
Figure 5-3C I/O Control Register 2 (IOCTL2)
5.4 Interrupt Logic and External Interrupt
The internal interrupt logic for each eight maskable interrupt of DMC73C168 is shown in Figure 5-4A-1,
54A-2. This interrupt logic will detect the output of each corresponding interrupt and latch the interrupt
Flag.
INTn
FLAG
INTn
Write
ACKNOWLEDGE
Read
Enable Latch
OR
INTn
Input
D
Q
CLR
D
Q
AND
Interrupt FLAG
FLAG READ
Interrupt Enable
(Status Register)
Figure 5-4A-1. Interrupt Logic
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
INTn
Happen
39
8Bit Single Chip Microcontroller
DMC73C168
Write
Enable Latch
INT FLAG
INPUT
INT
INPUT
Read
D
D
CLR
Q
Q
Interrupt Flag
AND
FLAG READ
INT Enable
FLAG READ
INT Enable
Read
OR
INT
D
INPUT
INT FLAG
CLEAR
CLR
Q
Q
Interrupt Flag
AND
D
D
INT Request
Q
Enable Latch
Write
Read
Note)
INT4-0 : INT4 External
INT4-1 : INT4 A/D Converter
Figure 5-4A-2. Interrupt 4 Logic
To even further conserve the already low power requirement, two low power modes are provided. These
modes are called Halt and Wake up and entered by executing a IDLE instruction. Either an external
interrupt or the timer interrupt will release the device from the low power depending on whether it is in
the Halt or Wake-up mode. See Section 5.12 for a complete description of the modes and interrupts.
When an external interrupt is first asserted, its level is gated into interrupt Flag. In order for an interrupt
signal to be detected the signal width must be a minimum of 5 internal clock cycles. The interrupt Flag
will be set to '1'. If INTn is removed before the interrupt is recognized, its occurrence is latched in by the
INTn Enable Flag. The INTn Enable bit is used separately to individually mask the interrupt levels. This
bit must be 1 before the interrupt to be recognized.
As previously stated, all interrupt control bits are implemented in the IOCTL0, IOCTL1 and IOCTL2
registers in the Peripheral File. I/O instructions may simply read from and write to each INTn Enable
bit. By the INTn input, the interrupt Flag is set to one at falling edge and become active through interrupt
is enabled. The interrupt service routine is executed after the currently executing instruction is completed.
the value of the Status Register and Program Counter (MSB and LSB) respectively moves onto the stack
and zeros the Status Register (see Section 4.3). The corresponding vector address is loaded into the
Program Counter and interrupt service routine is executed. The corresponding interrupt Flag is
automatically cleared. (But INT4F, INT40F, INT41F flags are not automatically cleared, because they
used same interrupt vector address. These flags are cleared by only program.)
The External interrupts, INT1, INT3 and INT4-0 have schmitt Trigger inputs and can be used as zerocross detector.
The following attention have to be paid due to using both as the External interrupt pins and general
purpose I/O pins.
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
40
8Bit Single Chip Microcontroller
DMC73C168
1) The port (A7/INT3, A6/INT4) used as the interrupt input should be input mode. The output
mode may cause to damage the device. If the content of the corresponding output port is
changed '1' to'0', the interrupt flag will also set to '1'.
2) If not used as the interrupt input, the corresponding Interrupt enable should be disabled,
but even if this interrupt Enable being disabled, the Interrupt Flag will be changed.
The External interrupt timing is shown in Figure 5-4B. And it needs an biditional circuitry when INT1,
INT3, INT4-0 are used as zero cross detector as shown in Figure 5-4C and the following conditions are
to be satisfied.
1) The External interrupt level should be range from VDD+0.3V to VSS, and it is necessary
for input current not to exceed the specification.
2) The noise on interrupt signal should be minimized because the noise debounce logic is not
implemented on chip. So the function may be failed due to the continuous interrupt.
VDD
External
Input Signal
VT+
VTVSS
Falling Edge
1
Interrupt
Execution
Last
Happen
0
Interrupt happen
Figure 5-4B External Interrupt Timing
VDD
DMC73C168
Resistor
INT1
INT3
INT4-0
Input
VSS
Figure 5-4C Additional Circuitry for External Input
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
41
8Bit Single Chip Microcontroller
DMC73C168
5.5 Programmable Timer / Event Counter
DMC73C168 features two on-chip timers with individual start and stop bits. Timer1 and Timer2 (shown
in Fig. 5-5 & Fig 5-6) consist of a 16 bit capture latch, and a 5-bit non-readable prescaler with a 5-bit
reload register.
The clock source of Timer1 and Timer2 shown in Table 5-1 is determined by bit 6 (SOURCE) of T1CLT1
and T2CTL1 respectively. A SOURCE bit of 0 selects the internally generated Fosc/4 clock and places
the Timer/Event Counter in the Real Timer Clock (RTC) mode. A SOURCE bit of 1 selects the external
clock source and places the Timer/Event Counter in the Event counter mode. In the external mode,
the clock source for Timer 1 and 2 are input on the two least significant Bits of I/O Port A(A4) and (A5)
respectively. Bit 7 of the timer control registers is the START bit for the respective programmable timers.
When a 0 is written to the START bit, regardless of whether it was a 0 or 1 before, the prescaler and
counter decrementers are loaded with the corresponding latch values, and the Timer/Event Counter
operation begins. When the prescaler and counter decrement through zero together, an interrupt flag is
set and the prescaler and counter decrementers are immediately and automatically reloaded with the
corresponding latch values.
The interrupt levels generated by the timers are INT2 for Timer1 and INT6 for Timer2. Timer1 and Timer2
each have a 16-bit Capture Latch (CL) associated with them which capture the current value of the
counter whenever INT3 for Timer1 and INT1 for Timer2 are triggered. The capture latch will store the
Timer value even when INT1/INT3 are disabled. Both capture latch is disabled during the IDLE instruction
when their corresponding timer HALT bits are 1.
Table 5-1. Timer 1 & Timer 2 clock Sources
Timer
Mode
1
RTC
0
EC
2
Source Cascade
Bit
Bit
Clock Source
Capture Latch
Trigger
Interrupt
-
Fosc/4
INT3
INT2
1
-
External Port A4
RTC
0
-
Fosc/4
EC
1
-
External Port A5
INT1
INT6
CASCADE
-
1
Timer1
In the Timer1 and Timer2, most significant byte readout latch is shared between the most significant
byte (MSB) of the decrementer and the MSB of the capture latch. It allows the complete 16-bit value of
the decrementer or the capture latch to be sampled at one moment. The least significant byte (LSB)
must be read first, which causes the MSB to be simultaneously loaded into the readout latch.
There is only one readout latch for each timer, but the some latch can be read from two address for
easier programming (see the diagrams for Timer1 and Timer2)
Timer1 MSB readout latch can be read from both P4(>0104) P6(>0106).
Similarly, Timer2 MSB readout latch can be read from both P8(>0108) and P10(010A)
Reading the LSB of the decrementer or capture latch will always update the contents of the readout
latch. In order to correctly read the entire 16-bit value of the decrementer or capture, the LSB must be
read first, which will load the MSB readout latch. The MSB readout latch must be read and stored
before reading the LSB of either the decrementer or capture latch.
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
42
8Bit Single Chip Microcontroller
DMC73C168
The order of 16-Bit read operations should be :
Timer1 : Decrementer : P5 then P4, or P5 then P6
Capture latch : P7 then P6, or P7 then P4
Timer2 : Decrementer : P9 then P8, or P9 then P10
Capture latch : P11 then P10, or P11 then P8
(P7.6)
T1CTL1
SOURCE
START
BIT
(P7.7)
P7
P4
Prescaler
Reload
Register
P5
16bit
Reload
Register
T1CTL0 (P6.6)
Normal
Port
Pin B0
(T1 OUT)
Fosc/4
Pin A4
5 bit
Prescaler
16 bit
Decrementer
Toggle Out
Timer 1
Interrupt (INT2)
IOCTL0 (P0.3)
(ECI1)
/INT3 FOR TIMER1 Capture Latch
Figure 5-5. Timer 1 Schematic Diagram
(P10.6)
P11
(P11.6) T2CTL0
Prescaler
T2CTL1 CASCADE
Reload
SOURC
T2CTL1
Register
E
START
(P11.7)
Fosc/4
Pin A5
(ECI2)
5 bit
Prescaler
P8
P9
16bit
Reload
Register
T2CTL0 (P6.6)
Normal
Port
Pin B1
(T2 OUT)
16 bit
Decrementer
Toggle Out
Timer 2
Interrupt (INT6)
IOCTL1 (P1.3)
CASCADE
OUTPUT OF TIMER1
/INT1 FOR TIMER2 Capture Latch
Figure 5-6. Timer 2 Schematic Diagram
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
43
8Bit Single Chip Microcontroller
DMC73C168
5.5.1 Timer Control Registers
The Timer Control registers are shown in Figure 5-5 for Timer1 and Figure 5-6 for Timer2.
P4
7
>0104
6
T1MSDATA
5
4
Timer 1 MS Data
3
2
R
16 bit TIMER MSB DECREMENTER VALUE
W
16 bit TIMER MSB RELOAD REGISTER
RESET
X
X
X
X
X
X
1
0
X
X
Bit 0 - 7 : decrementer value MSB
P5
7
>0105
6
T1LSDATA
5
4
Timer 1 LS Data
3
2
R
16 bit TIMER LSB DECREMENTER VALUE
W
16 bit TIMER LSB RELOAD REGISTER
RESET
X
X
X
X
1
0
X
X
X
X
3
2
1
0
Bit 0 - 7 : decrementer value LSB
P6
7
>0106
6
T1CTL0
5
R
4
MSB CAPTURE LATCH VALUE
W
X
T1OUT
X
X
X
X
X
X
RESET
X
O
X
X
X
X
X
X
1
0
READ
WRITE
Bit 0 - 7 : Capture latch value MSB
B 6 T1OUT Toggle out CNTC for B0 Port
0 : B0 is a normal I/O port
1 : T1OUT ; toggles B0 when T1 decrements through 0
P7
7
>0107
6
5
R
W
RESET
T1CTL1
4
3
2
LSB CAPTURE LATCH VALUE
START1
SOURC1
T1HALT
O
X
O
PRESCALER RELOAD REGISTER
X
X
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
X
X
X
44
8Bit Single Chip Microcontroller
DMC73C168
READ
Bit 0 - Bit 7
Provide the LSB value of Capture Register which contains the decrementer register
value at the time of INT1 was happened lately.
WRITE
Bit 1 - Bit 4 : Reloads the 5bit PRESCALER RELOAD REGISTER.
Bit 5 : T1HALT
0 - Timer 1 remains active during IDLE.
1 - Timer 1 will halt during IDLE
Bit 6 : SOURC1
0 - Internal clock source fosc/4
1 - External clock source from Port A4/ECI1.
Bit 7 : START1 : Timer 1 Start/Stop control
0 - Stop the Timer 1, hold current count value and clear INT2 FLAG.
1 - Reloads prescaler and decrementer and begin decrementing
CAUTION ! ! ! - START1 bit must set to be "0" before into HALT mode.
P8
7
>0108
6
5
T2MSDATA
4
Timer 2 MS Data
3
2
R
16 bit TIMER MSB DECREMENTER VALUE
W
16 bit TIMER MSB RELOAD REGISTER
RESET
X
X
X
X
X
X
1
0
X
X
Bit 0 - 7 : decrementer value MSB
P9
7
>0109
6
5
T2LSDATA
4
Timer 2 LS Data
3
2
R
16 bit TIMER LSB DECREMENTER VALUE
W
16 bit TIMER LSB RELOAD REGISTER
RESET
X
X
X
X
X
Bit 0 - 7 : decrementer value LSB
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
X
1
0
X
X
45
8Bit Single Chip Microcontroller
P10
7
>010A
6
RESET
T2CTL0
5
R
W
DMC73C168
4
3
2
1
0
MSB CAPTURE LATCH VALUE
CASCADE T2OUT
O
O
X
X
X
X
X
X
X
X
X
X
X
X
READ
Bit 0 - Bit 7 : Capture latch value MSB
WRITE
Bit 6 : T2OUT ; T2 Toggle out CNTC for B1 Port
0 - Toggle output disable.
1 - T2OUT ; toggle B1 when T2 decrements through 0
Bit 7 : CASCADE
0 - Clock determined by SOURCE bit.
1 - Clock source is Timer 1 reload signal, overrides SOURCE bit
P11
>010B
7
6
5
R
W
RESET
T2CTL1
4
3
2
1
0
LSB CAPTURE LATCH VALUE
START2
SOURC2
T2HALT
O
X
O
PRESCALER RELOAD REGISTER
X
X
X
X
X
READ
Bit 0 - Bit 7 : Capture latch value LSB
WRITE
Bit 0 - Bit 4 : Reloads the 5 bit PRESCALER RELOAD REGISTER
Bit 5 : T2HALT
0 - Timer 2 remains active during IDLE
1 - Timer 2 will halt during IDLE
Bit 6 : SOURC2
0 - Internal clock source fosc/4
1 - External clock source from Port A5/ECI2
Bit 7 : START2 ; Timer 2 Start/Stop control
0 - Stop the Timer 2, hold current count value and clear INT6 FLAG.
1 - Reloads prescaler and decrementer and begin decrementing
CAUTION ! ! ! : START2 bit must set to be "0" before into HALT mode.
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
46
8Bit Single Chip Microcontroller
DMC73C168
5.5.2 Real Time Clock mode (RTC)
In the Real Time Clock mode, Fosc/4 which is internally generated is the decrementer clock source.
Each positive pulse transition of the Fosc/4 period signal decrements the count chain.
5.5.3 Event Counter mode (EC)
When Timer1 or Timer2 is selected to use in the EC mode, pin A4 and A5 operate as clock source
decrementers for Timer1 and Timer2, respectively. The maximum clock frequency on A4 and A5
in the EC mode must not be greater than fosc/4. The minimum pulse width must not be less than
1.24 state clock cycles. Each positive pulse transition decreases the count chain.
5.5.4 Timer and Prescaled Clock
The timer clock, whether internal or external, is prescaled by a 5-bit module-N counter. The actual
prescaling value is determined by the least significant five bits of the timer control register, and the
actual prescaling value is equal to the timer control latch value plus one.
An INT2 interrupt for Timer1 and INT6 interrupt for Timer2 are momentarily pulsed when both the
prescaler and counter is decreased to zero value together. This sets the INT2 or INT6 flag flip-flop.
The prescaler and counter and then immediately reloaded with the contents of the prescale latch
(PL) and the timer latch (TL) and the timer will start decreasing with the PL and TL value.
5.5.5 Timer Interrupt Pulses
The period of the timer INT2 and INT6 interrupt pulses may be calculated by following formula :
tINT = tCLK * (PL + 1) * (TL + 1)
where
tINT = period of timer interrupt
tCLK = 4/Fosc for internal Real Time Clock mode or the
period of input external EC mode
PL = Prescaler Latch value
TL = Timer Latch value
At the falling edge of the INT3 and INT1 input, the Timer1 and Timer2 values are loaded into the
corresponding Capture Latch (CL), when read Timer1 and Timer2 control register contain the CL
value. This feature provides the capability to determine when an external event occurred relative
to the internal timer.
5.5.6 Timer Output Function
Timer1 and Timer2 can be cascaded together to form one large timer by setting the CASCADE
bit of T2CTL0 (P10) to "1". The CASCADE bit of 1 selects the output generated by Timer1 reload
pulse as the clock input to the prescaler of Timer 2.
The CASCADE bit overrides the SOURCE bit, that is, if the CASCADE bit is "1", the SOURCE
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
47
8Bit Single Chip Microcontroller
DMC73C168
bit of Timer2 has no effect. For right cascading operation, Timer2 is requested to be started first
and then Timer1.
A Timer output function exists on both Timer1 and Timer2 that allows the B0 and B1 outputs,
respectively, to be toggled every timer decrementing through zero.
This function is enabled by the T1OUT bit and T2OUT bit (bit6) in the timer control register
T1CTL0 and T2CTL0.
When operating in the timer output mode, the B0 and/or B1 output can not be changed timer's
START bit will reload and start the timer, but will not toggle the output. The output will toggle
only when the timer decreses through "0". The timer output feature is independent of INT2 and
INT6 and, therefore, will operate with INT2 and INT6 enabled or disabled.
Also, if the timer is active during the IDLE instruction, the timer output feature will continue to
operate. Whenever the T1OUT bit is returned to "0".
B0 or B1 will become an output-only pin like G0. The value in the B0 or B1 data register will be
the last value output by the timer output function. So that B0 or B1 data register will be the last
value output by the timer output function, so that B0 or B1 will not change as the T1OUT or
T2OUT BIT is returned to "0".
Whenever a read of B port is perfomed, the value on the B1 pin will always be returned, so the
current timer output value can be read by reading the B port.
The T1OUT and T2OUT bits are set to 0 by a reset, so the timer output function will not be
enabled unless the user sets T1OUT or T2OUT to 1.
5.5.7 Notes for Timer Usage
In the Timer1 and Timer2, most significant byte readout latch is shared between the most
significant byte (MSB) of the decrement and the MSB of capture latch to be sampled at on
moment. Timer 1 MSB readout latch can be read from both P4 and P6. Similarly, Timer2 MSB
readout latch can be read from both P8 and P10. Reading the LSB of the decrement or capture
latch will always update the content of the readout latch. In order to correctly read the entire
16 bit value of the decrementer or capture latch, the LSB must be read first, which will load the
MSB readout latch. The MSB readout latch must be read and stored after reading the LSB of
either the decrementer or capture latch.
5.6 A/D Converter
The key features of A/D converter are as follows.
- Total Unadjustabled Error
- Analog input
- Analog input range
- Conversion
- Resolution
- Conversion time
±1 LSB Max
2 channels
VSS to VDD
Ratiometric Conversion
8 bit
144 CPU machine cycles
(1 machine cycle = 2/fosc)
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
48
8Bit Single Chip Microcontroller
DMC73C168
The A/D Converter can be controlled by the three register on the Peripheral File.
The function block diagram is shown in Figure 5-7.
8-Bit
Data Register
ADDATA
(P15)
Port A
Analog
Comparator
A2
Temporaly
Register
Analog
Multiplexer
A3
VDD
VDD
8-Bit D/A
Converter
A/D START (P14, bit 6)
Analog Input Select (P14, bit 0)
Analog Select (P13, bit 2, 3)
Figure 5-7. A/D Converter Function Block Diagram
5.6.1 A/D Converter Control / Data Registers
P15
7
>010F
6
5
ADDATA
4
3
2
R
CONVERSION DATA REGISTER
W
I N V A L I D
1
0
1
0
Note : After reset, all bits have "0"
Bit 0 - Bit 7 A/D CONVERSION DATA (0 - 255)
P14
>010E
7
6
READY
START
5
ADCNTL
4
3
R
NOT USED
W
2
ANALOG
CHANNEL
SELECT
Bit 0 : ANALOG CHANNEL SELECT
ANALOG CHANNEL SELECT is determined by the value of P14 bit 0 at the beginning
of conversion. If a new value is loaded to these bits during A/D conversion, it is effective for
next conversion cycle.
PORT
A2
A3
BIT0
0
1
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
49
8Bit Single Chip Microcontroller
DMC73C168
Bit 1 : Bit 5 Not used.
Bit 6 : START FLAG
Even through the START FLAG is set to "1" or "0" during A/D conversion, the START
FLAG is ignored till the current conversion is completed.
WRITE
START A/D Converter Start/Stop Control bit.
0 = Stop A/D conversion
1 = Start A/D conversion
Bit 7 : READY FLAG
When the analog conversion data is set to ADDATA register (P16), the READY FLAG
will be set to "1". Then the ADDATA register can be read by software. After the ADDATA
register is read, the READY FLAG will be set to "0" automatically.
READ
0 = No operation or Incomplete conversion
1 = Complete conversion
WRITE
0 = Ineffect
1 = Clear READY FLAG
P13
R
W
>010D
7
6
INT3SE
INT40SE
APSLCT
5
4
NOT USED
3
2
1
0
AD2SEL
AD1SEL
AMIFSE
FMIFSE
Note : After reset, all bits have "0"
Bit 2 - Bit 3 : ANALOG INPUT ENABLE
BIT2 (AD1SEL) : AD1/PORT A2
BIT3 (AD2SEL) : AD2/PORT A3
Before the A/D Converter operation starts, the corresponding bits of ANALOG INPUT
ENABLE should be set to "1".
5.6.2 A/D Converter Operation
The A/D converter operation procedure is as follows.
1) Set the corresponding bits of ANALOG INPUT ENABLE register to "1".
2) Load the analog channel value to the ANALOG CHANNEL SELECT register bit 0.
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
50
8Bit Single Chip Microcontroller
DMC73C168
3) Set the START FLAG (ADCNTL register bit 6) to "1"
Then A/D conversion starts.
4) The conversion data is transfered to the ADDATA register, after A/D conversion completed.
Then the READY FLAG (ADCNTL register bit 7) set to "1" automatically.
5) Can read the ADDATA register.
If the START FLAG is set to "0" during A/D conversion, the A/D converter operation is terminated,
after the A/D converter is completed, this timing is shown in Figure 5-8 for the single conversion
and Figure 5-9 for the continous conversion. If the READY FLAG is set to occured as other
Interrupt.
5.6.3 Notes for A/D Converter usage
1) When the Port A2, A3 is defined as analog input function by the ANALOG INPUT ENABLE
register, reading the Port A2, A3 data register is "0". Each bit of the Port A2, A3 can be defined
individually by the ANALOG INPUT ENABLE register.
2) When the Port A2, A3 is used as analog input, the direction of Port A2, A3 should be set to
input mode by using the Port A Direction register.
3) The precision of the conversion value is influenced by the stability of VDD and VSS during
A/D conversion.
START flag
(P14.6)
Start
Stop
Clear
Minimum 12
Machine cycle
Cleared by reading ADDATA
READY flag
(P14.7)
1
0
144 Machine Cycles
ANALOG
CHANNEL
Select
SELECT (P14.0)
Data(1)
A/D Converter
operation
ADDATA
Select next analog channel
Conversion
(1)
Previous Conversion Data
Transfer data to ADDATA
Conversion Data
(P15)
(1)
Figure 5-8. Single A/D Conversion
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
51
8Bit Single Chip Microcontroller
START
(P14.6)
DMC73C168
Start
Stop
Cleared by reading ADDATA
READY flag
(P14.7)
ANALOG
144 Machine
cycles
144 Machine
cycles
CHANNEL
Analog
Analog Data
Analog Data
Analog Data
SELECT (P14.0)
Data(1)
(2)
(3)
(4)
Conversion
Conversion
Conversion
(1)
(2)
(3)
A/D Converter
operation
Transfer Data
ADDATA
Previous Conversion Data
(P15)
Transfer Data
Conversion Data
Conversion Data
(1)
(2)
Figure 5-9 Continous A/D Conversion
5.7 PLL
The ON-CHIP Phase Locked Loop (PLL) has reference frequency divider, two module prescaler.
4bit swallow counter, 12bit programmable counter. Phase detector and exclusive PLL ports like
VCOH, VCOL, EO1, CO2. Figure 5.7 shows PLL block diagram.
5.7.1 Reference Frequency Divider
The reference frequency divider consists of the crystal oscillator wich has connected external
crystal (4.5MHz). This frequency divider generates 8 kinds of reference frequencies I.e. 1KHz,
5KHz, 6.25KHz, 9KHz, 10KHz, 12.5KHz, 25KHz and 50KHz.
One of reference frequencies can be selected by the program (By setting peripheral file : P16,
bit 5, 4, 3).
5.7.2 PLL Control register
PLL control register are located in the two peripheral registers, P16 and P17. Figure 5-7-1 shows
how to set each bit of PLL control register for PLL lock detection time, Reference frequency and
AM/FM band Mode.
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
52
8Bit Single Chip Microcontroller
- PLLCTL0
Bit
Write
Reset
Value
P16
7
6
Mode Selector
INSL1
INSL0
O
O
DMC73C168
>0110
5
4
3
Reference Frequency
Selector
REF2
REF1
REF0
O
Mode Selector
- 00 : Not use
- 01 : AM direct
- 10 : AM swallow
- 11 : FM swallow
O
2
1
Detection Time Selector
DTM2
DTM1
DTM0
O
O
O
O
Reference
Frequency
Detection Time
- 000 : 0.44us
- 001 : 0.55us
- 010 : 0.66us
- 011 : 0.77us
- 100 : 0.88us
- 101 : 1.00us
- 110 : 1.11us
- 111 : 1.22us
- 000 : 1.0KHz
- 001 : 5.0KHz
- 010 : 6.25KHz
- 011 : 9.0KHz
- 100 : 10.0KHz
- 101 : 12.5KHz
- 110 : 25.0KHz
- 111 : 50.0KHz
at fosc = 4.5MHz
Figure 5-7-1 PLL Control Register
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
0
53
8Bit Single Chip Microcontroller
DMC73C168
PHASE LOCKED LOOP (PLL)
LATCH
VCOH
A
SWALLOW COUNTER
4BIT
1/16, 1/17
PRESCALER
T/F
4BIT REG.
4
Data BUS (8Bit)
4
SEL.
8
MSB
LSB
1
VCOL
8
A
12 BIT REG.
12 BIT
PROGRAM COUNTER
SEL
4
1
PLL Control
REG
1KHz
5KHz
PHASE
DETECTOR
6.25KHz
9KHz
10KHz
SEL
UL
12.5KHz
Xin
25KHz
4.5MHz
BF
BF
50KHz
EO2
XOUT
REF. DIVIDER
450KHz
6.25KHz 1KHz
100KHz 5KHz
Figure 5-7 PLL Block Diagram
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
EO1
54
8Bit Single Chip Microcontroller
DMC73C168
- UNLOCK F/F DETECTION TIME SELECTOR BIT
This bit must be set to satisfy your applied UNLOCK F/F detection time specification.
UNLOCK F/F detects the PLL Locking status affer detection time duration.
Fref
Programmable
Counter Output
Error Out
UNLOCK F/F
Detection Time
T1
T2
T1
T2
Figure 5-7-2. UNLOCK F/F DETECTION TIME
For example, if you select detection time - T1, UL F/F output is UNLOCK STATES, but you select
Detection time - T2, UL F/F output is Lock status under the same Error output conditions. This is very
useful to compensate for mechanical oscillation of VCO. Figure 5-7-2 shows two kinds of detection time
(T1 and T2) as for example.
- REFERENCE FREQUENCY SELECTOR BIT
These bits select reference frequency specification which is inputs to phase detector to compare the
phase difference with the VCO output divided by the programmable divider.
PLLCTL0
(P16,5,4,3)
1KHz
5KHz
6.25KHz
9KHz
SEL
TO PHASE
12.5KHz
DETECTOR
25KHz
OSCIN
50KHz
REF. FREQ. DIVIDER
OSCOUT
SYSTEM CLOCK
450K
100K 6.25K
5K
1K
For beep clock
Figure 5-7-3. REFERENCE FREQUENCY SELECTOR BIT
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
55
8Bit Single Chip Microcontroller
DMC73C168
- MODE SELECTOR BIT (AM, FM)
These bits selects dividing method whether pulse swallow dividing type or direct dividing type.
According to the input frequency band three combinations are available as follows.
INSL1
INSL0
Freq. Dividing Types
0
0
NOT USE
0
1
1
Direct Dividing
0
(1/16, 1/17)
Input Freq. Range
Input Port
Freq. Div Number
0.5 - 10MHz
VCOL=ACTIVE
M
LW MW SWL
VCOH=PULL-DOWN
5 - 40MHz
VCOL=ACTIVE
SWH
VCOH=PULL-DOWN
10 - 150MHz
VCOH=ACTIVE
FM
VCOL=PULL-DOWN
Pulse swallow type
1
1
(1/2x1/16, 1/17)
Pulse swallow type
(16M+S)
2(16M+S)
Figure 5-7-4. Mode Selector Bit
(Note) : M represents program counter dividing numeral value
S represents swallow dividing numeral value
- PLLCTL1
Bit
Read
Reset
Value
P17
7
6
READY
O
>0111
5
4
NOT USED
X
X
3
2
PLL TEST
X
O
- 0 : No operation
- 1 : Active
1
0
UNLOCK DETECTOR
O
UL1
UL0
O
O
UNLOCK DETECTOR
- * ATTENTION
- 00 : PLL LOCK/STOP/OFF
- 01 : REF FREQ>VCO
FREQ
- 10 : REF FREQ<VCO
FREQ
Bit
7
Write
PLLEN
Reset
Value
O
6
5
4
NOT USED
X
- 0 : No operation
- 1 : Active
X
3
2
PLL TEST
X
O
O
1
0
NOT USED
O
O
- * ATTENTION
These bits must be set to "0" in normal program
operation
Figure 5-7-5. PLL Control Register
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
56
8Bit Single Chip Microcontroller
DMC73C168
¤· READY
This bit must be set to satisfy The PLL conditions between PLL ON/START STATUS and PLL
OFF/STOP STATUS by programming.
¤· PLLEN BIT
When the PLL ON/START (PLLEN=1) OR PLL OFF/STOP (PLLEN=0) is set to PLLCTL1
register (P17), the READY bit will be set to 1 or 0 accordingly.
¤· UNLOCK DETECTOR BIT
This bit is automatically set by phase detector conditions.
Both the UL1 bit and UL0 bit are automatically set under conditions of PLL LOCK/STOP/OFF.
When reference frequency leads VCO frequency which is divided by programmable divider
(Fref>VCO/N), the UL1 bit is set to 0 and the UL0 bit is set to 1. When reference frequency
lags VCO frequency which is divided by programmable divider (Fref>VCO/N), the UL1 bit is
set to 1 and the UL0 bit is set to 0.
5.7.3 PLL Data Register
PLL data register are located in two peripheral registers as PF (18) and PF (19).
- PLLDATAH
Bit
P18
7
>0112
6
5
Write
Reset
Value
4
3
2
1
0
PLL PC MSB DATA
O
X
X
- PLLDATAL
Bit
X
P19
7
Write
Reset
Value
: PLL PC MSB DATA REGISTER
O
>0113
6
5
X
X
O
O
: PLL PC LSB DATA REGISTER
4
3
PLL PC LSB DATA
O
O
2
1
0
SWALLOW COUNTER VALUE
X
O
O
Figure 5-7-6. PLL DATA REGISTER
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
O
O
57
8Bit Single Chip Microcontroller
DMC73C168
5.7.4. Programmable Divider
Programmable divider is composed of two modules prescaler, 4bit swallow counter and 12 bit
binary programmable counter.
In pulse swallow dividing type, 1/16, 1/17 - modules prescaler is active in case of FM BAND and
1/2 divider is added to the front stage of prescaler.
LATCH
VCOH
AMP
1/2
VCOL
1/16, 1/17
SWALLOW COUNTER
4BIT
AMP
4BIT REG.
12BIT REG.
12 BIT
PROGRAMMABLE
COUNTER
TO PHASE
DETECTOR
Figure 5-7-7. Circuit Diagram of Programmable Divider
In direct dividing type, input frequency (VCOL) is transfered to programmable counter directly.
Both VCOH and VCOL ports have built-in AC AMP, INPUT signal must be cut by coupling
capacitor.
5.7.5. Phase Detector
Phase detector detects the difference of phased between the reference frequency(Fref) and
programmable counter output (VCO/N).
The output of this circuit puts out its error compoment to the EO1 and EO2 pins. Output from
EO1, EO2 can be feedback to VCO through low pass filter.
VDD
Reference
frequency
Fref
Programmable
counter output
VCO/N
PHASE
DETECTOR
BUFFER
EO1
BUFFER
VDD
EO2
Figure 5-7-8. Phase Detector Circuit Diagram
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
58
8Bit Single Chip Microcontroller
DMC73C168
Fref
VCO/N
High Level
Floating
EO1
Low Level
Figure 5-7-9, Error Output Time Chart
i) Fref > VCO/N : low level
ii) Fref < VCO/N : high level
iii) Fref = VCO/N : floating
Two Error output EO1, EO2, ports have the exactly same characteristics to optimize the design of
low pass filter constant for each FM/AM BAND.
5.7.6. Setting of Frequency Dividing Number
The relation between VCO and Fref is as follows.
VCO = { (m+1)S + m(M-S) }Fref ( put N = mM + S )
= (mM + S)Fref
VCO : Input frequency to pin VCOH/VCOL
VCO
N=
Fref : Reference frequency
Fref
m : STANDARD Prescaler Ratio (=16)
s
: The bit number of swallow counter
M : The bit number of programmable counter
1) Direct dividing type
- Frequency dividing number setting range
N = 16 ~ (212 - 1) => 10 ~ >FFF
Example : Reception of MW
(Reception frequency : 1440KHz, Reference frequency : 9KHz, IF frequency : 450KHz)
N=
(1440+450) x 103
9 x 103
= 210
= >0D2
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
59
8Bit Single Chip Microcontroller
DMC73C168
- PLL DATA REGISTER
P18
>0112
MSB
0 0 0 0
1
1
0
LSB
1
P19 >0113
MSB
0 0 1 0
211
///
///
///
LSB
///
2o
Figure 5-7-10.
2) Pulse Swallow Type
- Frequency dividing number setting range
N = 256 - (216 - 1)
Example : Reception of FM
(Reception frequency : 125MHz, Reference frequency : 25KHz, IF frequency : 10.7MHz)
In case of FM band, 1/2 divider is added to the front stage of prescaler.
6
N = (125+10.7) x 10 = 2714 = 16M + S
2 x 25 x 103
M : 169[10] = 0A9h
S : 10[10] = 0Ah
= >A9A
- PLL DATA REGISTER
P18
>0112
P19
MSB
0
0
0
0
1
0
1
LSB
MSB
0
1
>0113
LSB
0
0
1
1
2o
23
M value
211
0
1
0
S
2o
Figure 5-7-11.
5.8 IF Counter
The DMC73C168 has on-chip IF counter function to measure FMIF or AMIF frequencies.
The IF counter consists of 17 bits and is mainly used to detect the stop signal during auto search
tuning. If the desired IF frequency is counted by measuring frequencies input to pins PA0/FMIF
and PA1/AMIF during auto search tuning, a broadcast station can be considered to exist on the
reception frequency at that time.
Thus, by using the IF counter function to detect the stop signal, auto search tuning operation can
be accomplished with smaller channel spacings such as 25KHz/step in the FM band 1KHz/step
in the AM band.
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
60
8Bit Single Chip Microcontroller
DMC73C168
5.8.1. IF Counter Block Diagram
IF COUNTER is shown in Figure 5.8.1.
0
1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
LSB
P23
8bit
MSB
IFCLSD
8
9 10 11 12 13 14 15
0 1 2 3 4 5 6 7
8bit
LSB
P24
16
0 X X X X X X X
1bit
MSB LSB
IFCMSD
P25
MSB
IFCHSD
TG
PA0/FMIF
NAN
D
1/2
NAN
D
AND
TG
PA1/AMIF
NAN
D
1ms ~ 15ms
Gate signal
control circuit
To portA circuit
7
6
5
4
3
1KHz
2 1 0
IFTB
P22 IFCCTL
Figure 5-8-1. Configuration of IF counter
The IF counter of the DMC73C168 is 17bit binary counter and its value can be read the IFCLSD
(P23), IFCMSD (P24) and IFCHSD (P25).
IFCLSD, IFCMSD and IFCHSD are Registers for reading only, and data cannot be set in the IF
counter through these Registers.
One of the fifteen following count times (gate signals) of the IF counter can be selected by the
IF counter time bits (IFTB) : From 1msec to 15msec.
The frequency input to pin PA0/FMIF or pin PA1/AMIF can be countered by deciding the number
of pulses input to the IF counter within the above-mentioned times.
The IFCCTL can also select A0/FMIF or A1/AMIF (P22;bit6/5).
If one pin is selected the other pin is internally pulled down automatically through a resister.
The maximum frequency that can be input to pin A0/FMIF is 20MHz (Vin=0.1 Vp.p) and that
of pin A1/AMIF is 5MHz (Vin=0.1 Vp.p)
The signal input to pin A1/AMIF is input directly to the IF counter.
The signal input to pin A0/FMIF is input to the IF counter internally through the 1/2 frequency
divider.
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
61
8Bit Single Chip Microcontroller
DMC73C168
Therefore, the value of the IF counter will be 1/2 to the actual frequency to be input to pin A0/
FMIF if pin A1/AMIF is selected. The IF counter is reset during power ON reset (VDD = low to
high) and IF counter holds the present values when the counter is stopped. This values can be
cleared by program (IFCCTL;bit7). When the IF counter enters a halt mode, it maintains the state
before the halt state.
5.8.2. IF Counter Control Register (IFCCTL)
The IF counter register IFCCTL designates the input pin and input gate signal time of the IF
counter. The IFCCTL consists of 8bit Flip Flops and is set by the IFCCTL instruction.
IF COUNTER CONTROL REGISTER is Shown in figure 5-8-2. All the bits of the IF counter control
register are reset to "0" during power On reset (VDD = low to high) or when the clock is stopped.
Bit
Write
IFCCTL
P22
START
FMIF
>0116
AMIF
TSTIF
TP3
TP2
TP1
TP0
3
2
1
0
(at 4.5MHz fosc)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Not USED
1 mSec
2 mSec
3 mSec
4 mSec
5 mSec
6 mSec
7 mSec
8 mSec
9 mSec
10 mSec
11 mSec
12 mSec
13 mSec
14 mSec
15 mSec
IFTB
Count Time
Must be set to "0"
Bit6
Bit5
0
0
1
1
0
1
0
1
Input signal selection
Neither will be selected
AMIF input
FMIF input
not used
Bit7
0
1
Start/Stop
Inactive or counter is stopped
Start
Figure 5-8-2. IF Counter Control Register
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
62
8Bit Single Chip Microcontroller
DMC73C168
5.8.3. Gate Signal
The gate signal time of the IF counter is designated by the IF Time bits (IFTB) of the IF counter
control Register (IFCCTL). The basic clock of it is a 1ms pulse signal which is not synchronous
to the instruction.
Gate signals of 1mSec to 15mSec are generated based on this basic clock (1mSec).
For this reason, the IF counter starts immediately when the basic clock falls after the execution
of the IFCCTL instruction is generated. Figure 5-8-3 shows an example when a gating time of
1ms is designated.
(1KHz)
Actual Gate Signal
(1ms)
Start bit (bit7)
in IFCCTL
Hold
Counter value
Counter
Value
00
00
Figure 5-8-3. IF Counter Timing Chart.
As the timing chart in Figure 5-8-3 shows the delay time from the point counter start instruction
to the point of actual counting by the IF counter is 1 msec maximum.
5.8.4. Error
IF counter errors can be classified as gating time errors and counting errors. The gating time
error depends on the oscillation frequency of the 4.5MHz crystal resonator connected externally.
This because the basic pulse signal that decides the gating time is generated by dividing the
4.5MHz frequency.
Counting errors will be 0 to +1 (IFCCTL;Bit0) at maximum. When pin PA0/FMIF is selected,
pin PA0/FMIF is regarded equivalently as low if the gate closes with the input signal remaining
in a "high" state (or if pin PA0/FMIF becomes non-selective), and is counted larger by 1.
When pin PA1/AMIF is selected the signal of low to high is equivalently input to the counter
and is counted one more when the gate opens (or when pin PA1/AMIF is selected during
counting) if the level of pin PA1/AMIF is already high.
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
63
8Bit Single Chip Microcontroller
DMC73C168
5.8.5. Examples of IF Counter Data Calculations
(1) When pin FMIF is selected as IF counter input pin. The frequency input to pin PA0/FMIF is
input to the IF counter through the 1/2 frequency divider. For this reason, the data vlaue of the
IF counter will be 1/2 of the frequency input to pin PA0/FMIF.
Example : FMIF freuqency (fFMIF) : 10.7MHz
Gate signal (Tg) : 4ms
IF counter value (N)
N = 1/2 (fFMIF x Tg) = 2/1 x 10.7 x 106 x 4 x 10-3
= 21400
= >5398
IFCHSD MSB
0
0
IFCMSD
1
0
0
1
IFCLSD
0
0
5
1
1
1
0
3
0
1
1
LSB
0
9
0
0
8
(2) When pin AMIF is selected as IF counter input pin.
The frequency input to pin PA1/AMIF is directly input to the IF counter.
Example : AM IF frequency (fAMIF) : 450MHz
Gate signal (Tg) : 4ms
IF counter value (N)
N = fAMIF x Tg = 450 x 103 x 4 x 10-3
= 1800
= >708
IFCHSD MSB
0
0
IFCMS
0
0
0
0
0
IFCLSD
0
1
1
7
1
0
0
0
0
0
1
LSB
0
0
0
8
5.9. Serial Communication I/O Port : SIO1, SIO2
DMC73C168 contain 2 sets of full duplex serial communication port synchronized by an internal
or external clock (SCLK1, SCLK2) that consists of a double buffered receiver, double buffered
transmitter as shown in Figure 5-9A, 5-9B.
Figure 5-9-2 shows the serial communication frame format. One frame consists of eight bits
data only with eight bits fixed length. The period equals the SCLK period. LSB (=bit0) is received
or transmitted first, and subsequently bit 1, 2, 3, 4, 5, 6, 7.
The receiver (RX) receives data from E1 (E4) pin on the rising SCLK1 (SCLK2) edges and the
transmitter (TX) transmits data to E0 (E3) pin on the falling SCLK1 (SCLK2) edges as shown
in Figure 5-9-3.
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
64
8Bit Single Chip Microcontroller
DMC73C168
The transmitter and receiver process each data at the same bit position during the same SCLK1
(SCLK2), so an INT5 (INT7) interrupt by the transmitter is generated at the same time an INT5
(INT7) interrupt by the receiver.
SHIFT CLOCK
INTERNAL SCLK
EXTERNAL SCLK
Fosc
E2 (SCLK1), E5 (SCLK2)
Fosc/8, Fosc/16, Fosc/32, Fosc/64
Fosc/8 Max
SCLK1, 2 Output or I/O Port
SCLK1, 2 Input
SCLK Source
Band Rate
E2:SCLK1,E5:SCLK2
Character Length
8bit fixed length
Error Detection
Overrun
Table 5-9. SI/O Feature
(Fosc : Xtal Oscillation Frequency)
* 1 SCLK1E (P27,2)
0 : E2 Normal I/O
1 : - P41.2 = 0 : E2 External SCLK1 input
- P41.2 = 1 : E2 Internal SCLK1 output
SCLK2E (P29,2)
0 : E5 Normal I/O
1 : - P41.5 = 0 : E5 External SCLK1 input
- P41.5 = 1 : E5 Internal SCLK1 output
* 2 SO1ENA (P27.1)
0 : E0 Normal I/O
1 : E0 Serial data output SO1 (P41, 0 = 1)
SO2ENA (P29.1)
P28
SIO1AF
I
N
T
E
R
N
A
L
B
U
S
SI1 SHIFT
KEY
shift clock
E1 / SI1 PIN
EDATA Reg
(P40.2)
E2 / SCLK1 PIN
SCLK2E *1 (P27.2)
SO1 SHIFT
KEY
EDATA Reg
(P40.0)
P28
SIO1ST
Figure 5-9A. Serial I/O 1 Block Diagram
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
E3/SO2 PIN
SO2ENA *2 (P27.1)
65
8Bit Single Chip Microcontroller
DMC73C168
P30
SIO2AF
I
N
T
E
R
N
A
L
SI2 SHIFT
KEY
E4/SI2 PIN
EDATA Reg
(P40.5)
shift clock
E5/SCLK2 PIN
SCLK2E *1 (P29.2)
SO2 SHIFT
KEY
E3/SO2 PIN
EDATA Reg
(P40.3)
B
U
S
SO2ENA *2 (P29.1)
P30
SIO2ST
Masten
Figure 5-9B. Serial I/O2 Block Diagram
Slave
SCLKn
SIn
SOn
SCLKn
Son
SIn
Figure 5-9-1. Master-Slave Connection Example
SCLKn
LSB
1
DATA
0
0
0
1
1
0
Sin/Son
Figure 5-9-2. Serial Communication Format
SCLK
SI
SO
BIT0
BIT0
BIT1
BIT1
BIT2
BIT2
Figure 5-9-3. Serial I/O Timing
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
BIT7
BIT7
MSB
1
66
8Bit Single Chip Microcontroller
DMC73C168
6. OTP DEVICE SPECIFICATION
6.1 Pin Assignment of OTP and OTP Programming Adapter Board
The OTP Device can be programmed like any Texas Instruments Device on a wide variety of PROM
programmers. Programming the OTP Device requires a 80QFP to 28DIP adapter socket with the
XRESET and OSCIN pins grounded. The following diagram shows the connections needed to be
made on the 80QFP to 28DIP pin socket.
OPERATING MODE
PIN NO.
PIN NAME
I/O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
A0/FMIF
A1/AMIF
A2/AD1
A3/AD2
A4/ECI1
A5/ECI2
A6/INT4
A7/INT3
E0/SO1
E1/SI1
E2/SCLK1
E3/SO2
E4/SI2
E5/SCLK2
E6
E7/BEEP
F0
F1
F2
F3
F4
F5
F6
F7
VSS
OSCIN
OSCOUT
VDD
TEST
G0
G1
G2
G3
G4
G5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
O
I
I/O
I/O
I/O
I/O
I/O
I/O
EPROM MODE
OPERATING MODE
PIN NAME
I/O PIN NO.
PIN NAME
I/O
XPGM
XCE
XOE
EPTEST
EPTESTHV
I
I
I
I
I
VSS
VSS
VDD
VPP
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
I
I
I
I
I
I
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
G6
G7
H0
H1
H2
H3
H4
H5
H6
H7
B0/T1OUT
B1/T2OUT
B2
B3
B4
B5
B6
B7
D0
D1
D2
D3
D4
D5
D6
D7
C0
C1
C2
C3
C4
C5
C6
C7
NC
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
EPROM MODE
PIN NAME
I/O
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
I
I
I
I
I
I
I
I
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
67
8Bit Single Chip Microcontroller
OPERATING MODE
PIN NO.
PIN NAME
I/O
71
72
73
74
75
EO1
EO2
VSS
VASS
VCOH
DMC73C168
EPROM MODE
OPERATING MODE
PIN NAME
I/O PIN NO.
PIN NAME
I/O
O
O
76
77
78
79
80
VSS
I
VCOL
VREF
NC
CE/INT1
RESET
EPROM MODE
PIN NAME
I/O
I
VDD
I
I
VSS
Note 1) Important notice
A. EPTESTHV PIN Assigned to F4 and EPTEST PIN Assigned to F3.
EPTEST
EPTESTHV
0
1
1
OPERATION
0
0
1
PGM, PGM VERIFY, READ
Word Line Stress, Bit Line Stress
Other Function Test Mode
B. VPP Pin assigned to test pad.
C. ADDR (0 to 13) was assigned to HPORT (0 ~ 7), EPORT (0 ~ 5)
D. EPROM I/O DATA (8) was assigned to CPORT
Note 2) EPORM related pins
TOTAL 31 PIN
¤· DATA LINE
¤· ADDRESS
¤· CONTROL
¤· VPP
:
:
:
:
¤· OTHER PIN :
TOTAL
8 PIN
14 PIN (ADDR0 ~ ADDR13)
5 PIN (XCE, XOE, XPGM, EPTEST, EPTESTHV)
1 PIN
28 PINS
4 PIN (XRESET, OSCIN, VDD, VSS)
32 PINS
7. ELECTRICAL SPECIFICATION
7.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range
(unless otherwise noted *)
PARAMETER
SYMBOL
Supply voltage range (see Note 1)
VDD
Vref
RATING
-0.3
~
UNIT
7.0
V
Input
voltage
range
Port A,B,C,D,E,F,G,H,
RESET, INT4-0, INT3,
CE, OSCIN, VCOH, VCOL
VI
-0.3
~
VDD+0.3
V
Output
voltage
Port A,B,C,D,E,F,G,H,
EO1, EO2
VO
-0.3
~
VDD+0.3
V
Input current
Output current
II
IO
± 10
± 10
mA
mA
Total low-level output current
¢²IOL
Max 80
mA
Power dissipation
PD
0.5
W
Storage temperature range
TSTG
-55
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
~
125
¡É
68
8Bit Single Chip Microcontroller
DMC73C168
* Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage
to the device. This is a stress rating only and functional operating of the device at those or any other
conditions beyond those indicated in the "Recommended Operating Conditions" section of this
specification is not implied. Exposure to absolute-maximumrated conditions for extended periods
may affect device reliability.
Notes :
1. Unless otherwise noted, all voltages are with respect to VSS.
2. Test pin must connect to VSS.
7.2 Recommended Operating Conditions
(Vss = 0V, Topr = -40 to 85¡É)
PARAMETER
SYMBOL
CONDITION
MIN
Supply voltage
VDD1
CPU/PLL ON
4.5
5
5.5
V
VDD2
CPU ON/PLL STOP
3.5
5
5.5
V
Memory Retention
voltage
VDDR
OSC STOP
2.5
5
5.5
V
Analog supply voltage
VASS
-0.3
0
VREF
Input oscilation voltage
VIN-VCO
VIN-IF
Operation free air
TOPR
temperature range
(Note3)
High level input voltage
VIH
Low level input voltage
VIL
Positive-going
threshold voltage
VT+
(see Note3)
Negative-going
threshold voltage
VT(see Note3)
Hysterisis
VT+ ~ VT(see Note3)
IINT
INT input current
Notes : 3. VDD = 5.0V
TYPE
VDD
VCOL, VCOH
0.3
AMIF, FMIF
0.1
Port A, B, C, D, E,
F, G, H, OSCIN
VDD=2.5 ~ 5.5V
Port A, B, C, D, E,
F, G, H, OSCIN
VDD = 5V ±10%
INT1 (CE)
RESET
INT3, INT4-0
INT1 (CE)
RESET
INT3, INT4-0
INT1 (CE)
RESET
INT3, INT4-0
INT1 (CE)
RESET
INT3, INT4-0
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
MAX
UNIT
V
VDD+0.3
V
Vp-p
-40
85
¡É
0.7VDD
VDD
V
VSS
0.3VDD
V
3.0
4.0
V
1.0
2.0
V
1.5
2.5
V
10.0
uA
69
8Bit Single Chip Microcontroller
DMC73C168
7.3 Electrical Characteristics Over Full Range of Operation
PARAMETER
Input current
TEST CONDITION
II
VCOH, VCOL
(Vss = 0V, Topr = -40 to 85¡É)
MIN
NON
MAX UNIT
Vi = VSS ~ VDD
±20.0
uA
OSCIN
High level
IOH
output current
PORT A, B, C,
VDD = 5V ±10%
D, E, F, G, H,
VOH = VDD - 0.5V
EO1, EO2
VDD = 2.5 ~ 5.5V
-0.3
-1.2
mA
-0.1
-0.5
0.4
0.6
VOH = VDD - 0.5V
Low level
IOL
output current
PORT A, B, C,
VDD = 5V ±10%
D, E, F, G, H,
VOL = 0.4V
EO1, EO2
VDD = 2.5 ~ 5.5V
mA
1.7
2.4
VOL = 1.0V
High level
VOH PORT A, B, C,
output voltage
D, E, F, G, H,
EO1, EO2
VDD = 5V ±10%
VDD-0.5
VDD
IOH = -1.0mA
VDD = 2.5 ~ 5.5V
V
VDD-0.5
VDD
IOH = -0.3mA
Low level
VOL
output voltage
PORT A, B, C,
VDD = 5V ±10%
D, E, F, G, H,
IOL = -1.7mA
EO1, EO2
0.5
V
VDD = 2.5V ±10%
0.4
IOL = -0.4mA
Output leakage
current
Ileak
EO1, EO2
VO = VSS ~ VDD
nA
Ci
15
pF
Input
Operating mode
fosc = 4.5MHz
20.0
40.0
mA
fosc = 4.5MHz
1.5
3.0
mA
fosc = 4.5MHz
500
900
uA
Halt mode
VDD = 5V
1
5
uA
(OSC stop)
VDD = 3V
0.5
1
(PLL active)
Wake-up mode
Supply current
(Note 4)
ICC
(Timer active)
Halt mode
(OSC active)
Notes : 4. All I/O terminals which except OSCIN are open. And VDD = 5V
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
70
8Bit Single Chip Microcontroller
DMC73C168
7.4 AC Characteristics for Input/Output Ports
7.4.1 AC Characteristics for Input/Output Ports
(Vss = 0V, VDD = 4.5 ~ 5.5V, Topr = -40 to 85¡É)
PARAMETER
VCOH operating
TEST CONDITION
MIN
VCOH
Vin = 0.3 Vp-p
VCOL
NOM
MAX
UNIT
10
150
MHz
Vin = 0.3 Vp-p
0.5
40
MHz
FMIF
Vin = 0.1 Vp-p
1
20
MHz
AMIF
Vin = 0.1 Vp-p
0.1
5
MHz
TEST CONDITION
MIN
MAX
UNIT
frequency
VCOL Operating
frequency
FMIF operating
freuquency
AMIF operating
freuquency
7.4.2 AC Characteristics for clock I/O
PARAMETER
NOM
Clock pulse rise time
tr (c)
20
nS
Clock pulse hold time
tf (c)
10
nS
Clock pulse duty cycle
dty (c)
55
%
45
X
50
Y
XTAL IN
RTC IN
X OR Y
DUTY(%) = T (c)
x 100
T (c) = X + Y
Note : Timing points are 90% (high) and 10% (low)
Figure 7-1. External driven clock waveform
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
71
8Bit Single Chip Microcontroller
DMC73C168
7.5 A/D Converter Characteristics
(Vss = 0V, VDD = 4.5 ~ 5.5V, Topr = -40 to 85¡É)
PARAMETER
TEST CONDITION
MIN
NOM
MAX
UNIT
8
bit
±2
LSB
Resolution
Non-Linearity
Zero error
±1
Full-scale error
Conversion time
4.5 MHz
64
us
7.6 AC Characteristics for Serial I/O ports
SCLKn
td (SL-TD)
Son
td (RD-SL)
Sin
DON'T CARE
DON'T CARE
td (RD)
Figure 7.2 AC Characteristics for Serial I/O ports
PARAMETER
MIN
NOM
td (SL-TD)
SCLKn low to new Son data
tc (c)
td (RD-SL)
Sin data valid before SCLKn high
tc (c)
td (RD)
Sin data valid time
4t (c)
Note : VDD = 5V ±10%, tc(c) = 2/Fosc
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
MAX
UNIT
sec
72
8Bit Single Chip Microcontroller
DMC73C168
7.7 Schematic of Inputs/Outputs
Port A, B, C, D, E, F, G, H
VDD
DATA LATCH
NAND
XDDR
PIN
NOR
VSS
DATA IN
VCOH, VCOL
EO1, EO2
VDD
VDD
PDP OUT
INPUT
SIGNAL
PIN
PIN
PHASE
DETECTOR
PDP OUT
AMP OFF
VSS
VSS VSS
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
73
8Bit Single Chip Microcontroller
DMC73C168
7.8 80 Pin Plastic Flat Package (Mechanical Data)
[ Unit : Milimeter ]
80 QFP
19.80
20.20
3.10 MAX
64
41
65
40
17.20
18.00
13.80
14.20
80
25
24
1
0.80 TYP
0.10 MIN
0.25
0.45
23.20
24.00
1.70
1.90
0.70
1.10
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
74
8Bit Single Chip Microcontroller
DMC73C168
* APPENDICES
A. DMC73C168 Table
B. Development Support
C. OTP Programming
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
75
8Bit Single Chip Microcontroller
DMC73C168
Appendix A. DMC73C168 Table
DMC73C168
TECHNOLOGY
CMOS
ROM SIZE
16K BYTE
RAM SIZE
384 BYTE
A/D CONVERTER
8BIT x 2CH
TIMER
2
SERIAL I/O
I/O
2
PORT
64
INPUT
-
OUTPUT
-
I/O
64
DISPLAY DRIVER
-
EVENT COUNTER
2
OPEN DRAIN PORT
-
MAX IN FREQ.
FM
150MHz
AM
40MHz
INTERRUPT
EXTERNAL
3
INTERNAL
5
PACKAGE
80 QFP
IF COUNTER
17 BIT
Appendix B. Development Support
B.1 H/W Tool
B.1.1. EVM73C00(A)
EVM73C00(A) is a DMC73CXX evaluation module, referred to throuthout this manual as the EVM.
It is designed to emulate the SINGLE-CHIP MODE of the DMC73CXX families. It provides all the
signals that would be available from masked ROM parts. The EVM provides the ability to develop,
debug, and test programs prior to factory masking.
Note : The EVM does not support the expansion modes of the DMC73CXX family of processors.
B.1.2 Functional Overview
-The EVM is a single-board development system capable of emulating the single-chip of the
DMC73CXX family or microcomputers.
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
76
8Bit Single Chip Microcontroller
DMC73C168
The EVM stands alone as a development system using the text editor for creation of DMC73CXX
assembly language text files and can also accept text files from a host CPU through either of the
two EIA ports. In both situations the resident assembler will convert the incoming text into excutable
code in the second pass after resolving labels from the first assembly pass.
The EVM firmware supports two ports in the operations of loading and dumping data (text and
object code) for storage and display. Port1/2 conform to the EIA RS-232C standard.
PORT1/PORT2 User terminal / terminal emulator
Uplink / downlink to/from host CPU
The EVM supports the following baud rates :
300, 600, 1200, 2400, 4800, 9600
First, we set baud rate as 9600 bps. But if you want to set another value, you can change this
by means of changing jumper (baud rate) on the EVM.
The EVM firmware is contained in 24K bytes of EPROM. The unused portion of the U45 EPROM
is accessed with the monitor commands U0 through U9.
The EVM requires 2K bytes of system RAM that is separate from the 32K bytes of user RAM.
A wire-wrap development area, with all required signals provided and labeled, is available for
additional logic. Since the EVM is intended to be a development tool by using the emulation cable,
the crystal frequency of the EVM can be altered to fit the needs of the target system.
B.1.3 Operating System
-The EVM operating system firmware resides in 24K bytes of EPROM and can be devided into three
major parts.
¤·Debug monitor and EPROM programmer
¤·Text editor
¤·Assembler
All the software is designed to interact with the user to provide a complete, powerful, and easy to
used development tool. During assembly and debug operations, the EVM RAM can be configured
to emulate all DMC73CXX family members. For emulation of the DMC73CXX devices, the EVM
allows assembly of text files from RAM, leaving the text intact for immediate editing after execution.
After assembly of the text editor output, breakpoints can be set based on either addresses or
line numbers. During execution, several modes of fixed displays are available, providing a hex
display of the entire register and peripheral files or a binary display of the peripheral ports. During
a fixed display, subsequent execution to a breakpoint or execution of a single instruction step will
overwrite the old data on the screen with new data.
A programmable line of up to six register or peripheral locations is provided for display with
breakpoints and instruction steps. The text editor is cursor and line number, duplicate line, and
find string commands. The cursor oriented edit capability simulates a screen editor by allowing
editing of the previous or next line moving the cursor up or down.
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
77
8Bit Single Chip Microcontroller
DMC73C168
B.1.4 Overview of Tool
*** The Tool of DTS Application Micom ***
DEVICE
DMC73C168
OTP
TMX73CE168
OTP ADAPTER
RWB73CE168QFP
ADP
ADP73C168
EVM
EVM73C00(A)
OTP WRITER
EVM73C00(A)
Note 1 : If you have any question, please call to Daewoo Electronics.
Note 2 : When you use EVM73C00, read the user's manual of EVM73C00 first, and then use
EVM73C00.
Note 4 : EVM73C00A is a new version of EVM73C00.
B.2 S/W Tool
B.2.1. Assembler
DMC73CXX assembly language instructions are mnemonic operation codes (or mnemonics) that
correspond directly to binary machine instructions. An assembly language program(source
program) must be converted to a machine language program (object program) by a process called
assembling becore a computer can execute it. Assembling converts the mnemonics to binary
values and associates those values with binary addresses, creating machine language instructions.
Assembler directives control this process, place data in the object program, and assign values to
the symbols used in the object program.
DMC73CXX assembly language is processed by a two-pass macro assembler that executed on a
host computer.
During the first pass the assembler :
1) Maintains the location counter,
2) Builds a symbol table, and
3) Produces a copy of the source code.
During the first pass the assembler :
1) Reads the copy of the source code and
2) Assembles the object code using the opcodes and symbol table produced during the first pass.
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
78
8Bit Single Chip Microcontroller
DMC73C168
Note :
There are some version in assembler software such as "asm7.com" and "asm700.exe".
asm7.com : can support program which use many labels but can't support macro.
asm700.exe : can support macro instruction but can't be used in program with many labels.
TYPE FILENAME.ASM
A0RG >C006
**** PROGRAM ****
END
; absolute address (16K byte rom size)
ASM7 FILENAME.ASM
Listing File [FILENAME.LST]
Object File [FILENAME.MPO]
NO ERROR, NO WARNING
----> ENTER KEY
----> ENTER KEY
----> ENTER KEY
The filemane.mpo is object file of TI hex format which can be downloaded into EVM.
B.2.2. Linker
The DMC73CXX assembler creates both absolute and relocatable object code that can be linked to
form executable programs from separately assembled modules. An entire program need not be
assembled at one time. A long program can be divided into separately assembled modules, avoiding
a long assembly and reducing the symbol table size. Caution must be observed when assembling
a long program with excessive labels ; this may cause an assembler error from symbol table overflow.
Modules that are common to several programs can be assembled once and accessed when needed.
These separately generated modules can be linked together by the link editor, forming a single
linked object module that is stored in a library and/or loaded as required.
Note : See the below simple example.
DIR C:
HA0.ASM HA1.ASM HA2.ASM HA0.MPO HA1.MPO HA2.MPO HA.CTL
TYPE HA0.ASM
TYPE HA1.ASM
PSEG
**** PROGRAM ****
END
TYPE HA2.ASM
DSEG
DATA RESET
END
; If this program size is 16K byte, reset
; address is C006 (trap 0)
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
79
8Bit Single Chip Microcontroller
TYPE HA.CTL
TASK HA
PROGRAM >C006
DATA
>FFFE
INCLUDE HA0.MPO
INCLUDE HA1.MPO
INCLUDE HA2.MPO
END
DMC73C168
; program start address
; data start address which is trap vector (reset)
;
;
;
LINKER HA.CTL
MAPFILE [HA.MAP]
LOADFILE [HA.LOD]
The filename of HA.LOD is object file of this.
Note : The data format of filename.lod is same as filename.mpo.
So you can use each file although it is filename.mpo or filename.lod to download to EVM.
APPENDIX C. OTP PROGRAMMING
* Recomendation for TMX73CE168 Adapter (RWB73CE168QFP)
C-1. Program Flow
STEP 1) EVM Power Off
STEP 2) EVM Power On
STEP 3) Set-up EVM Environment (HS/DV)
HS 1
DV 5
; 16K Byte ROM Size
STEP 4) Download your MPO File on EVM Board
LM 1
INITIALIZE (Y)
------ FILE.MPO TRANSFER -----STEP 5) Insert OTP (TMX73CE168) into Adapter Socket
STEP 5.1) Insert Adapter Socket into EPROM Socket on EVM
* If you use EVM73C00A (Not EVM73C00), Goto the Step 6-1.
STEP 6) Check Device Blank Areas you want to use (EX ; VE 0 3FFF 4)
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
80
8Bit Single Chip Microcontroller
VE 0 3FFF 4
DMC73C168
; VE : Blank Check, >0 : Device Start Address
; >3FFF : Device end Address, 4: ROM Size = 16K Byte,
;
VPP = 13.0V (TMX73CE168 : 0000H - 3FFFH)
; 0000H - 3FFFH (C000H - FFFFH) ; DV 4 16K
If error happen, try again from Step 7.
STEP 7) Program Device
PE 6 3FFF C006 4 ; TMX73CE168
; PE : Program OTP, >6 : Device Start Address
; >3FFF : Device End Address, 4 ; ROM Size = 16K Byte,
; VPP = 13.0V
STEP 8) Compare Device with your MPO File.
If error happen, try again from Step 7.
STEP 9) Take off Adapter Sock from EPROM Sock on EVM.
If you want to program another device, you have to do repeatedly from Step 5 to Step 9.
If you use EVM73C00A (Not EVM73C00), you may use below "One Line" batch
command.
STEP 6-1) Enter "AU" : Batch Command for VE & PE & CE
AU <CR>
Then VE, PE, SE operations are automatically operated, and displayed below line
in monitor.
VE
PE
CE
ANOTHER DEVICE (Y/N) ?
If you want to program another device (OTP) continuously, change device with new one in
OTP Writer Board and type "Y". When you type "N", This process goes to end.
* Important
- If you replace programmed device with new device on EVM Power On, some error may happen
in access to EPROM area on TMX73CE168 because VCC of EPROM Socket is still asserted.
In case of this mentioned error, if you don't want to do repeatedly from Step 1, get rid of adapter
sock from EVM and then insert adapter socket to EVM again.
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
81,82
80
8Bit Single Chip Microcontroller
DMC73C168
C-2. Attention
- This adapter board was checked completedly against all of errors but if this board don't operate
normally, PLS check address line, data line and control line according to the attached pin
description for cold sodering.
- If you want to protect the programmed data, contact TI Korea.
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
81 ÂÊ
81,82
81
8Bit Single Chip Microcontroller
DMC73C168
APPENDIX D. PG TAPE REQUISITION FORM
C - MOS
PROTO SAMPLE PG TAPE REQUISITION FORM
DEVICE NAME
APPLICATION
SO NUMBER
MP NUMBER
DMC73C168
COMPANY & DIV :
ROM [
] TO TIJ /
FSE NAME & LOC :
/ EPROM TYPE : TMC
QTY :
PCS
SIGNATURE :
PRODUCTION START :
/
/
POTENTIAL :
(KU / YEAR)
(RISK ORDER :
PCS, CRD
PROTO QTY :
(ES :
PCS, CRD
/
/
)
(QS :
PCS, CRD
/
SPECIFICATION
STANDARD
(
)
PACKAGE TYPE
80 PIN QFP
(
)
SYMBOLIZATION
TIJ STANDARD (
OSC FEEDBACK OPTION
1M (
INSTRUCTION SET (CROM)
/
)
OTHER
(PEAF :
)
5M (
/
)
) SPECIAL (PEAF :
STANDARD (
/
)
)
)
SPECIAL (
)
APPLICATION INFORMATION
POWER SUPPLY VOLTAGE
V
OSCILLATOR FREQUENCY
MHz
OPERATING TEMPERATURE RANGE
TIJ STANDARD (-40 TO =85 ) (
OSCILLATOR COMPONENT
CERAMIC RESONATOR (
STAND-BY MODE
NOT USED (
ENTERNAL INTERRUPT
) INT 1 (
F.E. OR LOW LEVEL (
INT 3
F.E. OR LOW LEVEL (
INT 4-0
NOT USED (
)
NOT USED (
)
)
ADC
)
EXTERNAL (
)
)
) INT 4-0 (
)
RISING EDGE (
)
RISING EDGE (
)
)
INT 6 (
EC MODE (
)
)
)
TIMER OUT (
)
)
)
R.E. OR HIGH LEVEL (
)
)
)
R.E. OR HIGH LEVEL (
)
)
)
R.E. OR HIGH LEVEL (
INT 2 (
)
TO
HALT MODE (
RISING EDGE (
TIMER MODE (
CAPTURE LATCH (
PLL
)
)
INT 3 (
TIMER MODE (
CAPTURE LATCH (
TIMER 2
)
FALLING EDGE (
F.E. OR LOW LEVEL (
TIMER
)
FALLING EDGE (
SENSE MODE
TIMER 1
)
FALLING EDGE (
EXTERNAL INTERRUPT
XTAL (
) WAKE UP MODE (
NOT USED (
INT 1
)
) OTHER (
EC MODE (
)
)
TIMER OUT (
)
AM
NOT USED (
)
USED (
) : RANGE FREQ (
) - (
), LF (
)
FM
NOT USED (
)
USED (
) : RANGE FREQ (
) - (
), LF (
)
NOT USED (
)
COMMENT
£Ä£Á£Å£×£Ï£Ï
DAEWOO ELECTRONICS CO., LTD.
82 ÂÊ
USED (
)