TRIQUINT TQ8105

R
I
SONET/SDH
Overhead
Processor
Q
U
I
N
T
TQ8105
or
TQ8106
SONET/SDH
Transceiver
S E M I C O N D U C T O R, I N C .
Rx O/E
with
CDR
Tx O/E
Reference
Clock
TQ8105/8106
PRELIMINARY DATA SHEET
SONET/SDH
Transceivers
TELECOM
PRODUCTS
T
Features
SONET/SDH
Overhead
Processor
TQ8106
SONET/SDH
Transceiver
with CDR
Rx O/E
Tx O/E
• Single-chip, byte-wide Mux,
Demux, Framer, and Tx clocksynthesis PLL with enhanced
diagnostics
The TQ8105/TQ8106 are SONET/SDH transceivers that integrate
multiplexing, demultiplexing, SONET/SDH framing, clock-synthesis PLL, and
enhanced line and clock diagnostic functions into a single monolithic device.
The TQ8106 is a pin-compatible upgrade of the TQ8105 that includes a
Clock and Data Recovery (CDR) function. The TQ8105 and TQ8106 allow
maximum flexibility in the selection of internal/external Clock and Data
Recovery, Opto-Electronic (O/E) Module, and Reference Clock Sources.
• TQ8106 includes monolithic
Clock and Data Recovery
On-chip PLLs use external RC-based loop filters to allow custom tailoring of
loop response and support the wide range of reference clock frequencies
found in SONET/SDH/ATM systems. For transmit clock synthesis or for CDR,
the PLLs exceed ANSI, Bellcore, and ITU jitter specifications for systems
when combined with industry-typical O/E devices such as Sumitomo, AT&T,
HP, and AMP. The TQ8105/TQ8106 PLLs provide byte clocks and constantrate 38.88 MHz and 51.84 MHz, synthesized clock outputs, providing
clocking for UTOPIA and other system busses. Transmit data may also be
clocked into the devices with respect to the reference clock.
• 38.88 MHz and 51.84 MHz clock
outputs for UTOPIA as well as
byte clock rate (77.76 or 19.44 MHz)
Operating from a single +5V supply, the TQ8105/TQ8106 provides fully
compliant functionality and performance, utilizing direct-connected PECL
levels (differential or single-ended) for high-speed I/O. As compared to ACcoupled schemes, the direct-coupled connections reduce jitter and
switching-level offsets due to data patterns. The TQ8105/TQ8106 can also
provide direct connection to high-speed I/O utilizing ECL levels with a –5V
supply. Low-speed bus, control, and clock I/O utilize TTL levels. (An ECL/
PECL reference clock input is also provided; at 155.52 MHz the input should
be only PECL/ECL.) Output TTL pins can be tristated and may also be
configured for VOH with a 3.3V supply connection.
• SONET/SDH/ATM compliant for
STS-12/STM-4 (622 Mb/s) or
STS-3/STM-1 (155 Mb/s) rates
• 155.52, 77.76, 51.84, 38.88, or
19.44 MHz reference clock inputs
with TTL, PECL, or ECL level
• External RC-based loop filters
• Integrated loopbacks with
enhanced line and reference
clock diagnostics
• Direct-coupled standard, PECL,
high-speed I/O with ECL option
• Clean TTL interface to
PMC-Sierra devices
• 100-pin 14x14 mm JEDEC
plastic package
• +5V-only supply for PECL I/O
(–5.2V required for ECL I/O option)
• –40 to +125°C case operating
temperature
For additional information and latest specifications, see our website: www.triquint.com
1
TQ8105/TQ8106
PRELIMINARY DATA SHEET
The combination of a thermally enhanced, 100-pin
JEDEC, metric, plastic package, the low-power
dissipation of the device, and the wide casetemperature range permits operation without a heat
sink in most designs.
TQ8105/TQ8106 diagnostics include:
• Loss of Reference clock detector (LOR) output to
indicate that the PLL Reference Clock is not toggling
• Lock Indicator (RLOCK), which permits monitoring
of the receiver clock frequency, flagging when the
frequency drifts beyond approximately 500 ppm
The TQ8106 uses the same pinout as the TQ8105 and
is compatible with it.
• Loss of Signal (LOS) detector output to indicate that
the incoming data stream has no data transitions in
128-bit periods
The TQ8105/TQ8106 provides comprehensive,
integrated, loopback functionality and enhanced line
and reference clock diagnostics required of SONET/
SDH systems, minimizing additional external circuitry.
• ECL/PECL input (NSOL) to allow LOS from an O/E
module to force the data stream to all zeroes,
eliminating the need for external glue logic.
CKSRC(2:0)
MXD(7:0)
LBM(1:0)
DXD(7:0)
MMS
FP2
3
REFCKT
Clock
Phase
TxBC
PH(1:0)
FP1
LOR
SDHCK
SONETCK
OC3
Figure 1. TQ8105 Block Diagram
B
Y
PLL Clock
Synthesizer
A
2
B
8
Parallel
to
Serial
Clock
Clock
Data
Data
2
8
Hold
Register
11
Serial
to
Parallel
Clock
Data
Loop
Back &
Retime
Block
ECL/
PECL
I/O
Block
TXD
DVPP
VPP
/8
VNN
2
Clock
2
Data
RXCK
RXD
NSOL
8
2
TXCK
2
Ext. Clk
Clock/8
OOF
Framer
DXSYNC
FRPWR
CLRLOS
2
A
NRESET
LOS
REFCKE
Y
NOE
RxBC
2
LOS
Detect
Freq.
Lock
Detect
RLOCK
TQ8105
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TQ8105/TQ8106
PRELIMINARY DATA SHEET
MXD(7:0)
PRODUCTS
MMS
REFCKT
Clock
Phase
TxBC
PH(1:0)
FP2
3
B
Y
PLL Clock
Synthesizer
A
2
2
B
DXD(7:0)
A
Ext. Clk
Clock/8
8
2
Clock
Clock
Parallel
To
Serial
Data
Data
ECL/
PECL
I/O
Block
Loopback
& Retime
Block
2
8
Hold
Register
11
Serial
To
Parallel
Clock
B
Y
Clock
Data
Data
2
Clock
B
Data
Y
Clock
& Data
Recovery
VNN
2
Data
2
A
RXCK
RXD
NSOL
NRESET
RxBC
TXD
VPP
Clock
A
TXCK
DVPP
8
NOE
REFCKE
Y
/8
LBM(1:0)
TELECOM
PRODUCTS
CKSRC(2:0)
FP1
LOR
SDHCK
SONETCK
OC3
Figure 2. TQ8106 Block Diagram
OOF
Framer
DXSYNC
NCDREN
FRPWR
RLOCK
TQ8106
CDRFP2
CDRFP1
LOS
Detect
CDRGND
CLRLOS
Freq.
Lock
Detect
CDRAVDD
LOS
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3
TQ8105/TQ8106
PRELIMINARY DATA SHEET
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VDD
SVDD
DXD7
DGND
DXD6
VCC
DXD5
DGND
DXD4
VCC
DXD3
DGND
DXD2
VCC
DXD1
DGND
DXD0
VCC
DXSYNC
DGND
RXBC
VCC
NC/CDRAVDD*
VDD
SVDD
Figure 3. 100-Pin Enhanced Plastic 14x14 mm Package Pinout
CDRGND*/NC
GND
FRPWR
OOF
VCC
LOS
DGND
CLRLOS
RLOCK
LBM1
GND
LBM0
VDD
NOE
GND
NRESET
OC3
MMS
CKSRC2
CKSRC1
CKSRC0
PH1
PH0
VDD
SVDD
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
GND
NC/CDRFP2*
NC/CDRFP1*
VNN
NSOL
VPP
DVPP
RXCKN
RXCKP
DVPP
RXDP
RXDN
DVPP
TXDP
TXDN
DVPP
TXCKP
TXCKN
DVPP
REFCKEP
REFCKEN
DVPP
VPP
NC
VNN
GND 76
MXD0 77
MXD1 78
MXD2 79
MXD3 80
MXD4 81
MXD5 82
MXD6 83
MXD7 84
VCC 85
TXBC 86
DGND 87
88
SONETCK
VCC 89
SDHCK 90
DGND 91
LOR 92
AGND 93
FP2 94
FP1 95
AVDD 96
VDD 97
REFCKT 98
GND 99
NCDREN*/NC 100
Note: *TQ8106-specific signal
Table 1. Signal Descriptions (continues on next page)
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Note:
4
Signal
VNN
NC
VPP
DVPP
REFCKEN
REFCKEP
DVPP
TXCKN
TXCKP
DVPP
TXDN
TXDP
DVPP
RXDN
RXDP
Function
–5.2V/Ground
No Connect
Ground/+5V
Ground/+5V
ECL/PECL Input
ECL/PECL Input
Ground/+5V
ECL/PECL Out
ECL/PECL Out
Ground/+5V
ECL/PECL Out
ECL/PECL Out
Ground/+5V
ECL/PECL Input
ECL/PECL Input
Description
ECL/PECL section power
Do not connect
ECL/PECL Positive Supply (see Table 6B)
ECL/PECL Driver Return (see Table 6B)
Tx Ref. Clock or Bypass Clock, Complement
Tx Ref. Clock or Bypass Clock, True
ECL/PECL Driver Return (see Table 6B)
Transmit Clock, Complement
Transmit Clock, True
ECL/PECL Driver Return (see Table 6B)
Transmit Data, Complement
Transmit Data, True
ECL/PECL Driver Return (see Table 6B)
Receive Data, Complement
Receive Data, True
*TQ8106-specific signal
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TQ8105/TQ8106
PRELIMINARY DATA SHEET
Signal
DVPP
RXCKP
RXCKN
DVPP
VPP
NSOL
VNN
NC/CDRFP1*
NC/CDRFP2*
GND
SVDD
VDD
CDRAVDD*
Function
Ground/+5V
ECL/PECL Input
ECL/PECL Input
Ground/+5V
Ground/+5V
ECL/PECL Input
–5.2V/Ground
Analog Output
Analog Input
GND
+5V
+5V
Analog +5V
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
VCC
RxBC
DGND
DXSYNC
VCC
DXD0
DGND
DXD1
VCC
DXD2
DGND
DXD3
VCC
DXD4
DGND
DXD5
VCC
DXD6
DGND
DXD7
SVDD
VDD
NC/CDRGND*
GND
FRPWR
OOF
VCC
LOS
DGND
+5V/+3.3V
Tristate TTL Out
GND
Tristate TTL Out
+5V/+3.3V
Tristate TTL Out
GND
Tristate TTL Out
+5V/+3.3V
Tristate TTL Out
GND
Tristate TTL Out
+5V/+3.3V
Tristate TTL Out
GND
Tristate TTL Out
+5V/+3.3V
Tristate TTL Out
GND
Tristate TTL Out
+5V
+5V
GND
GND
TTL Input
TTL Input
+5V/+3.3V
Tristate TTL Output
GND
Note:
Description
ECL/PECL Driver Return (see Table 6B)
Receive Clock, True (Ignored when CDR used)
Receive Clock, Complement (Ignored when CDR used)
ECL/PECL Driver Return (see Table 6B)
ECL/PECL Positive Supply (see Table 6B)
Loss of Signal — zeroes serial data in when low; RXBC=TXCK/8
ECL/PECL section power (see Table 6B)
CDR Loop Filter Pin 1 — Charge Pump Out (ignored by TQ8105)
CDR Loop Filter Pin 2 — VCO Tune (ignored by TQ8105)
Core Ground
Output Driver Internal Positive Supply
Core Positive Supply
TQ8106 CDR Analog +5V Supply
(not connected if CDR not used; ignored by TQ8105)
TTL Driver Positive Supply
Demultiplexer Byte Clock
TTL Driver Ground
Frame Synchronization Signal
TTL Driver Positive Supply
Demultiplexer Data Bit 0 (LSB)
TTL Driver Ground
Demultiplexer Data Bit 1
TTL Driver Positive Supply
Demultiplexer Data Bit 2
TTL Driver Ground
Demultiplexer Data Bit 3
TTL Driver Positive Supply
Demultiplexer Data Bit 4
TTL Driver Ground
Demultiplexer Data Bit 5
TTL Driver Positive Supply
Demultiplexer Data Bit 6
TTL Driver Ground
Demultiplexer Data Bit 7 (MSB)
Output Driver Internal Positive Supply
Core Positive Supply
GND for TQ8106 to powerup CDR (ignored by TQ8105)
Core Ground
Framer Power Control (power on when high)
Out-of-Frame: Initiates Frame Search/Bit Alignment
TTL Driver Positive Supply
Loss of Signal (high when > 128 bit periods without transitions)
TTL Driver Ground
TELECOM
PRODUCTS
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
PRODUCTS
Table 1. Signal Descriptions (continued)
*TQ8106-specific signal
For additional information and latest specifications, see our website: www.triquint.com
5
TQ8105/TQ8106
PRELIMINARY DATA SHEET
Table 1. Signal Descriptions (continued)
Pin
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Signal
CLRLOS
RLOCK
LBM1
GND
LBM0
VDD
NOE
GND
NRESET
OC3
MMS
CKSRC2
CKSRC1
CKSRC0
PH1
PH0
VDD
SVDD
GND
MXD0
MXD1
MXD2
MXD3
MXD4
MXD5
MXD6
MXD7
VCC
TxBC
DGND
SONETCK
VCC
SDHCK
DGND
LOR
AGND
FP2
FP1
AVDD
VDD
REFCKT
GND
NC/NCDREN*
Function
TTL Input
Tristate TTL Output
TTL Input
GND
TTL Input
+5V
TTL Input
GND
TTL Input
TTL Input
TTL Input
TTL Input
TTL Input
TTL Input
TTL Input
TTL Input
+5V
+5V
GND
TTL Input
TTL Input
TTL Input
TTL Input
TTL Input
TTL Input
TTL Input
TTL Input
+5V/+3.3V
Tristate TTL Out
GND
Tristate TTL Out
+5V/+3.3V
Tristate TTL Out
GND
Tristate TTL Out
Analog Ground
Analog Output
Analog Input
Analog +5V
+5V
TTL Input
GND
TTL Input
Description
Active-high Clear LOS output
Receive Clock meets lock criteria when high
Loopback Mode Control (see Table 3)
Core Ground
Loopback Mode Control (see Table 3)
Core Positive Supply
TTL tristate control (active low to enable)
Core Ground
Global Reset (active low)
OC3/OC12 Mode Select
Master/Slave Mode Control
Clock Source Select (see Table 3)
Clock Source Select (see Table 3)
Clock Source Select (see Table 3)
TxBC Phase Select (see Table 3)
TxBC Phase Select (see Table 3)
Core Positive Supply
Output Driver Internal Positive Supply
Core Ground
Multiplexer Data Bit 0 (LSB)
Multiplexer Data Bit 1
Multiplexer Data Bit 2
Multiplexer Data Bit 3
Multiplexer Data Bit 4
Multiplexer Data Bit 5
Multiplexer Data Bit 6
Multiplexer Data Bit 7 (MSB)
TTL Driver Positive Supply
Transmit Byte Clock
TTL Driver Ground
51.84 MHz Clock Output
TTL Driver Positive Supply
38.88 MHz Clock Output
TTL Driver Ground
Indicates Reference Clock is Absent
VCO Analog Ground
Transmit PLL Loop Filter, Charge Pump Out
Transmit PLL Loop Filter, VCO Tune
VCO & Filter Analog VDD Supply
Core Positive Supply
Tx Reference Clock or Bypass Clock
Core Ground
Internal Pull-up, Low = CDR receiver clock; Float = Pin 17/18 Rx Clk
(ignored by TQ8105)
Note:*TQ8106-specific signal
6
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TQ8105/TQ8106
PLL
The TQ8105 & TQ8106 incorporate high-stability, lowjitter Phase Locked Loops (PLLs) running at 2488.32
MHz. The PLLs use external surface mounted loop filters
consisting of an RC network as shown in the diagrams
that accompany the values shown in Table 2. Analog
design principles should be applied to the loop filter
portions of the circuit to ensure optimal jitter generation
performance. To reduce cross-coupling of clocks, both
CDR clocks and analog pins should be isolated from the
transmit PLL clock and analog pins. An analog ground
plane under the two capacitors and the resistor, along
with guards around the filter pins is excellent practice, as
is a well-filtered analog supply (AVDD) and a clean
analog ground (AGND). The loop filter values specified in
this preliminary data sheet may change.
Reference clock sourcing can be through a variety of
mechanisms. As shown in Table 3, the MMS pin
determines whether the device operates in Master
mode (where the PLL reference comes in on either a
TTL or PECL/ECL pin), or a Slave mode (where the PLL
reference is derived from the DEMUX high-speed line
clock input). If the external reference clock pins are
used, note that they are logical ORs and that the
unused pin should be tied to (a) GND for unused
REFCKT, or (b) REFCKEN should be tied to VPP for TTL
reference operation. The reference clock frequency can
be selected from any number of values, as indicated in
Table 3. Note that the PLL may be bypassed, allowing
use of an external clock reference.
Internal dividers determine the operating line rate, as
shown in Table 3. The device is capable of operating at
STM1/STS-3 or STM4/STS-12 rates. The transmit PLL
provides high performance and compliance with ITU/
Bellcore requirements found in the first-generation
TQ8101. The TQ8106 receiver's CDR can be disabled
for backwards pin-compatibility with the TQ8105. For
circuits not requiring the TQ8106's CDR, the CDR is
disabled by floating NCDREN (pin 100). Further, the CDR
section of the TQ8106 can be powered down by
disconnecting the CDRGND and CDRAVDD pins, thereby
reducing power consumption. If the TQ8106 CDR is not
used, the CDR filter pins may be left unconnected.
The transmit PLL also provides constant-rate 38.88 MHz
and 51.84 MHz TTL outputs which may be tristated. The
38.88 MHz & 51.84 MHz output may also be achieved by
using high-speed receiver timing in Clock Source Mode
011 (see Table 3).
Framer
The TQ8105 and TQ8106 provide a clean interface to
devices from PMC-Sierra and others. The Out-of-Frame
(OOF) input is a state (level)-initiated event, rather than
the edge-triggered event found on TriQuint’s firstgeneration TQ8101 transceiver. When OOF is high, the
TQ8105/TQ8106 initiates a frame search for a serial bit
pattern of twelve A1s (three A1s in OC3 mode) followed
by three A2s. If a match occurs, the device realigns
byte boundaries and issues a logic high on the DXSYNC
pin during the third A2. In the absence of OOF, the
device will not realign byte boundaries, but will report
any bit-level matching of twelve A1s (three A1s in OC3
mode) followed by three A2s as a DXSYNC pulse.
Framer circuit power may be switched off by a TTL low on
the FRPWR pin, saving approximately 0.25W. No further
DXSYNC pulses will be issued, though bit alignment is
preserved in the demux. Note that the OOF and FRPWR
pins may be tied together, powering the framer only when
bit realignment is required (this is not recommended
practice, however, due to the inrush currents that may
result).
Loopbacks
As part of the TQ8105 and TQ8106 on-chip diagnostics,
four loopback modes are supported. These are selected
by the dedicated pins LBM0 and LBM1, as shown in
Table 3. The loopback modes are shown in Figure 5.
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7
TELECOM
PRODUCTS
Function Description
PRODUCTS
PRELIMINARY DATA SHEET
TQ8105/TQ8106
PRELIMINARY DATA SHEET
Functional Description (continued)
Enhanced Diagnostics
The TQ8105 and TQ8106 incorporate on-chip clock
diagnostics, allowing fast, efficient fault detection and
isolation at the systems level.
The LOR (Loss Of Reference) output goes high when the
reference clock is absent. Note that this signal is not
latched and is only high when the reference clock is
missing. A reference clock is required for the TQ8106
CDR to function correctly.
The NSOL (Loss-of-signal input, active low, PECL/ECL
level) input allows the receiver to force zeroes onto the
demux outputs. A TTL-level signal may also be used for
NSOL if the resistor network, shown in the applications
section of this data sheet, is used. NSOL is useful when a
Loss Of Signal occurs on the receive optics, and a
quieting of invalid data is desired. The receiver is clocked
from the transmit clock when NSOL is active, and the
output RXBC clock is obtained from the transmit portion
of the TQ8105/TQ8106. This ensures compatibility with
devices, such as the PMC-Sierra S/UNI-622 and STTX
components, which may contain dynamic registers that
lose contents if clocks are removed. NSOL forces the
CDR to lock on REFCLK, except when in slave mode.
The LOS (Loss Of Signal) output goes high whenever
128-bit periods occur without transitions on the data
input to the demux. CLRLOS forces LOS low.
The RLOCK (Receiver LOCK) output goes low whenever the
signal on RXCK or the recovered clock drifts more than
500 ppm from the reference frequency. This output returns
high whenever the frequency accuracy is within 100 ppm.
Demux
The TQ8105/TQ8106 demultiplexer converts an NRZ
PECL/ECL data input, at either 155 Mb/s or 622 Mb/s,
and its corresponding PECL/ECL clock into a byte-parallel
8
78 MHz or 19 MHz tristatable TTL data bus. The timing is
shown in Figures 6 through 8. See the previous “Framer”
description for bit alignment details. The TQ8106 can
recover both clock and data from a NRZ data stream,
whereas the TQ8105 requires NRZ data and a recovered
clock.
Mux
The TQ8105/TQ8106 multiplexer converts a 78 MHz or
19 MHz byte-wide bus to a serial NRZ PECL/ECL data
stream. The bytes are clocked into the device with the
TXBC byte clock output. The timing is shown in Figures
6 through 8. Note that the TXBC output can be adjusted
in 90-degree phase increments to accommodate
variations in interface requirements. See Table 3 for
settings on the PH0 and PH1 pins controlling this
function. Data may also be clocked into the TQ8105/
TQ8106 by a 77 MHz reference, oscillator-clock source,
provided the data is within the timing limits shown in the
timing diagram labelled “Reference Clock Based
Transmit Timing.” The TQ8105 and TQ8106 do not
require the transmit latch found on earlier TQ8101
reference designs and are backwards compatible with
designs that have the latch incorporated.
High-Speed I/O and TTL Interfaces
The TQ8105/06P will operate with either PECL or ECL
operation on the high-speed I/O. With a single +5V
supply, the part interfaces directly with TTL and PECL
(Positive Emitter Coupled Logic). By providing an
additional -5.2V supply, the device’s high-speed I/O
becomes ECL, instead of PECL. The TQ8105/06S is
designed only for PECL high-speed I/0 operation with a
single +5V supply. The power supply connections for
PECL and ECL are shown in Table 6B.
The TTL outputs (Vcc) may be connected to either +5V or
+3.3V supplies. True TTL may be obtained with the +5V
connection; clamped operation, when connected to +3.3V,
ensures that maximum Voh levels do not exceed +3.3V.
For additional information and latest specifications, see our website: www.triquint.com
TQ8105/TQ8106
These design notes are provided to assist the circuit
designer in achieving the highest possible performance
while reducing design time. Unless noted otherwise,
references to the TQ8105 apply equally to the TQ8106.
Interfacing to PMC-Sierra Devices
The transmit timing of the TQ8105 is such that the
PMC-Sierra byte outputs (POUT(0:7)) may be directly
connected to the TQ8105 mux inputs (MXD(0:7)). The
TQ8105 uses an Out-Of-Frame (OOF) input as a signal
to reframe while high, allowing direct connection of the
PM5355's OOF output to the TQ8105 OOF input. The
following summarizes connectivity between the devices.
clips soldered to the board to cross and hold the
heatsink. The clip holes in the board are at the corners of
a 1.275” x 1.5” rectangle. Another alternative is the
circular heatsink, #2288B from Thermalloy attached with
their Thermattach #19686-3.
Power Supplies
TELECOM
PRODUCTS
TQ8105/TQ8106 Design Notes
Good decoupling practices should be observed, with a
0.1 uF decoupling capacitor at each supply pin, ideally
on the component side of the board. Keep the analog
supplies (Vdd and AVdd) pristine. Proper design will
isolate the supply groups using point grounding to tie
supplies together (all grounds at a single point having
multiple vias).
PM5355
TQ8105/TQ8106
POUT(0:7)
MXD(0:7)
PIN(0:7)
DXD(0:7)
OOF
OOF
PICLK
RXBC
FPIN
DXSYNC
For the analog supply, flood copper under the loop filter
on the component side of the board, tying the flood to
the analog ground pin, with the point ground away from
the filter and analog pin, so that any switching currents
are kept away from these areas. If any switching,
power-supply frequencies below 500 kHz are used in
the system, use a supply filter on the analog supply pin.
These practices help minimize the generation of jitter.
TCLK
TXBC
High-Speed Connections
POP(0:5)
Any TQ8105 modes to be programmable
PIP(0:3)
Any TQ8105 diag outputs to be readable
Reference Design
A reference design (see Figure 4) and evaluation board
are available from TriQuint. They incorporate a 1x9 or
2x9 fiber optic transceiver (with the option of clock
recovery), the PM5355 PMC Sierra framer device, and
a TQ8105 or TQ8106.
Thermal Considerations
Figure 9 shows the region where the use of a heatsink is
not required. For example, the TQ8105 does not require
a heatsink for ambient temperatures up to 55°C in still
air. An airflow of 100 LFPM raised this temperature to
approximately 75°C, eliminating heatsink requirements.
Connections to E/O modules (and clock reference, if
used) are direct-coupled PECL and need to be terminated
with decoupled 50 ohms to 3V at the receiving end of the 50
ohm transmission line. Ensure that each 50 ohm resistor
(or Thevenin equivalent) has its own decoupling
capacitor. Place the resistor at the end of a 50 ohm
transmission line (use a controlled impedance layer),
ideally with a minimal-length stub attached to either the
resistor or the receiving device.
If there is no room for the resistor, use a minimallength stub to drop the signal at the receiving device
pins, continue the 50 ohm transmission line to an area
where the termination resistors can be placed, and
terminate at the endpoint of that line. If in doubt,
contact factory applications for assistance.
In applications requiring a heatsink, a standard pin-fin
heat-sink is appropriate. To attach the sink, use spring
For additional information and latest specifications, see our website: www.triquint.com
PRODUCTS
PRELIMINARY DATA SHEET
9
TQ8105/TQ8106
PRELIMINARY DATA SHEET
Figure 4. Reference Design Schematic
220
330
88
137
150
149
148
147
146
145
144
143
142
141
103
94
93
89
91
92
86
85
84
83
101
82
77
73
72
139
140
63
65
104
60
58
59
61
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
186
190
62
192
23
24
25
26
31
32
33
34
15
16
17
18
19
20
21
22
14
36
37
38
35
70
126
127
71
125
VDD
VDD
220
11111112
12468911236780
18060809985996
330
1112
1282580
0710235
gnd_s
VVVVVVV
DDDDDDD
DDDDDDD
_______
AAAAAAA
CCCCCCC
1234567
S/UNI 622
U?
VVVVVVVVVVVVVV
DDDDDDDDDDDDDD
DDDDDDDDDDDDDD
______________
DDDDDDDDDDDDDD
CCCCCCCCCCCCCC
12345678911111
01234
gnd_s
VDD
PICLK
FPOS
FPIN
PIN0
PIN1
PIN2
PIN3
PIN4
PIN5
PIN6
PIN7
TLAIS
TSD
TSOW
TSUC
TLRDI
TLD
TLOW
TTOH1
TTOH2
TTOH3
TTOH4
TTOHEN
TPOH
TPOHEN
97
74
TT
CF
LP
K
FPOUT
POUT0
POUT1
POUT2
POUT3
POUT4
POUT5
POUT6
POUT7
OOF
LOF
LOS
TSDCLK
123
122
121
116
115
114
113
112
111
164
163
169
102
TOWCLK 95
159
RSDCLK 160
RSD
ROWCLK 168
RSOW 162
RSUC 161
OHFP 175
171
LAIS
170
LRDI
RLDCLK 173
RLD 172
RLOW 167
90
TLDCLK
TPAIS
156
155
154
153
157
158
99
100
181
176
177
75
76
178
182
185
87
124
174
188
195
196
197
198
199
200
201
202
203
204
1
2
3
4
5
6
7
8
9
194
67
187
193
68
135
134
133
132
131
130
108
107
106
105
39
*0
*Note 3
VDD
2K
0.1u
VDD
gnd_s
*Note 2
*330
*330
*330
*330
330
330
330
330
330
2K
10
1
gnd_s
1
4
0.1u
U?
77.76M Osc
VDD
82
130
77
78
79
80
81
82
83
84
54
98
6
5
15
14
17
18
21
73
72
71
70
69
62
60
68
67
58
53
64
100
66
130
8
0.1u
7
gnd_s
47u
VDD
gnd_s gnd_s
Reset
10K
gnd_s
VDD
VDD
gnd_s
VDD
gnd_s
VDD
4.7K
VDD
gnd_s
(Decoupling not shown for PM5355)
*Only connections pertinent to the TQ8105/06
to S/UNI overhead processor chip are shown.*
INTB
PIP0
PIP1
PIP2
PIP3
POP0
POP1
POP2
POP3
POP4
POP5
TCP
RGFC
RCP
RCA
TCA
RDAT0
RDAT1
RDAT2
RDAT3
RDAT4
RDAT5
RDAT6
RDAT7
RDAT8
RDAT9
RDAT10
RDAT11
RDAT12
RDAT13
RDAT14
RDAT15
RXPRTY0
RXPRTY1
RSOC
LCD
GROCLK
GTOCLK
TSOUT
LOP
PAIS
PRDI
TPOHCLK
TPOHFP
RPOH
RPOHCLK
RPOHFP
TTOHCLK
TTOHFP
RTOHCLK
RTOHFP
TPRDI
6
9
RSICLK
RSIN
N
C
6
9
RTOH1
RTOH2
RTOH3
RTOH4
TSICLK
TFCLK
XOFF
TSOC
12467911111112
29149601236890
98866017
VVVVV
VVVVVVVVVSSSSS
SSSSSSSSSSSSSS
SSSSSSSSS_____
_ _ _ _ _ _ _ _ _ DDDDD
DDDDDDDDDC C C C C
CCCCCCCCC11111
12345678901234
TXPRTY0
TXPRTY1
TWRENB
TDAT0
TDAT1
TDAT2
TDAT3
TDAT4
TDAT5
TDAT6
TDAT7
TDAT8
TDAT9
TDAT10
TDAT11
TDAT12
TDAT13
TDAT14
TDAT15
RRDENB
RFCLK
TSEN
TGFC
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
A7
ALE
CSB
WRB
RDB
RSTB
TCK
TMS
TDI
TDO
TRSTB
1371112
3081580
7148
VVVVVVV
SSSSSSS
SSSSSSS
_______
AAAAAAA
CCCCCCC
1234567
gnd_s
VDD
MXD0
MXD1
MXD2
MXD3
MXD4
MXD5
MXD6
MXD7
OOF
REFCKT
25679
70347
SSS
VVV
DDD
DDD
___
123
247
695
VVVVVVVV
CCCCCCCC
CCCCCCCC
________
12345678
23344588
93715559
2
30
VDD
20K
34
36
38
40
42
44
46
48
32
30
86
4
7
10
13
16
19
12
11
9
8
88
90
92
56
59
95
94
96
93
23
24
28
51
LOR
470
NCI_2
NCI_3
NCI_4
NCI_5
FP1
FP2
AVDD
AGND
RLOCK
LOS
LOR
SONETCK
SDHCK
TXDP
TXDN
TXCKP
TXCKN
DVPP_1
DVPP_2
DVPP_3
DVPP_4
DVPP_5
DVPP_6
TXBC
VVVVV
DDDDD
DDDDD
_____
12345
VV
NN
NN
__
12
U?
TQ8105
V V DXD0
P P DXD1
PP
_ _ DXD2
1 2 DXD3
DXD4
DXD5
DXD6
DXD7
DXSYNC
RXBC
REFCKEP
REFCKEN
RXDP
RXDN
RXCKP
RXCKN
NSOL
PH0
PH1
CKSRC0
CKSRC1
CKSRC2
LBM0
LBM1
MMS
OC3
CLRLOS
DDDDDDDD
GGGGGGGG
NNNNNNNN
DDDDDDDD
________
12345678
2
12
FRPWR
NCI_1
GGGGGG
NNNNNN
NOE
DDDDDD
______
NRESET 1 2 3 4 5 6
33344589
15937771
82
gnd_s
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
*Note 1
82
130
C2
82
130
VDD
1uH
0.1u
10u
VDD
0.1u
R1
C1
gnd_s
0.1u
11
12
1
2
TD
TDN
T
X
V
C
C
1
3
R
X
V
C
C
1
4
10u
0.1u
gnd_s
0.1u
1uH
gnd_s
gnd_s
1uH
0.1u
gnd_s
15
4
3
17
16
U?
HFBR5207
RD
RDN
SD
CLK
CLKN
1
8
R
X
V
E
E
REFCLK
LCKREFN
T
X
V
E
E
gnd_s
1
0
gnd_s
4) May use SONETCK (51.84MHz) for
UTOPIA bus clock.
3) Install 0-ohm resistor for TQ8106 operation.
are determined at initial board evaluation.
(See Table 3 and associated text.)
2) Setting of PH(0:1) is board-layout dependent.
These 4 resistors are used as placeholders
for the appropriate strapped settings that
their respective input pins as possible.
Notes:
1) Place termination networks as close to
VDD
1uH
gnd_s
C4
10u
0.1u
gnd_s
gnd_s
gnd_s
VDD
NLOCKED
470
10u
UTOPIA
*Note 4
R2
C3
gnd_s
470
0.1u
0.1u
0.1u
LOS
0.1u
0.1u
0.1u
gnd_s
0.1u
0.1u
TQ8105 Decoupling
0.1u
0.1u
*Note 1
gnd_s
130
gnd_s
10u
10u
10u
Note: See Tables 2A & 2B
for loop filter values.
256679
521569
82
82
130
VDD
VDD
VDD
VDD
VDD
0.1u
For additional information and latest specifications, see our website: www.triquint.com
10
TQ8105/TQ8106
PRELIMINARY DATA SHEET
Divide
Ratio
Resistor
Value R1
(ohms)
Capacitor
Value C1
(µF)
Capacitor
Value C2
(pF)
19.44
32
1200
0.082
82
38.88
16
620
0.15
150
51.84
12
470
0.22
220
77.76
8
300
0.33
330
155.52*
4
300
0.33
330
TELECOM
PRODUCTS
Reference
Frequency
(MHz)
PRODUCTS
Table 2A. TQ8105/TQ8106 Recommended Transmit Loop Filter Values (Preliminary)
Note: *Internal divide by two on Reference
Table 2B. TQ8106 Recommended CDR Loop Filter Values
(Preliminary)
Incoming
NRZ Data Rate
(Mbs)
Resistor
Value R2
(ohms)
Capacitor
Value C3
(µF)
Capacitor
Value C4
(pF)
155.52
622.08
470
680
1.0
4.7
39
39
AVDD
CDRAVDD
C1
C3
C2
C4
R1
R2
FP1
CDRFP1
FP2
CDRFP2
Figure 5. Loopback Modes
Equipment
Normal
RXD
DXD
RXBC
RXCK
TXD
MXD
TXCK
RXD
DXD
RXCK
RXBC
TXD
TXCK
Split
Facility
RXD
DXD
RXCK
RXBC
TXD
MXD
TXCK
MXD
RXD
DXD
RXCK
TXD
MXD
TXCK
For additional information and latest specifications, see our website: www.triquint.com
11
TQ8105/TQ8106
PRELIMINARY DATA SHEET
Table 3. Mode Selection
Signals
LBM(1:0)
PH(1:0)
MMS
CKSRC(2:0)
OOF
NSOL
OC3
NRESET
NCDREN
Mode
Loopback: 00 = Normal, 01 = Equipment, 10 = Facility, 11 = Split
00 = 0 degrees delay, 01 = 90 degrees delay, 10 = 180 degrees delay, 11 = 270 degrees delay
1 = Master (use REFCKT/E as reference), 0 = Slave (use receive clock as reference)
Clock Source:
000 = PLL bypass
001 = 51.84 MHz PLL reference, SONETCK & SDHCK tristate
010 = 155.52 MHz PLL reference
011 = 51.84 MHz PLL reference, SONETCK=8, SDHCK derived from receiver timing
100 = 77.76 MHz PLL reference
101 = 51.84 MHz PLL reference
110 = 38.88 MHz PLL reference
111 = 19.44 MHz PLL reference
1 = Initiate frame search, 0 = Do not permit reframing (see FRPWR pin in Table 1)
1 = Pass receive data, 0 = Force receive data to 0
1 = Operate at STM1/STS-3 (or PLL bypass divided by 4), 0 = Operate at STM4/STS-12/PLL bypass
1 = Normal operation, 0 = Reset internal counters
1 = TQ8105/CDR Off mode, 0 = Enable CDR (TQ8106 only)
Table 4. Absolute Maximum Ratings
Parameter
Positive supply
Negative supply (VPP = 0 V)
Output voltage
Output current
Input voltage
Input current
Output voltage
Output current
Input voltage
Input current
Biased junction temperature
Storage temperature
12
Symbol
VCC, VPP, VDD, AVDD
VNN
VO
IO
VI
II
VO
IO
VI
II
TJ
TS
Level
GND
ECL/PECL
ECL/PECL
ECL/PECL
ECL/PECL
TTL
TTL
TTL
TTL
—
—
Minimum
7
–7
VNN–0.5
—
VNN–0.5
–1
–0.5
—
–0.5
–1
–55
–65
For additional information and latest specifications, see our website: www.triquint.com
Maximum
V
GND
VPP+0.5
40
VPP+0.5
1
VCC+0.5
100
VCC+0.5
1
+150
+150
Unit
V
V
mA
V
mA
V
mA
V
mA
°C
°C
TQ8105/TQ8106
PRELIMINARY DATA SHEET
Function
+5V supply
+5V / +3V supply
+5V / 0V supply
+5V supply
Power dissipation, Framer on, TQ8106 CDR off
Power dissipation, Framer off, TQ8106 CDR off
Power dissipation, Framer on, TQ8106 CDR on
Minimum
—
—
—
—
—
—
Typical
0.323
0.016
0.055
0.018
1.9
1.7
Maximum
TBD
TBD
TBD
TBD
2.3
2.1
2.75
Unit
I
I
I
I
W
W
W
Minimum
4.75
3.0
–5.5
–40
Typical
5.0
Maximum
5.25
5.25
–4.75
125
Unit
V
V
V
°C
Table 6A. Recommended Operating Conditions
Parameter
Positive supply
Output driver positive supply
Negative supply (ECL mode only)
Operating case temperature (see Figure 9)
Symbol
VPP
VCC
VNN
–5.2
Table 6B. Power Supply Connections
Pin
VDD
SVDD
VCC
AVDD
CDRAVDD
GND
AGND
CDRGND
VPP/DVPP
VNN
+5V TTL/PECL I/O
+5V
+5V
+5V
Filtered +5V
Filtered +5V
0V (ground)
0V (ground)
0V (ground)
+5V
0V (ground)
+3.3V TTL/PECL I/O
+5V
+5V
+3.3V
Filtered +5V
Filtered +5V
0V (ground)
0V (ground)
0V (ground)
+5V
0V (ground)
+5V TTL/ECL I/O
+5V
+5V
+5V
Filtered +5V
Filtered +5V
0V (ground)
0V (ground)
0V (ground)
0V (ground)
-5.2V
+3.3V TTL/ECL I/O
+5V
+5V
+3.3V
Filtered +5V
Filtered +5V
0V (ground)
0V (ground)
0V (ground)
0V (ground)
-5.2V
For additional information and latest specifications, see our website: www.triquint.com
13
TELECOM
PRODUCTS
Symbol
IDD
ICC
IPP
IADD
PDF
PD
P
PRODUCTS
Table 5. Power Consumption
TQ8105/TQ8106
PRELIMINARY DATA SHEET
Table 7. DC Characteristics—ECL/PECL I/O
(Specifications apply over recommended operating ranges).
Parameter
Internal ECL reference
Common mode voltage
Differential voltage
Input HIGH voltage
Input LOW voltage
Output HIGH voltage
VPP – 600
Unit
mV
mV
mV
mV
mV
mV
—
VPP – 1600
mV
—
–265
20
+130
–130
23
335
—
30
uA
uA
mA
IOL
0
5
8
mA
Input capacitance
CIN
—
—
TBD
pF
Output capacitance
ESD breakdown rating
COUT
VESD
—
Class I
—
—
TBD
—
pF
Symbol
VIH
VIL
IIH
IIL
VOH
VOL
IOZ
CIN
COUT
VESD
Minimum
2.0
0
—
–400
2.4
0
–100
—
—
Class I
Nominal
—
—
—
–200
—
—
—
—
—
—
Maximum
VCC
0.8
200
—
VCC
0.4
100
TBD
TBD
—
Output LOW voltage
Input HIGH current
Input LOW current
Output HIGH current
Output LOW current
Condition
Single-ended inputs
Differential inputs
Differential inputs
VREF = 1300 mV
RLOAD = 50 ohms
to VTT = VPP – 2.0V
RLOAD = 50 ohms
to VTT = VPP – 2.0V
VIH(MAX)
VIL(MIN)
(Not tested; consistent
with VOH and VOL tests)
(Not tested; consistent
with VOH and VOL tests)
(Design objective)
Symbol
VREF
VCOM
VDIFF
VIH
VIL
VOH
Minimum
—
VPP – 1500
200
VPP – 1050
VTT
VPP – 1000
Nominal
0.26 VNN + 0.74 VPP
—
Maximum
—
—
1200
VPP – 400
—
VPP – 1550
VOL
VTT
IIH
IIL
IOH
VPP – 1100
Note: VTT = VPP-2.0V
Table 8. DC Characteristics—TTL I/O
(Specifications apply over recommended operating ranges)
Parameter
Input HIGH voltage
Input LOW voltage
Input HIGH current
Input LOW current
Output HIGH voltage
Output LOW voltage
Tristate current
Input capacitance
Output capacitance
ESD breakdown rating
14
Condition
VIH(MAX)
VIL(MIN)
IOH = 50 mA
IOL = –20 mA
(Design objective)
For additional information and latest specifications, see our website: www.triquint.com
Unit
V
V
uA
uA
V
V
uA
pF
pF
TQ8105/TQ8106
PRELIMINARY DATA SHEET
Table 9. AC Characteristics
Symbol
TC(RXCK)
TC(REFCKE)
Nominal
—
—
—
—
—
—
—
T(OOFH)
Minimum
1.6
1.6
1.6
12.8
12.8
12.8
40
TBD
—
40
40
40
40
40
40
—
—
—
240
20
51.44
Unit
ns
ns
ns
ns
ns
ns
%
—
Maximum
—
—
—
—
—
—
60
TBD
—
60
60
60
60
60
60
500
320
3
—
—
—
T(DSYNC)
—
25.72
—
ns
T(DXSYNCPW)
TP(DXD)
11.0
0.5
—
—
1.0
ns
ns
TS(MXD)
TH(MXD)
TP(TXD)
600
600
200
—
—
—
—
—
400
ps
ps
ps
TC(TXCK)
TC(REFCKT)
TC(TXBC)
TC(RXBC)
TC(REF)
TSK(TXBC)
TC(SONETCK)
TDC(RXBC)
TDC(TXBC)
TDC(TXCK)
TDC(SONETCK)
TDC(SDHCK)
TDC(RXCK)
TH(R/F)
TH(R/F)
TL(R/F)
TS(RXD)
TH(RXD)
Notes: 1. At 0.8V/2.0V levels
2. With PH(1:0) set to 00, 18pF total loading
3. TTL outputs test load (VCC = +5V):
Vcc
330Ω
220Ω
19.29
50
50
50
50
50
50
—
—
—
—
—
TELECOM
PRODUCTS
Parameter
RXCK clock period
REFCKE clock period
TXCK clock period
REFCKT clock period
TXBC clock period
RXBC clock period
REFCKT/REFCKE clock duty cycle
REFCKT to TXBC skew2,3,5
SONETCK clock period
RXBC clock duty cycle3,5
TXBC clock duty cycle3,5
TXCK clock duty cycle6
SONETCK clock duty cycle3,5
SDHCK clock duty cycle3,5
RXCK clock duty cycle6
High-speed rise/fall time4 (> 79 MHz), Data
High-speed rise/fall time4 (>79 MHz), Clock
Low-speed rise/fall time1,3,5 (< 79 MHz)
RXD setup time to RXCK6 (see Figure 6)
RXD hold time to RXCK6 (see Figure 6)
OOF rising edge before A1 changes to A27
(see Figure 8)
DXSYNC rising edge from parallel data output
change from A1 to A27
DXSYNC pulse width3,5,7 (see Figure 8)
RXBC falling edge to valid parallel data output3
(see Figure 7)
MXD(0:7) setup time to TXBC2,3,5 (see Figure 6)
MXD(0:7) hold time to TXBC2,3,5 (see Figure 6)
TXCK falling edge to TXD6 (see Figure 7)
PRODUCTS
(Specifications apply over recommended operating ranges)
ns
%
%
%
%
%
ps
ps
ns
ps
ps
ns
4. 20%/80% levels
5. At 1.4V logic threshold level
6. Differential measurement
7. OC12 mode
18pF
For additional information and latest specifications, see our website: www.triquint.com
15
TQ8105/TQ8106
PRELIMINARY DATA SHEET
Figure 6. Input Timing
RXCKP
TS(RXD)
TH(RXD)
TS(MXD)
TH(MXD)
RXD
TXBC
MXD(7:0)
Figure 7. Output Timing
TXCK
TP(TXD)
TXD
RXBC
TP(DXD)
DXD(7:0)
TP(DXSYNC)
DXSYNC
16
For additional information and latest specifications, see our website: www.triquint.com
TQ8105/TQ8106
PRELIMINARY DATA SHEET
PRODUCTS
Figure 8. Demultiplexer Timing
A1
#1
RXD
A1
#2
A1
#n
A2
#1
A2
#2
TELECOM
PRODUCTS
RXCK
A2
#3
OOF
T(OOFH)
DXSYNC
T(DXSYNCPW)
RXBC
RXBC Resync
A1
#n-2
DXD(7:0)
A1
#n-1
A1
#n
A2
#1
A2
#2
A2
#3
Maximum ambient air temperature (˚C)
Figure 9. Required Airflow for Operation without Heatsink
100
TQ8105
90
TQ8106
80
70
60
50
40
30
0
100
200
300
400
500
600
Required airflow (LFPM)
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17
TQ8105/TQ8106
PRELIMINARY DATA SHEET
Figure 10. Mechanical Package (100 pins, 14 x 14 mm)
Package
Dimension
A
A1
A2
D
D1
E
E1
L
b
e
N
Package “P” 1
Value2
2.35
0.25 max
2.00
17.20 ±0.25
14.00
17.20 ±0.25
14.00
0.88 +0.15/–0.10
0.22
0.50
100 pins
D
Package “S”
Value2
1.7 max
0.10
1.40
16.00 ±0.4
14.00
16.00 ±0.4
14.00
0.50 ±0.20
0.18
0.50
100 pins
D
Exposed Heatsink
6.86 ± .50 dia.
1
Heatsink Intrusion
.0127 max.
N
1
E
B
A
Notes: 1. Not recommended for new designs.
2. All dimensions in millimeters (mm).
D
A2
A
e
A1
Standoff
A
.25
A1
Seating
Plane
L
18
C
b
.17 max.
ddd M C A-B S D S
Lead Coplanarity
ccc
For additional information and latest specifications, see our website: www.triquint.com
C
1
E
TQ8105/TQ8106
PRELIMINARY DATA SHEET
SONET/SDH
SONET/SDH
SONET/SDH
SONET/SDH
Transceiver, PECL/ECL I/O
Transceiver w/CDR, PECL/ECL I/O
Transceiver, PECL I/O
Transceiver w/CDR, PECL I/O
TELECOM
PRODUCTS
TQ8105P
TQ8106P
TQ8105S
TQ8106S
PRODUCTS
Ordering Information
Reference Designs
The following products are available for 14-day loan to qualified customers:
ATM SONET/SDH Line Interface Module (SLIM)
Supports OC12c/STM-4 (622.08 Mbps) and OC-3c/STM-1 (155.52 Mbps)
SLIM Documentation Package
• Functional Partition Drawing Set, including
block, state machine, and timing diagrams
• Schematics
• Programmable Logic Listings
• User’s Manual / Product Specification
• PCB Artwork (all layers)
• Component Placement Drawing
Additional Information
For latest specifications, additional product information,
worldwide sales and distribution locations, and information about TriQuint:
Web: www.triquint.com
Email: [email protected]
Tel: (503) 615-9000
Fax: (503) 615-8900
For technical questions and additional information on specific applications:
Email: [email protected]
The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or
omissions. TriQuint assumes no responsibility for the use of this information, and all such information
shall be entirely at the user's own risk. Prices and specifications are subject to change without notice.
No patent rights or licenses to any of the circuits described herein are implied or granted to any third party.
TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems.
Copyright © 1998 TriQuint Semiconductor, Inc. All rights reserved.
Revision 0.3.A
July 1998
For additional information and latest specifications, see our website: www.triquint.com
19