DS1222 BankSwitch Chip www.dalsemi.com FEATURES Provides bank switching for 16 banks of memory Bank switching is software-controlled by a pattern recognition sequence on four address inputs Automatically sets all 16 banks off on power-up Bank switching logic allows only one bank on at a time Custom recognition patterns are available to prevent unauthorized access Full ±10% operating range Low-power CMOS circuitry Can be used to expand the address range of microprocessors and decoders Optional 16-pin SOIC surface mount package PIN ASSIGNMENT CEI 1 14 VCC PFI 2 13 CEO AW 3 12 BS1 AX 4 11 BS2 AY 5 10 BS3 AZ 6 9 BS4 GND 7 8 NC DS1222 14-Pin DIP (300-mil) See Mech. Drawings Section CEI NC PFI AW AX AY AZ GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC CEO NC BS1 BS2 BS3 NC BS4 DS1222S 16-Pin SOIC (300-mil) See Mech. Drawings Section PIN DESCRIPTION AW-AZ CEI CEO NC BS1,BS2, BS3,BS4 PFI VCC GND - Address Inputs - Chip Enable Input - Chip Enable Output - No Connection - Bank Select Outputs - Bank Select Outputs - Power Fail Input - +5 Volts - Ground DESCRIPTION The DS1222 BankSwitch Chip is a CMOS circuit designed to select one of 16 memory banks under software control. Memory bank switching allows for an increase in memory capacity without additional address lines. Continuous blocks of memory are enabled by selecting proper memory bank through a pattern recognition sequence on four address inputs. Custom patterns from Dallas Semiconductor can provide security through uniqueness and prevent unauthorized access. By combining the DS1222 with the DS1212 Nonvolatile Controller x16 Chip, up to 16 banks of static RAMs can be selected. 1 of 4 111899 DS1222 OPERATION - BANK SWITCHING Initially, on power-up all four bank select outputs are low and the chip enable output ( CEO ) is held high. (Note: the power fail input [ PFI ] must be low prior to power-up to assure proper initialization.) Bank switching is achieved by matching a predefined pattern stored within the DS1222 with a 16-bit sequence received on four address inputs. Prior to entering the 16-bit pattern, which sets the bank switch, a read cycle of 1111 on address inputs AW through AZ should be executed to guarantee that pattern entry starts with bit 0. Each set of address inputs is clocked into the DS1222 when CEI is driven low. All 16 inputs must be consecutive read cycles. The first eleven cycles must match the exact bit pattern as shown in Table 1. The last five cycles must match the exact bit pattern as shown for addresses AX, AY, and AZ. However, address line AW defines the bank number to be enabled as per Table 2. Switching to a selected bank of memory occurs on the rising edge of CEI when the last set of bits is input and a match has been established. After bank selection CEO always follows CEI with a maximum propagation delay of 15 ns. The bank selected is determined by the levels set on Bank Select 1 through Bank Select 4 as per Table 2. These levels are held constant for all memory cycles until a new memory bank is selected. ADDRESS BIT SEQUENCE Table 1 BIT SEQUENCE ADDRESS INPUTS AW 0 1 1 0 2 1 3 0 4 0 5 0 6 1 7 1 8 0 9 1 10 0 11 x 12 x 13 x 14 x 15 x AX 0 1 0 1 1 1 0 0 1 0 1 0 0 0 1 1 AY 1 0 1 0 0 0 1 1 0 1 0 1 1 1 0 0 AZ 0 1 0 1 1 1 0 0 1 0 1 0 0 0 1 1 X See Table 2 BANK SELECT CONTROL Table 2 Bank Selected AW Bit Sequence Outputs *Banks Off 11 0 12 X 13 X 14 X 15 X Bank 0 1 0 0 0 0 Low Low Low Low Bank 1 1 0 0 0 1 High Low Low Low Bank 2 1 0 0 1 0 Low High Low Low Bank 3 1 0 0 1 1 High High Low Low Bank 4 1 0 1 0 0 Low Low High Low Bank 5 1 0 1 0 1 High Low High Low Bank 6 1 0 1 1 0 Low High High Low Bank 7 1 0 1 1 1 High High High Low Bank 8 1 1 0 0 0 Low Low Low High Bank 9 1 1 0 0 1 High Low Low High Bank 10 1 1 0 1 0 Low High Low High Bank 11 1 1 0 1 1 High High Low High Bank 12 1 1 1 0 0 Low Low Low High Bank 13 1 1 1 0 1 High Low High High Bank 14 1 1 1 1 0 Low High High High Bank 15 1 1 1 1 1 High High High High * CEO =VIH independent of CEI 2 of 4 BS1 Low BS2 Low BS3 Low BS4 Low DS1222 ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin Relative to Ground Operating Temperature Storage Temperature ∗ -0.3V to +7.0V 0°C to 70°C -55°C to +125°C This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS PARAMETER Power Supply Voltage Logic 1 Logic 0 SYMBOL VCC VIH VIL MIN 4.5 2.2 -0.3 DC ELECTRICAL CHARACTERISTICS PARAMETER Input Leakage Current I/O Leakage Current Output Current @ 2.4V Output Current @ 0.4V Operating Current SYMBOL IIL ILO IOH IOL ICC MIN -1.0 -1.0 -1.0 (0°C to 70°C) TYP 5.0 MAX 5.5 V CC +0.3 +0.8 TYP MAX +1.0 +1.0 +4.0 15 UNITS µA µA mA mA mA NOTES 2 2 (TA = 25°C) SYMBOL CIN CI/O MIN AC ELECTRICAL CHARACTERISTICS PARAMETER Address Setup Address Hold Read Recovery Propagation Delay Power Fail Input to First CEI Chip Enable Low NOTES 1 1 1 (0°C to 70°C; VCC = 5V ±10%) CAPACITANCE PARAMETER Input Capacitance Input/Output Capacitance UNITS V V V SYMBOL tAS tAH tRR tPD tPF tCW MIN 5 50 40 TYP 5 5 MAX 10 10 NOTES: 1. All voltages are referenced to ground. 2. Measured with a load as shown in Figure 1. 3 of 4 NOTES (0°C to 70°C; VCC = 5V ±10%) TYP MAX 15 50 110 UNITS pF pF UNITS ns ns ns ns ns ns NOTES 2 DS1222 OUTPUT LOAD Figure 1 TIMING DIAGRAM-ACCESS TO BANK SWITCH 4 of 4