SN74LVC1T45 www.ti.com ..................................................................................................................................................... SCES515I – DECEMBER 2003 – REVISED MAY 2009 SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS FEATURES 1 • Available in the Texas Instruments NanoFree™ Package • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V Power-Supply Range • VCC Isolation Feature – If Either VCC Input Is at GND, Both Ports Are in the High-Impedance State • DIR Input Circuit Referenced to VCCA • Low Power Consumption, 4-µA Max ICC • ±24-mA Output Drive at 3.3 V • Ioff Supports Partial-Power-Down Mode Operation • 2 DBV PACKAGE (TOP VIEW) VCCA 1 6 • • Max Data Rates – 420 Mbps (3.3-V to 5-V Translation) – 210 Mbps (Translate to 3.3 V) – 140 Mbps (Translate to 2.5 V) – 75 Mbps (Translate to 1.8 V) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DCK PACKAGE (TOP VIEW) VCCB VCCA GND GND 2 5 DIR A 3 4 B A 1 2 3 6 5 4 DRL PACKAGE (TOP VIEW) VCCB DIR 1 VCCA 6 VCCB GND 2 5 DIR A 3 4 B YZP PACKAGE (BOTTOM VIEW) A GND VCCA C1 3 4 C2 B1 2 5 B2 A1 1 6 A2 B DIR VCCB B See mechanical drawings for dimensions. DESCRIPTION/ORDERING INFORMATION This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes. The SN74LVC1T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ. The SN74LVC1T45 is designed so that the DIR input is powered by VCCA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature ensures that if either VCC input is at GND, then both ports are in the high-impedance state. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoFree is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2009, Texas Instruments Incorporated SN74LVC1T45 SCES515I – DECEMBER 2003 – REVISED MAY 2009 ..................................................................................................................................................... www.ti.com NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. ORDERING INFORMATION (1) PACKAGE (2) TA ORDERABLE PART NUMBER NanoFree™ – WCSP (DSBGA) 0.23-mm Large Bump – YZP (Pb-free) SOT (SOT-23) – DBV –40°C to 85°C SOT (SC-70) – DCK SOT (SOT-533) – DRL (1) (2) (3) Reel of 3000 SN74LVC1T45YZPR Reel of 3000 SN74LVC1T45DBVR Reel of 250 SN74LVC1T45DBVT Reel of 3000 SN74LVC1T45DCKR Reel of 250 SN74LVC1T45DCKT Reel of 4000 SN74LVC1T45DRLR TOP-SIDE MARKING (3) _ _ _TA_ CT1_ TA_ For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. DBV/DCK/DRL: The actual top-side marking has one additional character that designates the wafer fab/assembly site. YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). FUNCTION TABLE (1) (1) INPUT DIR OPERATION L B data to A bus H A data to B bus Input circuits of the data I/Os always are active. LOGIC DIAGRAM (POSITIVE LOGIC) DIR A 5 3 4 VCCA 2 B VCCB Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1T45 SN74LVC1T45 www.ti.com ..................................................................................................................................................... SCES515I – DECEMBER 2003 – REVISED MAY 2009 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V A port –0.5 VCCA + 0.5 B port –0.5 VCCB + 0.5 VCCA VCCB UNIT VO Voltage range applied to any output in the high or low state (2) (3) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through VCC or GND θJA Package thermal impedance (4) Tstg Storage temperature range DBV package 165 DCK package 259 DRL package 142 YZP package (1) (2) (3) (4) V °C/W 123 –65 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1T45 3 SN74LVC1T45 SCES515I – DECEMBER 2003 – REVISED MAY 2009 ..................................................................................................................................................... www.ti.com Recommended Operating Conditions (1) (2) (3) VCCI VCCA VCCB VCCO Supply voltage 1.65 V to 1.95 V High-level input voltage VIH MAX 1.65 5.5 1.65 5.5 1.7 3 V to 3.6 V VCCI × 0.7 1.65 V to 1.95 V VIL Data inputs (4) VCCI × 0.35 2.3 V to 2.7 V 0.7 3 V to 3.6 V 0.8 4.5 V to 5.5 V High-level input voltage DIR (referenced to VCCA) (5) VCCA × 0.65 2.3 V to 2.7 V 1.7 3 V to 3.6 V V 2 4.5 V to 5.5 V VCCA × 0.7 1.65 V to 1.95 V DIR (referenced to VCCA) (5) V VCCI × 0.3 1.65 V to 1.95 V VIH V V 2 4.5 V to 5.5 V Low-level input voltage UNIT VCCI × 0.65 2.3 V to 2.7 V Data inputs (4) MIN VCCA × 0.35 2.3 V to 2.7 V 0.7 3 V to 3.6 V 0.8 VIL Low-level input voltage VI Input voltage 0 5.5 V VO Output voltage 0 VCCO V 4.5 V to 5.5 V VCCA × 0.3 1.65 V to 1.95 V IOH High-level output current IOL Low-level output current Δt/Δv Input transition rise or fall rate Data inputs Control inputs TA (1) (2) (3) (4) (5) 4 V –4 2.3 V to 2.7 V –8 3 V to 3.6 V –24 4.5 V to 5.5 V –32 1.65 V to 1.95 V 4 2.3 V to 2.7 V 8 3 V to 3.6 V 24 4.5 V to 5.5 V 32 1.65 V to 1.95 V 20 2.3 V to 2.7 V 20 3 V to 3.6 V 10 4.5 V to 5.5 V 5 1.65 V to 5.5 V 5 Operating free-air temperature –40 85 mA mA ns/V °C VCCI is the VCC associated with the input port. VCCO is the VCC associated with the output port. All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. For VCCI values not specified in the data sheet, VIH min = VCCI × 0.7 V, VIL max = VCCI × 0.3 V. For VCCI values not specified in the data sheet, VIH min = VCCA × 0.7 V, VIL max = VCCA × 0.3 V. Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1T45 SN74LVC1T45 www.ti.com ..................................................................................................................................................... SCES515I – DECEMBER 2003 – REVISED MAY 2009 Electrical Characteristics (1) (2) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 µA IOH = –8 mA 1.65 V to 4.5 V 1.65 V to 4.5 V 1.65 V 1.65 V 1.2 2.3 V 2.3 V 1.9 VI = VIH DIR A port Ioff B port A or B port IOZ ICCA A port ΔICCA MAX V 3V 2.4 3.8 IOL = 100 µA 1.65 V to 4.5 V 1.65 V to 4.5 V 0.1 1.65 V 1.65 V 0.45 VI = VIL 2.3 V 2.3 V 0.3 IOL = 24 mA 3V 3V 0.55 IOL = 32 mA 4.5 V 4.5 V 0.55 1.65 V to 5.5 V 1.65 V to 5.5 V ±1 ±2 0V 0 to 5.5 V ±1 ±2 0 to 5.5 V 0V ±1 ±2 1.65 V to 5.5 V 1.65 V to 5.5 V ±1 ±2 1.65 V to 5.5 V 1.65 V to 5.5 V 3 5.5 V 0V 2 -2 VI = VCCA or GND VI or VO = 0 to 5.5 V VO = VCCO or GND VI = VCCI or GND, IO = 0 0V 5.5 V 1.65 V to 5.5 V 1.65 V to 5.5 V 3 5.5 V 0V -2 0V 5.5 V 2 1.65 V to 5.5 V 1.65 V to 5.5 V 4 3 V to 5.5 V 3 V to 5.5 V A port at VCCA – 0.6 V, DIR at VCCA, B port = open DIR at VCCA – 0.6 V, B port = open, A port at VCCA or GND ΔICCB B port B port at VCCB – 0.6 V, DIR at GND, A port = open Ci DIR Cio A or B port UNIT VCCO – 0.1 4.5 V DIR (1) (2) MIN 3V VI = VCCI or GND, IO = 0 ICCA + ICCB (see Table 1) MAX 4.5 V VI = VCCI or GND, IO = 0 ICCB TYP IOH = –32 mA IOL = 8 mA II MIN IOH = –24 mA IOL = 4 mA VOL –40°C to 85°C VCCB IOH = –4 mA VOH TA = 25°C VCCA V µA µA µA µA µA µA 50 µA 50 50 µA 3 V to 5.5 V 3 V to 5.5 V VI = VCCA or GND 3.3 V 3.3 V 2.5 pF VO = VCCA/B or GND 3.3 V 3.3 V 6 pF VCCO is the VCC associated with the output port. VCCI is the VCC associated with the input port. Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1T45 5 SN74LVC1T45 SCES515I – DECEMBER 2003 – REVISED MAY 2009 ..................................................................................................................................................... www.ti.com Switching Characteristics over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (see Figure 1) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH (1) tPZL (1) tPZH (1) tPZL (1) (1) FROM (INPUT) TO (OUTPUT) A B B A DIR A DIR B DIR A DIR B VCCB = 1.8 V ±0.15 V VCCB = 2.5 V ±0.2 V VCCB = 3.3 V ±0.3 V VCCB = 5 V ±0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX 3 17.7 2.2 10.3 1.7 8.3 1.4 7.2 2.8 14.3 2.2 8.5 1.8 7.1 1.7 7 3 17.7 2.3 16 2.1 15.5 1.9 15.1 2.8 14.3 2.1 12.9 2 12.6 1.8 12.2 5.2 19.4 4.8 18.5 4.7 18.4 5.1 17.1 2.3 10.5 2.1 10.5 2.4 10.7 3.1 10.9 7.4 21.9 4.9 11.5 4.6 10.3 2.8 8.2 4.2 16 3.7 9.2 3.3 8.4 2.4 6.4 33.7 25.2 23.9 21.5 36.2 24.4 22.9 20.4 28.2 20.8 19 18.1 33.7 27 25.5 24.1 ns ns ns ns ns ns The enable time is a calculated value, derived using the formula shown in the enable times section. Switching Characteristics over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (see Figure 1) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH (1) tPZL (1) tPZH (1) tPZL (1) 6 (1) FROM (INPUT) TO (OUTPUT) A B B A DIR A DIR B DIR A DIR B VCCB = 1.8 V ±0.15 V VCCB = 2.5 V ±0.2 V VCCB = 3.3 V ±0.3 V VCCB = 5 V ±0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX 2.3 16 1.5 8.5 1.3 6.4 1.1 5.1 2.1 12.9 1.4 7.5 1.3 5.4 0.9 4.6 2.2 10.3 1.5 8.5 1.4 8 1 7.5 2.2 8.5 1.4 7.5 1.3 7 0.9 6.2 3 8.1 3.1 8.1 2.8 8.1 3.2 8.1 1.3 5.9 1.3 5.9 1.3 5.9 1 5.8 6.5 23.7 4.1 11.4 3.9 10.2 2.4 7.1 3.9 18.9 3.2 9.6 2.8 8.4 1.8 5.3 29.2 18.1 16.4 12.8 32.2 18.9 17.2 13.3 21.9 14.4 12.3 10.9 21 15.6 13.5 12.7 ns ns ns ns ns ns The enable time is a calculated value, derived using the formula shown in the enable times section. Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1T45 SN74LVC1T45 www.ti.com ..................................................................................................................................................... SCES515I – DECEMBER 2003 – REVISED MAY 2009 Switching Characteristics over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) A B B A DIR A DIR B DIR A DIR B tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH (1) tPZL (1) tPZH (1) tPZL (1) (1) VCCB = 1.8 V ±0.15 V VCCB = 2.5 V ±0.2 V VCCB = 3.3 V ±0.3 V VCCB = 5 V ±0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX 2.1 15.5 1.4 8 0.7 5.8 0.7 4.4 2 12.6 1.3 7 0.8 5 0.7 4 1.7 8.3 1.3 6.4 0.7 5.8 0.6 5.4 1.8 7.1 1.3 5.4 0.8 5 0.7 4.5 2.9 7.3 3 7.3 2.8 7.3 3.4 7.3 1.8 5.6 1.6 5.6 2.2 5.7 2.2 5.7 5.4 20.5 3.9 10.1 2.9 8.8 2.4 6.8 3.3 14.5 2.9 7.8 2.4 7.1 1.7 4.9 22.8 14.2 12.9 10.3 27.6 15.5 13.8 11.3 21.1 13.6 11.5 10.1 19.9 14.3 12.3 11.3 ns ns ns ns ns ns The enable time is a calculated value, derived using the formula shown in the enable times section. Switching Characteristics over recommended operating free-air temperature range, VCCA = 5 V ±0.5 V (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) A B B A DIR A DIR B DIR A DIR B tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH (1) tPZL (1) tPZH (1) tPZL (1) (1) VCCB = 1.8 V ±0.15 V VCCB = 2.5 V ±0.2 V VCCB = 3.3 V ±0.3 V VCCB = 5 V ±0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX 1.9 15.1 1 7.5 0.6 5.4 0.5 3.9 1.8 12.2 0.9 6.2 0.7 4.5 0.5 3.5 1.4 7.2 1 5.1 0.7 4.4 0.5 3.9 1.7 7 0.9 4.6 0.7 4 0.5 3.5 2.1 5.4 2.2 5.4 2.2 5.5 2.2 5.4 0.9 3.8 1 3.8 1 3.7 0.9 3.7 4.8 20.2 2.5 9.8 1 8.5 2.5 6.5 4.2 14.8 2.5 7.4 2.5 7 1.6 4.5 22 12.5 11.4 8.4 27.2 14.4 12.5 10 18.9 11.3 9.1 7.6 17.6 11.6 10 8.6 ns ns ns ns ns ns The enable time is a calculated value, derived using the formula shown in the enable times section. Operating Characteristics TA = 25°C PARAMETER CpdA (1) CpdB (1) (1) A-port input, B-port output B-port input, A-port output A-port input, B-port output B-port input, A-port output TEST CONDITIONS CL = 0 pF, f = 10 MHz, tr = tf = 1 ns CL = 0 pF, f = 10 MHz, tr = tf = 1 ns VCCA = VCCB = 1.8 V VCCA = VCCB = 2.5 V VCCA = VCCB = 3.3 V VCCA = VCCB = 5 V TYP TYP TYP TYP 3 4 4 4 18 19 20 21 18 19 20 21 3 4 4 4 UNIT pF pF Power dissipation capacitance per transceiver Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1T45 7 SN74LVC1T45 SCES515I – DECEMBER 2003 – REVISED MAY 2009 ..................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE TA = 25°C, VCCA = 1.8 V 10 10 9 9 8 VCCB = 1.8 V 8 7 7 6 6 t PLH− ns t PHL − ns VCCB = 1.8 V VCCB = 2.5 V 5 4 VCCB = 2.5 V 5 VCCB = 3.3 V 4 VCCB = 5 V VCCB = 3.3 V 3 3 VCCB = 5 V 2 2 1 1 0 0 5 10 20 15 25 30 0 35 0 10 5 CL − pF 15 20 25 30 35 25 30 35 CL − pF TYPICAL PROPAGATION DELAY (B to A) vs LOAD CAPACITANCE TA = 25°C, VCCA = 1.8 V 10 10 9 9 VCCB = 1.8 V 8 VCCB = 2.5 V 8 7 7 6 6 t PLH − ns t PHL − ns VCCB = 1.8 V 5 VCCB = 2.5 V 4 VCCB = 3.3 V VCCB = 3.3 V VCCB = 5 V 5 4 VCCB = 5 V 3 3 2 2 1 1 0 0 5 10 15 20 25 30 35 0 0 5 CL − pF 8 10 15 20 CL − pF Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1T45 SN74LVC1T45 www.ti.com ..................................................................................................................................................... SCES515I – DECEMBER 2003 – REVISED MAY 2009 TYPICAL CHARACTERISTICS (continued) TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE TA = 25°C, VCCA = 2.5 V 10 10 9 9 8 8 7 VCCB = 1.8 V 6 t PLH − ns t PHL − ns 7 VCCB = 1.8 V 5 6 5 VCCB = 2.5 V 4 4 VCCB = 3.3 V 3 3 VCCB = 5 V VCCB = 2.5 V VCCB = 3.3 V 2 2 VCCB = 5 V 1 1 0 0 0 10 5 15 20 25 30 0 35 10 5 15 CL − pF 20 25 30 35 CL − pF 10 10 9 9 8 8 7 7 t PLH − ns t PHL − ns TYPICAL PROPAGATION DELAY (B to A) vs LOAD CAPACITANCE TA = 25°C, VCCA = 2.5 V 6 VCCB = 1.8 V 5 6 5 4 4 3 3 VCCB = 2.5 V VCCB = 3.3 V VCCB = 5 V 2 VCCB = 2.5 V VCCB = 3.3 V VCCB = 5 V 2 1 1 0 VCCB = 1.8 V 0 0 5 10 15 20 CL − pF 25 30 35 0 5 10 15 20 25 30 35 CL − pF Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1T45 9 SN74LVC1T45 SCES515I – DECEMBER 2003 – REVISED MAY 2009 ..................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE TA = 25°C, VCCA = 3.3 V 10 10 9 9 8 8 VCCB = 1.8 V 7 7 VCCB = 1.8 V 6 t PLH − ns t PHL − ns 6 5 4 VCCB = 2.5 V 5 VCCB = 2.5 V 4 VCCB = 3.3 V 3 3 2 2 VCCB = 5 V VCCB = 3.3 V 0 1 VCCB = 5 V 1 0 10 5 15 20 25 30 0 0 35 5 10 15 20 25 30 35 25 30 35 CL − pF CL − pF 10 10 9 9 8 8 7 7 6 6 t PLH − ns t PHL − ns TYPICAL PROPAGATION DELAY (B to A) vs LOAD CAPACITANCE TA = 25°C, VCCA = 3.3 V 5 VCCB = 1.8 V 4 5 VCCB = 1.8 V 4 VCCB = 2.5 V VCCB = 2.5 V 3 3 2 VCCB = 5 V VCCB = 5 V 1 VCCB = 3.3 V 2 VCCB = 3.3 V 1 0 0 0 5 10 15 20 25 30 35 0 5 15 20 CL − pF CL − pF 10 10 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1T45 SN74LVC1T45 www.ti.com ..................................................................................................................................................... SCES515I – DECEMBER 2003 – REVISED MAY 2009 TYPICAL CHARACTERISTICS (continued) TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE TA = 25°C, VCCA = 5 V 10 10 9 9 8 8 7 7 VCCB = 1.8 V VCCB = 1.8 V t PLH − ns t PHL − ns 6 5 4 VCCB = 2.5 V 3 6 5 VCCB = 2.5 V 4 VCCB = 3.3 V 3 2 2 VCCB = 5 V VCCB = 3.3 V 1 VCCB = 5 V 1 0 0 0 5 10 15 20 25 30 0 35 5 10 15 20 25 30 35 25 30 35 CL − pF CL − pF 10 10 9 9 8 8 7 7 6 6 t PLH − ns t PHL− ns TYPICAL PROPAGATION DELAY (B to A) vs LOAD CAPACITANCE TA = 25°C, VCCA = 5 V 5 4 VCCB = 1.8 V 3 VCCB = 2.5 V 5 VCCB = 1.8 V 4 VCCB = 2.5 V 3 2 2 VCCB = 3.3 V VCCB = 5 V VCCB = 3.3 V 1 0 1 VCCB = 5 V 0 5 0 10 15 20 25 30 35 0 5 CL − pF 10 15 20 CL − pF Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1T45 11 SN74LVC1T45 SCES515I – DECEMBER 2003 – REVISED MAY 2009 ..................................................................................................................................................... www.ti.com PARAMETER MEASUREMENT INFORMATION 2 × VCCO S1 RL From Output Under Test Open GND CL (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCCO GND RL tw LOAD CIRCUIT VCCI VCCI/2 Input VCCO CL RL VTP 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V 15 pF 15 pF 15 pF 15 pF 2 kΩ 2 kΩ 2 kΩ 2 kΩ 0.15 V 0.15 V 0.3 V 0.3 V VCCI/2 0V VOLTAGE WAVEFORMS PULSE DURATION VCCA Output Control (low-level enabling) VCCA/2 VCCA/2 0V tPZL VCCI Input VCCI/2 VCCI/2 0V tPLH Output tPHL VOH VCCO/2 VOL VCCO/2 tPLZ VCCO Output Waveform 1 S1 at 2 × VCCO (see Note B) VCCO/2 VOL + VTP VOL tPZH Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPHZ VCCO/2 VOH − VTP VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR v10 MHz, ZO = 50 Ω, dv/dt ≥ 1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. VCCI is the VCC associated with the input port. I. VCCO is the VCC associated with the output port. J. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 12 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1T45 SN74LVC1T45 www.ti.com ..................................................................................................................................................... SCES515I – DECEMBER 2003 – REVISED MAY 2009 APPLICATION INFORMATION Figure 2 shows an example of the SN74LVC1T45 being used in a unidirectional logic level-shifting application. VCC1 VCC1 VCC2 1 6 2 5 3 4 SYSTEM-1 VCC2 SYSTEM-2 PIN NAME FUNCTION 1 VCCA VCC1 SYSTEM-1 supply voltage (1.65 V to 5.5 V) DESCRIPTION 2 GND GND Device GND 3 A OUT Output level depends on VCC1 voltage. 4 B IN 5 DIR DIR GND (low level) determines B-port to A-port direction. 6 VCCB VCC2 SYSTEM-2 supply voltage (1.65 V to 5.5 V) Input threshold value depends on VCC2 voltage. Figure 2. Unidirectional Logic Level-Shifting Application Figure 3 shows the SN74LVC1T45 being used in a bidirectional logic level-shifting application. Since the SN74LVC1T45 does not have an output-enable (OE) pin, the system designer should take precautions to avoid bus contention between SYSTEM-1 and SYSTEM-2 when changing directions. VCC1 VCC1 VCC2 VCC2 I/O-1 Pullup/Down or Bus Hold(1) Pullup/Down or Bus Hold(1) 1 6 2 5 3 4 I/O-2 DIR CTRL SYSTEM-1 SYSTEM-2 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1T45 13 SN74LVC1T45 SCES515I – DECEMBER 2003 – REVISED MAY 2009 ..................................................................................................................................................... www.ti.com The following table shows data transmission from SYSTEM-1 to SYSTEM-2 and then from SYSTEM-2 to SYSTEM-1. STATE DIR CTRL I/O-1 I/O-2 1 H Out In 2 H Hi-Z Hi-Z SYSTEM-2 is getting ready to send data to SYSTEM-1. I/O-1 and I/O-2 are disabled. The bus-line state depends on pullup or pulldown. (1) 3 L Hi-Z Hi-Z DIR bit is flipped. I/O-1 and I/O-2 still are disabled. The bus-line state depends on pullup or pulldown. (1) 4 L Out In (1) DESCRIPTION SYSTEM-1 data to SYSTEM-2 SYSTEM-2 data to SYSTEM-1 SYSTEM-1 and SYSTEM-2 must use the same conditions, i.e., both pullup or both pulldown. Figure 3. Bidirectional Logic Level-Shifting Application Enable Times Calculate the enable times for the SN74LVC1T45 using the following formulas: • tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A) • tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A) • tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B) • tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B) In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is switched until an output is expected. For example, if the SN74LVC1T45 initially is transmitting from A to B, then the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified propagation delay. 14 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): SN74LVC1T45 PACKAGE OPTION ADDENDUM www.ti.com 1-May-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LVC1T45DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1T45DBVRE4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1T45DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1T45DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1T45DBVTE4 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1T45DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1T45DCKR ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1T45DCKRE4 ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1T45DCKRG4 ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1T45DCKT ACTIVE SC70 DCK 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1T45DCKTE4 ACTIVE SC70 DCK 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1T45DCKTG4 ACTIVE SC70 DCK 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1T45DRLR ACTIVE SOT DRL 6 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1T45DRLRG4 ACTIVE SOT DRL 6 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1T45YZPR ACTIVE DSBGA YZP 6 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 1-May-2009 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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OTHER QUALIFIED VERSIONS OF SN74LVC1T45 : • Enhanced Product: SN74LVC1T45-EP NOTE: Qualified Version Definitions: • Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Oct-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ SN74LVC1T45DBVR SOT-23 3000 180.0 9.2 DBV 6 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.23 3.17 1.37 4.0 8.0 Q3 SN74LVC1T45DBVT SOT-23 DBV 6 250 180.0 9.2 3.23 3.17 1.37 4.0 8.0 Q3 SN74LVC1T45DCKR SC70 DCK 6 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 SN74LVC1T45DCKT SC70 DCK 6 250 180.0 8.4 2.24 2.34 1.22 4.0 8.0 Q3 SN74LVC1T45DRLR SOT DRL 6 4000 180.0 9.2 1.78 1.78 0.69 4.0 8.0 Q3 SN74LVC1T45YZPR DSBGA YZP 6 3000 178.0 8.4 1.02 1.52 0.63 4.0 8.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Oct-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVC1T45DBVR SOT-23 DBV 6 3000 202.0 201.0 28.0 SN74LVC1T45DBVT SOT-23 DBV 6 250 202.0 201.0 28.0 SN74LVC1T45DCKR SC70 DCK 6 3000 180.0 180.0 18.0 SN74LVC1T45DCKT SC70 DCK 6 250 202.0 201.0 28.0 SN74LVC1T45DRLR SOT DRL 6 4000 202.0 201.0 28.0 SN74LVC1T45YZPR DSBGA YZP 6 3000 220.0 220.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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