Product Folder Sample & Buy Technical Documents Support & Community Tools & Software SN74AVC1T45 SCES530H – DECEMBER 2003 – REVISED DECEMBER 2014 SN74AVC1T45 Single-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation and 3-State Outputs 1 Features 2 Applications • • • • • 1 • • • • • • • • • Available in the Texas Instruments NanoFree™ Package Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.2-V to 3.6-V Power-Supply Range VCC Isolation Feature - If Either VCC Input Is At GND, Both Ports Are In The High-Impedance State DIR Input Circuit Referenced to VCCA ±12-mA Output Drive at 3.3 V I/Os Are 4.6-V Tolerant Ioff Supports Partial-Power-Down Mode Operation Typical Max Data Rates – 500 Mbps (1.8-V to 3.3-V Translation) – 320 Mbps (<1.8-V to 3.3-V Translation) – 320 Mbps (Translate to 2.5 V or 1.8 V) – 280 Mbps (Translate to 1.5 V) – 240 Mbps (Translate to 1.2 V) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – ±2000-V Human Body Model (A114-A) – 200-V Machine Model (A115-A) – ±1000-V Charged-Device Model (C101) Personal Electronic Industrial Enterprise Telecom 3 Description This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74AVC1T45 is optimized to operate with VCCA/VCCB set at 1.4 V to 3.6 V. It is operational with VCCA/VCCB as low as 1.2 V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage, bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) 2.90 mm × 1.60 mm SN74AVC1T45 SOT (6) 2.00 mm × 1.25 mm 1.60 mm × 1.20 mm DSBGA (6) 1.39 mm × 0.89 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Logic Diagram (Positive Logic) DIR A 5 3 4 VCCA B VCCB 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN74AVC1T45 SCES530H – DECEMBER 2003 – REVISED DECEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Description (continued)......................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 1 1 1 2 3 3 4 Absolute Maximum Ratings ..................................... 4 ESD Ratings.............................................................. 4 Recommended Operating Conditions ...................... 5 Thermal Information .................................................. 5 Electrical Characteristics .......................................... 6 Switching Characteristics: VCCA = 1.2 V ................... 7 Switching Characteristics: VCCA = 1.5 V ± 0.1 V....... 7 Switching Characteristics: VCCA = 1.8 V ± 0.15 V..... 8 Switching Characteristics: VCCA = 2.5 V ± 0.2 V....... 8 Switching Characteristics: VCCA = 3.3 V ± 0.3 V..... 9 Operating Characteristics........................................ 9 Typical Characteristics .......................................... 10 8 9 Parameter Measurement Information ................ 12 Detailed Description ............................................ 13 9.1 9.2 9.3 9.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 13 13 13 13 10 Application and Implementation........................ 14 10.1 Application Information.......................................... 14 10.2 Typical Applications .............................................. 14 11 Power Supply Recommendations ..................... 18 11.1 Power-Up Considerations ..................................... 18 12 Layout................................................................... 18 12.1 Layout Guidelines ................................................. 18 12.2 Layout Example .................................................... 19 13 Device and Documentation Support ................. 20 13.1 Trademarks ........................................................... 20 13.2 Electrostatic Discharge Caution ............................ 20 13.3 Glossary ................................................................ 20 14 Mechanical, Packaging, and Orderable Information ........................................................... 20 4 Revision History Changes from Revision G (January 2008) to Revision H • 2 Page Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated Product Folder Links: SN74AVC1T45 SN74AVC1T45 www.ti.com SCES530H – DECEMBER 2003 – REVISED DECEMBER 2014 5 Description (continued) The SN74AVC1T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the Aport outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ. The SN74AVC1T45 is designed so that the DIR input is powered by VCCA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature ensures that if either VCC input is at GND, then both ports are in the high-impedance state. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. 6 Pin Configuration and Functions See mechanical drawings in Mechanical, Packaging, and Orderable Information for dimensions. Pin Functions PIN NAME NO. I/O DESCRIPTION VCCA 1 P A-port supply voltage. 1.2 V ≤ VCCA ≤ 3.6 V GND 2 G Ground A 3 I/O Input/output A. Referenced to VCCA. B 4 I/O Input/output B. Referenced to VCCB. DIR 5 I Direction control signal VCCB 6 P B-port supply voltage. 1.2 V ≤ VCCB ≤ 3.6 V. Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated Product Folder Links: SN74AVC1T45 3 SN74AVC1T45 SCES530H – DECEMBER 2003 – REVISED DECEMBER 2014 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT –0.5 4.6 V I/O ports (A port) –0.5 4.6 I/O ports (B port) –0.5 4.6 Control inputs –0.5 4.6 A port –0.5 4.6 B port –0.5 4.6 A port –0.5 VCCA + 0.5 B port –0.5 VCCB + 0.5 VCCA, VCCB Supply voltage VI Input voltage VO Voltage applied to any output in the high-impedance or power-off state (2) VO Voltage applied to any output in the high or low state (2) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current –50 50 mA Continuous current through VCCA, VCCB, or GND –100 100 mA Storage temperature –65 150 °C Tstg (1) (2) (3) (2) (3) V V V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current ratings are observed. 7.2 ESD Ratings VALUE V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±1000 Machine model, per A115-A (1) (2) 4 UNIT V 200 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated Product Folder Links: SN74AVC1T45 SN74AVC1T45 www.ti.com SCES530H – DECEMBER 2003 – REVISED DECEMBER 2014 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) (2) (3) VCCI VCCO MIN MAX UNIT VCCA Supply voltage 1.2 3.6 V VCCB Supply voltage 1.2 3.6 V High-level input voltage VIH Low-level input voltage VIL Data inputs Data inputs 1.2 V to 1.95 V VCCI × 0.65 1.95 V to 2.7 V 1.6 2.7 V to 3.6 V 2 V 1.2 V to 1.95 V VCCI × 0.35 1.95 V to 2.7 V 0.7 2.7 V to 3.6 V High-level input voltage VIH Low-level input voltage VIL VI DIR (referenced to VCCA) DIR (referenced to VCCA) Output voltage IOH VCCA × 0.65 1.95 V to 2.7 V 1.6 2.7 V to 3.6 V 2 V 1.2 V to 1.95 V VCCA × 0.35 1.95 V to 2.7 V 0.7 2.7 V to 3.6 V 0.8 0 3.6 Active state 0 VCCO 3-state 0 3.6 High-level output current IOL Low-level output current Δt/Δv Input transition rise or fall rate TA Operating free-air temperature (1) (2) (3) 0.8 1.2 V to 1.95 V Input voltage VO V 1.2 V –3 1.4 V to 1.6 V –6 1.65 V to 1.95 V –8 2.3 V to 2.7 V –9 3 V to 3.6 V –12 1.2 V 3 1.4 V to 1.6 V 6 1.65 V to 1.95 V 8 2.3 V to 2.7 V 9 3 V to 3.6 V 12 –40 V V V mA mA 5 ns/V 85 °C VCCI is the VCC associated with the input port. VCCO is the VCC associated with the output port. All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, SCBA004. 7.4 Thermal Information SN74AVC1T45 THERMAL METRIC (1) DBV DCK DRL YZP UNIT 6 PINS RθJA Junction-to-ambient thermal resistance 24.3 290.7 236.2 130 RθJC(top) Junction-to-case (top) thermal resistance 174.7 97.0 97.6 54 RθJB Junction-to-board thermal resistance 92.4 99.2 71.0 51 ψJT Junction-to-top characterization parameter 61.1 2.1 8.3 1 ψJB Junction-to-board characterization parameter 92.0 98.4 70.8 50 RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A N/A (1) °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated Product Folder Links: SN74AVC1T45 5 SN74AVC1T45 SCES530H – DECEMBER 2003 – REVISED DECEMBER 2014 7.5 Electrical Characteristics (1) www.ti.com (2) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 μA VCCA VCCB 1.2 V to 3.6 V 1.2 V to 3.6 V 1.2 V 1.2 V IOH = –3 mA IOH = –6 mA VOH II Ioff IOZ B port B port A port ICCA MAX 0.95 1.05 1.2 IOH = –9 mA 2.3 V 2.3 V 1.75 2.3 V IOH = –12 mA 3V 3V IOL = 100 μA 1.2 V to 3.6 V 1.2 V to 3.6 V 1.2 V 1.2 V 1.4 V 1.4 V 0.35 1.65 V 1.65 V 0.45 IOL = 9 mA 2.3 V 2.3 V 0.55 IOL = 12 mA 3V 3V 0.7 1.2 V to 3.6 V 1.2 V to 3.6 V –0.25 ±0.025 0.25 –1 1 0V 0 to 3.6 V –1 ±0.1 1 –5 5 0 to 3.6 V 0V –1 ±0.1 1 –5 5 VI = VIL VI = VCCA or GND VI or VO = 0 to 3.6 V VI = VCCI or GND, IO = 0 0.2 0.15 0V 3.6 V –2.5 ±0.5 2.5 –5 5 3.6 V 0V –2.5 ±0.5 2.5 –5 5 1.2 V to 3.6 V 1.2 V to 3.6 V 10 0V 3.6 V –2 VO = VCCO or GND, VI = VCCI or GND UNIT VCCO – 0.2 1.4 V 3.6 V 0V 10 1.2 V to 3.6 V 1.2 V to 3.6 V 10 0V 3.6 V 10 3.6 V 0V –2 1.2 V to 3.6 V 1.2 V to 3.6 V 20 VI = VCCI or GND, IO = 0 ICCA + ICCB (see Table 4) MIN 1.65 V VI = VIH VI = VCCI or GND, IO = 0 ICCB MAX 1.4 V IOL = 8 mA A port TYP 1.65 V IOL = 6 mA DIR MIN –40°C to 85°C IOH = –8 mA IOL = 3 mA VOL TA = 25°C V μA μA μA μA μA μA Ci Control inputs VI = 3.3 V or GND 3.3 V 3.3 V 2.5 pF Cio A or B port VO = 3.3 V or GND 3.3 V 3.3 V 6 pF (1) (2) 6 VCCO is the VCC associated with the output port. VCCI is the VCC associated with the input port. Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated Product Folder Links: SN74AVC1T45 SN74AVC1T45 www.ti.com SCES530H – DECEMBER 2003 – REVISED DECEMBER 2014 7.6 Switching Characteristics: VCCA = 1.2 V over recommended operating free-air temperature range, VCCA = 1.2 V (see Figure 11) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH (1) tPZL (1) tPZH (1) tPZL (1) (1) FROM (INPUT) TO (OUTPUT) A B B A DIR A DIR B DIR A DIR B VCCB = 1.2 V VCCB = 1.5 V VCCB = 1.8 V VCCB = 2.5 V VCCB = 3.3 V TYP TYP TYP TYP TYP 3.3 2.7 2.4 2.3 2.4 3.3 2.7 2.4 2.3 2.4 3.3 3.1 2.9 2.8 2.7 3.3 3.1 2.9 2.8 2.7 5.1 5.2 5.3 5.2 3.7 5.1 5.2 5.3 5.2 3.7 5.3 4.3 4 3.3 3.7 5.3 4.3 4 3.3 3.7 8.6 7.3 6.8 6.1 6.4 8.6 7.3 6.8 6.1 6.4 8.3 7.8 7.7 7.5 5.8 8.3 7.8 7.7 7.5 5.8 UNIT ns ns ns ns ns ns The enable time is a calculated value, derived using the formula shown in the Enable Times section. 7.7 Switching Characteristics: VCCA = 1.5 V ± 0.1 V over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (see Figure 11) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH (1) tPZL (1) tPZH (1) tPZL (1) (1) FROM (INPUT) TO (OUTPUT) A B B A DIR A DIR B DIR A DIR B VCCB = 1.2 V VCCB = 1.5 V ± 0.1 V VCCB = 1.8 V ± 0.15 V VCCB = 2.5 V ± 0.2 V VCCB = 3.3 V ± 0.3 V TYP MIN MAX MIN MAX MIN MAX MIN MAX 2.9 0.7 5.6 0.6 5.2 0.5 4.2 0.5 3.8 2.9 0.7 5.6 0.6 5.2 0.5 4.2 0.5 3.8 2.6 0.6 5.5 0.4 5.3 0.3 4.9 0.3 4.8 2.6 0.6 5.5 0.4 5.3 0.3 4.9 0.3 4.8 3.8 1.6 6.7 1.5 6.8 0.3 6.9 0.9 6.9 3.8 1.6 6.7 1.5 6.8 0.3 6.9 0.9 6.9 5.1 1.8 8.1 1.6 7.1 1.1 4.7 1.4 4.5 5.1 1.8 8.1 1.6 7.1 1.1 4.7 1.4 4.5 7.7 13.6 12.4 9.6 9.3 7.7 13.6 12.4 9.6 9.3 6.7 12.3 12 11.1 10.7 6.7 12.3 12 11.1 10.7 UNIT ns ns ns ns ns ns The enable time is a calculated value, derived using the formula shown in the Enable Times section. Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated Product Folder Links: SN74AVC1T45 7 SN74AVC1T45 SCES530H – DECEMBER 2003 – REVISED DECEMBER 2014 www.ti.com 7.8 Switching Characteristics: VCCA = 1.8 V ± 0.15 V over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (see Figure 11) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH (1) tPZL (1) tPZH (1) tPZL (1) (1) FROM (INPUT) TO (OUTPUT) A B B A DIR A DIR B DIR A DIR B VCCB = 1.2 V VCCB = 1.5 V ± 0.1 V VCCB = 1.8 V ± 0.15 V VCCB = 2.5 V ± 0.2 V VCCB = 3.3 V ± 0.3 V TYP MIN MAX MIN MAX MIN MAX MIN MAX 2.7 0.6 5.3 0.5 5 0.4 3.9 0.4 3.4 2.7 0.6 5.3 0.5 5 0.4 3.9 0.4 3.4 2.3 0.5 5.2 0.4 5 0.3 4.6 0.2 4.4 2.3 0.5 5.2 0.4 5 0.3 4.6 0.2 4.4 3.8 1.6 5.9 1.6 5.9 1.6 5.9 0.5 6 3.8 1.6 5.9 1.6 5.9 1.6 5.9 0.5 6 5 1.8 7.7 1.4 6.8 1 4.4 1.4 5.3 5 1.8 7.7 1.4 6.8 1 4.4 1.4 5.3 7.3 12.9 11.8 9 8.7 7.3 12.9 11.8 9 8.7 6.5 11.2 10.9 9.8 9.4 6.5 11.2 10.9 9.8 9.4 UNIT ns ns ns ns ns ns The enable time is a calculated value, derived using the formula shown in the Enable Times section. 7.9 Switching Characteristics: VCCA = 2.5 V ± 0.2 V over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (see Figure 11) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH (1) tPZL (1) tPZH (1) tPZL (1) (1) 8 FROM (INPUT) TO (OUTPUT) A B B A DIR A DIR B DIR A DIR B VCCB = 1.2 V VCCB = 1.5 V ± 0.1 V VCCB = 1.8 V ± 0.15 V VCCB = 2.5 V ± 0.2 V VCCB = 3.3 V ± 0.3 V TYP MIN MAX MIN MAX MIN MAX MIN MAX 2.6 0.5 4.9 0.4 4.6 0.3 3.4 0.3 3 2.6 0.5 4.9 0.4 4.6 0.3 3.4 0.3 3 2.2 0.4 4.2 0.3 3.8 0.2 3.4 0.2 3.3 2.2 0.4 4.2 0.3 3.8 0.2 3.4 0.2 3.3 2.8 0.3 3.8 0.8 3.8 0.4 3.8 0.5 3.8 2.8 0.3 3.8 0.8 3.8 0.4 3.8 0.5 3.8 4.9 2 7.6 1.5 6.5 0.6 4.1 1 4 4.9 2 7.6 1.5 6.5 0.6 4.1 1 4 7.1 11.8 10.3 7.5 7.3 7.1 11.8 10.3 7.5 7.3 5.4 8.6 8.1 7 6.6 5.4 8.6 8.1 7 6.6 UNIT ns ns ns ns ns ns The enable time is a calculated value, derived using the formula shown in the Enable Times section. Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated Product Folder Links: SN74AVC1T45 SN74AVC1T45 www.ti.com SCES530H – DECEMBER 2003 – REVISED DECEMBER 2014 7.10 Switching Characteristics: VCCA = 3.3 V ± 0.3 V over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (see Figure 11) PARAMETER FROM (INPUT) TO (OUTPUT) A B B A DIR A DIR B DIR A DIR B tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH (1) tPZL (1) tPZH (1) tPZL (1) (1) VCCB = 1.5 V ± 0.1 V VCCB = 1.2 V VCCB = 1.8 V ± 0.15 V VCCB = 2.5 V ± 0.2 V VCCB = 3.3 V ± 0.3 V TYP MIN MAX MIN MAX MIN MAX MIN MAX 2.6 0.4 4.7 0.3 4.4 0.2 3.3 0.2 2.8 2.6 0.4 4.7 0.3 4.4 0.2 3.3 0.2 2.8 2.2 0.4 3.8 0.3 3.4 0.2 3 0.1 2.8 2.2 0.4 3.8 0.3 3.4 0.2 3 0.1 2.8 3.1 1.3 4.3 1.3 4.3 1.3 4.3 1.3 4.3 3.1 1.3 4.3 1.3 4.3 1.3 4.3 1.3 4.3 4 0.7 7.4 0.6 6.5 0.7 4 1.5 4.9 4 0.7 7.4 0.6 6.5 0.7 4 1.5 4.9 6.2 11.2 9.9 7 6.7 6.2 11.2 9.9 7 6.7 5.7 8.9 8.5 7.2 6.8 5.7 8.9 8.5 7.2 6.8 UNIT ns ns ns ns ns ns The enable time is a calculated value, derived using the formula shown in the Enable Times section. 7.11 Operating Characteristics TA = 25°C PARAMETER CpdA CpdB (1) (1) A-port input, B-port output B-port input, A-port output (1) A-port input, B-port output B-port input, A-port output TEST CONDITIONS CL = 0 pF, f = 10 MHz, tr = tf = 1 ns CL = 0 pF, f = 10 MHz, tr = tf = 1 ns VCCA = VCCB = 1.2 V VCCA = VCCB = 1.5 V VCCA = VCCB = 1.8 V VCCA = VCCB = 2.5 V VCCA = VCCB = 3.3 V TYP TYP TYP TYP TYP 3 3 3 3 4 13 13 14 15 15 13 13 14 15 15 3 3 3 3 3 UNIT pF pF Power dissipation capacitance per transceiver Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated Product Folder Links: SN74AVC1T45 9 SN74AVC1T45 SCES530H – DECEMBER 2003 – REVISED DECEMBER 2014 www.ti.com 7.12 Typical Characteristics 7.12.1 Typical Propagation Delay (A to B) vs Load Capacitance 6 6 5 5 4 4 tPLH - ns tPHL - ns TA = 25°C, VCCA = 1.2 V 3 2 3 2 VCCB = 1.2 V VCCB = 1.2 V VCCB = 1.5 V VCCB = 1.5 V VCCB = 1.8 V 1 VCCB = 2.5 V VCCB = 3.3 V 0 0 0 10 20 30 CL - pF 40 VCCB = 1.8 V 1 VCCB = 2.5 V VCCB = 3.3 V 50 60 0 10 20 30 40 50 60 CL - pF Figure 1. Typical Propagation Delay of High-to-Low (A to B) vs Load Capacitance TA = 25°C, VCCA = 1.2 V Figure 2. Typical Propagation Delay of Low-to-High (A to B) vs Load Capacitance TA = 25°C, VCCA = 1.2 V 7.12.2 Typical Propagation Delay (A to B) vs Load Capacitance 6 6 5 5 4 4 tPHL - ns tPLH - ns TA = 25°C, VCCA = 1.5 V 3 2 3 2 VCCB = 1.2 V VCCB = 1.2 V VCCB = 1.5 V VCCB = 1.5 V VCCB = 1.8 V 1 VCCB = 1.8 V 1 VCCB = 2.5 V VCCB = 2.5 V VCCB = 3.3 V VCCB = 3.3 V 0 0 10 20 30 40 50 60 0 0 CL - pF Figure 3. Typical Propagation Delay of High-to-Low (A to B) vs Load Capacitance TA = 25°C, VCCA = 1.5 V 10 10 20 30 CL - pF 40 50 60 Figure 4. Typical Propagation Delay of Low-to-High (A to B) vs Load Capacitance TA = 25°C, VCCA = 1.5 V Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated Product Folder Links: SN74AVC1T45 SN74AVC1T45 www.ti.com SCES530H – DECEMBER 2003 – REVISED DECEMBER 2014 7.12.3 Typical Propagation Delay (A to B) vs Load Capacitance 6 6 5 5 4 4 tPHL - ns tPLH - ns TA = 25°C, VCCA = 1.8 V 3 2 3 2 VCCB = 1.2 V VCCB = 1.2 V VCCB = 1.5 V VCCB = 1.8 V 1 0 VCCB = 1.5 V 0 10 20 30 40 VCCB = 1.8 V 1 VCCB = 2.5 V VCCB = 2.5 V VCCB = 3.3 V VCCB = 3.3 V 50 0 60 0 10 20 CL - pF Figure 5. Typical Propagation Delay of High-to-Low (A to B) vs Load Capacitance TA = 25°C, VCCA = 1.8 V 30 CL - pF 40 50 60 Figure 6. Typical Propagation Delay of Low-to-High (A to B) vs Load Capacitance TA = 25°C, VCCA = 1.8 V 7.12.4 Typical Propagation Delay (A to B) vs Load Capacitance TA = 25°C, VCCA = 2.5 V 6 6 VCCB = 1.2 V 5 VCCB = 1.2 V VCCB = 1.5 V VCCB = 1.5 V VCCB = 1.8 V VCCB = 1.8 V 5 VCCB = 2.5 V VCCB = 2.5 V VCCB = 3.3 V VCCB = 3.3 V 4 tPHL - ns tPLH - ns 4 3 3 2 2 1 1 0 0 10 20 30 40 50 0 60 0 10 20 CL - pF Figure 7. Typical Propagation Delay of High-to-Low (A to B) vs Load Capacitance TA = 25°C, VCCA = 2.5 V 30 CL - pF 40 50 60 Figure 8. Typical Propagation Delay of Low-to-High (A to B) vs Load Capacitance TA = 25°C, VCCA = 2.5 V 7.12.5 Typical Propagation Delay (A to B) vs Load Capacitance TA = 25°C, VCCA = 3.3 V 6 6 VCCB = 1.2 V 5 VCCB = 1.2 V VCCB = 1.5 V VCCB = 1.5 V VCCB = 1.8 V VCCB = 1.8 V 5 VCCB = 2.5 V VCCB = 2.5 V VCCB = 3.3 V VCCB = 3.3 V 4 tPHL - ns tPLH - ns 4 3 3 2 2 1 1 0 0 10 20 30 40 50 60 0 0 CL - pF Figure 9. Typical Propagation Delay of High-to-Low (A to B) vs Load Capacitance TA = 25°C, VCCA = 3.3 V 10 20 30 CL - pF 40 50 60 Figure 10. Typical Propagation Delay of Low-to-High (A to B) vs Load Capacitance TA = 25°C, VCCA = 3.3 V Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated Product Folder Links: SN74AVC1T45 11 SN74AVC1T45 SCES530H – DECEMBER 2003 – REVISED DECEMBER 2014 www.ti.com 8 Parameter Measurement Information 2 × VCCO S1 RL From Output Under Test Open GND CL (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCCO GND RL tw LOAD CIRCUIT VCCI VCCI/2 Input VCCO CL RL VTP 1.2 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 15 pF 15 pF 15 pF 15 pF 15 pF 2 kW 2 kW 2 kW 2 kW 2 kW 0.1 V 0.1 V 0.15 V 0.15 V 0.3 V VCCI/2 0V VOLTAGE WAVEFORMS PULSE DURATION VCCA Output Control (low-level enabling) VCCA/2 VCCA/2 0V tPLZ tPZL VCCI Input VCCI/2 VCCI/2 0V tPLH Output tPHL VOH VCCO/2 VOL VCCO/2 VCCO Output Waveform 1 S1 at 2 × VCCO (see Note B) VCCO/2 VOL + VTP VOL tPHZ tPZH Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCCO/2 VOH − VTP VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 W, dv/dt ≥ 1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. t PZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. VCCI is the VCC associated with the input port. I. VCCO is the VCC associated with the output port. Figure 11. Load Circuit and Voltage Waveforms 12 Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated Product Folder Links: SN74AVC1T45 SN74AVC1T45 www.ti.com SCES530H – DECEMBER 2003 – REVISED DECEMBER 2014 9 Detailed Description 9.1 Overview The SN74AVC1T45 is single-bit, dual-supply, noninverting voltage level translation. Pin A and direction control pin are support by VCCA and pin B is support by VCCB. The A port is able to accept I/O voltages ranging from 1.2 V to 3.6 V, while the B port can accept I/O voltages from 1.2 to 3.6 V. The high on DIR allows data transmission from A to B and a low on DIR allows data transmission from B to A. 9.2 Functional Block Diagram DIR A 5 3 4 VCCA B VCCB 9.3 Feature Description 9.3.1 Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.2-V to 3.6-V Power-Supply Range Both VCCA and VCCB can be supplied at any voltage between 1.2 V and 3.6 V making the device suitable for translating between any of the voltage nodes (1.2-V, 1.8-V, 2.5-V and 3.3-V). 9.3.2 Support High-Speed Translation SN74AVC1T45 can support high data-rate application. The translated signal data rate can be up to 500 Mbps when signal is translated from 1.8 V to 3.3 V. 9.3.3 Ioff Supports Partial-Power-Down Mode Operation Ioff will prevent backflow current by disabling I/O output circuits when device is in partial-power-down mode. 9.4 Device Functional Modes Table 1. Function Table (1) (1) INPUT DIR OPERATION L B data to A bus H A data to B bus Input circuits of the data I/Os always are active. Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated Product Folder Links: SN74AVC1T45 13 SN74AVC1T45 SCES530H – DECEMBER 2003 – REVISED DECEMBER 2014 www.ti.com 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information The SN74AVC1T45 device can be used in level-translation applications for interfacing devices or systems operating at different interface voltages with one another. The maximum data rate can be up to 500 Mbps when device translate signal from 1.8 V to 3.3 V. 10.1.1 Enable Times Calculate the enable times for the SN74AVC1T45 using the following formulas: • tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A) • tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A) • tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B) • tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B) In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is switched until an output is expected. For example, if the SN74AVC1T45 initially is transmitting from A to B, then the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified propagation delay. 10.2 Typical Applications 10.2.1 Unidirectional Logic Level-Shifting Application Figure 12 shows an example of the SN74AVC1T45 being used in a unidirectional logic level-shifting application. VCC1 VCC1 VCC2 1 6 2 5 3 4 SYSTEM-1 VCC2 SYSTEM-2 Figure 12. Unidirectional Logic Level-Shifting Application 14 PIN NAME FUNCTION 1 VCCA VCC1 SYSTEM-1 supply voltage (1.2 V to 3.6 V) DESCRIPTION 2 GND GND Device GND 3 A OUT Output level depends on VCC1 voltage. 4 B IN 5 DIR DIR GND (low level) determines B-port to A-port direction. 6 VCCB VCC2 SYSTEM-2 supply voltage (1.2 V to 3.6 V) Input threshold value depends on VCC2 voltage. Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated Product Folder Links: SN74AVC1T45 SN74AVC1T45 www.ti.com SCES530H – DECEMBER 2003 – REVISED DECEMBER 2014 10.2.1.1 Design Requirements For this design example, use the parameters listed in Table 2. Table 2. Design Parameters DESIGN PARAMETERS EXAMPLE VALUES Input voltage range 1.2 V to 3.6 V Output voltage range 1.2 V to 3.6 V 10.2.1.2 Detailed Design Procedure To begin the design process, determine the following: • Input voltage range – Use the supply voltage of the device that is driving the SN74AVC1T45 device to determine the input voltage range. For a valid logic-high, the value must exceed the VIH of the input port. For a valid logic low the value must be less than the VIL of the input port. • Output voltage range – Use the supply voltage of the device that the SN74AVC1T45 device is driving to determine the output voltage range. 10.2.1.3 Application Curve Figure 13. Translation Up (1.2 V to 3.3 V) at 2.5 MHz Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated Product Folder Links: SN74AVC1T45 15 SN74AVC1T45 SCES530H – DECEMBER 2003 – REVISED DECEMBER 2014 www.ti.com 10.2.2 Bidirectional Logic Level-Shifting Application Figure 14 shows the SN74AVC1T45 being used in a bidirectional logic level-shifting application. Because the SN74AVC1T45 does not have an output-enable (OE) pin, the system designer should take precautions to avoid bus contention between SYSTEM-1 and SYSTEM-2 when changing directions. VCC1 VCC1 VCC2 Pullup/Pulldown or Bus Hold† Pullup/Pulldown or Bus Hold† I/O-1 VCC2 1 6 2 5 3 4 I/O-2 DIR CTRL SYSTEM-1 SYSTEM-2 Figure 14. Bidirectional Logic Level-Shifting Application The following table shows data transmission from SYSTEM-1 to SYSTEM-2 and then from SYSTEM-2 to SYSTEM-1. Table 3. Data Transmission: SYSTEM-1 and SYSTEM-2 STATE DIR CTRL I/O-1 I/O-2 1 H Out In 2 H Hi-Z Hi-Z SYSTEM-2 is getting ready to send data to SYSTEM-1. I/O-1 and I/O-2 are disabled. The busline state depends on pullup or pulldown. (1) 3 L Hi-Z Hi-Z DIR bit is flipped. I/O-1 and I/O-2 still are disabled. The bus-line state depends on pullup or pulldown. (1) 4 L In Out SYSTEM-2 data to SYSTEM-1 (1) DESCRIPTION SYSTEM-1 data to SYSTEM-2 SYSTEM-1 and SYSTEM-2 must use the same conditions, i.e., both pullup or both pulldown. 10.2.2.1 Design Requirements Refer to Design Requirements. 10.2.2.2 Detailed Design Procedure Refer to Detailed Design Procedure. 16 Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated Product Folder Links: SN74AVC1T45 SN74AVC1T45 www.ti.com SCES530H – DECEMBER 2003 – REVISED DECEMBER 2014 10.2.2.3 Application Curve Figure 15. Translation Up (1.2 V to 3.3 V) at 2.5 MHz Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated Product Folder Links: SN74AVC1T45 17 SN74AVC1T45 SCES530H – DECEMBER 2003 – REVISED DECEMBER 2014 www.ti.com 11 Power Supply Recommendations The SN74AVC1T45 device uses two separate configurable power-supply rails, VCCA and VCCB. VCCA accepts any supply voltage from 1.2 V to 3.6 V and VCCB accepts any supply voltage from 1.2 V to 3.6 V. The A port and B port are designed to track VCCA and VCCB respectively allowing for low-voltage, bidirectional translation between any of the 1.2-V, 1.5 -V, 1.8-V, and 3.3-V voltage nodes. 11.1 Power-Up Considerations A proper power-up sequence always should be followed to avoid excessive supply current, bus contention, oscillations, or other anomalies. To guard against such power-up problems, take the following precautions: 1. Connect ground before any supply voltage is applied. 2. Power up VCCA. 3. VCCB can be ramped up along with or after VCCA. Table 4. Typical Total Static Power Consumption (ICCA + ICCB) VCCB VCCA 0V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 0V 0 <0.5 <0.5 <0.5 <0.5 <0.5 1.2 V <0.5 <1 <1 <1 <1 1 1.5 V <0.5 <1 <1 <1 <1 1 1.8 V <0.5 <1 <1 <1 <1 <1 2.5 V <0.5 1 <1 <1 <1 <1 3.3 V <0.5 1 <1 <1 <1 <1 UNIT μA 12 Layout 12.1 Layout Guidelines To • • • 18 ensure reliability of the device, following common printed-circuit board layout guidelines are recommended: Bypass capacitors should be used on power supplies. Short trace lengths should be used to avoid excessive loading. Placing pads on the signal paths for loading capacitors or pullup resistors to help adjust rise and fall times of signals depending on the system requirements. Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated Product Folder Links: SN74AVC1T45 SN74AVC1T45 www.ti.com SCES530H – DECEMBER 2003 – REVISED DECEMBER 2014 12.2 Layout Example Figure 16. PCB Layout Example Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated Product Folder Links: SN74AVC1T45 19 SN74AVC1T45 SCES530H – DECEMBER 2003 – REVISED DECEMBER 2014 www.ti.com 13 Device and Documentation Support 13.1 Trademarks NanoFree is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 13.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 20 Submit Documentation Feedback Copyright © 2003–2014, Texas Instruments Incorporated Product Folder Links: SN74AVC1T45 PACKAGE OPTION ADDENDUM www.ti.com 5-Feb-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) SN74AVC1T45DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (DT1F ~ DT1R) (DT1H ~ DT1P) SN74AVC1T45DBVRE4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (DT1F ~ DT1R) (DT1H ~ DT1P) SN74AVC1T45DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (DT1F ~ DT1R) (DT1H ~ DT1P) SN74AVC1T45DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU | Call TI Level-1-260C-UNLIM -40 to 85 DT1R DT1H SN74AVC1T45DBVTE4 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 DT1R DT1H SN74AVC1T45DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 DT1R DT1H SN74AVC1T45DCKR ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (TCF ~ TCR) (TCH ~ TCP) SN74AVC1T45DCKRE4 ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (TCF ~ TCR) (TCH ~ TCP) SN74AVC1T45DCKRG4 ACTIVE SC70 DCK 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (TCF ~ TCR) (TCH ~ TCP) SN74AVC1T45DCKT ACTIVE SC70 DCK 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (TCF ~ TCR) (TCH ~ TCP) SN74AVC1T45DCKTG4 ACTIVE SC70 DCK 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 (TCF ~ TCR) (TCH ~ TCP) SN74AVC1T45DRLR ACTIVE SOT DRL 6 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TCR TCH SN74AVC1T45DRLRG4 ACTIVE SOT DRL 6 4000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TCR TCH SN74AVC1T45YZPR ACTIVE DSBGA YZP 6 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 (TC2 ~ TC7 ~ TCN) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 5-Feb-2015 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 4-Jun-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ SN74AVC1T45DBVR SOT-23 3000 180.0 8.4 DBV 6 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.23 3.17 1.37 4.0 8.0 Q3 SN74AVC1T45DBVT SOT-23 DBV 6 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 SN74AVC1T45DCKR SC70 DCK 6 3000 180.0 8.4 2.41 2.41 1.2 4.0 8.0 Q3 SN74AVC1T45DCKR SC70 DCK 6 3000 180.0 8.4 2.3 2.52 1.2 4.0 8.0 Q3 SN74AVC1T45DCKT SC70 DCK 6 250 180.0 8.4 2.41 2.41 1.2 4.0 8.0 Q3 SN74AVC1T45DRLR SOT DRL 6 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3 SN74AVC1T45YZPR DSBGA YZP 6 3000 178.0 9.2 1.02 1.52 0.63 4.0 8.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 4-Jun-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AVC1T45DBVR SOT-23 DBV 6 3000 202.0 201.0 28.0 SN74AVC1T45DBVT SOT-23 DBV 6 250 202.0 201.0 28.0 SN74AVC1T45DCKR SC70 DCK 6 3000 202.0 201.0 28.0 SN74AVC1T45DCKR SC70 DCK 6 3000 214.0 199.0 55.0 SN74AVC1T45DCKT SC70 DCK 6 250 202.0 201.0 28.0 SN74AVC1T45DRLR SOT DRL 6 4000 202.0 201.0 28.0 SN74AVC1T45YZPR DSBGA YZP 6 3000 220.0 220.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE YZP0006 DSBGA - 0.5 mm max height SCALE 9.000 DIE SIZE BALL GRID ARRAY B A E BALL A1 CORNER D C 0.5 MAX SEATING PLANE 0.19 0.15 BALL TYP 0.05 C 0.5 TYP C SYMM 1 TYP B 0.5 TYP D: Max = 1.418 mm, Min =1.358 mm E: Max = 0.918 mm, Min =0.858 mm A 6X 0.015 0.25 0.21 C A B 1 2 SYMM 4219524/A 06/2014 NanoFree Is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. TM 3. NanoFree package configuration. www.ti.com EXAMPLE BOARD LAYOUT YZP0006 DSBGA - 0.5 mm max height DIE SIZE BALL GRID ARRAY (0.5) TYP 6X ( 0.225) 1 2 A (0.5) TYP SYMM B C SYMM LAND PATTERN EXAMPLE SCALE:40X ( 0.225) METAL 0.05 MAX METAL UNDER MASK 0.05 MIN ( 0.225) SOLDER MASK OPENING SOLDER MASK OPENING NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE 4219524/A 06/2014 NOTES: (continued) 4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SBVA017 (www.ti.com/lit/sbva017). www.ti.com EXAMPLE STENCIL DESIGN YZP0006 DSBGA - 0.5 mm max height DIE SIZE BALL GRID ARRAY (0.5) TYP 6X ( 0.25) (R0.05) TYP 2 1 A (0.5) TYP SYMM B METAL TYP C SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:40X 4219524/A 06/2014 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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